JP2015177225A - Source ground amplifier circuit and its slew rate improvement method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a source ground amplifier circuit 100 in which a load resistance 1 and a MOS transistor 2 are connected in series and the layout size is not increased, by improving the slew rate.SOLUTION: In a source ground amplifier circuit 100, the slew rate is improved by connecting a MOS transistor 3 of reverse type in parallel with a load resistance 1, and making the charge and discharge current of an output load 4 flow out from the MOS transistor 3 of reverse type.

Description

  The present invention relates to a common source amplifier circuit having an improved slew rate.

  The common-source amplifier circuit is a basic amplifier circuit and has a wide application range and is widely used.

  FIG. 2 is a typical circuit example of such a common source amplifier circuit. In FIG. 2A, an N-channel MOS transistor 21 is used as an input element, and a load resistor 11 is connected to constitute a common source amplifier circuit 111. Furthermore, the load represented by the output load 41 is driven. When the common source amplifier circuit 111 is in an analog operation in which input / output operates with a linear characteristic, the transistor 21 performs a driving operation by the input signal IN, and a charge / discharge current flows through the load resistor 11. Since the normal output load 41 has a capacitive impedance, with respect to the charge / discharge current flowing through the load resistor 11, the resistance of the load resistor 11 itself degrades the charge / discharge operation speed. That is, the load resistance 11 degrades the output slew rate.

  FIG. 2B shows a common source amplifier circuit 112 in which a capacitor 5 is connected in parallel to the load resistor 12. If the input signal IN of the transistor 22 is a high voltage, the output signal OUT is at or near 0 V of the ground, a high voltage is applied to the load resistor 12 and the capacitor 5, and the capacitor 5 is charged. Here, when the input signal IN of the transistor 22 changes to a low voltage, the output load 42 changes to a high voltage corresponding to the power supply voltage, and the load resistor 12 and the capacitor 5 are connected to the output load 42 having a capacitive impedance. Start charging. When the capacitor 5 is not present, the load resistor 12 delays charging, but the discharging of the capacitor 5 can accelerate the charging of the output load 42.

  If the input signal IN of the transistor 22 is a low voltage, the output signal OUT is a high voltage, almost no voltage is applied to the load resistor 12 and the capacitor 5, and the capacitor 5 is not charged. Here, when the input signal IN of the transistor 22 changes to a high voltage, the output load 42 changes to the ground voltage of 0 V or a value in the vicinity thereof, and the discharge of the capacitive impedance output load 42 starts. The discharge current at this time flows via the transistor 22.

  In FIG. 2, an N-channel transistor is exemplified. However, when a P-channel transistor is used, a slew rate is improved by connecting a capacitor in parallel to a load resistor. In this case, the discharge current becomes a problem.

  Here, it is assumed that the slew rate as an analog operation has a sufficiently linear characteristic when the output voltage changes to high and low voltages (changes in rising and falling). That is, when the slew rate is small, the waveform is distorted. For this reason, it is necessary to reduce the influence on the linear characteristic of the capacitive impedance of the output load, and the current to the output load is increased as much as possible.

Conventionally, the slew rate of a common source amplifier circuit using a load resistor has been improved as described above. That is, when the common source amplifier circuit is operated in an analog manner in the triode region of the MOS transistor, the slew rate of the output voltage is limited by the current that charges and discharges the capacitance in the amplifier circuit and the capacitance of the output load. . In order to improve the slew rate, it is common to reduce the load resistance so that the charge / discharge current increases. As a general method for reducing the load resistance, a capacitor is connected in parallel to the load resistance. The circuit operation by this is exemplified as described above. However, since the impedance of the capacitor decreases as the frequency increases, the load resistance appears to decrease as the operating frequency increases by connecting the capacitor in parallel with the load resistor. By making the load resistance appear small, the charge / discharge current increases and the slew rate improves.

JP 59-182608 A

The effect of the method of connecting the capacitor in parallel with the load resistance has an output load dependency and a use frequency dependency. When the output load is small, that is, when the capacity of the output load is large, the layout size increases in order to obtain a sufficient charge / discharge current.
In addition, since the capacitance connected in parallel with the load resistor has frequency characteristics, there is a problem that a large capacitance is required to obtain sufficient charge / discharge current even when the operating frequency is low, and the layout size increases.

  In view of the above problems, it is an object of the present invention to provide a grounded source amplifier circuit that improves the slew rate and does not increase the layout size in a grounded source amplifier circuit in which a load resistor and a MOS transistor are connected in series. To do.

The present invention has been made in view of the problems, and the invention of claim 1
In a source grounded amplifier circuit in which a load resistor and a MOS transistor are connected in series and input / output operates with a linear characteristic,
This is a grounded source amplifier circuit characterized in that a reverse type MOS transistor is connected in parallel with a load resistor.

The invention of claim 2 of the present invention
In the method for improving the slew rate of a common source amplifier circuit in which a load resistor and a MOS transistor are connected in series and the input / output operates with a linear characteristic,
This is a method for improving the slew rate of a grounded source amplifier circuit, characterized in that a reverse type MOS transistor is connected in parallel with the load resistance, and the charge / discharge current of the output load is caused to flow out by the reverse type MOS transistor. is there.

  Since the operational amplifier of the present invention is configured as described above, it is composed of a differential amplifier and an output stage amplifier, a load resistor and a MOS transistor are connected in series, and the input / output operates in a linear characteristic. A grounded source amplifier circuit with improved slew rate can be provided without increasing the layout size.

It is explanatory drawing which showed the example of embodiment of the common source amplifier circuit of this invention. It is explanatory drawing which showed the example of the conventional source grounding amplifier circuit.

Hereinafter, modes for carrying out the present invention will be described. FIG. 1 is an explanatory diagram showing an embodiment of a common source amplifier circuit according to the present invention. FIG. 1A shows an example in which the input transistor of the common source amplifier circuit uses an N channel transistor, and FIG. 1B shows an example in which the input transistor of the common source amplifier circuit uses a P channel transistor.

  The grounded source amplifier circuit of this embodiment is premised on a grounded source amplifier circuit in which a load resistor and a MOS transistor are connected in series and the input / output operates with linear characteristics. A reverse type MOS transistor is connected in parallel with the load resistor.

  When the MOS transistor is an N-channel transistor, the source-grounded amplifier circuit 100 of the present invention is configured such that the terminal of the load resistor 1 is connected to the power source and the terminal of the N-channel transistor 2 is grounded, as illustrated in FIG. A P-channel transistor 3 is connected in parallel to the load resistor 1. A signal IN is input to the input terminals of the N-channel transistor 2 and the P-channel transistor 3. An output load 4 mainly including a capacitive impedance is connected between the output signal OUT and the ground.

  When the MOS transistor is a P-channel transistor, the grounded-source amplifier circuit 110 of the present invention is configured such that the terminal of the load resistor 10 is connected to the ground and the terminal of the P-channel transistor 20 is the power source, as illustrated in FIG. The N-channel transistor 30 is connected in parallel to the load resistor 10. A signal IN is input to the input terminals of the N-channel transistor 20 and the P-channel transistor 30. An output load 40 mainly including a capacitive impedance is connected between the output signal OUT and the ground.

  In this embodiment, it is the above structures and has the following effects.

  In the circuit of FIG. 1A, when the input signal IN is a high voltage, the transistor 2 is in a low resistance state, the transistor 3 is in a high resistance state, and a low voltage is applied to the output load 4 to output the output signal. OUT is at a low voltage. A high voltage is applied to the load resistor 1 and a current flows. When the magnitude of the input signal IN gradually decreases from the high voltage in this state, the transistor 2 goes to the high resistance state and the transistor 3 goes to the low resistance state. As a result, the output load 4 is charged. In this case, the transistor 3 and the load resistor 1 cause a charging current to flow. In particular, since the charging current by the transistor 3 greatly contributes compared to the circuit having only the load resistor 1 as in the prior art, the output load 4 can be charged quickly, and the output signal OUT becomes a high voltage. Moreover, since it can charge rapidly, the influence on the linear characteristic by the capacitive impedance of the output load 4 is reduced. That is, the slew rate can be improved.

  When the input signal IN goes from the low voltage to the high voltage, the transistor 2 goes from the high resistance state to the low resistance state, and the transistor 3 goes from the low resistance state to the high resistance state. As a result, the output load 4 is discharged. In this case, the transistor 2 mainly causes the discharge current to flow, so that the transistor 2 can be discharged quickly, and there is almost no influence on the linear characteristics due to the capacitive impedance of the output load 4.

  Next, in the circuit of FIG. 1B, when the input signal IN is a low voltage, the transistor 20 is in a low resistance state, the transistor 30 is in a high resistance state, and a high voltage is applied to the output load 40. The output signal OUT is set to a high voltage. A high voltage is applied to the load resistor 10 and a current flows. In this state, when the magnitude of the input signal IN gradually increases from a low voltage, the transistor 20 goes to a high resistance state and the transistor 30 goes to a low resistance state. As a result, the output load 40 is discharged. In this case, the transistor 30 and the load resistor 10 cause a discharge current to flow. In particular, compared with a circuit having only the load resistor 10 as in the prior art, the discharge current by the transistor 30 contributes greatly, so that the output load 40 can be discharged quickly, and the output signal OUT becomes a low voltage. Moreover, since it can discharge quickly, the influence on the linear characteristic by the capacitive impedance of the output load 40 is reduced. That is, the slew rate can be improved.

  When the input signal IN goes from the high voltage to the low voltage, the transistor 20 goes from the high resistance state to the low resistance state, and the transistor 30 goes from the low resistance state to the high resistance state. As a result, the output load 40 is charged. In this case, the transistor 20 mainly causes a charging current to flow, so that the transistor 20 can be charged quickly, and the capacitive characteristic of the output load 40 has little influence on the linear characteristics.

  As described above, in the present invention, instead of the capacitance that was the conventional countermeasure, a transistor is connected in parallel with the load resistor to increase the charge / discharge current and improve the slew rate. Since the capacitor connected to improve the slew rate is replaced with a transistor, the layout size is not greatly increased. This circuit is particularly effective when the output load is small or the operating frequency is low.

1, 10, 11, 12 ... load resistance 2, 20, 21, 22 ... input transistors 3, 30, 31, 32 ... reverse type transistors 4, 40, 41, 42 ... output load 5 ... Capacitance 100, 110, 111, 112 ... Common source amplifier circuit

Claims (2)

In a source grounded amplifier circuit in which a load resistor and a MOS transistor are connected in series and input / output operates with a linear characteristic,
A source-grounded amplifier circuit comprising a reverse type MOS transistor connected in parallel with a load resistor. In the method for improving the slew rate of a common source amplifier circuit in which a load resistor and a MOS transistor are connected in series and the input / output operates with a linear characteristic,
A method for improving the slew rate of a grounded-source amplifier circuit, wherein a reverse type MOS transistor is connected in parallel with a load resistor, and charge / discharge current of an output load is caused to flow out by the reverse type MOS transistor.

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