JP2015046519A - Method for manufacturing circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a circuit board including a step of reducing a film thickness of an etching resist layer, by which etching failure caused by deposition of a resist chip broken in the film reduction step can be prevented.SOLUTION: The method for manufacturing a circuit board includes steps of, in the following order: (A) forming an etching resist layer on both surfaces of an insulating substrate in which metal layers on both surfaces and a conduction hole are formed; (C1) exposing a part of the etching resist layer above the conduction hole where a metal layer on an inner wall of the hole is to be removed in step (E) and exposing the etching resist layer excluding a region where a circuit is to be formed; (B) reducing a film thickness of the etching layer in an unexposed part by a thinning process liquid; (C2) exposing the etching resist layer except excluding a region where the etching resist layer is to be developed and removed in step (D); (D) removing the etching resist layer in an unexposed part by using a developing solution to partially expose the metal layer; and (E) removing the exposed metal layer by an etching process liquid.

Description

  The present invention relates to a circuit board manufacturing method using a subtractive method.

  As a method for manufacturing a circuit board, a subtractive method in which an etching resist layer is provided on a circuit portion of an insulating substrate having a metal layer on the surface, and a metal pattern of an exposed non-circuit portion is removed by etching to form a circuit pattern. There is. Compared to the additive and semi-additive methods, this method has many advantages such as fewer manufacturing processes and cost advantages, as well as a sufficiently large bond strength between the metal pattern and the insulating substrate. It has become the mainstream of circuit board manufacturing methods.

  In the subtractive method, the etching resist layer is formed by a screen printing method, a photofabrication method having an exposure development process using a photocrosslinkable resin, an ink jet method, or the like. Among these, a method using a sheet-like photocrosslinkable resin layer called a negative dry film resist is generally preferably used because it is easy to handle and can protect through holes by tenting.

  Now, with recent downsizing and multi-functionalization of electronic devices, circuit boards used inside the devices are also being densified and metal patterns are being miniaturized. Currently, the conductor width is 50 by the subtractive method. A circuit board having a metal pattern of ˜80 μm and a conductor gap of 50˜80 μm is manufactured. In addition, with higher density and finer wiring, ultrafine metal patterns with a conductor width or a conductor gap of 50 μm or less have been demanded. Along with this, the requirements for circuit pattern accuracy and impedance are also increasing. In order to form such a fine metal pattern, a semi-additive method has been studied in place of the subtractive method. However, there are problems such as a significant increase in the number of manufacturing processes and insufficient adhesive strength of electrolytically plated copper. there were.

  When producing a fine metal pattern using the subtractive method, it is of course necessary to improve the technical level and the management level of the entire production line, but the etching process is particularly important. This is because side etching that proceeds from the side of the conductor, which is a feature of the subtractive method, becomes a problem. In order to suppress the amount of side etching, it is necessary to adjust optimum etching conditions such as liquid composition management and the angle and strength of spraying the liquid onto the substrate. Further, side etching is influenced not only by adjusting the etching conditions but also by the film thickness of the etching resist layer. In other words, the thicker the etching resist layer, the worse the circulation of the liquid in the gap portion of the fine resist pattern, and as a result, the side etching increases. The film thickness of the dry film resist which is currently mainstream is around 25 μm, but in order to produce a fine metal pattern, it is necessary to make the resist film thickness as thin as possible, and in recent years the film thickness is 10 μm or less. Thin dry film resists have been developed and commercialized. However, such a thin dry film resist has a problem in that the mixing of bubbles with dust as a core and the unevenness followability become insufficient, and the resist is peeled off or disconnected.

  In order to solve such problems, a dry film resist having a film thickness of 25 μm or more is pasted on the substrate, and then the dry film resist is thinned to about 10 μm using a processing solution, and then exposure and development of a circuit pattern are performed. Has been proposed to form a resist pattern, and subsequently etch a metal layer other than the resist pattern portion (see, for example, Patent Documents 1 and 2).

  In recent years, circuit boards have been equipped with circuit wiring on both sides of the insulating substrate for high-density mounting, and grounding electrode wiring has been provided on the opposite side of the circuit wiring surface due to high-speed signals to be used for impedance matching. What you took is needed. Conventionally, these double-sided circuit boards are electrically connected by forming metal plated through holes on the inner wall surfaces of through holes provided in the substrate in order to connect the double-sided wirings.

  In such a circuit board, a through-hole to be insulated (insulating hole) that should not be electrically connected to an alignment through-hole, a double-sided wiring such as an outer lead window and a device hole of a TAB chip carrier, and the aforementioned through-hole Examples of a method for manufacturing a circuit board having both through-holes (conduction holes) through which the double-sided wiring is to be conducted by the subtractive method include the following methods.

  A conductive layer is formed by plating the entire insulating substrate having a through hole, and then etching process using a photofabrication method is performed to selectively select a plated layer of the through hole that becomes an insulating hole. By removing them, some of the conduction holes are changed to insulation holes. A circuit board having circuit wiring on both sides of an insulating substrate having a conductive hole and an insulating hole can be manufactured by preparing a resist pattern for forming a circuit by a photofabrication method when performing this etching process. it can.

  However, in producing a circuit board having circuit wiring on both surfaces of the insulating substrate having the conductive hole and the insulating hole, the dry film resist according to Patent Documents 1 and 2 is used for the purpose of producing a finer circuit wiring. When the thin film forming technique is used, there is a problem that the dry film on the through hole serving as the insulating hole becomes thin in the thin film forming process and is easily broken. The dry film resist on the through-hole which becomes the insulating hole is flexible because it is not photocrosslinked, and easily adheres to the dry film resist formed on the insulating substrate. If the piece adheres to the dry film resist in the part that forms the circuit wiring, it may cause etching failure in the circuit formation part, and if the torn resist piece adheres around the through hole that becomes the insulating hole Caused an etching failure in the insulating hole forming portion.

JP 2004-214253 A International Publication No. 2009/096438 Pamphlet

  An object of the present invention is a method of manufacturing a circuit board having a metal layer formed on both surfaces of an insulating substrate, a conduction hole having a metal layer formed on the inner wall, and an insulating hole having no metal layer formed on the inner wall. Etching failure caused by resist pieces that have been torn by the thinning process adhere to the dry film resist in the circuit formation portion can be prevented, and the resist pieces that have been torn off adhere to the periphery of the through-holes that become insulating holes. It is an object of the present invention to provide a method for manufacturing a circuit board that can prevent an etching failure of an insulating hole forming portion that occurs as a result.

  As a result of intensive studies to solve the above problems, the present inventors have found the following invention.

(1) In a method of manufacturing a circuit board having a metal layer formed on both surfaces of an insulating substrate, a conduction hole having a metal layer formed on the inner wall, and an insulating hole having no metal layer formed on the inner wall,
(A) a step in which an etching resist layer is formed on both sides of an insulating substrate in which metal layers on both sides and conductive holes are formed;
(C1) A part of the etching resist layer above the conduction hole from which the metal layer on the inner wall is removed in the subsequent step (E) and the etching resist layer other than the region where the circuit is formed in the subsequent step (E) are exposed. Process
(B) The step of thinning the unexposed portion of the etching resist layer with the thinning treatment solution (C2) The step of exposing the etching resist layer other than the region to be developed and removed in the subsequent step (D),
(D) a step in which an etching resist layer in an unexposed portion is removed by a developer and a part of the metal layer is exposed;
(E) a step of removing the metal layer exposed from the etching resist layer with an etching treatment liquid;
A circuit board manufacturing method comprising:

(2) Of the exposure area in step (C1), the exposure area for a part of the etching resist layer above the conduction hole where the metal layer on the inner wall is removed in the subsequent step (E) is concentric with the conduction hole. The method for producing a circuit board according to (1) above, which is other than a ring-shaped region having an inner diameter smaller than the diameter of the conduction hole and an outer diameter larger than the diameter of the conduction hole.

(3) The circuit board according to (2), wherein the outer diameter of the ring-shaped region is 105 to 115% with respect to the diameter of the conduction hole, and the inner diameter is 85 to 95% with respect to the diameter of the conduction hole. Method.

  According to the present invention, in a method of manufacturing a circuit board having a metal layer formed on both surfaces of an insulating substrate, a conduction hole having a metal layer formed on the inner wall, and an insulating hole having no metal layer formed on the inner wall, It is possible to prevent the etching failure caused by the resist piece torn by the processing process from adhering to the dry film resist of the circuit forming portion, and the resist piece torn around adheres to the periphery of the through hole serving as the insulating hole. Thus, it is possible to provide a method for manufacturing a circuit board that can prevent an etching failure of an insulating hole forming portion that occurs in the above.

It is explanatory drawing which shows the manufacturing method of the circuit board of this invention. In this invention, it is explanatory drawing which shows the shape of the exposure area | region at the time of exposing the etching resist layer on the conduction | electrical_connection hole changed into an insulation hole. In this invention, it is explanatory drawing which shows the exposure area | region at the time of exposing the etching resist layer on the conduction | electrical_connection hole changed to an insulation hole, and a non-exposure area | region.

  Hereinafter, the circuit board manufacturing method of the present invention will be described in detail.

  In the method for manufacturing a circuit board according to the present invention, an etching resist layer is formed on both surfaces of an insulating substrate on which metal layers on both sides and a conduction hole are formed, and then the etching resist layer on the conduction hole is changed to an insulation hole. The etching resist layer other than the portion and the region to be thinned is exposed. As a result, in the next thinning step, the etching resist layer on the conduction hole to be changed to the insulation hole is easily broken along the end of the conduction hole, so that the etching around the conduction hole to be changed to the insulation hole is performed. It is possible to prevent an etching failure caused by a resist piece that has been torn on the resist layer. In addition, since the torn resist piece is exposed and photocrosslinked, it is not flexible and is difficult to adhere on the etching resist layer, so that the torn resist piece adheres to the periphery of the circuit forming portion. Defects can also be prevented.

  The circuit board manufacturing method of the present invention will be described with reference to the drawings. First, the manufacturing method (1) of the circuit board of this invention is demonstrated using FIG. An insulating substrate 3 having a metal layer 1 on both sides and a conduction hole 2 is prepared (FIG. 1a). An etching resist layer 4 is formed on both surfaces of the insulating substrate 3 on which the metal layers 1 and the conduction holes 2 are formed (FIG. 1A). For the formation of the etching resist layer 4, for example, a thermocompression laminator apparatus that presses and presses a rubber roll heated to 100 ° C. or higher can be used.

  Next, by removing the metal layer 1 on the inner wall in the post-process (E), a circuit is formed in the post-process (E) with a part of the etching resist layer above the conduction hole 5 that changes to an insulating hole. The etching resist layer other than the region is exposed with actinic rays 6 (FIG. 1 (C1)). In the exposure of the step (C1), the etching resist layer on the conduction hole 2 that is the conduction hole 2 when the circuit board of the present invention is completed and the etching resist layer on the conduction hole 5 that changes to the insulation hole when the circuit board of the present invention is completed. A part of the light is exposed to the active light 6. In FIG. 1C1, the photomask 7 is used, but a direct drawing method may be used.

  Next, the etching resist layer 4 in the unexposed area is thinned with a thinning solution (FIG. 1B-1). The step of thinning the etching resist layer 4 according to the present invention (thinning step) is a micellarization treatment (thinning treatment) in which the components of the etching resist layer 4 in the unexposed portion are micellized by a thinning treatment liquid, And a step including a micelle removal process for removing micelles with a micelle removal solution. Further, the surface of the etching resist layer 4 that could not be removed, the remaining thinning treatment liquid and the micelle removal liquid may be washed with water, and may include a drying process for removing the washing water.

  In the method of manufacturing a circuit board according to the present invention, since a part of the etching resist layer 4 above the conduction hole 5 that changes to the insulation hole is exposed, the etching resist layer 4 above the conduction hole 5 that changes to the insulation hole. Is easily broken along the end of the conduction hole 5 which changes to an insulating hole. Therefore, in the thinning process, the etching resist layer on the conductive hole 5 that changes to the insulating hole is removed as shown in FIG.

  Next, the etching resist layer 4 other than the region to be developed and removed in the subsequent step (D) is exposed with actinic rays 6 (FIG. 1 (C2)). In FIG. 1C2, the photomask 7 is used, but a direct drawing method may be used.

  Next, the etching resist layer 4 in the unexposed portion is removed by the developer, so that the conductive holes 5 that change into insulating holes and a part of the metal layer 1 are exposed from the etching resist layer 4 (FIG. 1D). .

  Next, the metal layer 1 exposed from the etching resist layer 4 is removed by an etching treatment solution, so that the metal layer 1 formed on both surfaces of the insulating substrate 3 and the inner wall have a metal as shown in FIG. A circuit board having the conduction hole 2 in which the layer is formed and the insulating hole 8 in which the metal layer is not formed on the inner wall can be manufactured.

  The circuit board manufacturing method (2) of the present invention is the circuit board manufacturing method (1) of the present invention, wherein the etching resist on the upper part of the conductive hole 5 that changes to an insulating hole in the exposure region in the step (C1). In the method of manufacturing a circuit board, an exposure region for a part of the layer 4 is a concentric circle with the conduction hole 2 and is other than a ring-shaped region having an inner diameter smaller than the diameter of the conduction hole 2 and an outer diameter larger than the diameter of the conduction hole 2. is there.

  Further, in the circuit board manufacturing method (3) of the present invention, the outer diameter of the ring-shaped region in the circuit board manufacturing method (2) of the present invention is 105 to 115% with respect to the diameter of the conduction hole. Is a method for manufacturing a circuit board, which is 85 to 95% of the diameter of the conduction hole.

  An insulating substrate having a metal layer on both sides and a conduction hole according to the present invention is formed by forming a through hole in an insulating substrate (metal-clad laminate) having a metal layer on both sides and plating the inner wall of the through hole. It can produce by setting it as a conduction hole by giving.

  Examples of the insulating substrate having metal layers on both sides include a printed wiring board substrate. Examples of the printed wiring board substrate include a flexible substrate and a rigid substrate. The thickness of the insulating substrate of the flexible substrate is 5 to 125 μm, and a metal layer of 1 to 35 μm is provided on both sides or one side, and the flexibility is high. As the material for the insulating substrate, polyimide, polyamide, polyphenylene sulfide, polyethylene terephthalate, liquid crystal polymer, or the like is usually used. A material having a metal layer on an insulating substrate is a thin metal with a thickness of several nanometers formed on a resin film by an adhesive method of bonding with an adhesive, a casting method of applying a resin solution on a metal foil, or a sputtering or vapor deposition method. A layer produced by any method such as a sputtering / plating method in which a metal layer is formed by electrolytic plating on a layer (seed layer), or a laminating method in which the layer is attached by hot pressing may be used. As the metal of the metal layer, any metal such as copper, aluminum, silver, nickel, chromium, or an alloy thereof can be used, but copper is generally used.

  A rigid substrate is an insulating substrate that is made by immersing an epoxy resin or a phenolic resin in a paper base or glass base, and a metal foil is placed on one or both sides of the base and laminated by heating and pressing. And those provided with a metal layer. Moreover, the multilayer board which has a through-hole and a non-through-hole, and the multilayer shield board produced by laminating | stacking a prepreg, metal foil, etc. after an inner layer wiring pattern process is also mentioned. The thickness is 60 μm to 3.2 mm, and the material and thickness thereof are selected according to the final use form as a circuit board. Examples of the material for the metal layer include copper, aluminum, silver, and gold, but copper is the most common. Examples of these circuit boards are “Printed Circuit Technology Handbook-Second Edition” (edited by the Japan Society of Printed Circuits, published in 1987, published by Nikkan Kogyo Shimbun), and “Multilayer Printed Circuit Handbook” (edited by JA Scarlet). 1992, published by Modern Chemical Co., Ltd.).

  Examples of the etching resist layer according to the present invention include negative dry film resists in which a light irradiation part is photocrosslinked and insolubilized in a developer. The dry film resist contains at least a photocrosslinkable resin, and is coated with a photocrosslinkable resin on a carrier film such as polyester to form a photocrosslinkable resin layer. In some cases, the film is photocrosslinked with a protective film such as polyethylene. It is the structure which coat | covered the property resin layer. The photocrosslinkable resin layer is composed of, for example, a binder polymer containing a carboxyl group, a photopolymerizable compound having at least one polymerizable ethylenically unsaturated group in the molecule, a photopolymerization initiator, a solvent, and other additives. . Their blending ratio is determined by a balance of required properties such as sensitivity, resolution, degree of cross-linking and tenting property. In the composition design of the photocrosslinkable resin for high resolution, it is effective to suppress the photocrosslinkable resin in the photocrosslinked portion from being swollen by the developer. For this purpose, a binder having a low acid value is used. Is most effective. Examples of photocrosslinkable resin compositions are “Photopolymer Handbook” (edited by Photopolymer Social Society, published in 1989, published by Kogyo Kenkyukai) and “Photopolymer Technology” (edited by Akio Yamamoto and Mototaro Nagamatsu, 1988). Published by Nikkan Kogyo Shimbun, etc.), and a desired photocrosslinkable resin composition can be used. The thickness of the photocrosslinkable resin layer is preferably 15 to 100 μm, and more preferably 20 to 50 μm. If the thickness is less than 15 μm, resist peeling or disconnection may occur due to mixing of bubbles with dust as a nucleus or uneven followability, and if it exceeds 100 μm, the amount dissolved and removed by thinning increases. The thinning time may be long.

  The thinning process (micellar process) according to the present invention is a process in which the components of the etching resist layer are micellized with a thinning process liquid and the micelles are insolubilized in the thinning process liquid. Examples of the alkaline aqueous solution used as the thinning treatment liquid include alkali metal silicates such as lithium, sodium and potassium, alkali metal hydroxides, alkali metal phosphates, alkali metal carbonates, ammonium phosphates, An aqueous solution of an inorganic alkaline compound such as ammonium carbonate; monoethanolamine, diethanolamine, triethanolamine, methylamine, dimethylamine, ethylamine, diethylamine, triethylamine, cyclohexylamine, tetramethylammonium hydroxide (TMAH), tetraethylammonium hydroxide, An aqueous solution of an organic alkaline compound such as trimethyl-2-hydroxyethylammonium hydroxide (choline) can be used. The inorganic alkaline compound and organic alkaline compound can also be used as a mixture.

  The content of the alkaline compound can be 0.1% by mass or more and 50% by mass or less. Further, in order to make the etching resist layer surface more uniform, sulfates and sulfites can be added to the alkaline aqueous solution. Examples of the sulfate or sulfite include alkali metal sulfates or sulfites such as lithium, sodium or potassium, and alkaline earth metal sulfates or sulfites such as magnesium and calcium.

  Among these, as the thinning treatment liquid, among these, an inorganic alkaline compound selected from alkali metal carbonates, alkali metal phosphates, alkali metal hydroxides, alkali metal silicates; organic alkaline compounds selected from TMAH and choline Among these, a thinning treatment liquid containing at least one of them and having an alkaline compound content of 5 to 25% by mass can be preferably used because the surface can be thinned more uniformly. If it is less than 5% by mass, unevenness may easily occur in the process of thinning. Moreover, when it exceeds 25 mass%, precipitation of an inorganic alkaline compound will occur easily and it may be inferior to the temporal stability of a liquid, and workability | operativity. As for content of an alkaline compound, 7-17 mass% is more preferable, and 8-13 mass% is further more preferable. The pH of the thinning treatment solution is preferably 10 or more. Further, a surfactant, an antifoaming agent, a solvent and the like can be added as appropriate.

  As the thinning treatment, methods such as immersion treatment, paddle treatment, spray treatment, brushing, and scraping can be used, and immersion treatment is preferable. Treatment methods other than immersion treatment tend to generate bubbles in the thinning treatment liquid, and the generated bubbles may adhere to the surface of the etching resist layer during the thinning treatment, resulting in non-uniform film thickness. .

  In the micelle removal treatment for removing the micelles of the components of the etching resist layer insolubilized in the thinning treatment solution, the micelles are dissolved and removed at once by spraying the micelle removal solution.

  As the micelle removal liquid, tap water, industrial water, pure water or the like can be used. Further, by using an aqueous solution having a pH of 5 to 10 containing at least any one of inorganic alkaline compounds selected from alkali metal carbonates, alkali metal phosphates, and alkali metal silicates as a micelle removal solution, thinning treatment is performed. The components of the etching resist layer insolubilized with the liquid are easily redispersed. When the pH of the micelle removal solution is less than 5, the components of the etching resist layer may aggregate to form insoluble sludge and adhere to the surface of the thinned etching resist layer. On the other hand, if the pH of the micelle removal solution exceeds 10, the etching resist layer may be excessively dissolved and diffused, and film thickness unevenness may easily occur in the surface. In addition, the pH of the micelle removal solution can be adjusted using sulfuric acid, phosphoric acid, hydrochloric acid, or the like.

The spray conditions in the micelle removal process will be described. The spray conditions (temperature, time, spray pressure) are appropriately adjusted according to the dissolution rate of the etching resist layer to be thinned. Specifically, the treatment temperature is preferably 10 to 50 ° C, more preferably 15 to 35 ° C. The spray pressure is preferably 0.01 to 0.5 MPa, more preferably 0.1 to 0.3 MPa. The supply flow rate of the micelle removal liquid is preferably 0.030 to 1.0 L / min, more preferably 0.050 to 1.0 L / min, and more preferably 0.10 to 1.0 L / min per 1 cm ^{2 of the} etching resist layer. Further preferred. When the supply flow rate is within this range, the micelles can be removed substantially uniformly in the surface without leaving insoluble components on the surface of the etching resist layer after thinning. When the supply flow rate per 1 cm ^{2 of the} etching resist layer is less than 0.030 L / min, insoluble dissolution of the components of the insolubilized etching resist layer may occur. On the other hand, when the supply flow rate exceeds 1.0 L / min, parts such as a pump necessary for supply become enormous and a large-scale device may be required. Furthermore, when the supply amount exceeds 1.0 L / min, the effect on the dissolution and diffusion of the components of the etching resist layer may not change.

  After the micelle removal treatment, the etching resist layer that could not be removed and the thinning treatment solution remaining on the surface of the etching resist layer and the micelle removal solution can be washed away by a water washing treatment. As a method of washing with water, a spray method is preferable from the viewpoint of diffusion rate and liquid supply uniformity. As flush water, tap water, industrial water, pure water or the like can be used. Of these, it is preferable to use pure water. Pure water that is generally used for industrial purposes can be used.

  In the drying process, either hot air drying or room temperature ventilation drying can be used. Preferably, high-pressure air is supplied from an air gun or a blower, and a large amount of air is supplied from the air gun, and water remaining on the surface of the etching resist layer with an air knife. Drying method that blows away is good.

  As a developing method, a developer corresponding to the etching resist layer to be used is used, and spray is sprayed onto the surface of the circuit board to remove unnecessary portions of the etching resist layer. A dilute alkaline aqueous solution is used as the developer, and generally a 0.3 to 3 mass% sodium carbonate aqueous solution or potassium carbonate aqueous solution is used.

  The etching according to the present invention is a method for removing an exposed metal layer other than an etching resist layer formed by development. In the etching process, a method described in “Handbook of Printed Circuit Technology” (edited by Japan Printed Circuit Industry Association, published in 1987, published by Nikkan Kogyo Shimbun) can be used. The etching treatment solution may be one that can dissolve and remove the metal layer, and at least the etching resist layer has resistance. In general, when copper is used for the metal layer, a ferric chloride aqueous solution, a cupric chloride aqueous solution, or the like can be used.

  Exposure to the etching resist layer is performed by irradiating with actinic rays, reflection image exposure using a xenon lamp, high pressure mercury lamp, low pressure mercury lamp, ultra high pressure mercury lamp, UV fluorescent lamp as a light source, single-sided or double-sided contact exposure using a photomask, Proximity method, projection method, laser scanning exposure, and the like can be used. When performing scanning exposure, a laser light source such as a UV laser, a He—Ne laser, a He—Cd laser, an argon laser, a krypton ion laser, a ruby laser, a YAG laser, a nitrogen laser, a dye laser, or an excimer laser is used as an emission wavelength. Accordingly, the exposure can be performed by scanning exposure using SHG wavelength conversion or scanning exposure using a liquid crystal shutter or a micromirror array shutter.

  In the step (C1) of the circuit board manufacturing method (1) of the present invention, the metal on the inner wall at the time of exposing a part of the etching resist layer above the conduction hole from which the metal layer on the inner wall is removed in the step (E). It is preferable that the area ratio of a part of the exposure region with respect to the area of the conduction hole from which the layer is removed is 72 to 90%. When the area ratio is smaller than 72%, there are many unexposed portions of the resist pieces that are generated by breaking the etching resist layer on the conductive holes from which the metal layer on the inner wall is removed during the thinning process. The pieces are likely to adhere to the etching resist layer, which may cause an etching failure in the subsequent etching process. In addition, when the area ratio is larger than 90%, the etching resist layer on the conduction hole from which the metal layer on the inner wall is removed by the thinning process and the development process in the subsequent process cannot be removed. In some cases, the metal layer 1 on the inner wall cannot be removed.

  Further, the shape of the exposure region can be freely set such as a shape in which one or a plurality of various figures such as a circle, an ellipse, a quadrangle, and a pentagon formed at the exposure portion are arranged. FIG. 2 shows the etching of the upper part of the conduction hole (conduction hole 5 that changes to an insulation hole) from which the metal layer on the inner wall is removed by the step (E) in the step (C1) of the circuit board manufacturing method (1) of the present invention. An example of the figure when the shape of a part of the exposure region when part of the resist layer 4 is exposed is viewed from the upper side of the conduction hole 5 is shown. FIGS. 2A to 2E show an exposure in which an exposure portion 9 having various shapes such as a circle, an ellipse, a quadrangle, a pentagon, and a hexagon is arranged on the etching resist layer 4 on the conduction hole 5 that changes to an insulation hole. It is an example which shows the shape of a field. FIGS. 2F to H are examples showing the shape of an exposure area in which a plurality of exposure units 9 having various figures are arranged.

  In the process (C1) of the circuit board manufacturing methods (2) and (3) of the present invention, “a part of the etching resist layer above the conduction hole from which the metal layer on the inner wall is removed by the post-process (E)” The exposure area is other than the ring-shaped area that is concentric with the conduction hole and has an inner diameter smaller than the diameter of the conduction hole and an outer diameter larger than the diameter of the conduction hole. " “The conductive hole from which the metal layer on the inner wall is removed” is “the conductive hole 5 that changes to an insulating hole”. “Other than a ring-shaped region that is concentric with the conduction hole 5 that changes to an insulation hole and has an inner diameter that is smaller than the diameter of the conduction hole 5 that changes to an insulation hole and an outer diameter that is larger than the diameter of the conduction hole 5 that changes to an insulation hole As shown in FIG. 3A, the “region of” is a circle that is concentric with the conduction hole 5 that changes into an insulation hole, and that has a diameter smaller than the diameter of the conduction hole 5 (shown with a dotted line) that changes into an insulation hole. A circular outer region (etching resist layer) that is concentric with the inner region (graphic exposed portion 9) and the conductive hole 5 that changes into an insulating hole and has a diameter larger than the diameter of the conductive hole 5 that changes into an insulating hole. And the exposure unit 10).

  Among these regions, a circular diameter (diameter of the exposed portion 9 of the figure in FIG. 3A) that is concentric with the conduction hole 5 changing to an insulation hole and smaller than the diameter of the conduction hole 5 changing to an insulation hole. The inner diameter of the ring-shaped unexposed portion is preferably 85 to 95% with respect to the diameter of the conduction hole 5 that changes into an insulating hole. When the diameter is smaller than 85%, there are many unexposed portions of the resist piece that are generated by breaking the etching resist layer on the conduction hole from which the metal layer on the inner wall is removed during the thinning process. May easily adhere to the etching resist layer, which may cause etching failure in the subsequent etching process. When the diameter is larger than 95%, it becomes difficult to remove the etching resist layer on the conductive hole from which the inner wall metal layer is removed by the thinning process and the subsequent development process. It may be impossible to remove the layer.

  Also, the diameter of the circular shape (the diameter of the exposed portion 10 of the etching resist layer in FIG. 3A, the ring is concentric with the conduction hole 5 changing to an insulation hole and larger than the diameter of the conduction hole 5 changing to an insulation hole. The outer diameter of the unexposed portion is preferably 105 to 115% with respect to the diameter of the conduction hole 5 that changes into an insulating hole. When the diameter is smaller than 105%, it becomes difficult to remove the etching resist layer on the conductive hole from which the inner wall metal layer is removed by the thinning process and the subsequent development process. May not be able to be removed. When the diameter is larger than 115%, there are many unexposed portions of the resist piece generated by breaking the etching resist layer on the conduction hole from which the metal layer on the inner wall is removed during the thinning process. May easily adhere to the etching resist layer, which may cause etching failure in the subsequent etching process.

  EXAMPLES Hereinafter, although an Example demonstrates this invention further in detail, this invention is not limited to this Example.

(Examples 1 to 24)
<Process (A)>
A 4mmφ through-hole is opened in a copper-clad laminate in which 18μm thick copper foil (metal layer 1) is laminated on both sides of a glass base epoxy resin substrate (insulating substrate 3, area 250 × 340mm, thickness 1.6mm). After that, a copper plating process is performed to form a copper plating layer (metal layer 1) on the inner wall of the through hole, thereby forming a conduction hole 2, and an insulating substrate 3 having both sides of the metal layer 1 and the conduction hole 2 is prepared. did. A dry film resist (product name: AK4034, thickness: 40 μm) manufactured by Asahi Kasei E-Materials Co., Ltd. is heated by using a laminator for dry film resist on the insulating substrate 1 on which the metal layers 1 and the conduction holes 2 are formed. The etching resist layer 4 was formed by pressure bonding.

<Process (C1)>
Next, a part of the etching resist layer 4 above the conductive hole (the conductive hole 5 that changes to the insulating hole) from which the metal layer on the inner wall is removed in the subsequent step (E) is exposed in the shape shown in Table 1. As described above, contact exposure was performed using a photomask so that the etching resist layer other than the region where the circuit was formed was exposed in the subsequent step (E). The exposure shape at the time of exposing a part of the etching resist layer 4 above the conductive hole 5 that changes to the insulating hole, and the area ratio of the exposed portion 9 of the figure with respect to the area of the conductive hole 5 that changes to the insulating hole (exposure to the conductive hole) Table 1 shows the area ratio of parts. In addition, the positional relationship between each exposure shape in Table 1 and the conduction hole 5 that changes to an insulating hole is arranged in the same positional relationship as each exposure shape shown in FIG.

<Process (B)>
Next, after peeling off the carrier film, the film is thinned with respect to the unexposed portion of the etching resist layer 4 by immersing in a 10% by mass aqueous sodium hydrogen carbonate solution (thinning solution, liquid temperature: 25 ° C.) for 30 seconds. Processed. Thereafter, a micelle removal process, a water washing process, and a drying process were performed to reduce the thickness of the etching resist layer 4 in the circuit formation portion, and at the same time, the etching resist layer 4 above the conduction hole 5 that changed to an insulating hole was removed. Table 1 shows the removal rate of the etching resist layer 4 on the conduction holes 5 that changes into insulating holes (etching resist layer removal rate on the conduction holes). In Examples 1 to 24, the etching resist layer 4 on the conduction hole 5 that changed to an insulating hole could be removed by 100%.

<Process (C2)>
Next, the circuit formation part has a pattern with a line and space of 50 μm, and the upper part of the conduction hole (the conduction hole 5 that changes to the insulation hole) from which the metal layer on the inner wall is removed in the subsequent etching process. Adhesion exposure was performed using a photomask in which the upper portion of the etching resist layer 4 was not exposed.

<Process (D)>
Next, the unexposed portion of the etching resist layer 4 is removed by performing a development process for 36 seconds using a 1% by mass aqueous sodium carbonate solution (developer, liquid temperature 30 ° C., spray pressure 0.15 MPa). A portion of the metal layer 1 removed by etching in the step (E) of the step was exposed from the etching resist layer 4.

<Process E>
Next, the metal layer 1 exposed from the etching resist layer 4 was removed by etching with a ferric chloride solution (etching solution, liquid temperature 40 ° C., spray pressure 0.20 MPa). Next, the remaining etching resist layer 4 was removed with a 3 mass% sodium hydroxide solution at 40 ° C. to produce a circuit board of the present invention. As a result of observing the obtained metal pattern with an optical microscope, it was found that the short circuit of the circuit portion caused by adhesion of resist pieces and the metal in the insulating hole in the line and space 50 μm portion and the 4 mmφ insulating hole sparsely present in the surface Etching failure due to insufficient removal did not occur, and a circuit board having a good metal pattern, insulating holes 8 and conduction holes 2 could be obtained.

(Examples 25-33)
<Process (A)>
A 4mmφ through-hole is opened in a copper-clad laminate in which 18μm thick copper foil (metal layer 1) is laminated on both sides of a glass base epoxy resin substrate (insulating substrate 3, area 250 × 340mm, thickness 1.6mm). After that, a copper plating process is performed to form a copper plating layer (metal layer 1) on the inner wall of the through hole, thereby forming a conduction hole 2, and an insulating substrate 3 having both sides of the metal layer 1 and the conduction hole 2 is prepared. did. A dry film resist (product name: AK4034, thickness: 40 μm) manufactured by Asahi Kasei E-Materials Co., Ltd. is heated by using a laminator for dry film resist on the insulating substrate 1 on which the metal layers 1 and the conduction holes 2 are formed. The etching resist layer 4 was formed by pressure bonding.

<Process (C1)>
Next, of the etching resist layer 4 above the conductive hole (conductive hole 5 that changes to an insulating hole) from which the metal layer on the inner wall is removed in the subsequent step (E), concentric with the conductive hole 5 that changes to an insulating hole. So that an area other than the ring-shaped area consisting of an inner diameter smaller than the diameter of the conduction hole 5 changing to an insulation hole and an outer diameter larger than the diameter of the conduction hole 5 changing to an insulation hole is exposed. Adhesion exposure was performed using a photomask so that the etching resist layer other than the region where the circuit was formed was exposed in the subsequent step (E). At this time, photomasks having different ratios of the diameters of the ring-shaped unexposed portion inner diameter and the ring-shaped unexposed portion outer diameter with respect to the conduction hole 5 changing to an insulating hole were used. The ratio of the outer diameter of the ring-shaped region (the diameter of the exposed portion 10 of the etching resist layer in FIG. 3A) to the diameter of the conduction hole 5 that changes to the insulating hole of the used photomask (the outer diameter of the ring-shaped unexposed portion) The ratio (diameter ratio of the inner diameter of the ring-shaped unexposed portion) of the ring-shaped region (diameter of the exposed portion 9 of the figure in FIG. 3A) to the diameter of the conduction hole 5 that changes to the insulating hole is expressed. It was shown in 2.

<Process (B)>
Next, after peeling off the carrier film, the film is thinned with respect to the unexposed portion of the etching resist layer 4 by immersing in a 10% by mass aqueous sodium hydrogen carbonate solution (thinning solution, liquid temperature: 25 ° C.) for 30 seconds. Processed. Thereafter, the micelle removal process, the water washing process, and the drying process were performed to reduce the thickness of the etching resist layer 4 in the circuit forming portion, and at the same time, the etching resist layer 4 above the conduction hole 5 that changed to an insulating hole was removed. Table 2 shows the removal rate of the etching resist layer 4 on the conduction hole 5 (the removal rate of the etching resist layer on the conduction hole) that changes to the insulating hole. In Examples 25 to 33, the etching resist layer 4 on the conduction hole 5 that changed to an insulating hole could be removed 100%.

<Process (C2)>
Next, the circuit formation part has a pattern with a line and space of 50 μm, and the upper part of the conduction hole (the conduction hole 5 that changes to the insulation hole) from which the metal layer on the inner wall is removed in the subsequent etching process. Adhesion exposure was performed using a photomask in which the upper portion of the etching resist layer 4 was not exposed.

<Process (D)>
Next, the unexposed portion of the etching resist layer 4 is removed by performing a development process for 36 seconds using a 1% by mass aqueous sodium carbonate solution (developer, liquid temperature 30 ° C., spray pressure 0.15 MPa). A portion of the metal layer 1 removed by etching in the step (E) of the step was exposed from the etching resist layer 4.

<Process E>
Next, the metal layer 1 exposed from the etching resist layer 4 was removed by etching with a ferric chloride solution (etching solution, liquid temperature 40 ° C., spray pressure 0.20 MPa). Next, the remaining etching resist layer 4 was removed with a 3 mass% sodium hydroxide solution at 40 ° C. to produce a circuit board of the present invention. As a result of observing the obtained metal pattern with an optical microscope, it was found that the short circuit of the circuit portion caused by adhesion of resist pieces and the metal in the insulating hole in the line and space 50 μm portion and the 4 mmφ insulating hole sparsely present in the surface Etching failure due to insufficient removal did not occur, and a circuit board having a good metal pattern, insulating holes 8 and conduction holes 2 could be obtained.

(Examples 34 to 49)
<Process (A)>
A 4mmφ through-hole is opened in a copper-clad laminate in which 18μm thick copper foil (metal layer 1) is laminated on both sides of a glass base epoxy resin substrate (insulating substrate 3, area 250 × 340mm, thickness 1.6mm). After that, a copper plating process is performed to form a copper plating layer (metal layer 1) on the inner wall of the through hole, thereby forming a conduction hole 2, and an insulating substrate 3 having both sides of the metal layer 1 and the conduction hole 2 is prepared. did. A dry film resist (product name: AK4034, thickness: 40 μm) manufactured by Asahi Kasei E-Materials Co., Ltd. is heated by using a laminator for dry film resist on the insulating substrate 1 on which the metal layers 1 and the conduction holes 2 are formed. The etching resist layer 4 was formed by pressure bonding.

<Process (C1)>
Next, a part of the etching resist layer 4 above the conductive hole (the conductive hole 5 that changes to the insulating hole) from which the metal layer on the inner wall is removed in the subsequent step (E) is exposed in the shape shown in Table 3. As described above, contact exposure was performed using a photomask so that the etching resist layer other than the region where the circuit was formed was exposed in the subsequent step (E). The exposure shape at the time of exposing a part of the etching resist layer 4 above the conductive hole 5 that changes to the insulating hole, and the area ratio of the exposed portion 9 of the figure with respect to the area of the conductive hole 5 that changes to the insulating hole (exposure to the conductive hole) Table 3 shows the area ratio of parts. In addition, the positional relationship between each exposure shape in Table 3 and the conduction hole 5 that changes to an insulating hole is arranged in the same positional relationship as each exposure shape shown in FIG.

<Process (B)>
Next, after peeling off the carrier film, the film is thinned with respect to the unexposed portion of the etching resist layer 4 by immersing in a 10% by mass aqueous sodium hydrogen carbonate solution (thinning solution, liquid temperature: 25 ° C.) for 30 seconds. Processed. Thereafter, a micelle removal process, a water washing process, and a drying process were performed to reduce the thickness of the etching resist layer 4 in the circuit formation portion, and at the same time, the etching resist layer 4 above the conduction hole 5 that changed to an insulating hole was removed. Table 3 shows the removal rate of the etching resist layer 4 on the conduction hole 5 that changes into an insulation hole (etching resist layer removal rate on the conduction hole).

<Process (C2)>
Next, the circuit formation part has a pattern with a line and space of 50 μm, and the upper part of the conduction hole (the conduction hole 5 that changes to the insulation hole) from which the metal layer on the inner wall is removed in the subsequent etching process. Adhesion exposure was performed using a photomask in which the upper portion of the etching resist layer 4 was not exposed.

<Process (D)>
Next, the unexposed portion of the etching resist layer 4 is removed by performing a development process for 36 seconds using a 1% by mass aqueous sodium carbonate solution (developer, liquid temperature 30 ° C., spray pressure 0.15 MPa). A portion of the metal layer 1 removed by etching in the step (E) of the step was exposed from the etching resist layer 4.

<Process E>
Next, the metal layer 1 exposed from the etching resist layer 4 was removed by etching with a ferric chloride solution (etching solution, liquid temperature 40 ° C., spray pressure 0.20 MPa). Next, the remaining etching resist layer 4 was removed with a 3 mass% sodium hydroxide solution at 40 ° C. to produce a circuit board of the present invention. The obtained metal pattern was observed with an optical microscope, and the number of etching defects due to short circuit in the circuit part caused by adhesion of resist pieces, which was confirmed in the sparsely line-and-space part of 50 μm, is shown in Table 3. It was.

(Examples 50 to 58)
<Process (A)>
A 4mmφ through-hole is opened in a copper-clad laminate in which 18μm thick copper foil (metal layer 1) is laminated on both sides of a glass base epoxy resin substrate (insulating substrate 3, area 250 × 340mm, thickness 1.6mm). After that, a copper plating process is performed to form a copper plating layer (metal layer 1) on the inner wall of the through hole, thereby forming a conduction hole 2, and an insulating substrate 3 having both sides of the metal layer 1 and the conduction hole 2 is prepared. did. A dry film resist (product name: AK4034, thickness: 40 μm) manufactured by Asahi Kasei E-Materials Co., Ltd. is heated by using a laminator for dry film resist on the insulating substrate 1 on which the metal layers 1 and the conduction holes 2 are formed. The etching resist layer 4 was formed by pressure bonding.

<Process (C1)>
Next, of the etching resist layer 4 above the conductive hole (conductive hole 5 that changes to an insulating hole) from which the metal layer on the inner wall is removed in the subsequent step (E), concentric with the conductive hole 5 that changes to an insulating hole. So that an area other than the ring-shaped area consisting of an inner diameter smaller than the diameter of the conduction hole 5 changing to an insulation hole and an outer diameter larger than the diameter of the conduction hole 5 changing to an insulation hole is exposed. Adhesion exposure was performed using a photomask so that the etching resist layer other than the region where the circuit was formed was exposed in the subsequent step (E). At this time, photomasks having different ratios of the diameters of the ring-shaped unexposed portion inner diameter and the ring-shaped unexposed portion outer diameter with respect to the conduction hole 5 changing to an insulating hole were used. The ratio of the outer diameter of the ring-shaped region (the diameter of the exposed portion 10 of the etching resist layer in FIG. 3A) to the diameter of the conduction hole 5 that changes to the insulating hole of the used photomask (the outer diameter of the ring-shaped unexposed portion) The ratio (diameter ratio of the inner diameter of the ring-shaped unexposed portion) of the ring-shaped region (diameter of the exposed portion 9 of the figure in FIG. 3A) to the diameter of the conduction hole 5 that changes to the insulating hole is expressed. This is shown in FIG.

<Process (B)>
Next, after peeling off the carrier film, the film is thinned with respect to the unexposed portion of the etching resist layer 4 by immersing in a 10% by mass aqueous sodium hydrogen carbonate solution (thinning solution, liquid temperature: 25 ° C.) for 30 seconds. Processed. Thereafter, the micelle removal process, the water washing process, and the drying process were performed to reduce the thickness of the etching resist layer 4 in the circuit forming portion, and at the same time, the etching resist layer 4 above the conduction hole 5 that changed to an insulating hole was removed. Table 4 shows the removal rate of the etching resist layer 4 on the conduction hole 5 that changes into an insulation hole (etching resist layer removal rate on the conduction hole).

<Process (C2)>
Next, the circuit formation part has a pattern with a line and space of 50 μm, and the upper part of the conduction hole (the conduction hole 5 that changes to the insulation hole) from which the metal layer on the inner wall is removed in the subsequent etching process. Adhesion exposure was performed using a photomask in which the upper portion of the etching resist layer 4 was not exposed.

<Process (D)>
Next, the unexposed portion of the etching resist layer 4 is removed by performing a development process for 36 seconds using a 1% by mass aqueous sodium carbonate solution (developer, liquid temperature 30 ° C., spray pressure 0.15 MPa). A portion of the metal layer 1 removed by etching in the step (E) of the step was exposed from the etching resist layer 4.

<Process E>
Next, the metal layer 1 exposed from the etching resist layer 4 was removed by etching with a ferric chloride solution (etching solution, liquid temperature 40 ° C., spray pressure 0.20 MPa). Next, the remaining etching resist layer 4 was removed with a 3 mass% sodium hydroxide solution at 40 ° C. to produce a circuit board of the present invention. The obtained metal pattern was observed with an optical microscope, and the number of defective etching due to short-circuiting of the circuit portion caused by the adhesion of the resist piece, which was confirmed in the sparsely existing line and space of 50 μm, is shown in Table 4. It was.

(Comparative Example 1)
In the step (C), the same steps as those in Examples 34 to 49 are performed except that the etching resist layer 4 above the conduction hole (the conduction hole 5 that changes to the insulation hole) from which the metal layer on the inner wall is removed is not exposed. After that, the circuit board of Comparative Example 1 was produced. When the obtained metal pattern was observed with an optical microscope, a large number of etching defects due to short-circuiting of the circuit portion due to adhesion of resist pieces occurred in the line and space 50 μm portions sparsely present in the plane.

(Comparative Example 2)
Steps similar to those in Examples 34 to 49, except that in step (C), the entire surface of the etching resist layer 4 above the conduction hole (conduction hole 5 that changes into an insulation hole) from which the metal layer on the inner wall is removed is exposed. Then, the circuit board of Comparative Example 2 was produced. When the obtained circuit board was observed with an optical microscope, no etching resist layer 4 on the conduction hole from which the metal layer on the inner wall was removed could be removed.

  In Comparative Example 1, the etching resist layer 4 on the conduction hole from which the metal layer on the inner wall is removed (the conduction hole 5 that changes to the insulation hole) can be effectively removed, but the circuit is formed by adhesion of the resist pieces generated by the removal. Many etching defects occur in the portion. Further, in Comparative Example 2, since the etching resist layer 4 on the conduction hole (the conduction hole 5 that changes to the insulation hole) from which the metal layer on the inner wall is removed cannot be removed, the insulation hole can be produced. It will disappear.

  On the other hand, in Examples 34 to 49, a part of the etching resist layer 4 above the conductive hole (the conductive hole 5 that changes to the insulating hole) from which the metal layer on the inner wall was removed in the step (C1) was exposed. By this, the etching resist layer 4 on the conduction hole (the conduction hole 5 that changes to the insulating hole) from which the metal layer on the inner wall is removed can be effectively removed, and the circuit formation portion of the circuit formation portion due to the adhesion of the resist piece generated by the removal can be removed. Since etching defects can be effectively prevented, the metal layer 1 formed on both surfaces of the insulating substrate 3, the conduction hole 2 in which the metal layer is formed on the inner wall, and the insulating hole 8 in which the metal layer is not formed on the inner wall. It is effective as a method for manufacturing a circuit board having Furthermore, in Examples 1-24, the exposure area | region at the time of exposing a part of etching resist layer 4 of the conduction | electrical_connection hole (conduction hole 5 changed into an insulation hole) from which the metal layer of an inner wall is removed in process (C1) The etching resist layer 4 on the conduction hole (the conduction hole 5 that changes to the insulation hole) from which the metal layer on the inner wall is removed can be more effectively removed by setting the ratio of 72 to 90% with respect to the area of the conduction hole. In addition, since it is possible to more effectively prevent the etching failure of the circuit forming portion due to the adhesion of the resist piece generated by the removal, the metal layer 1 is formed on both surfaces of the insulating substrate 3 and the metal layer is formed on the inner wall. It is more effective as a method of manufacturing a circuit board having the conductive hole 2 and the insulating hole 8 in which the metal layer is not formed on the inner wall.

  In Examples 50 to 58, the exposure region for a part of the etching resist layer above the conduction hole from which the metal layer on the inner wall is removed in the step (C1) is concentric with the conduction hole and is smaller than the diameter of the conduction hole. By using a region other than the ring-shaped region having an inner diameter and an outer diameter larger than the diameter of the conduction hole, the metal layer on the inner wall is removed as compared with Comparative Example 2 on the conduction hole (conduction hole 5 that changes to an insulation hole). Since the etching resist layer 4 can be effectively removed, and the etching failure of the circuit forming portion due to the adhesion of the resist pieces generated by the removal can be effectively prevented as compared with the comparative example 1, both surfaces of the insulating substrate 3 can be prevented. It is effective as a method for producing a circuit board having the metal layer 1 formed on the inner surface, the conduction hole 2 having a metal layer formed on the inner wall, and the insulating hole 8 having no metal layer formed on the inner wall. Further, in Examples 25 to 33, the outer diameter of the ring-shaped unexposed region in Examples 50 to 58 is 105 to 115% with respect to the diameter of the conduction hole, and the inner diameter is 85 to 95 with respect to the diameter of the conduction hole. %, The etching resist layer 4 on the conductive hole from which the metal layer on the inner wall is removed (the conductive hole 5 that changes to an insulating hole) can be more effectively removed, and the resist pieces generated by the removal can be adhered. Since it is possible to more effectively prevent the etching failure of the circuit forming portion due to the metal layer 1, the metal layer 1 formed on both surfaces of the insulating substrate 3, the conduction hole 2 formed with the metal layer on the inner wall, and the metal layer formed on the inner wall This is more effective as a method of manufacturing a circuit board having the insulating holes 8 that are not formed.

  The present invention is widely used for producing a fine metal pattern using a subtractive method. For example, it can be used as a circuit board manufacturing method.

DESCRIPTION OF SYMBOLS 1 Metal layer 2 Conductive hole 3 Insulating substrate 4 Etching resist layer 5 Conductive hole which changes into an insulating hole 6 Actinic ray 7 Photomask 8 Insulating hole 9 Exposed part of figure 10 Exposed part of etching resist layer

Claims (3)

In a method of manufacturing a circuit board having a metal layer formed on both surfaces of an insulating substrate, a conduction hole in which a metal layer is formed on the inner wall, and an insulating hole in which the metal layer is not formed on the inner wall,
(A) a step in which an etching resist layer is formed on both sides of an insulating substrate in which metal layers on both sides and conductive holes are formed;
(C1) A part of the etching resist layer above the conduction hole from which the metal layer on the inner wall is removed in the subsequent step (E) and the etching resist layer other than the region where the circuit is formed in the subsequent step (E) are exposed. Process
(B) The step of thinning the unexposed portion of the etching resist layer with the thinning treatment solution (C2) The step of exposing the etching resist layer other than the region to be developed and removed in the subsequent step (D),
(D) a step in which an etching resist layer in an unexposed portion is removed by a developer and a part of the metal layer is exposed;
(E) a step of removing the metal layer exposed from the etching resist layer with an etching treatment liquid;
A circuit board manufacturing method comprising:   Of the exposure region in the step (C1), the exposure region for a part of the etching resist layer on the conductive hole where the metal layer on the inner wall is removed in the subsequent step (E) is concentric with the conductive hole. 2. The method of manufacturing a circuit board according to claim 1, wherein the circuit board is in a region other than a ring-shaped region having an inner diameter smaller than the diameter of the first electrode and an outer diameter larger than the diameter of the conduction hole.   3. The method of manufacturing a circuit board according to claim 2, wherein the outer diameter of the ring-shaped region is 105 to 115% with respect to the diameter of the conduction hole, and the inner diameter is 85 to 95% with respect to the diameter of the conduction hole.