JP2015019489A - Drive controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a switching loss by applying, in appropriate timing, a gate drive pulse to a semiconductor element in which a transistor structure and a diode structure are formed in the same semiconductor substrate.SOLUTION: A pulse control part 27 of drive ICs 24A and 24B, when determining that a current flows in semiconductor elements 1A and 1B in a forward direction of a diode element 6 during an H level of PWM signals FH and FL when electric conduction is switched between upper and lower arms, brings gate drive signals SGH and SGL to an H level from a time lapse point of a first time T1 to a time lapse point of a second time T2 by using a falling time point of the PWM signals FH and FL as a start point (pulse control). The larger the current flows in the semiconductor elements 1A and 1B during the H level of the PWM signals FH and FL, the longer a pulse width Tw of the gate drive pulse is set.

Description

  The present invention relates to a drive control device for a semiconductor element in which an insulated gate transistor structure and a diode structure are formed on the same semiconductor substrate.

  Transistor element and diode element such as RC-IGBT, MOS transistor, diode with MOS gate, etc. are formed on the same semiconductor substrate, and transistor element energization electrode (collector, emitter or drain, source) and diode element energization electrode A semiconductor element having a common electrode (cathode, anode) is known (see Non-Patent Document 1). When such a semiconductor element is used as a switching element in a power conversion device such as an inverter or a converter, it is necessary to reduce switching loss.

  The power conversion device has a half-bridge circuit as a basic configuration, and performs AC-DC voltage conversion and DC-AC voltage conversion by complementarily turning on and off the semiconductor elements of the upper and lower arms, or boosts and steps down the input voltage. In this half-bridge circuit, in order to prevent a power supply short circuit (arm short circuit), a dead time for simultaneously turning off the upper and lower semiconductor elements is provided.

  During the dead time, the load current flows back to the diode element of one of the semiconductor elements. When the other semiconductor element is turned on after the dead time is over, the load current is switched from the diode element to the other semiconductor element. At this time, a reverse recovery current flows due to the emission of carriers accumulated in the diode element. This reverse recovery current increases switching loss and causes noise.

  On the other hand, Non-Patent Document 1 discloses a method of applying a positive gate drive voltage to one semiconductor element slightly before the other semiconductor element is turned on. According to this method, the hole current decreases as the electron current of the semiconductor element increases, hole injection is suppressed, and the reverse recovery current can be reduced.

Zhenxue Xu, Bo Zhang and Alex Q. huang, "Experimental Demonstration of the MOS Controlled Diode (MCD)", IEEE 2000, Vol.2, p.1144-1148

  The method described in Non-Patent Document 1 that suppresses carrier injection by temporarily applying a gate drive voltage (gate drive pulse) to a semiconductor element is effective in reducing the reverse recovery current. However, since it is necessary to apply a gate drive pulse at the time of switching current between two semiconductor elements constituting the half-bridge circuit, an arm short circuit occurs when the application timing is slightly delayed. Conversely, if the application timing is early, the amount of holes injected again after the application of the gate drive pulse is increased, and the effect of reducing the reverse recovery current is reduced. Non-Patent Document 1 does not show the specific application timing or pulse width of the gate drive pulse. In order to put this method into practical use, it is necessary to establish means for applying such a gate drive pulse.

  The present invention has been made in view of the above circumstances, and its purpose is to perform switching by applying a gate drive pulse at an appropriate timing to a semiconductor element in which a transistor structure and a diode structure are formed on the same semiconductor substrate. An object of the present invention is to provide a drive control device that can reduce loss.

  According to a first aspect of the present invention, an insulated gate transistor structure to which a gate drive voltage is applied and a diode structure are formed on the same semiconductor substrate. The drive control of the semiconductor element made into the common electrode is performed. The drive control device includes: a current detection unit that outputs a current detection signal corresponding to a current flowing through the semiconductor element; a control unit that outputs a gate drive signal; a drive circuit that inputs the gate drive signal and outputs a gate drive voltage; It has.

  If the control means determines that the current flows in the forward direction of the diode structure in the semiconductor element during the period when the ON command signal for the semiconductor element is input based on the current detection signal, the subsequent OFF command signal A gate drive signal for instructing application of the gate drive voltage is output from the preset time point of the first time to the time point of the second time. The drive circuit inputs this gate drive signal and outputs a pulsed gate drive voltage (gate drive pulse).

  The semiconductor element to be driven has a common gate structure for the transistor structure and the diode structure. When energization is switched between the upper and lower arms, for example, when a control means applies a gate drive voltage to the one semiconductor element in a state where current flows in the diode structure of one semiconductor element, holes accumulated in the diode structure Decreases, and the effect of reducing the reverse recovery current occurs.

  However, for a semiconductor element to which an off command signal is input, a device current (transistor current) flows in the reverse direction when a device current (for example, a diode current) flows in the forward direction of the diode structure. In some cases, the waveform of the gate drive voltage when a gate drive pulse is applied is different. For example, in the former case, since a steep current change, voltage change and mirror period do not occur, the rise time and fall time of the gate drive voltage are shortened (or can be shortened). This reduces the delay and variation of the gate drive pulse. On the other hand, in the latter case, since a steep current change, voltage change, and mirror period occur, the delay and variation of the gate drive pulse increase. The drive control device applies a gate drive pulse only when a current flows through the semiconductor element in the forward direction of the diode structure, so control based on small delays and variations in the former case is possible, and the application timing Can improve the accuracy.

  For example, the semiconductor element is arranged in series on the high potential side (high side) and the low potential side (low side) across the output terminal to constitute a half-bridge circuit. The drive control device inputs at least one command signal among high-side and low-side command signals (for example, PWM signals) that change complementarily, and applies a gate drive voltage to at least one side semiconductor element. This command signal has a dead time at the time of switching. Since the dead time is a fixed time, the time from the input of the off command signal on one side to the input of the on command signal on the other side is accurately guaranteed.

  The control means measures the delay and variation described above in advance, grasps the dead time, and sets the time width between the first time and the second time during the period when the ON command signal for the semiconductor element is input. The value is controlled according to the magnitude of the current flowing in the current. As a result, it is possible to accurately set the timing of the gate drive signal necessary for applying the gate drive voltage at a desired timing, that is, the first time and the second time, starting from the input time point of the off command signal. Become.

  As a result, the time from when the gate drive pulse is applied to one semiconductor element until the reverse recovery current starts to flow, for example, the time when carriers (holes) are injected again into the diode structure after the application of the gate drive pulse (carrier) The reinjection time) can be accurately controlled. Therefore, according to this means, the reinjection time can be controlled to be short while preventing an arm short circuit, so that the reverse recovery current is reduced and the switching loss can be reduced. In addition, since the control means can apply the gate drive signal using the off command signal as a reference timing, a separate timing signal is not required, and replacement from a conventionally used drive control device is facilitated.

  The means described in claim 2 is an example of the half-bridge circuit described above. After an off command signal is input in a state where a current flows in the forward direction of the diode structure to the semiconductor element, an on command signal is input to the other semiconductor element after a certain dead time. , When the gate drive voltage is cut off after the second time has elapsed, and when the current (reverse recovery current) exceeding the current flowing in the one semiconductor element starts flowing in the transistor structure of the other semiconductor element The first time and the second time are set so that the time width is greater than zero and less than or equal to a predetermined allowable injection time.

  This time width is the above-described carrier reinjection time. By setting this time larger than zero, it is possible to prevent a short-circuit current from flowing through the half-bridge circuit. In addition, by setting this time to be equal to or less than the predetermined allowable injection time, the reverse recovery current can be limited to a magnitude corresponding to the allowable injection time, and switching loss can be reduced.

  According to the means described in claim 3, the time width between the first time and the second time is longer as the current flowing in the semiconductor element is larger during the period when the ON command signal to the semiconductor element is input. It is set to become. This is because the larger the current, the longer the time from when the OFF command signal is input until the reverse recovery current starts to flow. As a result, an increase in reinjection time can be suppressed regardless of the magnitude of current, and switching loss can be reduced.

  According to the means described in claim 4, the gate drive voltage based on the gate drive signal output from the elapse of the first time to the elapse of the second time increases monotonously or monotonically according to the gate drive capability of the drive circuit. As a decrease, the first time and the second time are set.

  The gate drive pulse applied after the input of the off command signal has an effect of reducing holes accumulated in the diode structure, and has no effect of energizing or disconnecting the semiconductor element. For this reason, the voltage between the current-carrying terminals of the transistor elements (between CE and DS) does not change, and the mirror period does not occur. Further, during the application period of the gate drive pulse, a current continues to flow in the semiconductor element in the forward direction of the diode structure, so that a special gate drive voltage having a protective action in preparation for an arm short circuit is not necessary. Therefore, the carrier reinjection time can be controlled to a desired value by setting the gate drive signal so that the gate drive voltage monotonously increases or decreases.

  According to the means described in claim 5, it is assumed that the mirror period does not occur in the gate drive voltage based on the gate drive signal output from the elapse of the first time to the elapse of the second time. Two hours are set. As a result, an increase in the carrier reinjection time can be suppressed as compared with the case where the gate drive signal is set assuming the occurrence of the mirror period.

  According to a sixth aspect of the present invention, the drive circuit outputs a gate drive voltage while maintaining a constant gate drive capability when the gate drive signal changes at the elapse of the first time. In driving to energize a semiconductor element, a method of reducing a short-circuit current when the semiconductor element has a short-circuit fault is used by temporarily keeping the gate drive voltage at an intermediate voltage in the course of increasing the gate drive voltage. . However, if a gate drive pulse is applied at an appropriate timing, a short-circuit current will not flow. According to this means, by maintaining a constant gate drive capability and eliminating unnecessary intermediate voltages, variations in the rise time of the gate drive voltage can be reduced and the reinjection time can be accurately controlled.

  According to the means described in claim 7, when the gate drive signal changes at the elapse of the first time and at the elapse of the second time, the drive circuit has a higher drive than when the semiconductor element is disconnected. The gate drive voltage is output with the ability. This is because, during the application period of the gate drive pulse, current continues to flow through the semiconductor element in the forward direction of the diode structure, so that a surge due to a steep current change or voltage change does not occur. Thereby, variations in the rise time and fall time of the gate drive voltage can be reduced, and the reinjection time can be accurately controlled.

The block diagram of the drive control system which shows one Embodiment of this invention Circuit diagram of main element and sense element Schematic longitudinal section of a semiconductor device Configuration diagram of drive circuit drive capacity switching circuit Block diagram of the pulse controller Configuration diagram of pulse start decision unit Voltage / current characteristics diagram of diode element in forward direction Waveform diagram related to Vf control and pulse control Diagram showing device current, gate drive voltage and carrier concentration in diode device Waveform diagram when the reinjection time is zero Diagram showing the relationship between reinjection time and switching loss Diagram showing the relationship between pulse width and switching loss Explanatory drawing of 1st time and 2nd time Operation explanatory diagram of pulse start decision unit Waveform diagram with and without mirror period Waveform diagram of gate drive voltage for different drive capabilities The figure which shows the modification of a current detection structure (1) FIG. 2 is a diagram showing a modification of the current detection configuration (2)

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drive control system shown in FIG. 1 is used in a power conversion device such as an inverter device that drives an inductive load such as a motor, or a converter device that includes an inductor and boosts / steps down a DC voltage. The semiconductor elements 1A and 1B, which are switching elements, are arranged in series between the high-potential side DC power supply line 2 and the low-potential side DC power supply line 3 with the output terminal Nt interposed therebetween to form the half-bridge circuit 4. doing.

  The semiconductor elements 1A and 1B having the same structure are reverse conducting IGBTs (RC-IGBTs) in which the insulated gate transistor element 5 and the diode element 6 are formed on the same semiconductor substrate. The energizing electrodes (collector and emitter) of the transistor element 5 and the energizing electrodes (cathode and anode) of the diode element 6 are common electrodes.

  In addition to the main element, a sense element including a transistor element 5s and a diode element 6s for supplying a minute current proportional to the current flowing through the main element is formed on the semiconductor substrate as shown in FIG. In FIG. 1, the main element and the sense element are simply shown. Sense resistors 7A and 7B are connected between the sense terminals S1 and S2 of the semiconductor elements 1A and 1B, respectively. The sense resistors 7A and 7B constitute current detection means together with a current detection unit 25 described later.

  As an example of the semiconductor elements 1A and 1B, FIG. 3 shows an RC-IGBT having a vertical structure. In the RC-IGBT of this embodiment, the transistor structure and the diode structure are provided on the same semiconductor substrate. The semiconductor substrate 8 is composed of an n− type silicon substrate. Although not shown, a guard ring is formed in the vicinity of the periphery of the element formation region of the semiconductor substrate 8 so as to surround the element formation region.

  A p-type base layer 9 is formed on the top surface portion of the semiconductor substrate 8. A plurality of trenches having a depth that reaches the semiconductor substrate 8 through the base layer 9 are formed in the base layer 9. Polysilicon is buried in the trench, whereby the gate electrode 10 having a trench structure is formed. A gate drive voltage is input to each gate electrode 10 through a common gate wiring 11. The gate electrodes 10 are provided in stripes at equal intervals in one direction along the surface layer portion of the base layer 9. Thereby, the base layer 9 is partitioned into a plurality of first regions 12 and a plurality of second regions 13 that are electrically separated from each other along the one direction. These first regions 12 and second regions 13 are alternately arranged, and the width of the second region 13 is wider than the width of the first region 12.

  In the surface layer portion of the first region 12, an n + -type emitter region 14 is formed adjacent to the gate electrode 10. An emitter electrode 15 is formed on the first region 12. The emitter electrode 15 is connected to the base layer 9 and the emitter region 14 in the first region 12. The first region 12 operates as a channel region of the transistor element 5 and also operates as an anode region of the diode element 6. That is, the emitter electrode 15 for the first region 12 becomes the emitter electrode of the transistor element 5 and the anode electrode of the diode element 6.

  The second region 13a provided above the collector region 16 (described later) is not connected to any electrode. A second region 13 b provided above the cathode region 17 (described later) is connected to the emitter electrode 15. Accordingly, only the second region 13 b provided above the cathode region 17 in the second region 13 operates as the anode region of the diode element 6. That is, the emitter electrode 15 becomes an anode electrode of the diode element 6 in the second region 13b.

  In the lower surface layer portion of the semiconductor substrate 8, a p + type collector region 16 is formed corresponding to a range (left side of the broken line) where the second region 13a is formed, and a range where the second region 13b is formed (broken line) N + type cathode region 17 is formed corresponding to the right side of FIG. The collector region 16 and the cathode region 17 are connected to the collector electrode 18. That is, the cathode electrode of the diode element 6 is in common with the collector electrode 18 of the transistor element 5. An n-type field stop layer 19 is formed between the semiconductor substrate 8 and the collector region 16 and the cathode region 17.

  In the drive control system shown in FIG. 1, a microcomputer 21 includes a PWM signal generation unit 22 that generates high-side and low-side PWM signals FH and FL of the half bridge circuit 4. The PWM signals FH and FL have a fixed dead time Td that is simultaneously at the L level (off command level). The PWM signals FH and FL are input to the drive ICs 24A and 24B via the photocouplers 23A and 23B, respectively. The on command signal referred to in the present invention is the PWM signals FH and FL having the H level (on command level), and the off command signal is the PWM signals FH and FL having the L level (off command level).

  The drive ICs 24A and 24B include a current detection unit 25, a Vf control unit 26, a pulse control unit 27, and a drive circuit 28, and operate when supplied with power supply voltages VDDA and VDDB (for example, 15V). Separate drive ICs 24A and 24B are provided for the high-side semiconductor element 1A and the low-side semiconductor element 1B, respectively. For this reason, the drive ICs 24A and 24B have a sufficient withstand voltage (that is, a withstand voltage according to the gate drive voltage) according to the power supply voltages VDDA and VDDB. Since the drive ICs 24A and 24B have the same configuration, the configuration of the drive IC 24B will be mainly described.

  The current detection unit 25 is a current detection unit that outputs a current detection signal (current polarity and magnitude) corresponding to the current flowing through the semiconductor element 1B based on the sense voltage VSL generated in the sense resistor 7B. The Vf control unit 26 and the pulse control unit 27 generate the gate drive signal SGL based on the PWM signal FL. The drive circuit 28 receives the gate drive signal SGL and outputs a gate drive voltage VGL.

  The Vf control unit 26 controls to cut off the gate drive voltage VGL when the current of the semiconductor element 1B flowing in the forward direction of the diode element 6 is equal to or greater than the current threshold It during the period in which the PWM signal FL is at the H level. I do. This control has the effect of reducing the conduction loss by lowering the voltage of the semiconductor element 1B (in the case of RC-IGBT, the forward voltage Vf of the diode element 6). In the following description, this is referred to as Vf control.

  The pulse control unit 27 performs pulse-shaped gate driving with reference to the falling edge of the PWM signal FL when a current in the forward direction of the diode element 6 flows through the semiconductor element 1B during the period in which the PWM signal FL is at the H level. The signal SGL is output. By this gate drive signal SGL, a pulsed gate drive voltage VGL (hereinafter referred to as a gate drive pulse) is applied to the gate of the semiconductor element 1B. This control has the effect of reducing the holes accumulated in the diode element 6 and reducing the reverse recovery current. In the following description, this is referred to as pulse control.

  The gate drive signal SGL generated by the Vf control unit 26 and the pulse control unit 27 is given to the gate of the semiconductor element 1B via the drive circuit 28. The drive circuit 28 can switch the gate drive capability in a plurality of ways as shown in FIG.

  The drive circuit 28 drives the gate by the MOS transistor 29 when turned on. The output voltage (A side) of the constant current drive amplifier 31 or the voltage of the floating ground FG (B side) is applied to the gate of the MOS transistor 29 via the changeover switch 30. In the former case, a normal driving capability is obtained, and in the latter case, a high driving capability is obtained. Further, the drive circuit 28 performs a protection operation against a short-circuit current during the driving in the case of a normal driving capability. Therefore, the constant current drive amplifier 31 temporarily keeps the gate drive voltage VGL at the intermediate voltage in the process of increasing the gate drive voltage VGL.

  The drive circuit 28 drives the gate by the MOS transistors 32 and 33 when turned off. When the changeover switch 34 is switched to the A side and driven only by the MOS transistor 32, the normal drive capability is obtained, and when the changeover switch 34 is switched to the B side and driven by the MOS transistors 32 and 33, high drive capability is obtained. The MOS transistor 33 has a lower on-resistance than the MOS transistor 32. The MOS transistor 33 is also used when the semiconductor element 1B is held in the off state.

  When a sharp change occurs in the current (element current) and voltage flowing in the semiconductor element 1B, such as when the PWM signal FL rises from the state where the current flows in the transistor element 5 at the rising edge of the PWM signal FL, a voltage surge occurs. In order to suppress the occurrence of this, it is switched to a normal driving capability. On the other hand, when there is no steep change in the device current or voltage as in pulse control, the driving capability is switched to high.

  Threshold setting circuits 35A, 36A, 37A are externally attached to the driving IC 24A. Threshold setting circuits 35B, 36B, and 37B are externally attached to the driving IC 24B. The threshold setting circuits 29A, 30A, 31A are configured with a floating ground FG equal to the emitter potential of the semiconductor element 1A as a reference potential. The threshold setting circuits 35A and 35B divide the voltages VDDA and VDDB by resistors R1 and R2 to generate a threshold voltage Vt. The threshold setting circuits 36A and 36B divide the voltages VDDA and VDDB by resistors R3 and R4 to generate a specified voltage Vm1. The threshold setting circuits 37A and 37B divide the voltages VDDA and VDDB by resistors R5 and R6 to generate a specified voltage Vm2.

  The threshold voltage Vt determines the magnitude of the current threshold It used in the Vf control unit 26. The characteristics of the forward voltage Vf with respect to the forward current If of the diode element 6 differ depending on the type of element (RC-IGBT, MOS transistor, etc.) and the breakdown voltage of the element. Therefore, the Vf control unit 26 selects an appropriate current threshold It based on the switching signal Sk and the threshold voltage Vt given from the outside.

  The specified voltage Vm1 determines the magnitude of the specified value Im1 used for determining whether to stop the Vf control. The specified voltage Vm2 determines the magnitude of the specified value Im2 used for determining whether or not to stop the pulse control. When the current is detected and when the gate drive voltages VGH and VGL are applied based on the polarity of the detected current, there is a possibility that the current polarity is reversed due to a delay in control. Therefore, the Vf control unit 26 stops the Vf control when the current detection value falls below the specified value Im1, and the pulse control unit 27 stops the pulse control when the current detection value falls below the specified value Im2.

The drive control device 38A is configured by the drive IC 24A and the sense resistor 7A described above, and the drive control device 38B is configured by the drive IC 24B and the sense resistor 7B.
Next, the operation of the drive control device 38B on the low side will be mainly described with reference to FIGS. The operation of the drive control device 38A on the high side is the same. First, Vf control will be briefly described. When a gate drive voltage is applied to the semiconductor elements 1A and 1B, which are RC-IGBTs, with a current flowing through the diode element 6, a channel is formed in the first region 12 and hole injection is suppressed. For this reason, as shown in FIG. 7, the forward voltage Vf of the diode element 6 through which the forward current If flows increases, and the conduction loss (Vf × If) of the diode element 6 increases.

  Therefore, when a current greater than or equal to the current threshold It flows through the diode element 6, the conduction loss can be reduced by cutting off the gate drive voltage. The current threshold It is substantially zero in the case of RC-IGBT, and is greater than zero in the case of a MOS transistor depending on the breakdown voltage or the like. When the RC-IGBT is driven, the switching signal Sk is switched to L level, for example, and when the MOS transistor is driven, the switching signal Sk is switched to H level, for example. When the switching signal Sk is at the H level, the Vf control unit 26 sets the current threshold It according to the threshold voltage Vt and executes the Vf control.

  FIG. 8 shows a case where the semiconductor element 1A is turned off and the semiconductor element 1B is turned on after the current flows from the output terminal Nt toward the load, and then the semiconductor element 1B is turned off and the semiconductor element 1A is turned on again. It is a waveform. From the top, the current of the semiconductor element 1A, the gate drive voltages VGH and VGL, the PWM signal FH, the gate drive signal SGL, and the PWM signal FL are shown. Vth is the threshold voltage of the semiconductor element 1A.

  The Vf control unit 26 of the drive IC 24B determines whether or not the detected current of the diode element 6 is equal to or greater than the current threshold It in the forward direction during the period when the PWM signal FL is at the H level (time t2 to t3). If it is determined that the detected current is equal to or greater than the current threshold It, an L level gate drive signal SGL is output as shown in FIG. As a result, the gate drive voltage VGL is cut off and the conduction loss is reduced.

  Next, pulse control will be described. In the pulse control, when the current flows through the diode element 6 of the semiconductor element 1B during the period in which the PWM signal FL is at the H level, after the PWM signal FL falls to the L level and before the reverse recovery current starts to flow, This is control for applying a gate drive pulse to the semiconductor element 1B. This is also the case when a current flows through the diode element 6 of the semiconductor element 1A during the period in which the PWM signal FH is at the H level, and the same applies after the PWM signal FH falls to the L level. As a result, carriers (holes) accumulated in the diode element 6 are reduced, so that an effect of reducing the reverse recovery current can be obtained.

  In FIG. 8, when the PWM signal FL falls to the L level (time t3), the pulse controller 27 indicates that a current is flowing through the diode element 6 of the semiconductor element 1B (the current detection value is equal to or greater than the specified value Im2). When the determination is made, the gate drive signal SGL is set to the H level from the time when the first time T1 has elapsed (time t4) to the time when the second time T2 has elapsed (time t6). By the above-described Vf control, the gate drive signal SGL is at the L level at the time of falling of the PWM signal FL.

  Even after the PWM signal FL falls to the L level, the pulse control unit 27 continues to determine whether or not a current flows through the diode element 6 of the semiconductor element 1B. When the current detection value falls below the specified value Im2, the pulse control unit 27 immediately returns the gate drive signal SGL to the L level even after the first time T1 has elapsed and before the second time T2 has elapsed.

  On the other hand, if the pulse control unit 27 determines that no current flows through the diode element 6 when the PWM signal FL falls to the L level, the pulse control unit 27 immediately maintains the gate drive signal SGL at the L level. That is, no gate drive pulse is applied.

  As shown in FIG. 8, when the energization is switched between the upper and lower arms, when the gate drive voltage VGH becomes equal to or higher than the threshold voltage Vth (time t9), the current flowing through the transistor element 5 of the semiconductor element 1A increases. Of the current flowing through the transistor element 5, the current exceeding the current flowing through the diode element 6 of the semiconductor element 1B is the reverse recovery current. In the drawing, hatching is shown (time t10 to t11). FIGS. 9 and 10 show a case where the load current (current flowing through the semiconductor elements 1A and 1B) is 100A and 200A.

  As shown in FIG. 9, when the gate drive voltage VGL (gate drive pulse) is applied, carriers in the diode element 6 of the semiconductor element 1B decrease, so that the carrier concentration decreases (time t5 to t8). When the application of the gate drive pulse is completed, carriers are injected again into the diode element 6, so that the carrier concentration increases. The time Tc (Tc1, Tc2) from the end of application of the gate drive pulse (time t8) until the reverse recovery current starts to flow (time t10) is the carrier reinjection time.

  The shorter the reinjection time Tc, the lower the carrier concentration accumulated in the diode element 6, and thus the reverse recovery current becomes smaller. As shown in FIG. 11, the switching loss decreases as the reinjection time Tc is shorter. Therefore, the reinjection time Tc is controlled to be equal to or less than the allowable injection time corresponding to the allowable reverse recovery current. FIG. 10 shows a case where the reinjection time Tc becomes zero. Actually, in order to prevent an arm short circuit, the reinjection time Tc is controlled to be equal to or longer than the short circuit margin time Tm (> 0).

  As shown in FIG. 9, the larger the load current, the later the time point (time t10) at which the reverse recovery current starts to flow. For this reason, when the application end point of the gate drive voltage VGL is fixed starting from the falling point of the PWM signal FL (time t8), the reinjection time becomes Tc1 when the load current is 100A, and reinjection when the load current is 200A. Time becomes Tc2 (> Tc1). That is, the larger the load current, the longer the reinjection time, and the reverse recovery current increases. Further, in order to sufficiently reduce the carrier concentration and reduce the switching loss, it is necessary to secure a sufficient width for reducing the carrier by securing a certain width of the gate drive pulse as shown in FIG. .

  For these reasons, the pulse control unit 27 controls the application timing of the gate drive voltage VGL according to the load current. The pulse control unit 27 sets the time width Tw between the first time T1 when the gate drive signal SGL is set to the H level and the second time T2 when the PWM signal FL is returned to the L level as the starting point. The value is set according to the magnitude of the current flowing in the diode element 6 during the H level period. Specifically, the longer time width is set as the current flowing through the diode element 6 during the period when the PWM signal FL is at the H level is larger.

  In the first time T1 and the second time T2, the application timing of the gate drive signal SGL and the actual gate drive voltage VGL are applied starting from the falling point of the PWM signal FL while changing the current flowing through the diode element 6 in various ways. The timing at which the reverse recovery current starts to flow and the timing at which the reverse recovery current starts to flow are set in advance. The first time T1 and the second time T2 are stored in the memory 39 described later in association with the current. Instead of the first time T1 and the second time T2, the first time T1 and the pulse width Tw (= T2−T1) may be stored.

  FIG. 5 is a block diagram of the pulse controller 27 for the drive IC 24B. The memory 39 receives the current detection signal and outputs the first time T1 and the second time T2 (or the first time T1 and the pulse width Tw) necessary for the pulse control. As shown in FIG. 13, the pulse start determination unit 40 generates a rising timing signal of the gate drive signal SGL from the PWM signal FL and the first time T1. The pulse width determination unit 41 generates a falling timing signal of the gate drive signal SGL from the PWM signal FL and the second time T2 (or pulse width Tw). The pulse generation unit 42 generates a gate drive signal SGL based on these timing signals and outputs it to the drive circuit 28.

  The pulse start determination unit 40 has a configuration shown in FIG. 6, for example. During the period when the PWM signal FL is at the H level, the MOS transistor 44 is turned on by the gate voltage via the buffer 43, so the voltage of the capacitor 45 is zero. When the PWM signal FL falls to the L level, the MOS transistor 44 is turned off and the capacitor 45 is charged by the constant current circuit 46. The comparator 47 compares the voltage of the capacitor 45 with a reference voltage corresponding to the first time T1, and outputs a timing signal. The pulse width determination unit 41 has the same configuration.

  FIG. 14 shows that the first time T1, that is, the reference voltage output from the memory 39 changes according to the current flowing in the diode element 6 during the period in which the PWM signal FL is at the H level, whereby the rise of the gate drive signal SGL. This shows how the timing signal changes. The memory 39 may store the first time T1 that is a constant value, and the read value may be changed according to the device current.

  The waveform of the gate drive voltage VGL when a gate drive pulse is applied differs between when the current flows through the diode element 6 and when the current flows through the transistor element 5 while the PWM signal FL is at the L level. . Therefore, in consideration of the following items (1) to (3), it is assumed that the gate drive voltage VGL monotonously increases or monotonously decreases according to the gate drive capability of the drive circuit 28. The second time T2 (or the first time T1 and the pulse width Tw) is set.

(1) Dead time Td
The dead time Td of the PWM signals FH and FL is a fixed time. Therefore, the time from when the PWM signal FL becomes L level until the PWM signal FH becomes H level and the time from when the PWM signal FH becomes L level until the PWM signal FL becomes H level are accurately guaranteed. ing. By utilizing this dead time Td, a gate drive pulse can be applied while preventing an arm short circuit.

(2) Mirror period When a current flows through the transistor element 5, the collector-emitter voltage changes when the gate drive voltage VGL is applied and when the gate drive voltage VGL is cut off, so that a mirror period occurs. This mirror period is long, and may be several μsec depending on conditions, for example. On the other hand, when a current flows through the diode element 6, the collector-emitter voltage does not change, and therefore no mirror period occurs.

  FIG. 15 shows the reinjection time when the gate drive pulse timing is set assuming that the mirror period exists, and when the gate drive pulse timing is set assuming that the mirror period does not exist. In the former case, if the reinjection time Tc is set assuming a mirror period, the actual reinjection time becomes longer than Tc because the mirror period does not actually occur. On the other hand, if it is set from the beginning that the mirror period does not occur, the target reinjection time Tc can be set. Therefore, the timing of the gate drive pulse is set using the time excluding the mirror period. This also has an effect of ensuring a longer pulse width Tw of the gate drive pulse.

(3) Drive capability of drive circuit 28 When a gate drive pulse is output, the drive circuit 28 switches the selector switches 30 and 34 (see FIG. 4) to the B side when the gate drive voltage VGL rises and falls. Thus, the gate drive voltage VGL is output with a high gate drive capability (here, the maximum gate drive capability). This is because current continues to flow through the diode element 6 during the application period of the gate drive pulse, so that a surge due to a steep current change does not occur.

  Further, the drive circuit 28 maintains a constant gate drive capability and outputs the gate drive voltage VGL when the gate drive voltage VGL rises. When a current flows through the transistor element 5, the other semiconductor element 1A is short-circuited by temporarily holding the gate drive voltage VGL at the intermediate voltage Vm (for example, 12V) in the process of increasing the gate drive voltage VGL. A method for reducing the short-circuit current is used. However, when a forward current flows through the diode element 6 of the semiconductor element 1B, there is no possibility of short-circuiting along the path through the semiconductor elements 1A and 1B. This eliminates the need for two-step driving using the intermediate voltage Vm.

  FIG. 16 shows waveforms when the drive circuit 28 outputs the gate drive voltage VGL with the normal drive capability and two-stage drive, and when the drive circuit 28 maintains the high drive capability and outputs the gate drive voltage VGL. In contrast. Since there are variations in the drive capability of the drive circuit 28, the gate capacity of the semiconductor element 1B, etc., variations also occur in the rise time and fall time of the gate drive voltage VGL. This variation becomes more significant as the driving capability is lower.

  Therefore, when the reinjection time Tc is always set to be equal to or longer than the short circuit margin time Tm, the drive circuit 28 maintains a high driving capability and outputs the gate drive voltage VGL, so that the reinjection time Tc and the short circuit margin are satisfied. Deviation from time Tm can be reduced. That is, the reinjection time Tc can be accurately controlled. Further, variation in the pulse width Tw of the gate drive pulse is reduced, and a longer pulse width Tw can be secured.

  As described above, in the drive control devices 38A and 38B according to the present embodiment, when the energization is switched between the upper and lower arms, the semiconductor elements 1A and 1B are in the order of the diode elements 6 during the period in which the PWM signals FH and FL are at the H level, respectively. If it is determined that the current is flowing in the direction, the gate drive signals SGH and SGL for instructing the application of the gate drive pulse are output. By this pulse control, the holes accumulated in the diode element 6 are reduced and the reverse recovery current is reduced, so that the switching loss can be reduced.

  The pulse control unit 27 of the drive ICs 24A and 24B sets the gate drive signals SGH and SGL to the H level from the time when the first time T1 elapses to the time when the second time T2 elapses, starting from the falling time of the PWM signals FH and FL. To do. Since the falling point of the PWM signals FH and FL is also the starting point of the dead time Td, the gate driving pulse can be applied while effectively preventing the arm short circuit by effectively using the dead time Td having a certain time.

  The first time T1 and the second time T2 (or the first time T1 and the pulse width Tw) are the dead time Td, the delay and variation of the gate drive voltages VGH and VGL measured in advance corresponding to the element current, and the reverse recovery current. Is set based on the time until the flow starts, and is stored in the memory 39 of the pulse control unit 27.

  When energization is switched between the upper and lower arms, the timing at which the reverse recovery current flows is delayed as the load current increases. Therefore, the time width (pulse width Tw) between the first time T1 and the second time T2 is set longer as the current flowing through the diode element 6 during the period in which the PWM signals FH and FL are at the H level is larger. Thereby, regardless of the magnitude of the load current, it is possible to suppress an increase in the carrier reinjection time Tc (the time from the end of application of the gate drive pulse to the start of reverse recovery current) with respect to the diode element 6, and the switching loss. Can be reduced.

  The first time T1 and the second time T2 are set so that the reinjection time Tc is greater than zero. Thereby, it is possible to prevent a short-circuit current from flowing through the half bridge circuit 4. Further, the pulse width Tw is set to be equal to or shorter than a predetermined allowable injection time. As a result, the reverse recovery current can be limited to a value corresponding to the allowable injection time or less, and the switching loss can be reduced.

  Further, the first time T1 and the second time T2 are set in consideration of the waveform of the gate drive voltage and the drive mode of the drive circuit 28 when the gate drive pulse is applied. That is, if a gate drive pulse is applied when a current flows through the diode element 6, a mirror period does not occur. Therefore, the first time T1 and the second time T2 are set as those in which the mirror period does not occur.

  In addition, since current continues to flow through the diode element 6 during the application period of the gate drive pulse, surge due to sudden current change and voltage change does not occur. Therefore, the drive circuit 28 outputs the gate drive voltages VGH and VGL according to the maximum gate drive capability that the drive circuit 28 has. Furthermore, if a current flows through the diode element 6, there is no possibility of a short circuit. Therefore, the drive circuit 28 monotonously increases the gate drive voltages VGL and VGH while maintaining a constant gate drive capability when the gate drive voltages VGL and VGH are raised. The first time T1 and the second time T2 are set in accordance with such a driving mode.

  The gate drive voltage when using a drive mode peculiar to such a gate drive pulse has a smaller delay and variation than the gate drive voltage when using a drive mode that cuts off the transistor element 5. Therefore, the drive ICs 24A and 24B can improve the accuracy of the application timing of the gate drive pulse, and can accurately control the reinjection time Tc. As a result, the reinjection time can be controlled to be short while preventing an arm short circuit, and the switching loss can be further reduced. Further, a wider pulse width Tw of the gate drive pulse can be secured. Further, since the pulse control unit 27 applies the gate drive signal starting from the falling point of the PWM signals FH and FL, no separate timing signal is required, and the drive control device used in the past can be replaced. It becomes easy.

  The pulse control unit 27 stops the current from flowing through the diode element 6 even during the period (time t4 to t6) in which the gate drive pulse is applied based on the pulse control (the detected current value is less than the specified value Im2). If it is determined that there is a possibility or no current is flowing, the application of the gate drive pulse is immediately stopped. Thereby, even when the load current changes suddenly, an arm short circuit can be reliably prevented. Furthermore, since it is not necessary to set the specified value Im2 higher in preparation for a sudden change in the load current, a wide current range for performing the pulse control can be secured, and the switching loss can be further reduced.

  As mentioned above, although preferred embodiment of this invention was described, this invention is not limited to embodiment mentioned above, A various deformation | transformation and expansion | extension can be performed within the range which does not deviate from the summary of invention.

  The RC-IGBT is not limited to a trench gate type but may be a planar gate type. The semiconductor elements 1A and 1B may be elements having a control gate and formed with a parasitic diode, such as a diode having a MOS transistor or a MOS gate. The MOS transistor is not limited to a trench gate type but may be a planar gate type. The MOS transistor may have an SJ (Super Junction) structure.

  In the above embodiment, the sense resistors 7A and 7B are provided as the current detection means after the sense elements are formed in the semiconductor elements 1A and 1B. Alternatively, as shown in FIG. 17, sense resistors 7A and 7B may be provided in series with the semiconductor elements 1A and 1B excluding the sense elements. Since the sense resistors 7A and 7B and the main element are directly connected, a high-speed answer is possible. Further, as shown in FIG. 18, Hall sensors 59A and 59B may be provided for the semiconductor elements 1A and 1B. Instead of the hall sensors 59A and 59B, a hall sensor may be provided on the output line from the output terminal Nt to the load. In any configuration, the current can be detected with high accuracy. An insulated current sensor such as a GMR (Giant Magneto Resistance) sensor may be used instead of the Hall sensor.

  In the drawings, 1A and 1B are semiconductor elements, 4 is a half-bridge circuit, 5 is a transistor element (transistor structure), 6 is a diode element (diode structure), 7A and 7B are sense resistors (current detection means), and 8 is a semiconductor substrate. , 15 is an emitter electrode (energized electrode), 18 is a collector electrode (energized electrode), 25 is a current detector (current detector), 27 is a pulse controller (controller), and 38A and 38B are drive controllers.

Claims (7)

An insulated gate transistor structure (5) to which a gate driving voltage is applied and a diode structure (6) are formed on the same semiconductor substrate (8), and the conducting electrode of the transistor structure and the conducting electrode of the diode structure are A drive control device (38A, 38B) for semiconductor elements (1A, 1B), which are common electrodes (15, 18),
Current detection means (7A, 7B, 25) for outputting a current detection signal corresponding to the current flowing through the semiconductor element;
On the basis of the current detection signal, when it is determined that a current flows in the forward direction of the diode structure in the semiconductor element during a period in which an ON command signal for the semiconductor element is input, a subsequent OFF command signal A control means (27) for outputting a gate drive signal for instructing application of the gate drive voltage from a preset first time to a second time, starting from an input time of
A drive circuit (28) for inputting the gate drive signal and outputting the gate drive voltage;
The time width between the first time and the second time is set to a value corresponding to the magnitude of the current flowing in the semiconductor element during the period when the ON command signal for the semiconductor element is input. A drive control device characterized by the above.   After an off command signal is input in a state in which a current flows in the forward direction of the diode structure to the semiconductor element, the other bridge which constitutes a half bridge circuit together with the one semiconductor element after a certain dead time When an ON command signal is input to the semiconductor element, the second driving time is passed and the gate drive voltage is cut off, and the transistor structure of the other semiconductor element flows to the one semiconductor element. The first time and the second time are set so that the time width from the time when the current exceeding the current that has started to flow is greater than zero and less than or equal to a predetermined allowable injection time. The drive control apparatus according to claim 1.   The time width between the first time and the second time is set such that the longer the current flowing in the semiconductor element during the period when the ON command signal is input to the semiconductor element, the longer the time is. The drive control apparatus according to claim 1, wherein:   The gate drive voltage based on the gate drive signal output from the elapse of the first time to the elapse of the second time is assumed to monotonously increase or monotonously decrease according to the gate drive capability of the drive circuit. 4. The drive control device according to claim 1, wherein one hour and the second time are set.   The first time and the second time are set so that a mirror period does not occur in the gate drive voltage based on the gate drive signal output from the time point of the first time to the time point of the second time. The drive control apparatus according to claim 4, wherein:   6. The drive circuit outputs the gate drive voltage while maintaining a constant gate drive capability when the gate drive signal changes at the elapse of the first time. Drive control device.   The drive circuit generates the gate drive voltage with a higher drive capability when the gate drive signal changes at the elapse of the first time and the elapse of the second time than when the semiconductor element is disconnected. The drive control device according to claim 1, wherein the drive control device outputs the drive control device.

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