WO2015004911A1 - Drive control device - Google Patents

Drive control device Download PDF

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Publication number
WO2015004911A1
WO2015004911A1 PCT/JP2014/003639 JP2014003639W WO2015004911A1 WO 2015004911 A1 WO2015004911 A1 WO 2015004911A1 JP 2014003639 W JP2014003639 W JP 2014003639W WO 2015004911 A1 WO2015004911 A1 WO 2015004911A1
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Prior art keywords
semiconductor element
gate drive
time
voltage
current
Prior art date
Application number
PCT/JP2014/003639
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French (fr)
Japanese (ja)
Inventor
剛志 井上
岩村　剛宏
昌弘 山本
Original Assignee
株式会社デンソー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2013144560A external-priority patent/JP5935768B2/en
Priority claimed from JP2014134227A external-priority patent/JP5939281B2/en
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to US14/901,767 priority Critical patent/US9590616B2/en
Priority to CN201480039343.7A priority patent/CN105379086B/en
Publication of WO2015004911A1 publication Critical patent/WO2015004911A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/538—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration
    • H02M7/53803—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/168—Modifications for eliminating interference voltages or currents in composite switches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K2017/307—Modifications for providing a predetermined threshold before switching circuits simulating a diode, e.g. threshold zero
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption

Definitions

  • the present disclosure includes Japanese application number 2013-144561 filed on July 10, 2013, Japanese application number 2013-144560 filed on July 10, 2013, and application filed on June 30, 2014. Which is based on Japanese Patent Application No. 2014-134227, which is incorporated herein by reference.
  • the present disclosure relates to a drive control device for a semiconductor element in which an insulated gate transistor structure and a diode structure are formed on the same semiconductor substrate.
  • Transistor element and diode element such as RC-IGBT, MOS transistor, diode with MOS gate, etc. are formed on the same semiconductor substrate, transistor element conducting electrode (collector, emitter or drain, source) and diode element conducting electrode A semiconductor element having a common electrode (cathode, anode) is known (see Non-Patent Document 1).
  • a semiconductor element is used as a switching element in a power conversion device such as an inverter or a converter, it is necessary to reduce switching loss and / or conduction loss.
  • the power conversion device has a half-bridge circuit as a basic configuration, and performs AC-DC voltage conversion and DC-AC voltage conversion by complementarily turning on and off the semiconductor elements of the upper and lower arms, or boosts and steps down the input voltage.
  • this half-bridge circuit in order to prevent a power supply short circuit (arm short circuit), a dead time for simultaneously turning off the upper and lower semiconductor elements is provided.
  • the load current flows back to the diode element of one semiconductor element.
  • the load current is switched from the diode element to the other semiconductor element.
  • a reverse recovery current flows due to the emission of carriers accumulated in the diode element. This reverse recovery current increases switching loss and causes noise.
  • Non-Patent Document 1 discloses a method in which a positive gate drive voltage is applied to one semiconductor element slightly before the other semiconductor element is turned on. According to this method, the hole current decreases as the electron current of the semiconductor element increases, hole injection is suppressed, and the reverse recovery current can be reduced.
  • the semiconductor element described above has a characteristic that, when a gate drive voltage is applied in a state where a current flows through the diode element, a channel is formed and hole injection is suppressed, so that conduction loss increases. is doing.
  • drive control in which it is determined whether or not a current is flowing through the diode element, the gate drive voltage is cut off when the current is flowing, and the gate drive voltage is applied when the current is not flowing.
  • Non-Patent Document 1 that suppresses carrier injection by temporarily applying a gate drive voltage (gate drive pulse) to a semiconductor element is effective in reducing the reverse recovery current.
  • a gate drive pulse since it is necessary to apply a gate drive pulse at the time of switching current between two semiconductor elements constituting the half-bridge circuit, an arm short circuit occurs when the application timing is slightly delayed. Conversely, if the application timing is early, the amount of holes injected again after the application of the gate drive pulse is increased, and the effect of reducing the reverse recovery current is reduced.
  • Non-Patent Document 1 does not show the specific application timing or pulse width of the gate drive pulse. In order to put this method into practical use, it is necessary to establish means for applying such a gate drive pulse.
  • the characteristics of the conduction loss of the semiconductor element due to application / cutoff of the gate drive voltage vary greatly depending on the type of the semiconductor element (RC-IGBT, MOS transistor, etc.). For this reason, there is a case in which the conduction loss cannot be sufficiently reduced according to the conventional criterion for determining whether or not a current flows through the semiconductor element in the forward direction of the diode element.
  • a switching loss can be reduced by applying a gate drive pulse at an appropriate timing to a semiconductor element in which a transistor structure and a diode structure are formed on the same semiconductor substrate.
  • An object of the present invention is to provide a drive control device that can sufficiently reduce the conduction loss of a semiconductor element regardless of the type of the semiconductor element.
  • each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate.
  • the two semiconductor elements constitute a half bridge circuit. The first time and the second time are set in advance so as not to cause an arm short circuit between the two semiconductor elements.
  • the gate drive signal necessary for applying the gate drive voltage at a desired timing starting from the input time point of the off command signal can be accurately set.
  • the reinjection time can be controlled to be short while preventing the arm short circuit, the reverse recovery current is reduced and the switching loss can be reduced.
  • the first control means can apply the gate drive signal using the off command signal as a reference timing, a separate timing signal is not required, and the replacement from the conventionally used drive control device is facilitated.
  • an insulated gate transistor structure to which a gate driving voltage is applied and a diode structure are formed on the same semiconductor substrate, and the current-carrying electrode of the transistor structure and the current-carrying electrode of the diode structure are
  • a common drive control device for a semiconductor element includes: a current detection unit that outputs a current detection signal corresponding to a current flowing through the semiconductor element; and the current detection signal during a period when an ON command signal is input to the semiconductor element. If the current of the semiconductor element flowing in the forward direction of the diode structure is determined to be greater than or equal to the current threshold value based on the second, a gate drive signal for commanding the interruption of the gate drive voltage is output. Control means.
  • the second control means is configured such that the current of the semiconductor element that flows in the forward direction of the diode structure is based on the current detection signal during the period when the ON command signal for the semiconductor element is input. If it is determined that the value is less than the value, a gate drive signal for instructing application of the gate drive voltage is output. When a current flows through the semiconductor element in the forward direction of the diode structure, the conduction loss when the gate drive voltage is cut off is equal to the conduction loss when the gate drive voltage is applied. The current value is measured in advance and set as a current threshold value.
  • the conduction loss can be appropriately reduced regardless of the type and breakdown voltage of the semiconductor element.
  • the gate drive voltage is reliably applied to the semiconductor element during the period in which the current flows in the reverse direction of the diode structure, the current according to the ON command signal can be supplied to the transistor structure.
  • each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate.
  • the detection means detects a change in the current detection signal, a pulse is output so that an arm short circuit does not occur between the two semiconductor elements.
  • the time is prior to the point of input of the ON command signal for the one of the semiconductor elements, two semiconductor elements constitute a half-bridge circuit.
  • each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized.
  • the drive control device for two semiconductor elements in which the electrode and the current-carrying electrode of the diode structure are common, a voltage detection means for outputting a voltage detection signal based on the electrode potential of one of the semiconductor elements, and the one semiconductor element
  • Control means for outputting a pulse from an input time point of an ON command signal to the one semiconductor element so as not to cause an arm short circuit.
  • the two semiconductor elements constitute a half bridge circuit.
  • Each semiconductor element has the insulated gate type transistor structure and diode structure to which a gate drive voltage is applied formed in the same semiconductor substrate, and electricity supply of the said transistor structure
  • a pulse is generated in response to an OFF command signal being input to the input means.
  • And means for outputting comprises a control means for outputting a pulse a predetermined time before the input time of the ON command signal for the one of the semiconductor element so arm short circuit does not occur between the two semiconductor elements.
  • the two semiconductor elements constitute a half bridge circuit.
  • each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate drive voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized.
  • a drive control device for two semiconductor elements in which an electrode and a current-carrying electrode of the diode structure are common, a voltage detection means for outputting a voltage detection signal based on an electrode potential of one of the semiconductor elements, and the other semiconductor element Input means for inputting a command signal to the one semiconductor element, and when the off-command signal for the one semiconductor element is input, the one semiconductor element has the diode structure based on the voltage detection signal and the input signal of the input means.
  • a pulse is generated in response to an OFF command signal being input to the input means.
  • the two semiconductor elements constitute a half bridge circuit.
  • each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized.
  • the ON command signal Starting from the time when the OFF command signal is input through the input, the gate drive power is supplied from the time when the first time has elapsed to the time when the second time has elapsed.
  • a control means for outputting a gate drive signal for commanding the application The first time and the second time are set in advance so as not to cause an arm short circuit between the two semiconductor elements.
  • an insulated gate transistor structure to which a gate drive voltage is applied and a diode structure are formed on the same semiconductor substrate, and the conduction electrode of the transistor structure and the conduction electrode of the diode structure are
  • the drive control device for a semiconductor element having a common electrode includes a current detection unit that outputs a current detection signal corresponding to a current flowing through the semiconductor element, and an on command signal for the semiconductor element based on the current detection signal.
  • a preset first time elapses from the input time point of the subsequent off command signal Control means for outputting a gate drive signal for instructing application of the gate drive voltage from a time point until a lapse of a second time; and If the input signal and a drive circuit for outputting the gate drive voltage.
  • the time width between the first time and the second time is set to a value corresponding to the magnitude of the current flowing in the semiconductor element during the period when the ON command signal for the semiconductor element is input.
  • the time from when the gate drive pulse is applied to one semiconductor element until the reverse recovery current starts to flow for example, the time when carriers (holes) are injected again into the diode structure after the application of the gate drive pulse is completed.
  • Carrier reinjection time can be accurately controlled. Therefore, according to this means, the reinjection time can be controlled to be short while preventing an arm short circuit, so that the reverse recovery current is reduced and the switching loss can be reduced.
  • the control means can apply the gate drive signal using the off command signal as a reference timing, a separate timing signal is not required, and replacement from a conventionally used drive control device is facilitated.
  • FIG. 1 is a configuration diagram of a drive control system showing the first embodiment.
  • FIG. 2 is a circuit configuration diagram of the main element and the sense element.
  • FIG. 3 is a schematic longitudinal sectional view of a semiconductor element
  • FIG. 4 is a voltage-current characteristic diagram in the forward direction of the diode element.
  • FIG. 5 is a waveform diagram relating to Vf control and pulse control.
  • FIG. 6 shows the second embodiment, and is a voltage-current characteristic diagram in the case where current flows in the forward direction of the diode element in the MOS transistor.
  • FIG. 1 is a configuration diagram of a drive control system showing the first embodiment.
  • FIG. 2 is a circuit configuration diagram of the main element and the sense element.
  • FIG. 3 is a schematic longitudinal sectional view of a semiconductor element
  • FIG. 4 is a voltage-current characteristic diagram in the forward direction of the diode element.
  • FIG. 5 is a waveform diagram relating to Vf control and pulse control.
  • FIG. 6 shows the
  • FIG. 7 is a waveform diagram relating to Vf control and pulse control when using synchronous rectification
  • FIG. 8 is a configuration diagram of a drive control system showing the third embodiment.
  • FIG. 9 is a configuration diagram of the drive control system showing the fourth embodiment.
  • FIG. 10 is a configuration diagram of the drive control system showing the fifth embodiment.
  • FIG. 11 is a configuration diagram of a drive control system showing the sixth embodiment.
  • FIG. 12 is a configuration diagram of a drive control system showing the seventh embodiment.
  • FIG. 13 is a configuration diagram of a drive control system showing the eighth embodiment.
  • FIG. 14 is a configuration diagram of the drive control system showing the ninth embodiment.
  • FIG. 15 is a diagram illustrating a modification of the current detection configuration.
  • FIG. 16 is a diagram illustrating a modification of the current detection configuration.
  • FIG. 15 is a diagram illustrating a modification of the current detection configuration.
  • FIG. 17 is a configuration diagram of a drive control system showing the tenth embodiment.
  • FIG. 18 is a waveform diagram relating to Vf control and pulse control according to the tenth embodiment
  • FIG. 19 is a waveform diagram relating to Vf control and pulse control when using synchronous rectification according to the eleventh embodiment.
  • FIG. 20 is a configuration diagram of the drive control system showing the twelfth embodiment.
  • FIG. 21 is a block diagram of a drive control system showing the thirteenth embodiment.
  • FIG. 22 is a configuration diagram of the drive control system showing the fourteenth embodiment.
  • FIG. 23 is a configuration diagram of the drive control system showing the fifteenth embodiment
  • FIG. 24 is a schematic cross-sectional view of a semiconductor structure showing an intermediate potential detection mode according to the sixteenth embodiment, FIG.
  • FIG. 25 is an explanatory diagram schematically showing a change characteristic of the collector electrode potential according to the direction and magnitude of the load current in each embodiment.
  • FIG. 26 is an explanatory diagram schematically showing a change characteristic of the collector electrode potential according to the direction and magnitude (near zero current) of the load current in each embodiment.
  • FIG. 27 is a waveform diagram relating to Vf control and pulse control when using synchronous rectification showing a modification of the first to sixteenth embodiments;
  • FIG. 28 is a configuration diagram of a drive control system showing a modification of the first to sixteenth embodiments,
  • FIG. 29 is a configuration diagram of a drive control system showing a modification of the first to sixteenth embodiments, FIG.
  • FIG. 30 is a configuration diagram of a drive control system showing a modification of the first to sixteenth embodiments
  • FIG. 31 is a configuration diagram of a drive control system showing a modification of the first to sixteenth embodiments
  • FIG. 32 is a waveform diagram relating to Vf control and pulse control when using synchronous rectification showing a modification of the first to sixteenth embodiments
  • FIG. 33 is a configuration diagram of a drive control system showing a seventeenth embodiment of the present disclosure.
  • FIG. 34 is a configuration diagram of the drive capability switching circuit of the drive circuit.
  • FIG. 35 is a block diagram of the pulse control unit.
  • FIG. 36 is a block diagram of the pulse start determination unit
  • FIG. 37 is a voltage-current characteristic diagram in the forward direction of the diode element.
  • FIG. 38 is a waveform diagram relating to Vf control and pulse control
  • FIG. 39 is a diagram showing the device current, the gate drive voltage, and the carrier concentration in the diode device
  • FIG. 40 is a waveform diagram when the reinjection time becomes zero
  • FIG. 41 is a diagram showing the relationship between reinjection time and switching loss
  • FIG. 42 is a diagram showing the relationship between the pulse width and the switching loss
  • FIG. 43 is an explanatory diagram of the first time and the second time
  • FIG. 44 is a diagram for explaining the operation of the pulse start determining unit.
  • FIG. 45 is a waveform diagram when the mirror period exists and when it does not exist
  • FIG. 46 is a waveform diagram of the gate drive voltage for different drive capabilities
  • FIG. 47 is a diagram showing a modification of the current detection configuration.
  • FIG. 48 is a diagram illustrating a modification of the current detection configuration.
  • the drive control system shown in FIG. 1 is used in a power conversion device such as an inverter device that drives an inductive load such as a motor, or a converter device that includes an inductor and boosts / steps down a DC voltage.
  • the semiconductor elements 1A and 1B which are switching elements, are arranged in series between the high-potential side DC power supply line 2 and the low-potential side DC power supply line 3 with the output terminal Nt interposed therebetween to form the half-bridge circuit 4. is doing.
  • the semiconductor elements 1A and 1B having the same structure are reverse conducting IGBTs (RC-IGBTs) in which the insulated gate transistor element 5 and the diode element 6 are formed on the same semiconductor substrate.
  • the energizing electrodes (collector and emitter) of the transistor element 5 and the energizing electrodes (cathode and anode) of the diode element 6 are common electrodes.
  • a sense element comprising a transistor element 5s and a diode element 6s for passing a minute current proportional to the current flowing through the main element is formed on the semiconductor substrate as shown in FIG. In FIG. 1, the main element and the sense element are simply shown.
  • Sense resistors 7A and 7B are connected between the sense terminals S1 and S2 of the semiconductor elements 1A and 1B, respectively.
  • the sense resistors 7A and 7B constitute current detection means together with a current detection unit 25 described later.
  • FIG. 3 shows an RC-IGBT having a vertical structure as an example of the semiconductor elements 1A and 1B.
  • the transistor structure and the diode structure are provided on the same semiconductor substrate.
  • the semiconductor substrate 8 is composed of an n-type silicon substrate.
  • a guard ring is formed in the vicinity of the periphery of the element formation region of the semiconductor substrate 8 so as to surround the element formation region.
  • a p-type base layer 9 is formed on the upper surface portion of the semiconductor substrate 8.
  • a plurality of trenches having a depth penetrating the base layer 9 are formed in the base layer 9.
  • Polysilicon is buried in the trench, whereby the gate electrode 10 having a trench structure is formed.
  • a gate drive voltage is input to each gate electrode 10 through a common gate wiring 11.
  • the gate electrodes 10 are provided in stripes at equal intervals in one direction along the surface layer portion of the base layer 9.
  • the base layer 9 is partitioned into a plurality of first regions 12 and a plurality of second regions 13 that are electrically separated from each other along the one direction. These first regions 12 and second regions 13 are alternately arranged, and the width of the second region 13 is wider than the width of the first region 12.
  • an n + -type emitter region 14 is formed adjacent to the gate electrode 10.
  • An emitter electrode 15 is formed on the first region 12.
  • the emitter electrode 15 is connected to the base layer 9 and the emitter region 14 in the first region 12.
  • the first region 12 operates as a channel region of the transistor element 5 and also operates as an anode region of the diode element 6. That is, the emitter electrode 15 for the first region 12 becomes the emitter electrode of the transistor element 5 and the anode electrode of the diode element 6.
  • the second region 13a provided above the collector region 16 (described later) is not connected to any electrode.
  • a second region 13 b provided above the cathode region 17 (described later) is connected to the emitter electrode 15. Accordingly, only the second region 13 b provided above the cathode region 17 in the second region 13 operates as the anode region of the diode element 6. That is, the emitter electrode 15 becomes an anode electrode of the diode element 6 in the second region 13b.
  • a p + type collector region 16 is formed corresponding to a range (left side of the broken line) where the second region 13a is formed, and a range where the second region 13b is formed (broken line) N + type cathode region 17 is formed corresponding to the right side of FIG.
  • the collector region 16 and the cathode region 17 are connected to the collector electrode 18. That is, the cathode electrode of the diode element 6 is in common with the collector electrode 18 of the transistor element 5.
  • An n-type field stop layer 19 is formed between the semiconductor substrate 8 and the collector region 16 and the cathode region 17.
  • the microcomputer 21 includes a PWM signal generation unit 22 that generates the high-side and low-side PWM signals FH and FL of the half-bridge circuit 4.
  • the PWM signals FH and FL have a fixed dead time Td that is simultaneously at the L level (off command level).
  • the PWM signals FH and FL are input to the drive ICs 24A and 24B via the photocouplers 23A and 23B, respectively.
  • the ON command signal referred to in the present disclosure is the PWM signals FH and FL having the H level (ON command level), and the OFF command signal is the PWM signals FH and FL having the L level (OFF command level).
  • the drive ICs 24A and 24B include a current detection unit 25, a Vf control unit 26, a pulse control unit 27, and a drive circuit 28, and operate when supplied with power supply voltages VDDA and VDDB (for example, 15V). Separate drive ICs 24A and 24B are provided for the high-side semiconductor element 1A and the low-side semiconductor element 1B, respectively. For this reason, the drive ICs 24A and 24B have a sufficient withstand voltage (that is, a withstand voltage according to the gate drive voltage) according to the power supply voltages VDDA and VDDB. Since the drive ICs 24A and 24B have the same configuration, the configuration of the drive IC 24B will be mainly described.
  • the current detector 25 is a current detector that outputs a current detection signal (polarity and magnitude of current) corresponding to the current flowing through the semiconductor element 1B based on the sense voltage VSL generated in the sense resistor 7B.
  • the Vf control unit 26 and the pulse control unit 27 generate the gate drive signal SGL based on the PWM signal FL.
  • the drive circuit 28 receives the gate drive signal SGL and outputs a gate drive voltage VGL.
  • the Vf control unit 26 controls to cut off the gate drive voltage VGL when the current of the semiconductor element 1B flowing in the forward direction of the diode element 6 is equal to or greater than the current threshold It during the period in which the PWM signal FL is at the H level. I do.
  • This control has the effect of reducing the conduction loss by lowering the voltage of the semiconductor element 1B (in the case of RC-IGBT, the forward voltage Vf of the diode element 6). In the following description, this is referred to as Vf control.
  • the pulse control unit 27 performs pulse-shaped gate driving with reference to the falling edge of the PWM signal FL when a current in the forward direction of the diode element 6 flows through the semiconductor element 1B during the period in which the PWM signal FL is at the H level.
  • the signal SGL is output.
  • a pulsed gate drive voltage VGL (hereinafter referred to as a gate drive pulse) is applied to the gate of the semiconductor element 1B.
  • This control has the effect of reducing the holes accumulated in the diode element 6 and reducing the reverse recovery current. In the following description, this is referred to as pulse control.
  • the gate drive signal SGL generated by the Vf control unit 26 and the pulse control unit 27 is given to the gate of the semiconductor element 1B via the drive circuit 28.
  • the drive circuit 28 can switch the driving ability to charge / discharge the gate in a plurality of ways. That is, when a sharp change occurs in the current (element current) or voltage flowing through the semiconductor element 1B, such as at the rising edge of the PWM signal FL or at the falling edge of the PWM signal FL from the state where the current flows in the transistor element 5, In order to suppress the occurrence of a voltage surge, the driving capability can be switched to a low level. In this case, the drive circuit 28 is driven by using a constant current circuit at the time of turn-on, and is driven by using a switch element having an increased on-resistance at the time of turn-off.
  • the drive circuit 28 is driven by using a constant voltage circuit at the time of turn-on, and is driven by connecting in parallel a switch element having a higher on-resistance and a switch element having a lower on-resistance at the time of turn-off.
  • Threshold value setting circuits 29A, 30A, 31A are externally attached to the driving IC 24A.
  • Threshold setting circuits 29B, 30B, 31B are externally attached to the driving IC 24B.
  • the threshold setting circuits 29A, 30A, 31A are configured with a floating ground FG equal to the emitter potential of the semiconductor element 1A as a reference potential.
  • the threshold setting circuits 29A and 29B divide the voltages VDDA and VDDB by the resistors R1 and R2 to generate a threshold voltage Vt.
  • the threshold setting circuits 30A and 30B divide the voltages VDDA and VDDB by resistors R3 and R4 to generate a specified voltage Vm1.
  • the threshold setting circuits 31A and 31B divide the voltages VDDA and VDDB by the resistors R5 and R6 to generate a specified voltage Vm2.
  • the threshold voltage Vt determines the magnitude of the current threshold It used in the Vf control unit 26. As will be described later, the characteristic of the forward voltage Vf with respect to the forward current If of the diode element 6 varies depending on the type of element (RC-IGBT, MOS transistor, etc.) and the breakdown voltage of the element. Therefore, the Vf control unit 26 selects an appropriate current threshold It based on the switching signal Sk and the threshold voltage Vt given from the outside.
  • the specified voltage Vm1 determines the magnitude of the specified value Im1 used for determining whether or not to stop the Vf control.
  • the specified voltage Vm2 determines the magnitude of the specified value Im2 used for determining whether or not to stop the pulse control.
  • the drive control device 32A is configured by the drive IC 24A and the sense resistor 7A described above, and the drive control device 32B is configured by the drive IC 24B and the sense resistor 7B.
  • Vf control will be described.
  • the semiconductor elements 1A and 1B which are RC-IGBTs
  • a gate drive voltage is applied in a state where a current flows through the diode element 6, a channel is formed in the first region 12 and hole injection is suppressed.
  • the forward voltage Vf of the diode element 6 through which the forward current If flows increases, and the conduction loss (Vf ⁇ If) of the diode element 6 increases.
  • the semiconductor elements 1A and 1B are MOS transistors (see the second embodiment).
  • the thickness of the drift region increases due to the higher breakdown voltage of the element, the resistance ratio of the channel occupying the entire on-resistance decreases, and the conduction loss of the diode element 6 tends to increase when a gate drive voltage is applied.
  • the diode element 6 has a small current value (current threshold It) at which the conduction loss when the gate drive voltage is cut off is equal to the conduction loss when the gate drive voltage is applied. . In the case shown in FIG. 4, it is almost zero.
  • the conduction loss of the diode element 6 when the gate drive voltage is cut off is equal to the conduction loss of the transistor element 5 when the gate drive voltage is applied.
  • the current value (current threshold value It) is a relatively large value (see FIG. 6). That is, the current threshold It varies depending on the type and breakdown voltage of the semiconductor elements 1A and 1B, and is measured in advance.
  • the switching signal Sk When driving the RC-IGBT, the switching signal Sk is switched to L level, for example, and when driving the MOS transistor, the switching signal Sk is switched to H level, for example.
  • the switching signal Sk is a threshold value specifying signal for specifying the current threshold value It from the outside.
  • the Vf control unit 26 sets the current threshold It to zero and executes Vf control.
  • the switching signal Sk is at the H level, the current threshold value It corresponding to the threshold voltage Vt input from the outside is set and the Vf control is executed.
  • FIG. 5 shows a case where the semiconductor element 1A is turned off and the semiconductor element 1B is turned on when the current flows from the output terminal Nt toward the load, and then the semiconductor element 1B is turned off and the semiconductor element 1A is turned on again. It is a waveform.
  • the current of the semiconductor element 1A, the gate drive voltages VGH and VGL, the PWM signal FH, and the gate drive signal SGL and the PWM signal FL for commanding the gate drive voltage VGL are shown.
  • Vth is the threshold voltage of the semiconductor element 1A.
  • the Vf control unit 26 of the drive IC 24B determines whether or not the detected current of the diode element 6 is equal to or higher than the current threshold It in the forward direction during the period when the PWM signal FL is at the H level (time t2 to t3). If it is determined that the current is less than the current threshold It, an H level gate drive signal SGL is output. Based on the gate drive signal SGL, the gate drive voltage VGL is applied to the gate of the semiconductor element 1B in accordance with the delay in the drive circuit 28, the charging time of the element capacitance of the semiconductor element 1B, and the like. On the other hand, if it is determined that the detected current is equal to or greater than the current threshold It (in the case shown in FIG. 5), an L level gate drive signal SGL is output. Thereby, the gate drive voltage VGL is cut off.
  • pulse control when the current flows through the diode element 6 of the semiconductor element 1B during the period in which the PWM signal FL is at the H level, after the PWM signal FL falls to the L level and before the reverse recovery current starts to flow, This is control for applying a gate drive pulse to the semiconductor element 1B. This is also the case when a current flows through the diode element 6 of the semiconductor element 1A during the period in which the PWM signal FH is at the H level, and the same applies after the PWM signal FH falls to the L level. As a result, carriers (holes) accumulated in the diode element 6 are reduced, so that an effect of reducing the reverse recovery current can be obtained.
  • the pulse control unit 27 causes a current to flow through the diode element 6 of the semiconductor element 1B when the PWM signal FL is at the H level, more preferably when the PWM signal FL falls to the L level (time t3). It is determined whether or not.
  • current is flowing (however, when the detected current value is equal to or greater than the specified value Im2)
  • the second time T2 has elapsed from the time when the first time T1 has elapsed (time t4), starting from the falling time of the PWM signal FL.
  • the gate drive signal SGL is kept at the H level until the time (time t6).
  • the gate drive signal SGL is at the L level at the time of falling of the PWM signal FL.
  • the pulse control unit 27 continues to determine whether or not a current is flowing through the diode element 6 of the semiconductor element 1B even after the PWM signal FL falls to the L level. When the current detection value falls below the specified value Im2, the pulse control unit 27 immediately returns the gate drive signal SGL to the L level even after the first time T1 has elapsed and before the second time T2 has elapsed.
  • the pulse control unit 27 determines that no current flows through the diode element 6 when the PWM signal FL falls to the L level, the pulse control unit 27 immediately maintains the gate drive signal SGL at the L level. That is, no gate drive pulse is applied.
  • the first time T1 and the second time T2 are set in advance so as not to cause an arm short circuit.
  • the waveform of the gate drive voltage VGL when a gate drive pulse is applied differs between when the current flows through the diode element 6 and when the current flows through the transistor element 5 while the PWM signal FL is at the L level. .
  • the drive circuit 28 can output the gate drive voltage VGL with a higher gate drive capability than usual when the gate drive voltage VGL rises and falls. Further, when a current flows through the diode element 6, there is no possibility of short-circuiting along a path through the semiconductor elements 1A and 1B. For this reason, in the process of increasing the gate drive voltage VGL, it is necessary to perform the two-stage drive for temporarily holding the gate drive voltage VGL at the intermediate voltage and reducing the short-circuit current when the semiconductor element 1A on the other side is short-circuited. There is no.
  • the first time T1 and the second time T2 are monotonous according to the gate drive capability of the drive circuit 28 in consideration of the waveform of the gate drive voltage VGL when the gate drive pulse is applied and the drive mode of the drive circuit 28. Set to increase or decrease monotonically.
  • the time Tc carrier reinjection time
  • the allowable injection time is specified according to the allowable reverse recovery current.
  • the first time T1 and the second time T2 vary the current flowing through the diode element 6 while changing the current flowing through the diode element 6 and starting from the falling point of the PWM signal FL.
  • the timing at which the drive voltage VGL is applied and the timing at which the reverse recovery current starts to flow are set in advance by measurement.
  • the first time T1 and the second time T2 are stored in a memory or the like in the pulse control unit 27 in association with the current.
  • the first time T1 and the second time T2 can also be generated using one or several patterns of logic circuits or analog delay circuits.
  • the pulse control unit 27 When applying the gate drive pulse, the pulse control unit 27 refers to the current detection signal to obtain the current flowing in the diode element 6 and calculates the first time T1 and the second time T2 corresponding to the current value from the memory. read out.
  • the pulse control unit 27 starts from the falling point of the PWM signal FL, and raises the gate driving signal SGL when the first time T1 has elapsed, and lowers the gate driving signal SGL when the second time T2 has elapsed.
  • the drive control devices 32A and 32B have the currents (diodes of the semiconductor elements 1A and 1B flowing in the forward direction of the diode element 6 during the period in which the PWM signals FH and FL are at the H level, respectively. If it is determined that (current) is equal to or greater than the current threshold It (0 in this embodiment), the gate drive signals SGH and SGL are set to the L level.
  • the current threshold It is the conduction loss of the semiconductor elements 1A and 1B when the gate drive voltages VGH and VGL are cut off, and the conduction of the semiconductor elements 1A and 1B when the gate drive voltages VGH and VGL are applied. This is the current value at which the loss becomes equal. With this Vf control, the conduction loss of the diode element 6 can be reduced regardless of the type and breakdown voltage of the semiconductor elements 1A and 1B.
  • the pulse control unit 27 of the drive ICs 24A and 24B sets the gate drive signals SGH and SGL to the H level from the time when the first time T1 has elapsed to the time when the second time T2 has elapsed, starting from the falling time of the PWM signals FH and FL. To do. Since the falling point of the PWM signals FH and FL is also the starting point of the dead time Td, the gate driving pulse can be applied while effectively preventing the arm short circuit by effectively using the dead time Td having a certain time.
  • the first time T1 and the second time T2 are set based on the dead time Td, the delay and variation of the gate drive voltages VGH and VGL measured in advance corresponding to the element current, and the time until the reverse recovery current starts to flow. ing.
  • the first time T1 and the second time T2 are set in consideration of the waveform of the gate drive voltage and the drive mode of the drive circuit 28 when the gate drive pulse is applied. Thereby, a wide pulse width Tw of the gate drive pulse can be secured.
  • the accuracy of the application timing of the gate drive pulse can be increased, and the reinjection time Tc can be accurately controlled. As a result, the reinjection time Tc can be controlled to be short while preventing an arm short circuit, and the switching loss can be further reduced.
  • the pulse control unit 27 stops the current from flowing through the diode element 6 even during the period (time t4 to t6) in which the gate drive pulse is applied based on the pulse control (the detected current value is less than the specified value Im2). If it is determined that there is a possibility or no current is flowing, the application of the gate drive pulse is immediately stopped. Thereby, even when the load current changes suddenly, an arm short circuit can be reliably prevented. Furthermore, since it is not necessary to set the specified value Im2 higher in preparation for a sudden change in the load current, a wide current range for performing the pulse control can be secured, and the switching loss can be further reduced.
  • the pulse control unit 27 applies the gate drive signal starting from the falling point of the PWM signals FH and FL, no separate timing signal is required, and the replacement from the conventionally used drive control device is easy. Become.
  • the drive control devices 32A and 32B have high response because the control loop is short. Since the drive ICs 24A and 24B are provided on the half bridge circuit 4 side via the photocouplers 23A and 23B, the current detection unit 25 does not need an insulating function.
  • the Vf control unit 26 and the pulse control unit 27 stop the Vf control and the pulse control and perform the normal control when the magnitude of the load current becomes smaller than the specified values Im1 and Im2, respectively.
  • the normal control is control that raises the gate drive signal when the PWM signal rises and lowers the gate drive signal when the PWM signal falls regardless of the current flowing through the diode element 6. Thereby, erroneous control due to a decrease in current detection accuracy can be prevented.
  • FIGS. 1A and 1B A second embodiment using MOS transistors for the semiconductor elements 1A and 1B will be described with reference to FIGS.
  • the configuration of the drive control devices 32A and 32B is as shown in FIG.
  • the operation of the drive control device 32B on the low side will be mainly described.
  • the operation of the drive control device 32A on the high side is the same.
  • the switching signal Sk is switched to, for example, the H level.
  • Drive control device 32B sets current threshold It according to threshold voltage Vt input from threshold setting circuit 29B, and executes Vf control.
  • FIG. 6 is a voltage-current characteristic diagram when a current flows through the MOS transistor in the forward direction of the diode element 6.
  • the forward voltage Vf of the diode element 6 when the gate drive voltage is cut off and the drain-source voltage VDS of the transistor element 5 when the gate drive voltage is applied
  • the magnitude relationship of is reversed.
  • region 1 where voltage VDS ⁇ voltage Vf
  • region 2 where voltage VDS ⁇ voltage Vf, conduction loss can be reduced by cutting off the gate drive voltage.
  • the Vf control unit 26 When the current in the region 1 flows through the semiconductor element 1B during the period when the PWM signal FL is at the H level, the Vf control unit 26 performs normal control (synchronous rectification) to apply the gate drive voltage VGL. Thereafter, when the PWM signal FL becomes L level, it is necessary to apply a gate drive pulse to the semiconductor element 1B.
  • the pulse control unit 27 starts from the time when the PWM signal FL falls and the second time T2 elapses from the time when the first time T1 elapses.
  • the gate drive signal SGL may be kept at the H level until the time point.
  • the conduction loss can be reduced by continuously applying the gate drive voltage VGL until the second time T2 elapses, rather than once interrupting the gate drive voltage VGL. Therefore, the Vf control unit 26 performs pulse control following the Vf control, and outputs the H-level gate drive signal SGL by extending it beyond the time t3 until the elapse of the second time T2 (time t6) ( Pulse expansion).
  • the Vf control unit 26 and the pulse control unit 27 are the same as the RC-IGBT control shown in FIG.
  • the gate drive signal SGL is output.
  • the current in the range of the regions 1 and 2 does not flow through the semiconductor element 1B during the period in which the PWM signal FL is at the H level, that is, the current in the forward direction of the MOS transistor (the reverse direction of the diode element 6).
  • the Vf control unit 26 and the pulse control unit 27 perform normal control. According to this embodiment, the same effect as that of the first embodiment can be obtained.
  • (Third, fourth and fifth embodiments) 8, 9, and 10 show drive control devices 52, 54, and 56 using drive ICs 51, 53, and 55 that have a high breakdown voltage.
  • the high breakdown voltage is a breakdown voltage according to the power supply voltage applied to the half bridge circuit 4.
  • the drive control devices 52, 54, and 56 drive and control the two semiconductor elements 1 ⁇ / b> A and 1 ⁇ / b> B that constitute the half-bridge circuit 4.
  • the driving ICs 51, 53, and 55 are provided with a common Vf control unit 26 and a common pulse control unit 27 for the semiconductor elements 1A and 1B, and operate when supplied with a power supply voltage VDD (for example, 15 V).
  • VDD power supply voltage
  • the gate drive signal SGH is given to the semiconductor element 1A via the level shift circuit 57 and the drive circuit 28, and the gate drive signal SGL is given to the semiconductor element 1B via the drive circuit 28.
  • the drive IC 51 includes a current detection unit 25 that outputs a current detection signal based on the sense voltages VSH and VSL generated in the sense resistors 7A and 7B.
  • the high-side current detection unit 25 outputs a current detection signal via the level shift circuit 58.
  • the drive IC 53 has a configuration in which the high-side current detection unit 25 and the level shift circuit 58 are omitted.
  • the drive IC 55 includes a current detection circuit 60 and inputs a sense signal from the hall sensor 59 or the like instead of the sense voltage VSL.
  • the current detection unit 25 of the drive IC 53 and the current detection circuit 60 of the drive IC 55 estimate the current flowing to the other (for example, the semiconductor element 1A) based on the current detection signal flowing to either one (for example, the semiconductor element 1B).
  • Other configurations are the same as those of the first embodiment.
  • the pulse control unit 27 Since the pulse control unit 27 generates the gate drive signals SGH and SGL, the gate drive voltage applied to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements 1A and 1B. Can be prohibited. As a result, since the PWM signals FH and FL are input to the Vf control unit 26 of the control IC 63, the Vf control unit 26 and the pulse control unit 27 can collectively control the one and the other arms. , Arm short circuit can be surely prevented. Further, since the current detection unit 25 or the current detection circuit 60 can be shared between the high side and the low side, the circuit configuration can be simplified (FIGS. 9 and 10).
  • the high-side specified values Im1 and Im2 may be set larger than in the first embodiment based on the specified voltages Vm1 and Vm2 generated by the threshold setting circuits 30 and 31. preferable.
  • operations and effects similar to those of the first and second embodiments can be obtained.
  • FIGSixth and seventh embodiments 11 and 12 show drive control devices 61 and 62 configured by separating the control unit and the drive circuit.
  • the drive control devices 61 and 62 drive and control the two semiconductor elements 1A and 1B constituting the half bridge circuit 4.
  • the drive control device 61 includes a control IC 63, photocouplers 64A and 64B, drive ICs 65A and 65B, a current detection circuit 60, and the like.
  • the control IC 63 includes a dedicated ASIC, a microcomputer hardware IP (Intellectual Property), an FPGA, and the like, and the Vf control unit 26 and the pulse control unit 27 described above are mounted thereon.
  • the photocouplers 64A and 64B are insulation circuits that electrically insulate the gate drive signals SGH and SGL and transmit them to the drive ICs 65A and 65B.
  • the drive ICs 65A and 65B include a drive circuit 28, which receives gate drive signals SGH and SGL and outputs gate drive voltages VGH and VGL.
  • the current detection circuit 60 detects a load current with the hall sensor 59 or the like, and outputs a current detection signal to the control IC 63.
  • the drive control device 62 includes photocouplers 67A and 67B that receive the sense voltages VSH and VSL and a current polarity detection circuit 68 in place of the hall sensor 59 and the current detection circuit 60.
  • the current polarity detection circuit 68 detects the value of current flowing in the semiconductor elements 1A and 1B or the direction (polarity) of the current. That is, the magnitude of the current may be detected or only the polarity of the current may be detected. Thereby, pulse control and Vf control for RC-IGBT can be executed.
  • the pulse control unit 27 can prohibit the application of the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements 1A and 1B. . Thereby, an arm short circuit can be prevented reliably.
  • Example 7 As in the fourth embodiment, either one of the photocouplers 67A and 67B may be omitted. At this time, the sense elements (5s, 6s) and the sense resistor (7) corresponding to the omitted photocouplers 67A and 67B may be omitted.
  • the current polarity detection unit 68 estimates the polarity of the current flowing in the other (for example, the semiconductor element 1A) based on the polarity detection signal of the current flowing in one (for example, the semiconductor element 1B).
  • a photocoupler having the same configuration as that of the photocouplers 67A and 67B may be provided not in the previous stage of the current polarity detection unit 68 but in the subsequent stage of the current polarity detection unit 68.
  • the current detection circuit 60 and the current polarity detection circuit 68 may be formed in the control IC 63 or the drive IC 65.
  • FIG. 13 and 14 show drive control devices 71 and 72 having a configuration in which the control unit and the drive circuit are separated and the Vf control unit 26, the pulse control unit 27, and the current detection unit 25 are incorporated in the microcomputer 21. .
  • the drive control devices 71 and 72 drive and control the two semiconductor elements 1A and 1B constituting the half bridge circuit 4.
  • the drive control device 71 includes the microcomputer 21, photocouplers 64A and 64B, drive ICs 65A and 65B, and the like.
  • the drive control device 72 includes photocouplers 67A and 67B that receive the sense voltages VSH and VSL.
  • the microcomputer 21 implements the functions of the Vf control unit 26, the pulse control unit 27, and the current detection unit 25 described above by executing a control program stored in advance in the memory 73.
  • the microcomputer 21 of the drive control device 71 receives a sense signal from the hall sensor 59 and obtains a current detection signal.
  • the microcomputer 21 of the drive control device 72 obtains a current detection signal via the output signals of the photocouplers 67A and 67B.
  • the memory 73 also stores a first time T1, a second time T2, a threshold value, and the like.
  • the pulse control unit 27 can prohibit the application of the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements 1A and 1B. . Thereby, an arm short circuit can be prevented reliably.
  • the Vf control unit 26 and the pulse control unit 27 can collectively control the one and other arms. According to this embodiment, the same operation and effect as those of the first and second embodiments can be obtained.
  • Example 9 as in the fourth embodiment, either one of the photocouplers 67A and 67B may be omitted.
  • the sense elements (5s, 6s) and the sense resistor (7) corresponding to the omitted photocouplers 67A and 67B may be omitted.
  • the current polarity detection unit 68 estimates the polarity of the current flowing in the other (for example, the semiconductor element 1A) based on the polarity detection signal of the current flowing in one (for example, the semiconductor element 1B).
  • Each embodiment may be changed to a configuration in which only the Vf control is performed among the Vf control by the Vf control unit 26 and the pulse control by the pulse control unit 27, or a configuration in which only the pulse control is performed.
  • the Vf control unit 26 applies the gate drive voltage to one of the semiconductor elements 1A and 1B during the other semiconductor element. Of course, the application of the gate drive voltage to is prohibited.
  • the configuration for inputting the switching signal Sk and the threshold voltage Vt (setting of the current threshold value It) may be provided as necessary.
  • the Vf control unit 26 and the pulse control unit 27 stop the Vf control and the pulse control and perform the normal control when the magnitude of the load current becomes smaller than the specified values Im1 and Im2, respectively.
  • the switching control may be executed as necessary.
  • the current detection unit 25 may obtain a current detection signal by inputting a sense signal of the Hall sensor 59 instead of the sense voltages VSH and VSL.
  • the Vf control and the pulse control may be stopped and the normal control may be performed, respectively.
  • the control switching function between the region 1 and the region 2 may be omitted from the Vf control unit 26. That is, the Vf control unit 26 always applies the gate drive voltage VGL to the gate of the semiconductor element 1B while the PWM signal FL is at the H level.
  • the Vf control unit 26 determines that the current flows in the forward direction of the diode element 6 in the semiconductor element 1B during the period, the Vf control unit 26 determines that the second time T2 has elapsed (time t6) as in the second embodiment. ) To extend the pulse.
  • a threshold value specifying signal for specifying the current threshold value It can be input from the outside, and threshold setting circuits 29A and 29B are provided. Good. Further, the threshold setting circuits 30A, 30B, 31A and 31B may be provided, and when the magnitude of the load current becomes smaller than the specified values Im1 and Im2, the Vf control and the pulse control are stopped and the normal control is performed.
  • the third to ninth embodiments can be applied to the configuration using MOS transistors for the semiconductor elements 1A and 1B in the same manner as the second embodiment.
  • the semiconductor elements 1A and 1B may be elements having a control gate and having a parasitic diode formed thereon, for example, diodes having MOS gates.
  • the RC-IGBT is not limited to the trench gate type but may be a planar gate type.
  • the MOS transistor is not limited to a trench gate type but may be a planar gate type.
  • the MOS transistor may have an SJ (Super Junction) structure.
  • the sense resistors 7A and 7B are provided as the current detection means after forming the sense elements in the semiconductor elements 1A and 1B.
  • a hall sensor 59 is provided.
  • sense resistors 7A and 7B may be provided in series with the semiconductor elements 1A and 1B excluding the sense elements. Since the sense resistors 7A and 7B and the main element are directly connected, high response is possible.
  • Hall sensors 59A and 59B may be provided for the semiconductor elements 1A and 1B. In any configuration, the current can be detected with high accuracy.
  • an insulated current sensor such as a GMR (Giant Magneto Resistance) sensor may be used instead of the Hall sensor.
  • the operation region of the drive control system is always region 1, so that the control switching function is omitted, and in the configuration shown in FIG.
  • the current detection unit 25 or the current detection circuit 60 may be replaced with the current polarity detection circuit 68, and the pulse control and the Vf control may be executed similarly to the seventh embodiment.
  • application of the gate drive voltage to the other semiconductor element can be prohibited while the gate drive voltage is applied to one of the semiconductor elements 1A and 1B.
  • the current polarity detection circuit 68 can estimate the polarity of the current flowing through the other semiconductor element based on the polarity detection signal of the current flowing through the one semiconductor element.
  • the current polarity detection circuit 68 is based on the collector-emitter voltage (or drain-source voltage) or the gate drive voltages VGH, VGL of the transistor element 5 instead of the sense voltages VSH, VSL generated in the sense resistors 7A, 7B. The polarity of the current flowing through the semiconductor elements 1A and 1B can be detected.
  • FIGS. 17 to 18 show a tenth embodiment, in which semiconductor elements 101A and 101B are used instead of the semiconductor elements 1A and 1B, and a voltage detector 125 is used instead of the current detector 25.
  • FIG. The same or similar components are denoted by the same or similar reference numerals and description thereof is omitted.
  • the semiconductor elements 101A and 101B are reverse conducting IGBTs (RC-IGBTs) in which the insulated gate transistor element 105 and the diode element 106 are formed on the same semiconductor substrate 8, and the transistor elements 5 of the above-described embodiment Main elements (transistor element 105 and diode element 106) respectively corresponding to the diode element 6 are shown.
  • the current-carrying electrodes (collector and emitter) of the transistor element 105 and the current-carrying electrodes (cathode and anode) of the diode element 106 are common electrodes.
  • a sense element for detecting the collector potential (corresponding to the electrode potential) of the main element is configured on the semiconductor substrate.
  • the conducting electrodes (collector and emitter) of the sense transistor 105s and the conducting electrodes (cathode and anode) of the sense diode 106s are common electrodes.
  • the gate and emitter of the insulated gate type sense transistor 105s are connected in common.
  • Sense resistors 107A and 107B are connected between the emitter electrode of the sense transistor 105s and the emitter electrode of the transistor element 105.
  • the sense resistors 107A and 107B constitute a voltage detection unit together with the voltage detection unit 125.
  • the voltage detection part 125 is comprised in drive IC124A, 124B replaced with drive IC24A, 24B.
  • the drive ICs 124A and 124B are configured with a Vf control unit 26, a pulse control unit 27, and a drive circuit 28.
  • the configurations of the Vf control unit 26, the pulse control unit 27, and the drive circuit 28 are denoted by the same reference numerals in the drawing because the control method is similar to that of the above-described embodiment. Since the drive ICs 124A and 124B have the same configuration, only the configuration of the voltage detection unit 125, which is a different part in the drive IC 124B, will be described.
  • the voltage detector 125 is a voltage detector that outputs a voltage detection signal of the semiconductor element 101B based on the sense voltage VSL generated in the sense resistor 107B.
  • the voltage detector 125 detects a divided voltage divided by the voltage across the sense diode 106s and the sense resistors 107A, 107B.
  • the Vf control unit 26 and the pulse control unit 27 generate the gate drive signal SGL based on the PWM signal FL.
  • the drive circuit 28 receives the gate drive signal SGL and outputs a gate drive voltage VGL. Since other configurations are the same as those of the above-described embodiment, detailed description thereof is omitted. Further, although the operation is almost the same as that of the first embodiment, the pulse control which is different from the first embodiment will be described with reference to FIG.
  • the semiconductor element 101B is gated. It is the same in that a drive pulse is applied. However, the condition determination for applying the gate drive pulse is different from that in the first embodiment.
  • the collector-emitter voltage of the semiconductor element 101A increases.
  • the collector electrode potential Vco of the semiconductor element 101B decreases.
  • the voltage detector 125 can detect the decrease timing of the electrode potential Vco by the sense elements (105s, 106s). Note that the collector-emitter voltage of the semiconductor element 101A gradually increases in the mirror period and then rapidly increases. For this reason, the collector electrode potential Vco gradually decreases during the mirror period, and then rapidly decreases.
  • the voltage detector 125 detects the decrease timing of the collector electrode potential Vco during the above-described mirror period (time t1a).
  • the Vf control unit 26 can detect a decrease in the electrode potential Vco by the voltage detection unit 125 and estimate the polarity according to the relationship between the on / off command signal of the input PWM signal FL and the collector electrode potential Vco.
  • the Vf control unit 26 of the driving IC 124B determines whether or not to input the ON command signal of the PWM signal FL from the time (t1a) when it is detected that the collector electrode potential Vco has decreased, and when the ON command signal is input
  • the L level gate drive signal SGL is output to (time t2 to t3).
  • a gate drive voltage VGL corresponding to the gate drive signal SGL is applied to the gate of the semiconductor element 101B.
  • the gate drive voltage VGL is cut off.
  • the polarity determination is continued.
  • FIG. 25 and FIG. 26 show reference diagrams of the change characteristics of the collector electrode potential according to the direction and magnitude of the load current.
  • the load current is defined as negative in the direction in which current flows from the load to the node Nt shown in FIG. 17 (left column in FIG. 25A), and the load current is defined as positive in the direction flowing out from the node Nt in FIG. 25 (a) right column).
  • FIG. 25B which is an enlarged view of the portion NM in FIG. 25A
  • the collector electrode potential Vco increases in principle. Since the current flows out from the node Nt to the load side when the load current is positive, an enlarged view of the portion NP in FIG. 25A is shown in FIG. Lower.
  • the detection voltage by the voltage detection unit 125 is determined according to the balance of the on-resistance of the semiconductor elements 101A and 101B.
  • the collector electrode potential Vco largely fluctuates or causes chattering.
  • the Vf control unit 26 continues to output the L level gate drive signal SGL.
  • the Vf control unit 26 instructs the PWM signal FL to A gate drive signal SGL that matches the signal is output. In this case, control response performance can be improved.
  • the collector electrode potential Vco may be input before the timing at which the voltage rapidly decreases.
  • the Vf control unit 26 performs the same control as described above on the condition that the voltage detection unit 125 detects that the collector electrode potential Vco rapidly decreases within a predetermined time from the input time point of the ON command signal of the PWM signal FL.
  • the gate drive signal SGL may be output by a technique.
  • the voltage detection unit 125 can detect the increase timing of the electrode potential Vco by the divided voltage of the voltage of the diode 6 and the voltage of the resistor 107A by the sense elements (105s, 106s).
  • the pulse control unit 27 receives the OFF command signal of the PWM signal FL (time t3).
  • the gate drive signal SGL is set to the H level from the elapsed time (time t4) of the first time T1 to the elapsed time (time t6) of the second time T2.
  • a gate drive pulse VGL is applied to the gate of the semiconductor element 101B.
  • the pulse control unit 27 determines whether or not the voltage of the voltage detection unit 125 has changed, so that a current flows through the diode element 106 of the semiconductor element 101B. Continue to determine whether or not. On the other hand, if the pulse control unit 27 determines that no current flows through the diode element 6 when the PWM signal FL falls to the L level, the pulse control unit 27 immediately maintains the gate drive signal SGL at the L level. That is, no gate drive pulse is applied.
  • the first time T1 and the second time T2 shown in FIG. 18 are set in advance so as not to cause an arm short circuit.
  • the waveform of the gate drive voltage VGL when a gate drive pulse is applied differs between when the current flows through the diode element 106 and when the current flows through the transistor element 105 while the PWM signal FL is at the L level. .
  • the drive circuit 28 can output the gate drive voltage VGL with a higher gate drive capability than usual when the gate drive voltage VGL rises and falls.
  • the first time T1 and the second time T2 take into account the waveform of the gate drive voltage VGL when the gate drive pulse is applied and the drive mode of the drive circuit 28, and the gate drive voltage VGL is monotonous according to the gate drive capability of the drive circuit 28. It is set to increase or decrease monotonically.
  • the time Tc carrier reinjection time
  • the allowable injection time is specified according to the allowable reverse recovery current.
  • the first time T1 and the second time T2 change the current flowing through the diode element 106 in various ways, starting from the falling point of the PWM signal FL, and the application timing of the gate drive signal SGL, actually the gate
  • the timing at which the drive voltage VGL is applied and the timing at which the reverse recovery current starts to flow are set in advance by measurement.
  • the first time T1 and the second time T2 are stored in a memory or the like in the pulse control unit 27 in this embodiment.
  • the first time T1 and the second time T2 can also be configured using one or several patterns of logic circuits or analog delay circuits.
  • the pulse control unit 27 reads the first time T1 and the second time T2 from the memory when applying the gate drive pulse.
  • the pulse control unit 27 starts the gate drive signal SGL at the time when the first time T1 has elapsed, and lowers the gate drive signal SGL at the time when the second time T2 has elapsed, starting from the detection timing of the decrease in the collector electrode potential Vco.
  • FIG. 19 shows an eleventh embodiment, and shows a timing chart when conduction loss can be reduced by performing synchronous rectification using MOS transistors or the like for the semiconductor elements 101A and 101B.
  • the configuration of the drive control devices 132A and 132B is as shown in FIG. Here, the operation of the drive control device 132B on the low side will be mainly described. The operation of the drive control device 132A on the high side is the same.
  • the MOS transistor as shown in FIG. 6, in the region 1 where the voltage VDS ⁇ the voltage Vf, the conduction loss can be reduced by applying the gate drive voltage. In region 2 where voltage VDS ⁇ voltage Vf, conduction loss can be reduced by cutting off the gate drive voltage.
  • the voltage detector 125 detects the decrease timing of the collector electrode potential Vco during the above-described mirror period (time t1a).
  • the Vf control unit 26 can detect a decrease in the electrode potential Vco by the voltage detection unit 125 and estimate the polarity according to the relationship between the on / off command signal of the input PWM signal FL and the collector electrode potential Vco.
  • the Vf control unit 26 of the driving IC 124B determines whether or not to input the ON command signal of the PWM signal FL from the time (t1a) when it is detected that the collector electrode potential Vco has decreased, and when the ON command signal is input H level gate drive signal SGL is output at time t2 to t3. At this time, a gate drive voltage VGL corresponding to the gate drive signal SGL is applied to the gate of the semiconductor element 101B.
  • the Vf control unit 26 performs normal control (synchronous rectification) for applying the gate drive voltage VGL. Execute. Thereafter, when the PWM signal FL becomes L level, the Vf control unit 26 applies a gate drive pulse to the semiconductor element 101B.
  • the pulse control unit 27 may set the gate drive signal SGL to the H level from the time when the first time T1 has elapsed to the time when the second time T2 has elapsed, starting from the input time of the off command signal.
  • the conduction loss can be reduced by continuously applying the gate drive voltage VGL until the second time T2 elapses, rather than once interrupting the gate drive voltage VGL. Therefore, since the Vf control unit 26 performs pulse control following the Vf control, the Vf control unit 26 may output the H-level gate drive signal SGL by extending it beyond the time t3 to the lapse of the second time T2 (time t6). (Pulse extension).
  • the control means (Vf control unit 26 or pulse control unit 27) outputs the ON command signal input time (t2) retroactively so as to follow the normal Vf control by the Vf control unit 26.
  • pulse control may be performed (refer to the expansion of the pulse in the interval from time t1b ⁇ t2).
  • the gate drive voltage VGL is from the time when the gate drive voltage VGH becomes less than the threshold voltage Vth (ie, when the current stops flowing) to the time when the threshold voltage Vth is reached again (ie when the current starts flowing). Can be raised.
  • the Vf control unit 26 and the pulse control unit 27 From the time when the gate drive signal SGL is given until the gate drive voltage VGL is raised, the Vf control unit 26 and the pulse control unit 27 generate delay times for performing various processes such as a signal generation process. This delay time is measured in advance using experiments, simulations, and the like, and the Vf control unit 26 and the pulse control unit 27 drive the gate so that no arm short circuit occurs during the period when the gate drive voltage VGL is increased. It is preferable to extend the pulse of the signal SGL.
  • a margin time (margin time Ma in FIG. 19) between the timing when the gate driving voltage VGH becomes less than the threshold voltage Vth (that is, when the current stops flowing) and the timing when the gate driving voltage VGL becomes equal to or higher than the threshold voltage Vth. It is good to provide.
  • a margin time (margin time Mb in FIG. 19) is provided between the timing when the gate drive voltage VGL becomes lower than the threshold voltage Vth and the timing when the gate drive voltage VGH becomes equal to or higher than the threshold voltage Vth (that is, when current flows). good.
  • delay variation from when the voltage is detected by the voltage detection unit 125 until actual control is performed (variation of the voltage detection unit 125, configuration variation of the semiconductor element 101A, etc., change in temperature characteristics, aging deterioration, etc.
  • the voltage detector 125 detects the decrease timing of the collector electrode potential Vco during the above-described mirror period (time t1a).
  • the Vf control unit 26 can detect a decrease in the electrode potential Vco by the voltage detection unit 125 and estimate the polarity according to the relationship between the on / off command signal of the input PWM signal FL and the collector electrode potential Vco. This polarity estimation method is the same as the method shown in the tenth embodiment.
  • the Vf control unit 26 executes normal control (synchronous rectification) in which the gate drive voltage VGL is applied. Thereafter, when the PWM signal FL becomes L level, it is necessary to apply a gate drive pulse to the semiconductor element 101B.
  • the pulse control unit 27 starts from the time when the PWM signal FL falls and the second time T2 elapses from the time when the first time T1 elapses.
  • the gate drive signal SGL may be kept at the H level until the time point.
  • the conduction loss can be reduced by continuously applying the gate drive voltage VGL until the second time T2 elapses, rather than once interrupting the gate drive voltage VGL. Therefore, the Vf control unit 26 performs pulse control following the Vf control, and outputs the H-level gate drive signal SGL by extending it beyond the time t3 until the elapse of the second time T2 (time t6) ( Pulse expansion).
  • the detection process from the time point t1a to the time point t2 is performed by the same method as in the tenth embodiment.
  • the Vf control unit 26 keeps the gate drive signal SGL at the H level after the time point t2, the condition that the load current is close to zero. Even when the polarity of the load current is reversed, the chattering described in the tenth embodiment is not caused. Therefore, the Vf control unit 26 may continue to output the H level gate drive signal SGL as it is from time t2 to time t6.
  • FIG. 20 shows a twelfth embodiment
  • FIG. 21 shows a thirteenth embodiment, both of which show drive control devices 152 and 154 using drive ICs 151 and 153 having a high breakdown voltage.
  • the high breakdown voltage is a breakdown voltage according to the power supply voltage applied to the half bridge circuit 4.
  • the drive control devices 152 and 154 drive and control the two semiconductor elements 101A and 101B constituting the half bridge circuit 4.
  • the drive ICs 151 and 153 are provided with a common Vf control unit 26 and a common pulse control unit 27 for the semiconductor elements 101A and 101B, and operate when supplied with a power supply voltage VDD (for example, 15V).
  • VDD power supply voltage
  • the gate drive signal SGH is given to the semiconductor element 101A via the level shift unit 57 and the drive circuit 28, and the gate drive signal SGL is given to the semiconductor element 101B via the drive circuit 28.
  • the drive IC 151 includes a voltage detection unit 125 that outputs a voltage detection signal based on the sense voltages VSH and VSL generated in the sense resistors 107A and 107B.
  • the high-side voltage detection unit 125 outputs a voltage detection signal via the level shift circuit 58.
  • the drive IC 153 has a configuration in which the high-side voltage detection unit 125 and the level shift circuit 58 are omitted.
  • the pulse control unit 27 Since the pulse control unit 27 generates the gate drive signals SGH and SGL, the gate drive voltage applied to the other semiconductor element during the period when the gate drive voltage is applied to one of the two semiconductor elements 101A and 101B. Can be prohibited. Thereby, an arm short circuit can be prevented reliably.
  • the circuit configuration can be simplified.
  • the sense elements (105s, 106s) and the sense resistor (107) corresponding to the voltage detection unit 125 omitted by sharing may be omitted.
  • sharing it is preferable to set the specified voltage on the high side larger than that in the tenth embodiment based on the specified voltages Vm1 and Vm2 generated by the threshold setting circuits 30 and 31.
  • operations and effects similar to those of the tenth and eleventh embodiments can be obtained.
  • FIG. 22 shows a fourteenth embodiment and shows a drive control device 162 configured by separating a control unit and a drive circuit.
  • the drive control device 162 controls the drive of the two semiconductor elements 101A and 101B constituting the half bridge circuit 4.
  • the drive control device 162 includes a control IC 163, photocouplers 64A, 64B, 67A, 67B, drive ICs 65A, 65B, a voltage detection unit 168, and the like.
  • the control IC 163 includes a dedicated ASIC, a microcomputer hardware IP (Intellectual Property), an FPGA, and the like, and the Vf control unit 26 and the pulse control unit 27 described above are mounted thereon.
  • the photocouplers 64A and 64B are insulation circuits that electrically insulate the gate drive signals SGH and SGL and transmit them to the drive ICs 65A and 65B.
  • the drive ICs 65A and 65B include a drive circuit 28, which receives gate drive signals SGH and SGL and outputs gate drive voltages VGH and VGL.
  • the voltage detector 168 detects the sense voltages VSH and VSL through the photocouplers 67A and 67B.
  • the voltage detection unit 168 can detect the value of the current flowing in the semiconductor elements 101A and 101B or the direction (polarity) of the current based on the divided voltage of the voltage applied to the sense elements 105s and 106s and the voltage applied to the resistors 107A and 107B. Thereby, pulse control and Vf control for RC-IGBT can be executed.
  • the pulse control unit 27 can prohibit the application of the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements 101A and 101B. . Thereby, an arm short circuit can be prevented reliably. Further, either one of the photocouplers 67A and 67B may be omitted. At this time, the sense elements (105s, 106s) and the sense resistor (107) corresponding to the omitted photocouplers 67A and 67B may be omitted. In this case, the voltage detection unit 168 estimates the polarity of the current flowing through the other semiconductor element 101A based on the polarity detection signal of the current flowing through the semiconductor element 101B.
  • a photocoupler having a configuration similar to that of the photocouplers 67A and 67B may be provided not in the previous stage of the voltage detection unit 168 but in the subsequent stage of the voltage detection unit 168.
  • the voltage detection unit 168 may be formed in the control IC 63 or the drive IC 65.
  • the Vf control unit 26 and the pulse control unit 27 can collectively control the one and the other arms. Also according to this embodiment, the same operation and effect as those of the tenth and eleventh embodiments can be obtained.
  • FIG. 23 shows a fifteenth embodiment, in which a controller and a drive circuit are separated, and a drive controller 172 having a configuration in which a Vf controller 26, a pulse controller 27, and a voltage detector 125 are incorporated in a microcomputer 121. Is shown.
  • the drive control device 172 controls the drive of the two semiconductor elements 101A and 101B constituting the half bridge circuit 4.
  • the drive control device 172 includes a microcomputer 121, photocouplers 64A and 64B, drive ICs 65A and 65B, and the like.
  • the drive controller 172 includes photocouplers 67A and 67B that receive the sense voltages VSH and VSL.
  • the microcomputer 121 implements the functions of the Vf control unit 26, the pulse control unit 27, and the voltage detection unit 125 described above by executing a control program stored in advance in the memory 73.
  • the microcomputer 121 of the drive control device 172 obtains a voltage detection signal via the output signals of the photocouplers 67A and 67B.
  • the memory 73 also stores a first time T1, a second time T2, a threshold value, and the like.
  • the microcomputer 121 can prohibit the application of the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements 101A and 101B. Thereby, an arm short circuit can be prevented reliably. Further, either one of the photocouplers 67A and 67B may be omitted. At this time, the sense elements (105s, 106s) and the sense resistor (107) corresponding to the omitted photocouplers 67A and 67B may be omitted. In the case of sharing, it is preferable to set the specified voltage on the high side larger than that in the tenth embodiment based on the specified voltages Vm1 and Vm2 generated by the threshold setting circuits 30 and 31. In addition, operations and effects similar to those of the tenth and eleventh embodiments can be obtained.
  • the Vf control unit 26 and the pulse control unit 27 can collectively control the one and the other arms.
  • the photocoupler 67A may be omitted. Also in these embodiments, the same operations and effects as those in the tenth and eleventh embodiments can be obtained.
  • FIG. 24 shows a sixteenth embodiment and shows a mode in which a voltage detection unit 180 is provided as voltage detection means for detecting a voltage of an intermediate potential. 24 is provided so as to detect the potential of the guard ring 8a provided on the semiconductor substrate 8 on the outer peripheral side of the element formation region 100 of the transistor element 105 and the diode structure 106.
  • the voltage detector 180 shown in FIG. The cathode region 17 of the diode structure 6 and the collector electrode 18 of the transistor structure 5 are formed on the lower surface side layer portion of the semiconductor substrate 8. The region 101 is reached.
  • a guard ring 8a is formed in the pressure resistant holding region 101.
  • a plurality of guard rings 8a are formed.
  • the guard ring 8a is formed in a conductivity type different from that of the semiconductor layer 8 (in this case, p + (reverse conductivity type)), and is formed concentrically in a plan view so as to surround the outer periphery of the element formation region 100. Has been.
  • an n + equivalent potential ring (EQR) 8b having the same conductivity type as that of the semiconductor substrate 8 is formed as a channel stopper region in the outermost peripheral region which is the outer peripheral region of the guard ring 8a of the semiconductor substrate 8.
  • the guard rings 8a are formed to be separated from each other on the outer peripheral edge side of the semiconductor substrate 8, and are provided to alleviate the electric field generated between the outermost equivalent potential ring 8b and the source electrode provided on the element forming region 100 side. ing.
  • the potential of these guard rings 8a decreases step by step from the outer peripheral side and can maintain a withstand voltage.
  • the voltage detector 180 can detect the intermediate potential between the collector and emitter by detecting the voltage from the upper part of any one of the guard ring 8a layers.
  • the change in the intermediate potential is the same change as the change in the collector electrode potential VCO described in the above-described embodiment, and even if the voltage detection unit 180 detects the intermediate potential as described above, it can be controlled similarly.
  • the voltage detection unit 180 shown in this embodiment can be used in place of the voltage detection unit 125 of the tenth to fifteenth embodiments, or may be used together with the voltage detection unit 125. Further, it may be used in combination with the configuration of the current detection means (7A, 7B, 25, 59, 60, 68) shown in the respective embodiments of the first to ninth embodiments.
  • the intermediate potential detected from the voltage detection unit 180 may be further stepped down by resistance division or the like as necessary.
  • Each embodiment may be changed to a configuration in which only the Vf control is performed among the Vf control by the Vf control unit 26 and the pulse control by the pulse control unit 27, or a configuration in which only the pulse control is performed.
  • the Vf control unit 26 applies the gate drive voltage to one of the semiconductor elements 1A and 1B during the other semiconductor element. Of course, the application of the gate drive voltage to is prohibited.
  • the Vf control unit 26 and the pulse control unit 27 stop the Vf control and the pulse control and perform the normal control when the magnitude of the detected voltage becomes smaller than the specified value, respectively. What is necessary is just to perform as needed.
  • the Vf control and the pulse control may be stopped and the normal control may be performed, respectively.
  • the control switching function between the region 1 and the region 2 may be omitted from the Vf control unit 26. That is, the Vf control unit 26 always applies the gate drive voltage VGL to the gate of the semiconductor element 1B while the PWM signal FL is at the H level. If the Vf control unit 26 determines that a current flows in the forward direction of the diode element 6 in the semiconductor element 1B during the period, the second time T2 elapses from the time t2 as in the eleventh embodiment. The pulse is expanded until the time (time t6).
  • the twelfth to sixteenth embodiments can be applied to a configuration using MOS transistors for the semiconductor elements 101A and 101B in the same manner as the eleventh embodiment.
  • the semiconductor elements 101A and 101B may be elements having a control gate and formed with a parasitic diode, for example, a diode having a MOS gate.
  • the RC-IGBT is not limited to the trench gate type but may be a planar gate type.
  • the MOS transistor is not limited to a trench gate type but may be a planar gate type.
  • the MOS transistor may have an SJ (Super Junction) structure.
  • the sense diode 106s is configured alone as a sense element, and the voltage detection unit 125 has a direct current voltage applied to both ends of the sense element ( DC voltage) may be detected.
  • DC voltage DC voltage
  • These configurations can be used not only for voltage detection but also for current detection.
  • a DC voltage DC voltage
  • the sense transistor 105s may be used alone as a sense element. In this case, since the sense transistor 105s functions as a transistor capacitance, a voltage change can be detected as a pulse voltage / current.
  • the current detection unit 25 detects the current of the semiconductor element 1A, and at the time t1c when the fluctuation of this current is detected, the Vf control unit 26 precedes t2.
  • the pulse may be extended to output the gate drive signal SGL as the H level.
  • another form of the current detection unit 25 may be provided, or the current polarity detection circuit 68 of the seventh embodiment may be provided.
  • a voltage detector 225 for detecting the gate drive voltage VGH on the reverse arm side is provided as a control voltage detector based on the configuration shown in FIG. 17 and is detected by this voltage detector 225.
  • the Vf control unit 26 extends the pulse before t2 and outputs the gate drive signal SGL as the H level. You may do it.
  • Waveforms of control signals, drive signals, and the like at each node relating to Vf control and pulse control are the same as those in FIG.
  • the voltage detection unit 225 may be incorporated in the drive ICs 124A and 124B or may be configured independently of the drive ICs 124A and 124B.
  • a voltage detection unit 225 for detecting the gate drive voltage VGH on the reverse arm side is provided via the photocouplers 267A and 267B, respectively.
  • the Vf control unit 26 extends the pulse before t2 and outputs the gate drive signal SGL as the H level. You may do it.
  • the waveforms of control signals, drive signals, etc. at each node are the same as in FIG.
  • the voltage detection unit 225 shown in FIG. 29 may be incorporated in the control IC 63 or may be configured independently of the control IC 63.
  • the drive ICs 24A and 24B on the own arm side input the PWM signal FL or FH on the opposite arm side to the Vf control unit 26 (or pulse control unit 27), and the Vf control unit 26 (or At a timing when a predetermined time has elapsed since the pulse control unit 27) detected the fall of the PWM signal, the Vf control unit 26 performs pulse expansion before t2 and outputs the gate drive signal SGL as the H level. May be.
  • the predetermined time may be set to a predetermined time so as not to short-circuit between the arms in advance.
  • the drive ICs 124A and 124B on the own arm side input the PWM signal FL or FH on the opposite arm side to the Vf control unit 26 (or pulse control unit 27), and the Vf control unit 26 (or At a timing when a predetermined time has elapsed since the pulse control unit 27) detected the fall of the PWM signal, the Vf control unit 26 performs pulse expansion before t2 and outputs the gate drive signal SGL as the H level. May be.
  • the predetermined time may be set to a predetermined time so as not to short-circuit between the arms in advance.
  • FIGS. 28 to 31 show an example.
  • the current detection means current detection unit 25, hall sensor 59, current detection circuit 60, current polarity detection circuit 68 shown in the first to ninth embodiments is shown.
  • Etc. a combination of any two of the voltage detection means (voltage detection section 125, voltage detection section 168, etc.) and control voltage detection means (voltage detection section 225) shown in the tenth to fifteenth embodiments. You may do it.
  • the Vf control unit 26 expands the pulse from the time point t1b before the time point t2 to drive the gate without causing an arm short circuit.
  • the signal SGL can be output as an H level.
  • the margin period Ma (see FIG. 19) of the gate drive voltage VGL can be made the shortest ( ⁇ 0).
  • the form in which the PWM signals FH and FL on the reverse arm side are input to the Vf control unit 26 or the pulse control unit 27 of the drive ICs 24A and 24B on the own arm side is determined by the current detection unit 25, the voltage detection unit 125, and the voltage detection unit 225. Or you may combine with the form which detects and controls a voltage.
  • the falling detection time of the collector electrode potential Vco is the semiconductor element 101A. It can be seen that it is faster than the current falling point.
  • the forward direction of the diode structure 6 is based on the voltage detection signal.
  • the gate drive voltage VGL rises, the timing at which the current starts to flow to the semiconductor element 101A t1c (for example, the current flows to the semiconductor element 101B), as shown in FIG.
  • the gate drive signal SGL may be pulse-expanded from the time point t1b before the timing t2 so as to be later than the timing at which it flows out.
  • a predetermined delay time is required until the gate drive voltage VGL is generated after the pulse is extended and the gate drive signal SGL is output. For this reason, the delay time may be measured in advance, and the timing t1b at which the pulse expansion starts may be set in advance before the time t2 in anticipation of the measurement time.
  • various delay variations occur in the voltage detection unit 125, the driver 28, the semiconductor elements 101A and 101B, and the delay variation is measured in advance to allow for a margin. good.
  • the timing of the pulse expansion start can be determined at the time when the voltage fluctuation is detected (t1a). It is not necessary to set the timing for starting the pulse expansion before the time t2 after measurement in advance.
  • the pulse expansion of the eleventh embodiment performed by the Vf control unit 26 is performed at a faster time point than when the control is performed using only the current detection means described in the first to ninth embodiments.
  • the time required for the gate driving process can be secured and the synchronous rectification period can be extended, and the maximum effect can be obtained.
  • 1A, 1B, 101A and 101B are semiconductor elements
  • 4 is a half-bridge circuit
  • 5 and 105 are transistor elements (transistor structure)
  • 6 and 106 are diode elements (diode structure)
  • 7A, 7B, 107A and 107B are Sense resistor (current detection means)
  • 8 is a semiconductor substrate
  • 8a is a guard ring (electric field limiting ring)
  • 15 is an emitter electrode (energized electrode)
  • 18 is a collector electrode (energized electrode)
  • 21 and 121 are microcomputers (control IC) 24A, 24B, 124A, 124B, 51, 53, 55, 151, and 153 are drive ICs (ICs)
  • 25 is a current detector (current detector)
  • 125 and 168 are voltage detectors (voltage detector)
  • 26 Is a Vf control section (control means, second control means, input means)
  • 27 is a pulse control section (control means, first control means, input means)
  • FIG. 33 (corresponding to FIG. 1 of the first embodiment) which is a basic configuration.
  • the drive control system shown in FIG. 33 is used in a power conversion device such as an inverter device that drives an inductive load such as a motor or a converter device that includes an inductor and boosts / steps down a DC voltage.
  • the semiconductor elements 1001A and 1001B which are switching elements, are arranged in series with the output terminal Nt sandwiched between the high potential side DC power supply line 1002 and the low potential side DC power supply line 1003 to form a half-bridge circuit 1004. is doing.
  • the gate drive signal SGL generated by the Vf control unit 1026 and the pulse control unit 1027 is given to the gate of the semiconductor element 1001B through the drive circuit 1028.
  • the drive circuit 1028 can switch the gate drive capability in a plurality of ways as shown in FIG.
  • the drive circuit 1028 drives the gate by the MOS transistor 1029 when it is turned on.
  • the output voltage (A side) of the constant current drive amplifier 1031 or the voltage of the floating ground FG (B side) is applied to the gate of the MOS transistor 1029 via the changeover switch 1030.
  • the drive circuit 1028 performs a protection operation against a short-circuit current during driving in the case of normal driving capability. Therefore, the constant current drive amplifier 1031 temporarily keeps the gate drive voltage VGL at the intermediate voltage in the process of increasing the gate drive voltage VGL.
  • the drive circuit 1028 drives the gate by the MOS transistors 1032 and 1033 when turned off.
  • the changeover switch 1034 is switched to the A side and driven only by the MOS transistor 1032, normal driving capability is obtained, and when the changeover switch 1034 is switched to the B side and driven by the MOS transistors 1032, 1033, high driving capability is obtained.
  • the MOS transistor 1033 has a lower on-resistance than the MOS transistor 1032. Note that the MOS transistor 1033 is also used when the semiconductor element 1001B is held in an off state.
  • Threshold value setting circuits 1035A, 1036A, and 1037A are externally attached to the driving IC 1024A. Threshold setting circuits 1035B, 1036B, and 1037B are externally attached to the driving IC 1024B.
  • the threshold setting circuits 1029A, 1030A, 1031A are configured with a floating ground FG equal to the emitter potential of the semiconductor element 1001A as a reference potential.
  • the threshold setting circuits 1035A and 1035B divide the voltages VDDA and VDDB by the resistors R1 and R2 to generate the threshold voltage Vt.
  • the threshold setting circuits 1036A and 1036B divide the voltages VDDA and VDDB by the resistors R3 and R4 to generate the specified voltage Vm1.
  • the threshold setting circuits 1037A and 1037B divide the voltages VDDA and VDDB by the resistors R5 and R6 to generate a specified voltage Vm2.
  • the threshold voltage Vt determines the magnitude of the current threshold It used in the Vf control unit 1026.
  • the characteristic of the forward voltage Vf with respect to the forward current If of the diode element 1006 varies depending on the type of element (RC-IGBT, MOS transistor, etc.) and the breakdown voltage of the element. Therefore, the Vf control unit 1026 selects an appropriate current threshold It based on the switching signal Sk and the threshold voltage Vt given from the outside.
  • the specified voltage Vm1 determines the magnitude of the specified value Im1 used for determining whether or not to stop the Vf control.
  • the specified voltage Vm2 determines the magnitude of the specified value Im2 used for determining whether or not to stop the pulse control.
  • the drive control device 1038A is configured by the drive IC 1024A and the sense resistor 1007A described above, and the drive control device 1038B is configured by the drive IC 1024B and the sense resistor 1007B.
  • Vf control will be briefly described.
  • a gate drive voltage is applied to the semiconductor elements 1001A and 1001B that are RC-IGBTs while a current is flowing through the diode element 1006, a channel is formed in the first region 1012 and hole injection is suppressed.
  • the forward voltage Vf of the diode element 1006 through which the forward current If flows increases, and the conduction loss (Vf ⁇ If) of the diode element 1006 increases.
  • the conduction loss can be reduced by cutting off the gate drive voltage.
  • the current threshold It is substantially zero in the case of RC-IGBT, and is greater than zero in the case of a MOS transistor depending on the breakdown voltage or the like.
  • the switching signal Sk is switched to L level, for example, and when the MOS transistor is driven, the switching signal Sk is switched to H level, for example.
  • the Vf control unit 1026 sets the current threshold It according to the threshold voltage Vt and executes Vf control.
  • FIG. 38 shows a case where the semiconductor element 1001A is turned off and the semiconductor element 1001B is turned on and then the semiconductor element 1001B is turned off and the semiconductor element 1001A is turned on again when a current flows from the output terminal Nt toward the load. It is a waveform.
  • the current of the semiconductor element 1001A, the gate drive voltages VGH and VGL, the PWM signal FH, the gate drive signal SGL, and the PWM signal FL are shown.
  • Vth is a threshold voltage of the semiconductor element 1001A.
  • the Vf control unit 1026 of the driving IC 1024B determines whether or not the detected current of the diode element 1006 is equal to or higher than the current threshold It in the forward direction during the period when the PWM signal FL is at the H level (time t2 to t3). If it is determined that the detected current is greater than or equal to the current threshold It, an L level gate drive signal SGL is output as shown in FIG. As a result, the gate drive voltage VGL is cut off and the conduction loss is reduced.
  • pulse control when the current flows through the diode element 1006 of the semiconductor element 1001B during the period in which the PWM signal FL is at the H level, after the PWM signal FL falls to the L level and before the reverse recovery current starts to flow, This is control for applying a gate drive pulse to the semiconductor element 1001B.
  • carriers (holes) accumulated in the diode element 1006 are reduced, so that an effect of reducing the reverse recovery current can be obtained.
  • the pulse control unit 1027 has a current flowing through the diode element 1006 of the semiconductor element 1001B (the current detection value is equal to or greater than the specified value Im2).
  • the gate drive signal SGL is set to the H level from the time when the first time T1 has elapsed (time t4) to the time when the second time T2 has elapsed (time t6).
  • the gate drive signal SGL is at the L level at the time of falling of the PWM signal FL.
  • the pulse control unit 1027 continues to determine whether or not a current is flowing through the diode element 1006 of the semiconductor element 1001B even after the PWM signal FL falls to the L level. When the detected current value falls below the specified value Im2, the pulse controller 1027 immediately returns the gate drive signal SGL to the L level even after the first time T1 has elapsed and before the second time T2 has elapsed.
  • the pulse control unit 1027 determines that no current flows through the diode element 1006 when the PWM signal FL falls to the L level, the pulse control unit 1027 immediately maintains the gate drive signal SGL at the L level. That is, no gate drive pulse is applied.
  • the reinjection time Tc is controlled to be equal to or less than the allowable injection time corresponding to the allowable reverse recovery current.
  • FIG. 40 shows a case where the reinjection time Tc becomes zero. Actually, in order to prevent an arm short circuit, the reinjection time Tc is controlled to be equal to or longer than the short circuit margin time Tm (> 0).
  • the time (time t10) at which reverse recovery current begins to flow is delayed. For this reason, when the application end point of the gate drive voltage VGL is fixed starting from the falling point of the PWM signal FL (time t8), the reinjection time becomes Tc1 when the load current is 100A, and reinjection when the load current is 200A. Time becomes Tc2 (> Tc1). That is, the larger the load current, the longer the reinjection time, and the reverse recovery current increases. Further, since the carrier concentration itself stored in the diode element 1006 is higher as the load current is larger, in order to sufficiently reduce the carrier concentration and reduce the switching loss, the gate drive pulse width is ensured to some extent as shown in FIG. Therefore, it is necessary to secure a sufficient time for carrier reduction.
  • the pulse controller 1027 controls the application timing of the gate drive voltage VGL according to the load current.
  • the pulse control unit 1027 starts from the falling point of the PWM signal FL, and sets the time width Tw between the first time T1 when the gate drive signal SGL is set to the H level and the second time T2 when the gate drive signal SGL is returned to the L level.
  • the value is set according to the magnitude of the current flowing in the diode element 1006 during the H level period. Specifically, the longer time width is set as the current flowing through the diode element 1006 during the period when the PWM signal FL is at the H level is larger.
  • the application timing of the gate drive signal SGL and the actual gate drive voltage VGL are applied starting from the falling point of the PWM signal FL while changing the current flowing through the diode element 6 in various ways.
  • the timing at which the reverse recovery current starts to flow and the timing at which the reverse recovery current starts to flow are set in advance.
  • the first time T1 and the second time T2 are stored in a memory 1039 or the like (which may be designed with an analog circuit or the like) described later in association with the current.
  • FIG. 35 is a block diagram of the pulse control unit 1027 for the drive IC 1024B.
  • the memory 1039 receives the current detection signal and outputs the first time T1 and the second time T2 (or the first time T1 and the pulse width Tw) necessary for the pulse control.
  • the pulse start determining unit 1040 generates a rising timing signal of the gate drive signal SGL from the PWM signal FL and the first time T1.
  • the pulse width determination unit 1041 generates a falling timing signal of the gate drive signal SGL from the PWM signal FL and the second time T2 (or pulse width Tw).
  • the pulse generation unit 1042 generates a gate drive signal SGL based on these timing signals and outputs it to the drive circuit 1028.
  • the pulse start determination unit 1040 has a configuration shown in FIG. 36, for example. During the period when the PWM signal FL is at the H level, the MOS transistor 1044 is turned on by the gate voltage via the buffer 1043, so the voltage of the capacitor 1045 is zero. When the PWM signal FL falls to the L level, the MOS transistor 1044 is turned off, and the capacitor 1045 is charged by the constant current circuit 1046. The comparator 1047 compares the voltage of the capacitor 1045 with a reference voltage corresponding to the first time T1, and outputs a timing signal. The pulse width determination unit 1041 has the same configuration.
  • the first time T1 that is, the reference voltage output from the memory 1039 changes according to the current flowing in the diode element 1006 during the period in which the PWM signal FL is at the H level, and thereby the rise of the gate drive signal SGL. This shows how the timing signal changes.
  • the first time T1 may be stored in the memory 1039, and the read value may be changed according to the element current.
  • the waveform of the gate drive voltage VGL when a gate drive pulse is applied differs between when the current flows through the diode element 1006 and when the current flows through the transistor element 1005 while the PWM signal FL is at the L level. . Therefore, in consideration of the following items (1) to (3), it is assumed that the gate drive voltage VGL monotonously increases or monotonously decreases according to the gate drive capability of the drive circuit 1028.
  • the second time T2 (or the first time T1 and the pulse width Tw) is set.
  • Dead time Td The dead time Td of the PWM signals FH and FL is a fixed time.
  • FIG. 45 shows the reinjection time when the gate drive pulse timing is set assuming that the mirror period exists, and when the gate drive pulse timing is set assuming that the mirror period does not exist.
  • the reinjection time Tc when the reinjection time Tc is set assuming the mirror period, the actual reinjection time becomes longer than Tc because the mirror period does not actually occur.
  • the target reinjection time Tc can be set. Therefore, the timing of the gate drive pulse is set using the time excluding the mirror period. This also has an effect of ensuring a longer pulse width Tw of the gate drive pulse.
  • (3) Drive capability of drive circuit 1028 When a gate drive pulse is output, the drive circuit 1028 switches the changeover switches 1030 and 1034 (see FIG.
  • the gate drive voltage VGL is output with a high gate drive capability (here, the maximum gate drive capability). This is because, during the application period of the gate drive pulse, current continues to flow through the diode element 1006, so that a surge due to a steep current change does not occur.
  • the drive circuit 1028 outputs a gate drive voltage VGL while maintaining a certain gate drive capability when the gate drive voltage VGL is raised.
  • the other semiconductor element 1001A is short-circuited by temporarily holding the gate drive voltage VGL at the intermediate voltage Vm (for example, 12V) in the process of increasing the gate drive voltage VGL.
  • Vm for example, 12V
  • a method for reducing the short-circuit current is used.
  • a forward current flows through the diode element 1006 of the semiconductor element 1001B, there is no possibility of short-circuiting along the path through the semiconductor elements 1001A and 1001B. This eliminates the need for two-step driving using the intermediate voltage Vm.
  • the drive circuit 1028 maintains a high driving capability and outputs the gate drive voltage VGL. Deviation from time Tm can be reduced. That is, the reinjection time Tc can be accurately controlled. Further, variation in the pulse width Tw of the gate drive pulse is reduced, and a longer pulse width Tw can be secured.
  • the semiconductor elements 1001A and 1001B are in the order of the diode elements 1006 during the period when the PWM signals FH and FL are at the H level, respectively. If it is determined that the current is flowing in the direction, the gate drive signals SGH and SGL for instructing the application of the gate drive pulse are output. By this pulse control, holes accumulated in the diode element 1006 are reduced and the reverse recovery current is reduced, so that switching loss can be reduced.
  • the pulse control unit 1027 of the drive ICs 1024A and 1024B sets the gate drive signals SGH and SGL to the H level from the time when the first time T1 elapses to the time when the second time T2 elapses, starting from the falling time of the PWM signals FH and FL. To do. Since the falling point of the PWM signals FH and FL is also the starting point of the dead time Td, the gate driving pulse can be applied while effectively preventing the arm short circuit by effectively using the dead time Td having a certain time.
  • the first time T1 and the second time T2 are the dead time Td, the delay and variation of the gate drive voltages VGH and VGL measured in advance corresponding to the element current, and the reverse recovery current. Is set based on the time until the flow starts, and is stored in the memory 1039 of the pulse control unit 27.
  • the time width (pulse width Tw) between the first time T1 and the second time T2 is set longer as the current flowing through the diode element 1006 during the period in which the PWM signals FH and FL are at the H level is larger.
  • the first time T1 and the second time T2 are set so that the reinjection time Tc is greater than zero. Thereby, it is possible to prevent a short-circuit current from flowing through the half bridge circuit 4. Further, the pulse width Tw is set to be equal to or shorter than a predetermined allowable injection time. As a result, the reverse recovery current can be limited to a value corresponding to the allowable injection time or less, and the switching loss can be reduced.
  • the first time T1 and the second time T2 are set in consideration of the waveform of the gate drive voltage and the drive mode of the drive circuit 1028 when the gate drive pulse is applied. That is, if a gate drive pulse is applied when a current flows through the diode element 1006, the mirror period does not occur. Therefore, the first time T1 and the second time T2 are set as those in which the mirror period does not occur.
  • the drive circuit 1028 outputs the gate drive voltages VGH and VGL according to the maximum gate drive capability that the drive circuit 1028 has. Furthermore, if a current flows through the diode element 1006, there is no possibility of a short circuit. Therefore, the drive circuit 1028 monotonously increases the gate drive voltages VGL and VGH while maintaining a constant gate drive capability when the gate drive voltages VGL and VGH are raised.
  • the first time T1 and the second time T2 are set in accordance with such a driving mode.
  • the gate driving voltage when using a driving mode peculiar to such a gate driving pulse has a smaller delay and variation than the gate driving voltage when using a driving mode that cuts off the transistor element 1005. Therefore, the drive ICs 1024A and 1024B can increase the accuracy of the application timing of the gate drive pulse, and can accurately control the reinjection time Tc. As a result, the reinjection time can be controlled to be short while preventing an arm short circuit, and the switching loss can be further reduced. Further, a wider pulse width Tw of the gate drive pulse can be secured. Further, since the pulse control unit 1027 applies the gate drive signal starting from the falling point of the PWM signals FH and FL, no separate timing signal is required, and the conventional drive control device can be replaced. It becomes easy.
  • the pulse control unit 1027 stops the current from flowing through the diode element 1006 even during the period (time t4 to t6) in which the gate drive pulse is applied based on the pulse control (the detected current value becomes less than the specified value Im2). If it is determined that there is a possibility or no current is flowing, the application of the gate drive pulse is immediately stopped. Thereby, even when the load current changes suddenly, an arm short circuit can be reliably prevented. Furthermore, since it is not necessary to set the specified value Im2 higher in preparation for a sudden change in the load current, a wide current range for performing the pulse control can be secured, and the switching loss can be further reduced.
  • the conduction loss can be reduced by using a MOS transistor or the like for the semiconductor elements 1A and 1B as described in the second embodiment and performing the synchronous rectification, a diode is added to the semiconductor element. If it is determined that the current is flowing in the forward direction of the structure, instead of the first time T1, the rising edge (t2) of the gate drive control signals SGL and SGH and the second time T2 as shown in FIG. Accordingly, it is preferable to output the gate drive voltages VGH and VGL with a high drive capability.
  • the drive control system having a circuit configuration corresponding to the first embodiment has been described.
  • the present invention can also be applied to the drive control system described in the fifth, sixth, seventh, eighth, and ninth embodiments.
  • the semiconductor element 1A, 1B described in FIGS. 8, 9, 10, 11, 12, 13, 14 can be reduced in conduction loss by performing synchronous rectification using a MOS transistor or the like, the semiconductor element If it is determined that the current flows in the forward direction of the diode structure, the rise (t2) of the gate drive control signals SGL and SGH and the second time as shown in FIG. 7 instead of the first time T1. It is preferable to output the gate drive voltages VGH and VGL with high drive capability according to T2.
  • the drive control system having a circuit configuration corresponding to the first embodiment has been described.
  • 13, 14, and 15 can also be applied to the drive control system.
  • the order of the diode structure in the semiconductor element is reduced. If it is determined that a current is flowing in the direction of the direction, instead of the first time T1, as shown in FIG. 19, it is high according to the rise (t2) of the gate drive control signals SGL and SGH and the second time T2.
  • the gate drive voltages VGH and VGL may be output with the drive capability.
  • the drive control system having the circuit configuration corresponding to the first embodiment has been described.
  • FIG. 33 corresponding to the first embodiment
  • FIG. , 19, 27, 32 can be applied to the drive control system described in the modified examples of the first to sixteenth embodiments.
  • gate drive is performed with high driving capability in accordance with the rise (t2, t1c, t1b) of the gate drive control signals SGL, SGH and the second time T2.
  • the voltages VGH and VGL should be output.
  • RC-IGBT is not limited to a trench gate type, but may be a planar gate type.
  • the semiconductor elements 1001A and 1001B may be elements having a control gate and formed with a parasitic diode, for example, a MOS transistor and a diode having a MOS gate.
  • the MOS transistor is not limited to a trench gate type but may be a planar gate type.
  • the MOS transistor may have an SJ (Super Junction) structure.
  • the sense resistors 1007A and 1007B are provided as the current detection means after the sense elements are formed in the semiconductor elements 1001A and 1001B.
  • sense resistors 1007A and 1007B may be provided in series with the semiconductor elements 1001A and 1001B excluding the sense elements. Since the sense resistors 1007A and 1007B and the main element are directly connected, a high-speed answer is possible.
  • Hall sensors 1059A and 1059B may be provided for the semiconductor elements 1001A and 1001B.
  • Hall sensors may be provided on the output lines from the output terminal Nt to the load. In any configuration, the current can be detected with high accuracy.
  • An insulated current sensor such as a GMR (Giant Magneto Resistance) sensor may be used instead of the Hall sensor.
  • This disclosure includes the following aspects.
  • each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate.
  • the two semiconductor elements constitute a half bridge circuit. The first time and the second time are set in advance so as not to cause an arm short circuit between the two semiconductor elements.
  • the semiconductor element to be driven has a common gate structure for the transistor structure and the diode structure.
  • the first control unit applies a gate drive voltage to the one semiconductor element in a state where a current flows through the diode structure of one semiconductor element, the current is accumulated in the diode structure.
  • the number of holes to be reduced is reduced, and the effect of reducing the reverse recovery current occurs.
  • a device current flows in the reverse direction when a device current (for example, a diode current) flows in the forward direction of the diode structure.
  • the waveform of the gate drive voltage when a gate drive pulse is applied is different.
  • the drive control device applies a gate drive pulse only when a current flows through the semiconductor element in the forward direction of the diode structure, so control based on small delays and variations in the former case is possible, and the application timing Can improve the accuracy.
  • the first control means inputs at least one of the command signals (for example, PWM signals) on the high potential side (high side) and the low potential side (low side) that change in a complementary manner.
  • a gate drive voltage is applied to the semiconductor element.
  • This command signal has a dead time (period in which both sides are off to prevent arm short circuit) at the time of switching. Since the dead time is a fixed time, the time from the input of the off command signal on one side to the input of the on command signal on the other side is accurately guaranteed.
  • the gate drive signal necessary for applying the gate drive voltage at a desired timing starting from the input time point of the off command signal can be accurately set.
  • the time from when the gate drive pulse is applied to one semiconductor element until the reverse recovery current starts to flow for example, the time when carriers (holes) are injected again into the diode structure after the application of the gate drive pulse is completed. (Reinjection time) can be accurately controlled. As a result, since the reinjection time can be controlled to be short while preventing an arm short circuit, the reverse recovery current is reduced and the switching loss can be reduced. In addition, since the first control means can apply the gate drive signal using the off command signal as a reference timing, a separate timing signal is not required, and the replacement from the conventionally used drive control device is facilitated.
  • the drive control device may be configured such that the current of the semiconductor element that flows in the forward direction of the diode structure is a current based on the current detection signal during a period in which an ON command signal is input to the semiconductor element to be driven and controlled. If it is determined that the threshold value is equal to or greater than the threshold value, a second control unit that outputs a gate drive signal that instructs to shut off the gate drive voltage may be further provided.
  • the second control means is configured to cause the current of the semiconductor element that flows in the forward direction of the diode structure based on the current detection signal during a period in which an ON command signal is input to the semiconductor element to be driven and controlled, to the current direction.
  • a gate drive signal for instructing application of the gate drive voltage is output.
  • the conduction loss when the gate drive voltage is cut off is equal to the conduction loss when the gate drive voltage is applied.
  • the current value is measured in advance and set as a current threshold value.
  • the semiconductor element has a characteristic that the conduction loss differs when the gate drive voltage is cut off and when it is applied. This is because hole injection is affected by channel formation.
  • the magnitude relationship between the conduction loss when the gate drive voltage is cut off and the conduction loss when the gate drive voltage is applied varies depending on the type of semiconductor element, withstand voltage, and the like. Therefore, in this means, this relationship is measured in advance, and a current threshold value at which the magnitude relationship is switched is set.
  • the second control means outputs a gate drive voltage cutoff command when the current flowing in the forward direction of the diode structure in the semiconductor element is equal to or greater than the current threshold, and when the current is less than the current threshold, the gate drive voltage The application command is output.
  • the conduction loss can be appropriately reduced regardless of the type and breakdown voltage of the semiconductor element.
  • the gate drive voltage is reliably applied to the semiconductor element during the period in which the current flows in the reverse direction of the diode structure, the current according to the ON command signal can be supplied to the transistor structure.
  • the second control means is configured such that a current less than the current threshold is applied to the semiconductor element in a forward direction of the diode structure during a period in which an ON command signal is input to the semiconductor element to be driven and controlled. If it is determined that the current is flowing, the gate drive signal for instructing the application of the gate drive voltage may be output after the input time of the off command signal to the semiconductor element is extended to the time point of the second time. .
  • control by the second control means and the control by the first control means can be executed by a series of gate drive voltages, and the conduction loss can be further reduced.
  • the drive control device outputs a gate drive signal for instructing application of the gate drive voltage during a period in which an on-command signal for the semiconductor element to be driven is input, and the diode is supplied to the semiconductor element during the period
  • a gate drive signal for instructing application of the gate drive voltage is set to a time point at which the second time has passed after an input time point of the off command signal to the semiconductor element.
  • a second control means for extending the output to the output.
  • the gate drive voltage during the period when the ON command signal is inputted and the gate drive voltage related to the control of the first control means can be executed as a series of gate drive voltages, and the conduction loss can be further reduced.
  • an insulated gate transistor structure to which a gate driving voltage is applied and a diode structure are formed on the same semiconductor substrate, and the current-carrying electrode of the transistor structure and the current-carrying electrode of the diode structure are
  • a common drive control device for a semiconductor element includes: a current detection unit that outputs a current detection signal corresponding to a current flowing through the semiconductor element; and the current detection signal during a period when an ON command signal is input to the semiconductor element. If the current of the semiconductor element flowing in the forward direction of the diode structure is determined to be greater than or equal to the current threshold value based on the second, a gate drive signal for commanding the interruption of the gate drive voltage is output. Control means.
  • the second control means is configured such that the current of the semiconductor element that flows in the forward direction of the diode structure is based on the current detection signal during the period when the ON command signal for the semiconductor element is input. If it is determined that the value is less than the value, a gate drive signal for instructing application of the gate drive voltage is output. When a current flows through the semiconductor element in the forward direction of the diode structure, the conduction loss when the gate drive voltage is cut off is equal to the conduction loss when the gate drive voltage is applied. The current value is measured in advance and set as a current threshold value.
  • the second control means determines that the current flowing in the forward direction of the diode structure in the semiconductor element is greater than or equal to the current threshold based on the current detection signal during the period when the ON command signal for the semiconductor element is input. Then, a gate drive signal for instructing shutoff of the gate drive voltage is output. If it is determined that it is less than the current threshold value, a gate drive signal for instructing application of the gate drive voltage is output. According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above. Furthermore, the conduction loss can be appropriately reduced regardless of the type and breakdown voltage of the semiconductor element. In addition, since the gate drive voltage is reliably applied to the semiconductor element during the period in which the current flows in the reverse direction of the diode structure, the current according to the ON command signal can be supplied to the transistor structure.
  • the second control means may be configured to be able to input a threshold value specifying signal for specifying the current threshold value from the outside.
  • the second control means uses a current threshold value corresponding to the input threshold value specifying signal for determination of a current flowing through the semiconductor element during a period in which the ON command signal is input.
  • the drive control device can drive various semiconductor elements of different types, withstand voltages, etc. with low conduction loss.
  • At least one of the first control means or the second control means may perform normal control.
  • at least one of the first control means and the second control means receives an ON command signal for the semiconductor element to be driven and controlled when the current flowing to the load through the semiconductor element is smaller than a specified value.
  • a gate drive signal for instructing application of the gate drive voltage.
  • at least one of the first control means and the second control means receives an off command signal for the semiconductor element to be driven and controlled when the current flowing through the semiconductor element to the load is smaller than a specified value.
  • a gate drive signal for instructing to cut off the gate drive voltage.
  • the drive control device may further include a drive circuit that inputs the gate drive signal and outputs the gate drive voltage.
  • the drive circuit is composed of an IC having a withstand voltage corresponding to the gate drive voltage.
  • a drive control device is provided for each semiconductor element constituting the half bridge circuit. Since it is only necessary to replace the drive control device (drive IC) with a drive system for semiconductor elements that has already been widely used, the drive system can be easily changed.
  • the drive control device may drive and control two semiconductor elements constituting the half bridge circuit.
  • the drive control device is composed of an IC having a withstand voltage corresponding to the power supply voltage applied to the half bridge circuit.
  • the IC includes a drive circuit that inputs the gate drive signal and outputs the gate drive voltage.
  • the current detection means is provided so as to detect a current flowing in at least one of the two semiconductor elements.
  • At least one of the first control means and the second control means is configured to apply the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements. Prohibit application.
  • the current detection means detects a current flowing through at least one of the two semiconductor elements. If one current can be detected, the current of the other semiconductor element can also be detected indirectly.
  • This drive control device can grasp the drive state of the two semiconductor elements constituting the half bridge circuit.
  • the control unit prohibits application of the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements. Thereby, an arm short circuit can be prevented reliably.
  • the drive control device may drive and control the two semiconductor elements constituting the half bridge circuit.
  • the drive control device includes a control IC that provides at least one of the first control means and the second control means, and a drive that applies the gate drive voltage to each semiconductor element based on a gate drive signal input from the control IC. It comprises an IC, an insulating circuit that electrically insulates the gate drive signal output from the control IC and transmits the signal to the drive IC, and the current detection means.
  • the control IC outputs a gate drive signal for prohibiting application of the gate drive voltage to the other semiconductor element during a period in which the gate drive voltage is applied to one of the two semiconductor elements.
  • This drive control device can grasp the drive state of the two semiconductor elements constituting the half bridge circuit.
  • the control IC outputs a gate drive signal for prohibiting application of the gate drive voltage to the other semiconductor element during a period in which the gate drive voltage is applied to one of the two semiconductor elements. Thereby, an arm short circuit can be prevented reliably.
  • the current detection means can detect only one of the two semiconductor elements, the current of the other semiconductor element can also be indirectly detected.
  • the current detection means may be provided by the control IC.
  • control IC performs software processing for each control described above.
  • each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate.
  • the detection means detects a change in the current detection signal, a pulse is output so that an arm short circuit does not occur between the two semiconductor elements.
  • the time is prior to the point of input of the ON command signal for the one of the semiconductor elements, two semiconductor elements constitute a half-bridge circuit.
  • each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized.
  • the drive control device for two semiconductor elements in which the electrode and the current-carrying electrode of the diode structure are common, a voltage detection means for outputting a voltage detection signal based on the electrode potential of one of the semiconductor elements, and the one semiconductor element
  • Control means for outputting a pulse from an input time point of an ON command signal to the one semiconductor element so as not to cause an arm short circuit.
  • the two semiconductor elements constitute a half bridge circuit.
  • the drive control device includes: a current detection unit that outputs a current detection signal corresponding to a current flowing through at least one semiconductor element; and the current detection signal when an off command signal is input to the one semiconductor element.
  • a current detection unit that outputs a current detection signal corresponding to a current flowing through at least one semiconductor element; and the current detection signal when an off command signal is input to the one semiconductor element.
  • Each semiconductor element has the insulated gate type transistor structure and diode structure to which a gate drive voltage is applied formed in the same semiconductor substrate, and electricity supply of the said transistor structure
  • a pulse is generated in response to an OFF command signal being input to the input means.
  • And means for outputting comprises a control means for outputting a pulse a predetermined time before the input time of the ON command signal for the one of the semiconductor element so arm short circuit does not occur between the two semiconductor elements.
  • the two semiconductor elements constitute a half bridge circuit.
  • each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate drive voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized.
  • a drive control device for two semiconductor elements in which an electrode and a current-carrying electrode of the diode structure are common, a voltage detection means for outputting a voltage detection signal based on an electrode potential of one of the semiconductor elements, and the other semiconductor element Input means for inputting a command signal to the one semiconductor element, and when the off-command signal for the one semiconductor element is input, the one semiconductor element has the diode structure based on the voltage detection signal and the input signal of the input means.
  • a pulse is generated in response to an OFF command signal being input to the input means.
  • the two semiconductor elements constitute a half bridge circuit.
  • the drive control device may further include control voltage detection means for outputting a control voltage detection signal corresponding to the control voltage of the other semiconductor element.
  • the control means outputs a pulse based on the fluctuation of the control voltage detection signal of the control voltage detection means.
  • each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized.
  • the ON command signal Starting from the time when the OFF command signal is input through the input, the gate drive power is supplied from the time when the first time has elapsed to the time when the second time has elapsed.
  • a control means for outputting a gate drive signal for commanding the application The first time and the second time are set in advance so as not to cause an arm short circuit between the two semiconductor elements.
  • control means may determine the current flowing through the load by determining whether or not the voltage has changed by the voltage detector. When the control means determines that the current of the load is within a predetermined range near 0, the control means outputs a gate drive signal for instructing cutoff of the gate drive voltage. When the control means determines that the load current is outside a predetermined range near 0, the control means outputs a gate drive signal for instructing application of the gate drive voltage.
  • control means determines that the current flows in the forward direction of the diode structure based on the voltage detection signal during a period in which an ON command signal is input to the semiconductor element to be driven and controlled.
  • You may output the gate drive signal which designates interruption
  • the control means determines that the current does not flow in the forward direction of the diode structure based on the voltage detection signal during a period in which an ON command signal is input to the semiconductor element to be driven and controlled, A gate drive signal for commanding application is output.
  • the drive control device may further include a drive circuit that inputs the gate drive signal and outputs the gate drive voltage.
  • the drive circuit is composed of an IC having a withstand voltage corresponding to the gate drive voltage.
  • the drive control device may drive and control the two semiconductor elements constituting the half bridge circuit.
  • the drive control device is composed of an IC having a withstand voltage corresponding to the power supply voltage applied to the half bridge circuit.
  • the IC provides a drive circuit that inputs the gate drive signal and outputs the gate drive voltage.
  • the voltage detecting means is provided so as to detect at least one voltage of the two semiconductor elements.
  • the control means prohibits application of the gate drive voltage to the other semiconductor element during a period in which the gate drive voltage is applied to one of the two semiconductor elements.
  • the drive control device may drive and control the two semiconductor elements constituting the half bridge circuit.
  • the drive control device includes a control IC having the control means, a drive IC for applying the gate drive voltage to the semiconductor element based on a gate drive signal input from the control IC, and a gate drive output from the control IC
  • An insulating circuit that electrically insulates the signal and transmits the signal to the drive IC and the voltage detection means are configured.
  • the control IC outputs a gate drive signal for prohibiting application of the gate drive voltage to the other semiconductor element during a period in which the gate drive voltage is applied to one of the two semiconductor elements.
  • the voltage detection means may be provided by the control IC.
  • the voltage detection means may be formed on the semiconductor substrate apart from the outer periphery of the element formation region of the semiconductor element.
  • the voltage detecting means detects an intermediate potential using an electric field limiting ring having a conductivity type opposite to the conductivity type of the semiconductor substrate.
  • an insulated gate transistor structure to which a gate drive voltage is applied and a diode structure are formed on the same semiconductor substrate, and the conduction electrode of the transistor structure and the conduction electrode of the diode structure are
  • the drive control device for a semiconductor element having a common electrode includes a current detection unit that outputs a current detection signal corresponding to a current flowing through the semiconductor element, and an on command signal for the semiconductor element based on the current detection signal.
  • a preset first time elapses from the input time point of the subsequent off command signal Control means for outputting a gate drive signal for instructing application of the gate drive voltage from a time point until a lapse of a second time; and If the input signal and a drive circuit for outputting the gate drive voltage.
  • the time width between the first time and the second time is set to a value corresponding to the magnitude of the current flowing in the semiconductor element during the period when the ON command signal for the semiconductor element is input.
  • the semiconductor element to be driven has a common gate structure for the transistor structure and the diode structure.
  • a control means applies a gate drive voltage to the one semiconductor element in a state where current flows in the diode structure of one semiconductor element, holes accumulated in the diode structure Decreases, and the effect of reducing the reverse recovery current occurs.
  • a device current flows in the reverse direction when a device current (for example, a diode current) flows in the forward direction of the diode structure.
  • the waveform of the gate drive voltage when a gate drive pulse is applied is different.
  • the rise time and fall time of the gate drive voltage are shortened (or can be shortened). This reduces the delay and variation of the gate drive pulse.
  • the delay and variation of the gate drive pulse increase.
  • the drive control device applies a gate drive pulse only when a current flows through the semiconductor element in the forward direction of the diode structure, so control based on small delays and variations in the former case is possible, and the application timing Can improve the accuracy.
  • the semiconductor element is, for example, arranged in series on the high potential side (high side) and the low potential side (low side) across the output terminal to constitute a half bridge circuit.
  • the drive control device inputs at least one command signal among high-side and low-side command signals (for example, PWM signals) that change complementarily, and applies a gate drive voltage to at least one side semiconductor element.
  • This command signal has a dead time at the time of switching. Since the dead time is a fixed time, the time from the input of the off command signal on one side to the input of the on command signal on the other side is accurately guaranteed.
  • the control means measures the delay and variation described above in advance, grasps the dead time, and sets the time width between the first time and the second time during the period when the ON command signal for the semiconductor element is input.
  • the value is controlled according to the magnitude of the current flowing in the current.
  • the time from when the gate drive pulse is applied to one semiconductor element until the reverse recovery current starts to flow for example, the time when carriers (holes) are injected again into the diode structure after the application of the gate drive pulse (carrier)
  • the reinjection time can be accurately controlled. Therefore, according to this means, the reinjection time can be controlled to be short while preventing an arm short circuit, so that the reverse recovery current is reduced and the switching loss can be reduced.
  • the control means can apply the gate drive signal using the off command signal as a reference timing, a separate timing signal is not required, and replacement from a conventionally used drive control device is facilitated.
  • the semiconductor element may include one semiconductor element and the other semiconductor element.
  • One semiconductor element and the other semiconductor element constitute a half-bridge circuit. After an off command signal is input to the semiconductor element in a state where a current flows in the forward direction of the diode structure, an on command signal is input to the other semiconductor element after a certain dead time.
  • an on command signal is input to the other semiconductor element after a certain dead time.
  • the gate drive voltage is cut off after the second time has elapsed, and when a current exceeding the current flowing in the one semiconductor element starts flowing in the transistor structure of the other semiconductor element.
  • the first time and the second time are set so that the time width is greater than zero and less than or equal to a predetermined allowable injection time.
  • the above time width is the above-described carrier reinjection time. By setting this time larger than zero, it is possible to prevent a short-circuit current from flowing through the half-bridge circuit. In addition, by setting this time to be equal to or less than the predetermined allowable injection time, the reverse recovery current can be limited to a magnitude corresponding to the allowable injection time, and switching loss can be reduced.
  • the time width between the first time and the second time is set to be longer as the current flowing in the semiconductor element is larger during the period when the ON command signal to the semiconductor element is input. May be.
  • the time width between the first time and the second time is set to be longer as the current flowing through the semiconductor element is larger during the period when the ON command signal is input to the semiconductor element. ing. This is because the larger the current, the longer the time from when the OFF command signal is input until the reverse recovery current starts to flow. As a result, an increase in reinjection time can be suppressed regardless of the magnitude of current, and switching loss can be reduced.
  • the gate drive voltage based on the gate drive signal output from the time point of the first time to the time point of the second time monotonously increases or decreases monotonously according to the gate drive capability of the drive circuit.
  • the first time and the second time may be set.
  • the gate drive pulse applied after the input of the off command signal has the effect of reducing the holes accumulated in the diode structure and does not have the effect of energizing or disconnecting the semiconductor element. For this reason, the voltage between the current-carrying terminals of the transistor elements (between CE and DS) does not change and the mirror period does not occur. Further, during the application period of the gate drive pulse, a current continues to flow in the semiconductor element in the forward direction of the diode structure, so that a special gate drive voltage having a protective action in preparation for an arm short circuit is not necessary. Therefore, the carrier reinjection time can be controlled to a desired value by setting the gate drive signal so that the gate drive voltage monotonously increases or decreases.
  • the first time and the second time are set on the assumption that a mirror period does not occur in the gate drive voltage based on the gate drive signal output from the elapse of the first time to the elapse of the second time. May be.
  • the first time and the second time are set on the assumption that the mirror period does not occur in the gate drive voltage based on the gate drive signal output from the elapse of the first time to the elapse of the second time. Yes.
  • an increase in the carrier reinjection time can be suppressed as compared with the case where the gate drive signal is set assuming the occurrence of the mirror period.
  • the drive circuit may output the gate drive voltage while maintaining a constant gate drive capability when the gate drive signal changes at the time when the first time has elapsed.
  • the drive circuit outputs a gate drive voltage while maintaining a constant gate drive capability when the gate drive signal changes at the elapse of the first time.
  • a method of reducing a short-circuit current when the semiconductor element has a short-circuit fault is used by temporarily holding the gate drive voltage at an intermediate voltage in the process of increasing the gate drive voltage. .
  • a gate drive pulse is applied at an appropriate timing, a short-circuit current will not flow. According to this means, by maintaining a constant gate drive capability and eliminating unnecessary intermediate voltages, variations in the rise time of the gate drive voltage can be reduced and the reinjection time can be accurately controlled.
  • the drive circuit has a high driving capability when the gate driving signal changes at the time when the first time elapses and at the time when the second time elapses.
  • a drive voltage may be output.
  • the drive circuit increases the gate drive voltage with a higher driving capability than when the semiconductor element is disconnected. Output. This is because, during the application period of the gate drive pulse, current continues to flow through the semiconductor element in the forward direction of the diode structure, so that a surge due to a steep current change or voltage change does not occur. Thereby, variations in the rise time and fall time of the gate drive voltage can be reduced, and the reinjection time can be accurately controlled.
  • each section is expressed as S100, for example.
  • each section can be divided into a plurality of subsections, while a plurality of sections can be combined into one section.
  • each section configured in this manner can be referred to as a device, module, or means.

Abstract

This drive control device (32A, 32B, 52, 54, 56, 61, 62, 71, 72) of two semiconductor elements (1A, 1B) having a diode structure (6) and a transistor structure (5) having a powered electrode (15, 18) in common is provided with: a current detection means (7A, 7B, 25, 59, 60, 68) that outputs a current detection signal of the semiconductor elements; and a first control means (27) that, when it has been determined that current is flowing in the forward direction of the diode structure in the semiconductor element during the period that an on command signal is being input to the semiconductor element, outputs a gate drive signal from the point in time that a first time has elapsed to the point of time a second time has elapsed relative to the point in time that a subsequent off command signal is input. The first time and second time are pre-set in a manner such that an arm short-circuit does not arise between the two semiconductor elements.

Description

駆動制御装置Drive control device 関連出願の相互参照Cross-reference of related applications
　本開示は、２０１３年７月１０日に出願された日本出願番号２０１３－１４４５６１号と、２０１３年７月１０日に出願された日本出願番号２０１３－１４４５６０号と、２０１４年６月３０日に出願された日本出願番号２０１４－１３４２２７号とに基づくもので、ここにその記載内容を援用する。 The present disclosure includes Japanese application number 2013-144561 filed on July 10, 2013, Japanese application number 2013-144560 filed on July 10, 2013, and application filed on June 30, 2014. Which is based on Japanese Patent Application No. 2014-134227, which is incorporated herein by reference.
　本開示は、絶縁ゲート型のトランジスタ構造とダイオード構造とが同一の半導体基板に形成された半導体素子の駆動制御装置に関するものである。 The present disclosure relates to a drive control device for a semiconductor element in which an insulated gate transistor structure and a diode structure are formed on the same semiconductor substrate.
　ＲＣ－ＩＧＢＴ、ＭＯＳトランジスタ、ＭＯＳゲートを備えたダイオードなど、トランジスタ素子とダイオード素子とが同一の半導体基板に形成され、トランジスタ素子の通電電極（コレクタ、エミッタまたはドレイン、ソース）とダイオード素子の通電電極（カソード、アノード）とが共通の電極とされた半導体素子が知られている（非特許文献１参照）。こうした半導体素子を、インバータやコンバータなどの電力変換装置においてスイッチング素子として用いる場合、スイッチング損失および／または導通損失を低減することが必要である。 Transistor element and diode element such as RC-IGBT, MOS transistor, diode with MOS gate, etc. are formed on the same semiconductor substrate, transistor element conducting electrode (collector, emitter or drain, source) and diode element conducting electrode A semiconductor element having a common electrode (cathode, anode) is known (see Non-Patent Document 1). When such a semiconductor element is used as a switching element in a power conversion device such as an inverter or a converter, it is necessary to reduce switching loss and / or conduction loss.
　電力変換装置は、ハーフブリッジ回路を基本構成とし、上下アームの半導体素子を相補的にオンオフさせることで交流－直流電圧変換、直流－交流電圧変換を行い、或いは入力電圧を昇圧、降圧する。このハーフブリッジ回路において、電源短絡（アーム短絡）を防止するため、上下の半導体素子を同時にオフするデッドタイムが設けられている。 The power conversion device has a half-bridge circuit as a basic configuration, and performs AC-DC voltage conversion and DC-AC voltage conversion by complementarily turning on and off the semiconductor elements of the upper and lower arms, or boosts and steps down the input voltage. In this half-bridge circuit, in order to prevent a power supply short circuit (arm short circuit), a dead time for simultaneously turning off the upper and lower semiconductor elements is provided.
　デッドタイムの期間中は、一方の半導体素子のダイオード素子に負荷電流が還流する。デッドタイムの終了後、他方の半導体素子がオンすると、負荷電流が上記ダイオード素子から当該他方の半導体素子に切り替わる。この際、ダイオード素子に蓄積されていたキャリアの放出による逆回復電流が流れる。この逆回復電流は、スイッチング損失を増加させるとともにノイズの発生要因となる。 During the dead time, the load current flows back to the diode element of one semiconductor element. When the other semiconductor element is turned on after the dead time is over, the load current is switched from the diode element to the other semiconductor element. At this time, a reverse recovery current flows due to the emission of carriers accumulated in the diode element. This reverse recovery current increases switching loss and causes noise.
　これに対し、非特許文献１には、他方の半導体素子がターンオンする少し前に、一方の半導体素子に正のゲート駆動電圧を印加する方法が開示されている。この方法によれば、半導体素子の電子電流の増加とともにホール電流が減少し、ホールの注入が抑制され、逆回復電流が低減できる。 On the other hand, Non-Patent Document 1 discloses a method in which a positive gate drive voltage is applied to one semiconductor element slightly before the other semiconductor element is turned on. According to this method, the hole current decreases as the electron current of the semiconductor element increases, hole injection is suppressed, and the reverse recovery current can be reduced.
　一方、上述した半導体素子は、ダイオード素子に電流が流れている状態でゲート駆動電圧が印加されると、チャネルが形成されてホールの注入が抑制されるので、導通損失が増大するという特性を有している。これに対し、ダイオード素子に電流が流れているか否かを判定し、電流が流れているときにはゲート駆動電圧を遮断し、流れていないときにはゲート駆動電圧を印加する駆動制御が提案されている。 On the other hand, the semiconductor element described above has a characteristic that, when a gate drive voltage is applied in a state where a current flows through the diode element, a channel is formed and hole injection is suppressed, so that conduction loss increases. is doing. On the other hand, there has been proposed drive control in which it is determined whether or not a current is flowing through the diode element, the gate drive voltage is cut off when the current is flowing, and the gate drive voltage is applied when the current is not flowing.
　半導体素子に一時的にゲート駆動電圧（ゲート駆動パルス）を印加してキャリアの注入を抑制させる非特許文献１記載の方法は、逆回復電流を低減するために有効である。しかし、ハーフブリッジ回路を構成する２つの半導体素子の間で電流を切り替える過渡時にゲート駆動パルスを印加する必要があるため、印加タイミングがわずかでも遅れるとアーム短絡が発生する。逆に印加タイミングが早いと、ゲート駆動パルスの印加終了後に再び注入されるホールの量が増え、逆回復電流の低減効果が減少する。上記非特許文献１には、ゲート駆動パルスの具体的な印加タイミングやパルス幅が示されていない。当該方法を実用化するには、こうしたゲート駆動パルスの印加手段の確立が必要である。 The method described in Non-Patent Document 1 that suppresses carrier injection by temporarily applying a gate drive voltage (gate drive pulse) to a semiconductor element is effective in reducing the reverse recovery current. However, since it is necessary to apply a gate drive pulse at the time of switching current between two semiconductor elements constituting the half-bridge circuit, an arm short circuit occurs when the application timing is slightly delayed. Conversely, if the application timing is early, the amount of holes injected again after the application of the gate drive pulse is increased, and the effect of reducing the reverse recovery current is reduced. Non-Patent Document 1 does not show the specific application timing or pulse width of the gate drive pulse. In order to put this method into practical use, it is necessary to establish means for applying such a gate drive pulse.
　一方、ゲート駆動電圧の印加／遮断による半導体素子の導通損失の特性は、半導体素子の種類（ＲＣ－ＩＧＢＴ、ＭＯＳトランジスタ等）により大きく異なる。このため、半導体素子にダイオード素子の順方向の向きに電流が流れているか否かの従来の判定基準では、導通損失を十分に低減できない場合が生じる。 On the other hand, the characteristics of the conduction loss of the semiconductor element due to application / cutoff of the gate drive voltage vary greatly depending on the type of the semiconductor element (RC-IGBT, MOS transistor, etc.). For this reason, there is a case in which the conduction loss cannot be sufficiently reduced according to the conventional criterion for determining whether or not a current flows through the semiconductor element in the forward direction of the diode element.
　本開示は、トランジスタ構造とダイオード構造とが同一の半導体基板に形成された半導体素子に対し、第１に、ゲート駆動パルスを適切なタイミングで印加することによりスイッチング損失を低減でき、第２に、半導体素子の種類にかかわらず半導体素子の導通損失を十分に低減できる駆動制御装置を提供することを目的とする。 In the present disclosure, first, a switching loss can be reduced by applying a gate drive pulse at an appropriate timing to a semiconductor element in which a transistor structure and a diode structure are formed on the same semiconductor substrate. An object of the present invention is to provide a drive control device that can sufficiently reduce the conduction loss of a semiconductor element regardless of the type of the semiconductor element.
　本開示の第一の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、前記２つの半導体素子のうち少なくとも一方に流れる電流に応じた電流検出信号を出力する電流検出手段と、前記電流検出信号に基づいて、前記半導体素子に対するオン指令信号が入力されている期間に前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、その後のオフ指令信号の入力時点を起点として、第１時間の経過時点から第２時間の経過時点まで、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する第１の制御手段とを備える。二つの半導体素子は、ハーフブリッジ回路を構成する。第１時間と第２時間は、二つの半導体素子の間でアーム短絡が生じないように予め設定されている。 In the first aspect of the present disclosure, each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate. The drive control device for two semiconductor elements, wherein the electrode and the current-carrying electrode of the diode structure are common, current detection means for outputting a current detection signal corresponding to a current flowing in at least one of the two semiconductor elements; On the basis of the current detection signal, when it is determined that a current flows in the forward direction of the diode structure in the semiconductor element during a period in which an ON command signal for the semiconductor element is input, a subsequent OFF command signal Starting from the input time point of the first to the second time point, the gate commanding the application of the gate drive voltage And a first control means for outputting a motion signal. The two semiconductor elements constitute a half bridge circuit. The first time and the second time are set in advance so as not to cause an arm short circuit between the two semiconductor elements.
　本手段によれば、上述した遅延やばらつきを予め測定しデッドタイムを把握した上で、オフ指令信号の入力時点を起点として、ゲート駆動電圧を所望のタイミングで印加するために必要なゲート駆動信号のタイミング、すなわち第１時間と第２時間を正確に設定することが可能となる。 According to this means, after measuring the delay and variation described above in advance and grasping the dead time, the gate drive signal necessary for applying the gate drive voltage at a desired timing starting from the input time point of the off command signal. That is, the first time and the second time can be accurately set.
　その結果、アーム短絡を防止しつつ再注入時間を短く制御することができるので、逆回復電流が減少し、スイッチング損失を低減できる。また、第１の制御手段は、オフ指令信号を基準タイミングとしてゲート駆動信号を印加できるので、別のタイミング信号が不要となり、従来から使用している駆動制御装置からの置き替えが容易になる。 As a result, since the reinjection time can be controlled to be short while preventing the arm short circuit, the reverse recovery current is reduced and the switching loss can be reduced. In addition, since the first control means can apply the gate drive signal using the off command signal as a reference timing, a separate timing signal is not required, and the replacement from the conventionally used drive control device is facilitated.
　本開示の第二の態様において、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とが同一の半導体基板に形成され、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通とされた半導体素子の駆動制御装置は、前記半導体素子に流れる電流に応じた電流検出信号を出力する電流検出手段と、前記半導体素子に対するオン指令信号が入力されている期間、前記電流検出信号に基づいて、前記ダイオード構造の順方向の向きに流れる前記半導体素子の電流が前記電流しきい値以上であると判定すると、前記ゲート駆動電圧の遮断を指令するゲート駆動信号を出力する第２の制御手段とを備えている。第２の制御手段は、前記半導体素子に対するオン指令信号が入力されている期間、前記電流検出信号に基づいて、前記ダイオード構造の順方向の向きに流れる前記半導体素子の電流が前記電流しきい値未満であると判定すると、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する。前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れる場合において、前記ゲート駆動電圧が遮断されている時における導通損失と前記ゲート駆動電圧が印加されている時における導通損失とが等しくなる電流値が予め測定されて、電流しきい値として設定されている。 In a second aspect of the present disclosure, an insulated gate transistor structure to which a gate driving voltage is applied and a diode structure are formed on the same semiconductor substrate, and the current-carrying electrode of the transistor structure and the current-carrying electrode of the diode structure are A common drive control device for a semiconductor element includes: a current detection unit that outputs a current detection signal corresponding to a current flowing through the semiconductor element; and the current detection signal during a period when an ON command signal is input to the semiconductor element. If the current of the semiconductor element flowing in the forward direction of the diode structure is determined to be greater than or equal to the current threshold value based on the second, a gate drive signal for commanding the interruption of the gate drive voltage is output. Control means. The second control means is configured such that the current of the semiconductor element that flows in the forward direction of the diode structure is based on the current detection signal during the period when the ON command signal for the semiconductor element is input. If it is determined that the value is less than the value, a gate drive signal for instructing application of the gate drive voltage is output. When a current flows through the semiconductor element in the forward direction of the diode structure, the conduction loss when the gate drive voltage is cut off is equal to the conduction loss when the gate drive voltage is applied. The current value is measured in advance and set as a current threshold value.
　この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。さらに、半導体素子の種類や耐圧にかかわらず、導通損失を適切に低減することができる。また、半導体素子にダイオード構造の逆方向の向きに電流が流れる期間に確実にゲート駆動電圧が印加されるので、トランジスタ構造にオン指令信号に従った電流を流すことができる。 According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above. Furthermore, the conduction loss can be appropriately reduced regardless of the type and breakdown voltage of the semiconductor element. In addition, since the gate drive voltage is reliably applied to the semiconductor element during the period in which the current flows in the reverse direction of the diode structure, the current according to the ON command signal can be supplied to the transistor structure.
　本開示の第三の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、前記２つの半導体素子のうち少なくとも一方に流れる電流に応じた電流検出信号を出力する電流検出手段と、前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電流検出信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、前記電流検出手段により電流検出信号の変動を検出した時点で、二つの半導体素子の間でアーム短絡が生じないようにパルスを出力させる制御手段とを備え、当該時点は、前記一方の半導体素子に対するオン指令信号の入力時点の前である、二つの半導体素子は、ハーフブリッジ回路を構成する。 In a third aspect of the present disclosure, each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate. The drive control device for two semiconductor elements, wherein the electrode and the current-carrying electrode of the diode structure are common, current detection means for outputting a current detection signal corresponding to a current flowing in at least one of the two semiconductor elements; When it is determined that a current flows in the forward direction of the diode structure to the one semiconductor element based on the current detection signal when an off command signal is input to the one semiconductor element, the current When the detection means detects a change in the current detection signal, a pulse is output so that an arm short circuit does not occur between the two semiconductor elements. And a that control means, the time is prior to the point of input of the ON command signal for the one of the semiconductor elements, two semiconductor elements constitute a half-bridge circuit.
　この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。 According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above.
　本開示の第四の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、一方の前記半導体素子の電極電位に基づく電圧検出信号を出力する電圧検出手段と、前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電圧検出信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、二つの半導体素子の間でアーム短絡が生じないように前記一方の半導体素子に対するオン指令信号の入力時点からパルスを出力させる制御手段と、を備える。二つの半導体素子は、ハーフブリッジ回路を構成する。 In the fourth aspect of the present disclosure, each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized. The drive control device for two semiconductor elements, in which the electrode and the current-carrying electrode of the diode structure are common, a voltage detection means for outputting a voltage detection signal based on the electrode potential of one of the semiconductor elements, and the one semiconductor element When it is determined that a current flows in the forward direction of the diode structure in the one semiconductor element based on the voltage detection signal when an off command signal is input to the two semiconductor elements, Control means for outputting a pulse from an input time point of an ON command signal to the one semiconductor element so as not to cause an arm short circuit. The two semiconductor elements constitute a half bridge circuit.
　この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。 According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above.
　本開示の第五の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、一方の前記半導体素子に流れる電流に応じた電流検出信号を出力する電流検出手段と、他方の前記半導体素子に対する指令信号を入力する入力手段と、前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電流検出信号及び前記入力手段の入力信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、前記入力手段にオフ指令信号が入力されることに応じてパルスを出力させる手段であって、二つの半導体素子の間でアーム短絡が生じないように前記一方の半導体素子に対するオン指令信号の入力時点より所定時間前にパルスを出力させる制御手段を備える。二つの半導体素子は、ハーフブリッジ回路を構成する。 5th aspect of this indication WHEREIN: Each semiconductor element has the insulated gate type transistor structure and diode structure to which a gate drive voltage is applied formed in the same semiconductor substrate, and electricity supply of the said transistor structure The drive control device for two semiconductor elements, in which the electrode and the current-carrying electrode of the diode structure are common, current detection means for outputting a current detection signal corresponding to the current flowing through one of the semiconductor elements, and the other semiconductor An input means for inputting a command signal for the element, and the diode structure in the one semiconductor element based on the current detection signal and the input signal of the input means when an OFF command signal for the one semiconductor element is input. When it is determined that a current is flowing in the forward direction, a pulse is generated in response to an OFF command signal being input to the input means. And means for outputting comprises a control means for outputting a pulse a predetermined time before the input time of the ON command signal for the one of the semiconductor element so arm short circuit does not occur between the two semiconductor elements. The two semiconductor elements constitute a half bridge circuit.
　この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。 According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above.
　本開示の第六の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、一方の前記半導体素子の電極電位に基づく電圧検出信号を出力する電圧検出手段と、他方の前記半導体素子に対する指令信号を入力する入力手段と、前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電圧検出信号及び前記入力手段の入力信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、前記入力手段にオフ指令信号が入力されることに応じてパルスを出力させる手段であって、二つの半導体素子の間でアーム短絡が生じないように前記一方の半導体素子に対するオン指令信号の入力時点より所定時間前にパルスを出力させる制御手段を備える。二つの半導体素子は、ハーフブリッジ回路を構成する。 In a sixth aspect of the present disclosure, each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate drive voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized. A drive control device for two semiconductor elements, in which an electrode and a current-carrying electrode of the diode structure are common, a voltage detection means for outputting a voltage detection signal based on an electrode potential of one of the semiconductor elements, and the other semiconductor element Input means for inputting a command signal to the one semiconductor element, and when the off-command signal for the one semiconductor element is input, the one semiconductor element has the diode structure based on the voltage detection signal and the input signal of the input means. When it is determined that a current is flowing in the forward direction, a pulse is generated in response to an OFF command signal being input to the input means. A means for force, a control means for outputting a pulse a predetermined time before the input time of the ON command signal for the one of the semiconductor element so arm short circuit does not occur between the two semiconductor elements. The two semiconductor elements constitute a half bridge circuit.
　この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。 According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above.
　本開示の第七の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、少なくとも一方の半導体素子の電極電位に応じた電圧検出信号を出力する電圧検出手段と、前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電圧検出信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、その後にオン指令信号の入力を経てオフ指令信号が入力された時点を起点として、第１時間の経過時点から第２時点の経過時点まで、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する制御手段と、を備える。第1時間と第2時間は、二つの半導体素子の間でアーム短絡が生じないように予め設定されている。二つの半導体素子は、ハーフブリッジ回路を構成する。 In a seventh aspect of the present disclosure, each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized. The drive control device for two semiconductor elements, in which the electrode and the current-carrying electrode of the diode structure are common, a voltage detection means for outputting a voltage detection signal corresponding to the electrode potential of at least one of the semiconductor elements, and the one semiconductor When it is determined that a current flows in the forward direction of the diode structure to the one semiconductor element based on the voltage detection signal when an off command signal is input to the element, the ON command signal Starting from the time when the OFF command signal is input through the input, the gate drive power is supplied from the time when the first time has elapsed to the time when the second time has elapsed. And a control means for outputting a gate drive signal for commanding the application. The first time and the second time are set in advance so as not to cause an arm short circuit between the two semiconductor elements. The two semiconductor elements constitute a half bridge circuit.
　この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。 According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above.
　本開示の第八の態様において、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とが同一の半導体基板に形成され、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通の電極とされた半導体素子の駆動制御装置は、前記半導体素子に流れる電流に応じた電流検出信号を出力する電流検出手段と、前記電流検出信号に基づいて、前記半導体素子に対するオン指令信号が入力されている期間に前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、その後のオフ指令信号の入力時点を起点として、予め設定された第１時間の経過時点から第２時間の経過時点まで前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する制御手段と、前記ゲート駆動信号を入力して前記ゲート駆動電圧を出力するドライブ回路とを備える。前記第１時間と前記第２時間との時間幅は、前記半導体素子に対するオン指令信号が入力されている期間に前記半導体素子に流れていた電流の大きさに応じた値に設定されている。 In an eighth aspect of the present disclosure, an insulated gate transistor structure to which a gate drive voltage is applied and a diode structure are formed on the same semiconductor substrate, and the conduction electrode of the transistor structure and the conduction electrode of the diode structure are The drive control device for a semiconductor element having a common electrode includes a current detection unit that outputs a current detection signal corresponding to a current flowing through the semiconductor element, and an on command signal for the semiconductor element based on the current detection signal. When it is determined that a current is flowing in the semiconductor element in the forward direction of the diode structure during the input period, a preset first time elapses from the input time point of the subsequent off command signal Control means for outputting a gate drive signal for instructing application of the gate drive voltage from a time point until a lapse of a second time; and If the input signal and a drive circuit for outputting the gate drive voltage. The time width between the first time and the second time is set to a value corresponding to the magnitude of the current flowing in the semiconductor element during the period when the ON command signal for the semiconductor element is input.
　上記によれば、一方の半導体素子に対するゲート駆動パルスの印加終了時点から逆回復電流が流れ始めるまでの時間、例えばゲート駆動パルスの印加終了後に当該ダイオード構造に再びキャリア（ホール）が注入される時間（キャリアの再注入時間）を正確に制御可能となる。従って、本手段によれば、アーム短絡を防止しつつ再注入時間を短く制御することができるので、逆回復電流が減少し、スイッチング損失を低減できる。また、制御手段は、オフ指令信号を基準タイミングとしてゲート駆動信号を印加できるので、別のタイミング信号が不要となり、従来から使用している駆動制御装置からの置き替えが容易になる。 According to the above, the time from when the gate drive pulse is applied to one semiconductor element until the reverse recovery current starts to flow, for example, the time when carriers (holes) are injected again into the diode structure after the application of the gate drive pulse is completed. (Carrier reinjection time) can be accurately controlled. Therefore, according to this means, the reinjection time can be controlled to be short while preventing an arm short circuit, so that the reverse recovery current is reduced and the switching loss can be reduced. In addition, since the control means can apply the gate drive signal using the off command signal as a reference timing, a separate timing signal is not required, and replacement from a conventionally used drive control device is facilitated.
　本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。その図面は、
図1は、第１の実施形態を示す駆動制御システムの構成図であり、 図２は、メイン素子とセンス素子の回路構成図であり、 図３は、半導体素子の模式的な縦断面図であり、 図４は、ダイオード素子の順方向の電圧電流特性図であり、 図５は、Ｖｆ制御とパルス制御に係る波形図であり、 図６は、第２の実施形態を示し、ＭＯＳトランジスタにおいてダイオード素子の順方向の向きに電流が流れる場合の電圧電流特性図であり、 図７は、同期整流を使用したときの、Ｖｆ制御とパルス制御に係る波形図であり、 図８は、第３の実施形態を示す駆動制御システムの構成図であり、 図９は、第４の実施形態を示す駆動制御システムの構成図であり、 図１０は、第５の実施形態を示す駆動制御システムの構成図であり、 図１１は、第６の実施形態を示す駆動制御システムの構成図であり、 図１２は、第７の実施形態を示す駆動制御システムの構成図であり、 図１３は、第８の実施形態を示す駆動制御システムの構成図であり、 図１４は、第９の実施形態を示す駆動制御システムの構成図であり、 図１５は、電流検出構成の変形例を示す図であり、 図１６は、電流検出構成の変形例を示す図であり、 図１７は、第１０の実施形態を示す駆動制御システムの構成図であり、 図１８は、第１０の実施形態を示すＶｆ制御とパルス制御に係る波形図であり、 図１９は、第１１の実施形態を示す同期整流を使用したときのＶｆ制御とパルス制御に係る波形図であり、 図２０は、第１２の実施形態を示す駆動制御システムの構成図であり、 図２１は、第１３の実施形態を示す駆動制御システムの構成図であり、 図２２は、第１４の実施形態を示す駆動制御システムの構成図であり、 図２３は、第１５の実施形態を示す駆動制御システムの構成図であり、 図２４は、第１６の実施形態を示す中間電位の検出態様を示す模式的な半導体構造断面図であり、 図２５は、各実施形態において負荷電流の方向、大きさに応じたコレクタ電極電位の変化特性を概略的に示す説明図であり、 図２６は、各実施形態における負荷電流の方向、大きさ（ゼロ電流付近）に応じたコレクタ電極電位の変化特性を概略的に示す説明図であり、 図２７は、第１～第１６の実施形態の変形例を示す同期整流を使用したときのＶｆ制御とパルス制御に係る波形図であり、 図２８は、第１～第１６の実施形態の変形例を示す駆動制御システムの構成図であり、 図２９は、第１～第１６の実施形態の変形例を示す駆動制御システムの構成図であり、 図３０は、第１～第１６の実施形態の変形例を示す駆動制御システムの構成図であり、 図３１は、第１～第１６の実施形態の変形例を示す駆動制御システムの構成図であり、 図３２は、第１～第１６の実施形態の変形例を示す同期整流を使用したときのＶｆ制御とパルス制御に係る波形図であり、 図３３は、本開示の第１７実施形態を示す駆動制御システムの構成図であり、 図３４は、ドライブ回路の駆動能力切替回路の構成図であり、 図３５は、パルス制御部のブロック構成図であり、 図３６は、パルス開始決定部の構成図であり、 図３７は、ダイオード素子の順方向の電圧電流特性図であり、 図３８は、Ｖｆ制御とパルス制御に係る波形図であり、 図３９は、素子電流、ゲート駆動電圧およびダイオード素子内のキャリア濃度を示す図であり、 図４０は、再注入時間がゼロとなる場合の波形図であり、 図４１は、再注入時間とスイッチング損失との関係を示す図であり、 図４２は、パルス幅とスイッチング損失との関係を示す図であり、 図４３は、第１時間と第２時間の説明図であり、 図４４は、パルス開始決定部の動作説明図であり、 図４５は、ミラー期間が存在する場合と存在しない場合の波形図であり、 図４６は、異なる駆動能力に対するゲート駆動電圧の波形図であり、 図４７は、電流検出構成の変形例を示す図であり、 図４８は、電流検出構成の変形例を示す図である。 The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a configuration diagram of a drive control system showing the first embodiment. FIG. 2 is a circuit configuration diagram of the main element and the sense element. FIG. 3 is a schematic longitudinal sectional view of a semiconductor element, FIG. 4 is a voltage-current characteristic diagram in the forward direction of the diode element. FIG. 5 is a waveform diagram relating to Vf control and pulse control. FIG. 6 shows the second embodiment, and is a voltage-current characteristic diagram in the case where current flows in the forward direction of the diode element in the MOS transistor. FIG. 7 is a waveform diagram relating to Vf control and pulse control when using synchronous rectification, FIG. 8 is a configuration diagram of a drive control system showing the third embodiment. FIG. 9 is a configuration diagram of the drive control system showing the fourth embodiment. FIG. 10 is a configuration diagram of the drive control system showing the fifth embodiment. FIG. 11 is a configuration diagram of a drive control system showing the sixth embodiment. FIG. 12 is a configuration diagram of a drive control system showing the seventh embodiment. FIG. 13 is a configuration diagram of a drive control system showing the eighth embodiment. FIG. 14 is a configuration diagram of the drive control system showing the ninth embodiment. FIG. 15 is a diagram illustrating a modification of the current detection configuration. FIG. 16 is a diagram illustrating a modification of the current detection configuration. FIG. 17 is a configuration diagram of a drive control system showing the tenth embodiment. FIG. 18 is a waveform diagram relating to Vf control and pulse control according to the tenth embodiment, FIG. 19 is a waveform diagram relating to Vf control and pulse control when using synchronous rectification according to the eleventh embodiment. FIG. 20 is a configuration diagram of the drive control system showing the twelfth embodiment. FIG. 21 is a block diagram of a drive control system showing the thirteenth embodiment. FIG. 22 is a configuration diagram of the drive control system showing the fourteenth embodiment. FIG. 23 is a configuration diagram of the drive control system showing the fifteenth embodiment, FIG. 24 is a schematic cross-sectional view of a semiconductor structure showing an intermediate potential detection mode according to the sixteenth embodiment, FIG. 25 is an explanatory diagram schematically showing a change characteristic of the collector electrode potential according to the direction and magnitude of the load current in each embodiment. FIG. 26 is an explanatory diagram schematically showing a change characteristic of the collector electrode potential according to the direction and magnitude (near zero current) of the load current in each embodiment. FIG. 27 is a waveform diagram relating to Vf control and pulse control when using synchronous rectification showing a modification of the first to sixteenth embodiments; FIG. 28 is a configuration diagram of a drive control system showing a modification of the first to sixteenth embodiments, FIG. 29 is a configuration diagram of a drive control system showing a modification of the first to sixteenth embodiments, FIG. 30 is a configuration diagram of a drive control system showing a modification of the first to sixteenth embodiments, FIG. 31 is a configuration diagram of a drive control system showing a modification of the first to sixteenth embodiments, FIG. 32 is a waveform diagram relating to Vf control and pulse control when using synchronous rectification showing a modification of the first to sixteenth embodiments; FIG. 33 is a configuration diagram of a drive control system showing a seventeenth embodiment of the present disclosure. FIG. 34 is a configuration diagram of the drive capability switching circuit of the drive circuit. FIG. 35 is a block diagram of the pulse control unit. FIG. 36 is a block diagram of the pulse start determination unit, FIG. 37 is a voltage-current characteristic diagram in the forward direction of the diode element. FIG. 38 is a waveform diagram relating to Vf control and pulse control, FIG. 39 is a diagram showing the device current, the gate drive voltage, and the carrier concentration in the diode device, FIG. 40 is a waveform diagram when the reinjection time becomes zero, FIG. 41 is a diagram showing the relationship between reinjection time and switching loss, FIG. 42 is a diagram showing the relationship between the pulse width and the switching loss, FIG. 43 is an explanatory diagram of the first time and the second time, FIG. 44 is a diagram for explaining the operation of the pulse start determining unit. FIG. 45 is a waveform diagram when the mirror period exists and when it does not exist, FIG. 46 is a waveform diagram of the gate drive voltage for different drive capabilities, FIG. 47 is a diagram showing a modification of the current detection configuration. FIG. 48 is a diagram illustrating a modification of the current detection configuration.
　各実施形態において実質的に同一部分には同一符号を付して説明を省略する。 In each embodiment, substantially the same parts are denoted by the same reference numerals and description thereof is omitted.
　（第１の実施形態）
　以下、本開示の第１の実施形態について図１ないし図５を参照しながら説明する。図１に示す駆動制御システムは、モータ等の誘導性負荷を駆動するインバータ装置、インダクタを備えて直流電圧を昇圧／降圧するコンバータ装置などの電力変換装置に用いられる。スイッチング素子である半導体素子１Ａ、１Ｂは、高電位側の直流電源線２と低電位側の直流電源線３との間に出力端子Ｎｔを挟んで直列に配されて、ハーフブリッジ回路４を構成している。 (First embodiment)
Hereinafter, a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 5. The drive control system shown in FIG. 1 is used in a power conversion device such as an inverter device that drives an inductive load such as a motor, or a converter device that includes an inductor and boosts / steps down a DC voltage. The semiconductor elements 1A and 1B, which are switching elements, are arranged in series between the high-potential side DC power supply line 2 and the low-potential side DC power supply line 3 with the output terminal Nt interposed therebetween to form the half-bridge circuit 4. is doing.
　同一構造を持つ半導体素子１Ａ、１Ｂは、絶縁ゲート型のトランジスタ素子５とダイオード素子６とが同一の半導体基板に形成された逆導通型ＩＧＢＴ（ＲＣ－ＩＧＢＴ）である。トランジスタ素子５の通電電極（コレクタ、エミッタ）とダイオード素子６の通電電極（カソード、アノード）は共通の電極とされている。 The semiconductor elements 1A and 1B having the same structure are reverse conducting IGBTs (RC-IGBTs) in which the insulated gate transistor element 5 and the diode element 6 are formed on the same semiconductor substrate. The energizing electrodes (collector and emitter) of the transistor element 5 and the energizing electrodes (cathode and anode) of the diode element 6 are common electrodes.
　このメイン素子に加え、半導体基板には、図２に示すようにメイン素子に流れる電流に比例した微小な電流を流すトランジスタ素子５ｓとダイオード素子６ｓとからなるセンス素子が形成されている。図１ではメイン素子とセンス素子を簡易的に表している。半導体素子１Ａ、１Ｂのセンス端子Ｓ１、Ｓ２間には、それぞれセンス抵抗７Ａ、７Ｂが接続されている。センス抵抗７Ａ、７Ｂは、後述する電流検出部２５とともに電流検出手段を構成している。 In addition to this main element, a sense element comprising a transistor element 5s and a diode element 6s for passing a minute current proportional to the current flowing through the main element is formed on the semiconductor substrate as shown in FIG. In FIG. 1, the main element and the sense element are simply shown. Sense resistors 7A and 7B are connected between the sense terminals S1 and S2 of the semiconductor elements 1A and 1B, respectively. The sense resistors 7A and 7B constitute current detection means together with a current detection unit 25 described later.
　半導体素子１Ａ、１Ｂの一例として、図３に縦型構造のＲＣ－ＩＧＢＴを示す。本実施形態のＲＣ－ＩＧＢＴは、トランジスタ構造とダイオード構造とが同一の半導体基板に設けられている。半導体基板８は、ｎ－型のシリコン基板により構成されている。図示しないが、半導体基板８の素子形成領域の周縁部近傍には、当該素子形成領域を囲むようにガードリングが形成されている。 FIG. 3 shows an RC-IGBT having a vertical structure as an example of the semiconductor elements 1A and 1B. In the RC-IGBT of this embodiment, the transistor structure and the diode structure are provided on the same semiconductor substrate. The semiconductor substrate 8 is composed of an n-type silicon substrate. Although not shown, a guard ring is formed in the vicinity of the periphery of the element formation region of the semiconductor substrate 8 so as to surround the element formation region.
　半導体基板８の上面側表層部には、ｐ型のベース層９が形成されている。ベース層９には、ベース層９を貫通する深さを持つ複数のトレンチが形成されている。トレンチ内にはポリシリコンが埋め込まれており、これによりトレンチ構造を持つゲート電極１０が形成されている。各ゲート電極１０には、共通のゲート配線１１を通してゲート駆動電圧が入力される。ゲート電極１０は、ベース層９の表層部に沿う一方向に等間隔でストライプ状に設けられている。これにより、ベース層９は、上記一方向に沿って互いに電気的に分離した複数の第１領域１２と複数の第２領域１３とに区画される。これら第１領域１２と第２領域１３は交互に配設されており、第２領域１３の幅は第１領域１２の幅よりも広くなっている。 A p-type base layer 9 is formed on the upper surface portion of the semiconductor substrate 8. A plurality of trenches having a depth penetrating the base layer 9 are formed in the base layer 9. Polysilicon is buried in the trench, whereby the gate electrode 10 having a trench structure is formed. A gate drive voltage is input to each gate electrode 10 through a common gate wiring 11. The gate electrodes 10 are provided in stripes at equal intervals in one direction along the surface layer portion of the base layer 9. Thereby, the base layer 9 is partitioned into a plurality of first regions 12 and a plurality of second regions 13 that are electrically separated from each other along the one direction. These first regions 12 and second regions 13 are alternately arranged, and the width of the second region 13 is wider than the width of the first region 12.
　第１領域１２の表層部には、ゲート電極１０に隣接してｎ＋型のエミッタ領域１４が形成されている。第１領域１２の上にはエミッタ電極１５が形成されている。エミッタ電極１５は、第１領域１２のベース層９とエミッタ領域１４とに接続されている。第１領域１２は、トランジスタ素子５のチャネル領域として動作するとともに、ダイオード素子６のアノード領域として動作する。すなわち、第１領域１２に対するエミッタ電極１５は、トランジスタ素子５のエミッタ電極およびダイオード素子６のアノード電極となる。 In the surface layer portion of the first region 12, an n + -type emitter region 14 is formed adjacent to the gate electrode 10. An emitter electrode 15 is formed on the first region 12. The emitter electrode 15 is connected to the base layer 9 and the emitter region 14 in the first region 12. The first region 12 operates as a channel region of the transistor element 5 and also operates as an anode region of the diode element 6. That is, the emitter electrode 15 for the first region 12 becomes the emitter electrode of the transistor element 5 and the anode electrode of the diode element 6.
　コレクタ領域１６（後述）の上方に設けられた第２領域１３ａは、何れの電極にも接続されていない。カソード領域１７（後述）の上方に設けられた第２領域１３ｂは、エミッタ電極１５と接続されている。これにより、第２領域１３のうちカソード領域１７の上方に設けられた第２領域１３ｂだけが、ダイオード素子６のアノード領域として動作する。すなわち、エミッタ電極１５は、第２領域１３ｂにおいてダイオード素子６のアノード電極となる。 The second region 13a provided above the collector region 16 (described later) is not connected to any electrode. A second region 13 b provided above the cathode region 17 (described later) is connected to the emitter electrode 15. Accordingly, only the second region 13 b provided above the cathode region 17 in the second region 13 operates as the anode region of the diode element 6. That is, the emitter electrode 15 becomes an anode electrode of the diode element 6 in the second region 13b.
　半導体基板８の下面側表層部には、第２領域１３ａが形成される範囲（破線の左側）に対応してｐ＋型のコレクタ領域１６が形成され、第２領域１３ｂが形成される範囲（破線の右側）に対応してｎ＋型のカソード領域１７が形成されている。コレクタ領域１６とカソード領域１７は、コレクタ電極１８と接続されている。すなわち、ダイオード素子６のカソード電極は、トランジスタ素子５のコレクタ電極１８と共通になっている。半導体基板８とコレクタ領域１６およびカソード領域１７との間には、ｎ型のフィールドストップ層１９が形成されている。 In the lower surface layer portion of the semiconductor substrate 8, a p + type collector region 16 is formed corresponding to a range (left side of the broken line) where the second region 13a is formed, and a range where the second region 13b is formed (broken line) N + type cathode region 17 is formed corresponding to the right side of FIG. The collector region 16 and the cathode region 17 are connected to the collector electrode 18. That is, the cathode electrode of the diode element 6 is in common with the collector electrode 18 of the transistor element 5. An n-type field stop layer 19 is formed between the semiconductor substrate 8 and the collector region 16 and the cathode region 17.
　図１に示す駆動制御システムにおいて、マイクロコンピュータ（マイコン）２１は、ハーフブリッジ回路４のハイサイドとローサイドのＰＷＭ信号ＦＨ、ＦＬを生成するＰＷＭ信号生成部２２を備えている。ＰＷＭ信号ＦＨ、ＦＬは、同時にＬレベル（オフ指令レベル）となる一定幅のデッドタイムＴｄを有している。ＰＷＭ信号ＦＨ、ＦＬは、それぞれフォトカプラ２３Ａ、２３Ｂを介して駆動ＩＣ２４Ａ、２４Ｂに入力される。本開示で言うオン指令信号とは、Ｈレベル（オン指令レベル）を持つＰＷＭ信号ＦＨ、ＦＬであり、オフ指令信号とは、Ｌレベル（オフ指令レベル）を持つＰＷＭ信号ＦＨ、ＦＬである。 In the drive control system shown in FIG. 1, the microcomputer 21 includes a PWM signal generation unit 22 that generates the high-side and low-side PWM signals FH and FL of the half-bridge circuit 4. The PWM signals FH and FL have a fixed dead time Td that is simultaneously at the L level (off command level). The PWM signals FH and FL are input to the drive ICs 24A and 24B via the photocouplers 23A and 23B, respectively. The ON command signal referred to in the present disclosure is the PWM signals FH and FL having the H level (ON command level), and the OFF command signal is the PWM signals FH and FL having the L level (OFF command level).
　駆動ＩＣ２４Ａ、２４Ｂは、電流検出部２５、Ｖｆ制御部２６、パルス制御部２７およびドライブ回路２８を備えており、電源電圧ＶDDA、ＶDDB（例えば１５Ｖ）が供給されることで動作する。ハイサイド側の半導体素子１Ａ、ローサイド側の半導体素子１Ｂに対し、それぞれ別個の駆動ＩＣ２４Ａ、２４Ｂが設けられている。このため、駆動ＩＣ２４Ａ、２４Ｂは、電源電圧ＶDDA、ＶDDBに応じた耐圧（すなわちゲート駆動電圧に応じた耐圧）で十分である。駆動ＩＣ２４Ａ、２４Ｂは同一構成であるため、主に駆動ＩＣ２４Ｂについての構成を説明する。 The drive ICs 24A and 24B include a current detection unit 25, a Vf control unit 26, a pulse control unit 27, and a drive circuit 28, and operate when supplied with power supply voltages VDDA and VDDB (for example, 15V). Separate drive ICs 24A and 24B are provided for the high-side semiconductor element 1A and the low-side semiconductor element 1B, respectively. For this reason, the drive ICs 24A and 24B have a sufficient withstand voltage (that is, a withstand voltage according to the gate drive voltage) according to the power supply voltages VDDA and VDDB. Since the drive ICs 24A and 24B have the same configuration, the configuration of the drive IC 24B will be mainly described.
　電流検出部２５は、センス抵抗７Ｂに生じるセンス電圧ＶSLに基づいて、半導体素子１Ｂに流れる電流に応じた電流検出信号（電流の極性と大きさ）を出力する電流検出手段である。Ｖｆ制御部２６とパルス制御部２７は、ＰＷＭ信号ＦＬに基づいてゲート駆動信号ＳGLを生成する。ドライブ回路２８は、ゲート駆動信号ＳGLを入力してゲート駆動電圧ＶGLを出力する。 The current detector 25 is a current detector that outputs a current detection signal (polarity and magnitude of current) corresponding to the current flowing through the semiconductor element 1B based on the sense voltage VSL generated in the sense resistor 7B. The Vf control unit 26 and the pulse control unit 27 generate the gate drive signal SGL based on the PWM signal FL. The drive circuit 28 receives the gate drive signal SGL and outputs a gate drive voltage VGL.
　Ｖｆ制御部２６は、ＰＷＭ信号ＦＬがＨレベルの期間において、ダイオード素子６の順方向の向きに流れる半導体素子１Ｂの電流が電流しきい値Ｉｔ以上のときに、ゲート駆動電圧ＶGLを遮断する制御を行う。この制御は、半導体素子１Ｂの電圧（ＲＣ－ＩＧＢＴの場合にはダイオード素子６の順方向電圧Ｖｆ）を低下させて導通損失を低減する作用を持つ。以下の説明ではＶｆ制御と称する。 The Vf control unit 26 controls to cut off the gate drive voltage VGL when the current of the semiconductor element 1B flowing in the forward direction of the diode element 6 is equal to or greater than the current threshold It during the period in which the PWM signal FL is at the H level. I do. This control has the effect of reducing the conduction loss by lowering the voltage of the semiconductor element 1B (in the case of RC-IGBT, the forward voltage Vf of the diode element 6). In the following description, this is referred to as Vf control.
　パルス制御部２７は、ＰＷＭ信号ＦＬがＨレベルの期間に半導体素子１Ｂにダイオード素子６の順方向の向きの電流が流れているとき、ＰＷＭ信号ＦＬの立ち下がりを基準として、パルス状のゲート駆動信号ＳGLを出力する。このゲート駆動信号ＳGLにより、半導体素子１Ｂのゲートにパルス状のゲート駆動電圧ＶGL（以下、ゲート駆動パルスと称す）が印加される。この制御は、ダイオード素子６に蓄積されるホールを減少させ、逆回復電流を低減する作用を持つ。以下の説明ではパルス制御と称する。 The pulse control unit 27 performs pulse-shaped gate driving with reference to the falling edge of the PWM signal FL when a current in the forward direction of the diode element 6 flows through the semiconductor element 1B during the period in which the PWM signal FL is at the H level. The signal SGL is output. By this gate drive signal SGL, a pulsed gate drive voltage VGL (hereinafter referred to as a gate drive pulse) is applied to the gate of the semiconductor element 1B. This control has the effect of reducing the holes accumulated in the diode element 6 and reducing the reverse recovery current. In the following description, this is referred to as pulse control.
　Ｖｆ制御部２６とパルス制御部２７とで生成されたゲート駆動信号ＳGLは、ドライブ回路２８を介して半導体素子１Ｂのゲートに与えられる。ドライブ回路２８は、ゲートを充放電する駆動能力を複数通りに切り替えられる。すなわち、ＰＷＭ信号ＦＬの立ち上がり時、トランジスタ素子５に電流が流れている状態からのＰＷＭ信号ＦＬの立ち下がり時など、半導体素子１Ｂに流れる電流（素子電流）や電圧に急峻な変化が生じるときには、電圧サージの発生を抑制するため低い駆動能力に切り替えられる。この場合、ドライブ回路２８は、ターンオン時においては定電流回路を用いて駆動し、ターンオフ時においてはオン抵抗を高めたスイッチ素子を用いて駆動する。 The gate drive signal SGL generated by the Vf control unit 26 and the pulse control unit 27 is given to the gate of the semiconductor element 1B via the drive circuit 28. The drive circuit 28 can switch the driving ability to charge / discharge the gate in a plurality of ways. That is, when a sharp change occurs in the current (element current) or voltage flowing through the semiconductor element 1B, such as at the rising edge of the PWM signal FL or at the falling edge of the PWM signal FL from the state where the current flows in the transistor element 5, In order to suppress the occurrence of a voltage surge, the driving capability can be switched to a low level. In this case, the drive circuit 28 is driven by using a constant current circuit at the time of turn-on, and is driven by using a switch element having an increased on-resistance at the time of turn-off.
　これに対し、パルス制御のように素子電流や電圧に急峻な変化が生じないときには、高い駆動能力に切り替えられる。この場合、ドライブ回路２８は、ターンオン時においては定電圧回路を用いて駆動し、ターンオフ時においてはオン抵抗を高めたスイッチ素子とオン抵抗を下げたスイッチ素子とを並列に接続して駆動する。 On the other hand, when there is no steep change in the device current or voltage as in pulse control, the driving capability can be switched to high. In this case, the drive circuit 28 is driven by using a constant voltage circuit at the time of turn-on, and is driven by connecting in parallel a switch element having a higher on-resistance and a switch element having a lower on-resistance at the time of turn-off.
　駆動ＩＣ２４Ａには、しきい値設定回路２９Ａ、３０Ａ、３１Ａが外付けされている。駆動ＩＣ２４Ｂには、しきい値設定回路２９Ｂ、３０Ｂ、３１Ｂが外付けされている。しきい値設定回路２９Ａ、３０Ａ、３１Ａは、半導体素子１Ａのエミッタ電位に等しいフローティンググランドＦＧを基準電位として構成されている。しきい値設定回路２９Ａ、２９Ｂは、電圧ＶDDA、ＶDDBを抵抗Ｒ１、Ｒ２で分圧してしきい値電圧Ｖｔを生成する。しきい値設定回路３０Ａ、３０Ｂは、電圧ＶDDA、ＶDDBを抵抗Ｒ３、Ｒ４で分圧して規定電圧Ｖm1を生成する。しきい値設定回路３１Ａ、３１Ｂは、電圧ＶDDA、ＶDDBを抵抗Ｒ５、Ｒ６で分圧して規定電圧Ｖm2を生成する。 Threshold value setting circuits 29A, 30A, 31A are externally attached to the driving IC 24A. Threshold setting circuits 29B, 30B, 31B are externally attached to the driving IC 24B. The threshold setting circuits 29A, 30A, 31A are configured with a floating ground FG equal to the emitter potential of the semiconductor element 1A as a reference potential. The threshold setting circuits 29A and 29B divide the voltages VDDA and VDDB by the resistors R1 and R2 to generate a threshold voltage Vt. The threshold setting circuits 30A and 30B divide the voltages VDDA and VDDB by resistors R3 and R4 to generate a specified voltage Vm1. The threshold setting circuits 31A and 31B divide the voltages VDDA and VDDB by the resistors R5 and R6 to generate a specified voltage Vm2.
　しきい値電圧Ｖｔは、Ｖｆ制御部２６で用いられる電流しきい値Ｉｔの大きさを決定する。後述するように、ダイオード素子６の順方向電流Ｉｆに対する順方向電圧Ｖｆの特性は、素子の種類（ＲＣ－ＩＧＢＴ、ＭＯＳトランジスタ等）や素子の耐圧によって異なる。そこで、Ｖｆ制御部２６は、外部から与えられる切替信号Ｓｋとしきい値電圧Ｖｔとに基づいて、適切な電流しきい値Ｉｔを選択する。 The threshold voltage Vt determines the magnitude of the current threshold It used in the Vf control unit 26. As will be described later, the characteristic of the forward voltage Vf with respect to the forward current If of the diode element 6 varies depending on the type of element (RC-IGBT, MOS transistor, etc.) and the breakdown voltage of the element. Therefore, the Vf control unit 26 selects an appropriate current threshold It based on the switching signal Sk and the threshold voltage Vt given from the outside.
　規定電圧Ｖm1は、Ｖｆ制御を停止するか否かの判定に用いる規定値Ｉm1の大きさを決定する。規定電圧Ｖm2は、パルス制御を停止するか否かの判定に用いる規定値Ｉm2の大きさを決定する。電流検出時と、その検出電流の極性に基づいてゲート駆動電圧ＶGH、ＶGLを印加した時とでは、制御の遅れにより電流極性が反転している虞もある。このため、Ｖｆ制御部２６は、電流検出値が規定値Ｉm1を下回るとＶｆ制御を停止し、パルス制御部２７は、電流検出値が規定値Ｉm2を下回るとパルス制御を停止する。 The specified voltage Vm1 determines the magnitude of the specified value Im1 used for determining whether or not to stop the Vf control. The specified voltage Vm2 determines the magnitude of the specified value Im2 used for determining whether or not to stop the pulse control. When the current is detected and when the gate drive voltages VGH and VGL are applied based on the polarity of the detected current, there is a possibility that the current polarity is reversed due to a delay in control. Therefore, the Vf control unit 26 stops the Vf control when the current detection value falls below the specified value Im1, and the pulse control unit 27 stops the pulse control when the current detection value falls below the specified value Im2.
　以上説明した駆動ＩＣ２４Ａとセンス抵抗７Ａにより駆動制御装置３２Ａが構成され、駆動ＩＣ２４Ｂとセンス抵抗７Ｂにより駆動制御装置３２Ｂが構成されている。 The drive control device 32A is configured by the drive IC 24A and the sense resistor 7A described above, and the drive control device 32B is configured by the drive IC 24B and the sense resistor 7B.
　次に、図４および図５を参照しながら、主としてローサイド側の駆動制御装置３２Ｂの作用について説明する。ハイサイド側の駆動制御装置３２Ａの作用も同様となる。 Next, the operation of the drive control device 32B on the low side will be mainly described with reference to FIGS. The operation of the drive control device 32A on the high side is the same.
　はじめにＶｆ制御について説明する。ＲＣ－ＩＧＢＴである半導体素子１Ａ、１Ｂは、ダイオード素子６に電流が流れている状態でゲート駆動電圧が印加されると、第１領域１２にチャネルが形成されてホールの注入が抑制される。このため、図４に示すように、順方向電流Ｉｆが流れているダイオード素子６の順方向電圧Ｖｆが高くなり、ダイオード素子６の導通損失（Ｖｆ×Ｉｆ）が増大する。 First, Vf control will be described. In the semiconductor elements 1A and 1B, which are RC-IGBTs, when a gate drive voltage is applied in a state where a current flows through the diode element 6, a channel is formed in the first region 12 and hole injection is suppressed. For this reason, as shown in FIG. 4, the forward voltage Vf of the diode element 6 through which the forward current If flows increases, and the conduction loss (Vf × If) of the diode element 6 increases.
　半導体素子１Ａ、１ＢがＭＯＳトランジスタの場合（第２の実施形態を参照）でも同様の作用が生じる。一般に、素子の高耐圧化によりドリフト領域の厚さが増すほど、全体のオン抵抗に占めるチャネルの抵抗割合が小さくなり、ゲート駆動電圧の印加時にダイオード素子６の導通損失が増大する傾向を示す。 The same effect occurs even when the semiconductor elements 1A and 1B are MOS transistors (see the second embodiment). Generally, as the thickness of the drift region increases due to the higher breakdown voltage of the element, the resistance ratio of the channel occupying the entire on-resistance decreases, and the conduction loss of the diode element 6 tends to increase when a gate drive voltage is applied.
　ＲＣ－ＩＧＢＴの場合、ダイオード素子６について、ゲート駆動電圧が遮断されている時における導通損失と印加されている時における導通損失とが等しくなる電流値（電流しきい値Ｉｔ）は小さい値になる。図４に示す場合にはほぼゼロである。これに対し、ＭＯＳトランジスタ等の場合には、ゲート駆動電圧が遮断されている時におけるダイオード素子６の導通損失と、ゲート駆動電圧が印加されている時におけるトランジスタ素子５の導通損失とが等しくなる電流値（電流しきい値Ｉｔ）は、比較的大きい値になる（図６参照）。すなわち、電流しきい値Ｉｔは、半導体素子１Ａ、１Ｂの種類や耐圧によって異なるため、予め測定されている。 In the case of the RC-IGBT, the diode element 6 has a small current value (current threshold It) at which the conduction loss when the gate drive voltage is cut off is equal to the conduction loss when the gate drive voltage is applied. . In the case shown in FIG. 4, it is almost zero. On the other hand, in the case of a MOS transistor or the like, the conduction loss of the diode element 6 when the gate drive voltage is cut off is equal to the conduction loss of the transistor element 5 when the gate drive voltage is applied. The current value (current threshold value It) is a relatively large value (see FIG. 6). That is, the current threshold It varies depending on the type and breakdown voltage of the semiconductor elements 1A and 1B, and is measured in advance.
　ＲＣ－ＩＧＢＴを駆動する場合には切替信号Ｓｋが例えばＬレベルに切り替えられ、ＭＯＳトランジスタを駆動する場合には切替信号Ｓｋが例えばＨレベルに切り替えられる。切替信号Ｓｋは、外部から電流しきい値Ｉｔを特定するしきい値特定信号である。Ｖｆ制御部２６は、切替信号ＳｋがＬレベルのときに、電流しきい値Ｉｔをゼロに設定してＶｆ制御を実行する。一方、切替信号ＳｋがＨレベルのときに、外部から入力するしきい値電圧Ｖｔに応じた電流しきい値Ｉｔを設定してＶｆ制御を実行する。 When driving the RC-IGBT, the switching signal Sk is switched to L level, for example, and when driving the MOS transistor, the switching signal Sk is switched to H level, for example. The switching signal Sk is a threshold value specifying signal for specifying the current threshold value It from the outside. When the switching signal Sk is at the L level, the Vf control unit 26 sets the current threshold It to zero and executes Vf control. On the other hand, when the switching signal Sk is at the H level, the current threshold value It corresponding to the threshold voltage Vt input from the outside is set and the Vf control is executed.
　図５は、出力端子Ｎｔから負荷に向かって電流が流れている場合に、半導体素子１Ａをオフして半導体素子１Ｂをオンした後、半導体素子１Ｂをオフして再度半導体素子１Ａをオンしたときの波形である。上から順に、半導体素子１Ａの電流、ゲート駆動電圧ＶGH、ＶGL、ＰＷＭ信号ＦＨ、ゲート駆動電圧ＶGLを指令するゲート駆動信号ＳGL、ＰＷＭ信号ＦＬを示している。Ｖthは、半導体素子１Ａのしきい値電圧である。 FIG. 5 shows a case where the semiconductor element 1A is turned off and the semiconductor element 1B is turned on when the current flows from the output terminal Nt toward the load, and then the semiconductor element 1B is turned off and the semiconductor element 1A is turned on again. It is a waveform. In order from the top, the current of the semiconductor element 1A, the gate drive voltages VGH and VGL, the PWM signal FH, and the gate drive signal SGL and the PWM signal FL for commanding the gate drive voltage VGL are shown. Vth is the threshold voltage of the semiconductor element 1A.
　上下アーム間で通電が切り替わるとき、ゲート駆動電圧ＶGHがしきい値電圧Ｖth以上になると（時刻ｔ９）、半導体素子１Ａのトランジスタ素子５に流れる電流が増加する。図５に示す場合、増加するトランジスタ素子５の電流のうち、半導体素子１Ｂのダイオード素子６に流れていた電流を超える電流が逆回復電流である。図面ではハッチングで示している（時刻ｔ１０～ｔ１１）。 When energization is switched between the upper and lower arms, when the gate drive voltage VGH becomes equal to or higher than the threshold voltage Vth (time t9), the current flowing through the transistor element 5 of the semiconductor element 1A increases. In the case shown in FIG. 5, among the increasing current of the transistor element 5, the current exceeding the current flowing in the diode element 6 of the semiconductor element 1B is the reverse recovery current. In the drawing, hatching is indicated (time t10 to t11).
　駆動ＩＣ２４ＢのＶｆ制御部２６は、ＰＷＭ信号ＦＬがＨレベルの期間（時刻ｔ２～ｔ３）、ダイオード素子６の検出電流がその順方向において電流しきい値Ｉｔ以上であるか否かを判定する。ここで、電流しきい値Ｉｔ未満であると判定すると、Ｈレベルのゲート駆動信号ＳGLを出力する。このゲート駆動信号ＳGLに基づいて、ドライブ回路２８での遅延、半導体素子１Ｂの素子容量の充電時間などに応じて、ゲート駆動電圧ＶGLが半導体素子１Ｂのゲートに印加される。これに対し、検出電流が電流しきい値Ｉｔ以上であると判定すると（図５に示す場合）、Ｌレベルのゲート駆動信号ＳGLを出力する。これにより、ゲート駆動電圧ＶGLが遮断される。 The Vf control unit 26 of the drive IC 24B determines whether or not the detected current of the diode element 6 is equal to or higher than the current threshold It in the forward direction during the period when the PWM signal FL is at the H level (time t2 to t3). If it is determined that the current is less than the current threshold It, an H level gate drive signal SGL is output. Based on the gate drive signal SGL, the gate drive voltage VGL is applied to the gate of the semiconductor element 1B in accordance with the delay in the drive circuit 28, the charging time of the element capacitance of the semiconductor element 1B, and the like. On the other hand, if it is determined that the detected current is equal to or greater than the current threshold It (in the case shown in FIG. 5), an L level gate drive signal SGL is output. Thereby, the gate drive voltage VGL is cut off.
　次に、パルス制御について説明する。パルス制御は、ＰＷＭ信号ＦＬがＨレベルの期間に半導体素子１Ｂのダイオード素子６に電流が流れている場合、ＰＷＭ信号ＦＬがＬレベルに立ち下がった後、逆回復電流が流れ始める前までに、半導体素子１Ｂにゲート駆動パルスを印加する制御である。ＰＷＭ信号ＦＨがＨレベルの期間に半導体素子１Ａのダイオード素子６に電流が流れている場合であって、ＰＷＭ信号ＦＨがＬレベルに立ち下がった後も同様である。これにより、ダイオード素子６に蓄積されるキャリア（ホール）が減少するので、逆回復電流を低減する作用が得られる。 Next, pulse control will be described. In the pulse control, when the current flows through the diode element 6 of the semiconductor element 1B during the period in which the PWM signal FL is at the H level, after the PWM signal FL falls to the L level and before the reverse recovery current starts to flow, This is control for applying a gate drive pulse to the semiconductor element 1B. This is also the case when a current flows through the diode element 6 of the semiconductor element 1A during the period in which the PWM signal FH is at the H level, and the same applies after the PWM signal FH falls to the L level. As a result, carriers (holes) accumulated in the diode element 6 are reduced, so that an effect of reducing the reverse recovery current can be obtained.
　図５において、パルス制御部２７は、ＰＷＭ信号ＦＬがＨレベルの期間、より好ましくはＰＷＭ信号ＦＬがＬレベルに立ち下がったときに（時刻ｔ３）、半導体素子１Ｂのダイオード素子６に電流が流れているか否かを判定する。電流が流れている場合（ただし、電流検出値が規定値Ｉm2以上の場合）、ＰＷＭ信号ＦＬの立ち下がり時点を起点として、第１時間Ｔ１の経過時点（時刻ｔ４）から第２時間Ｔ２の経過時点（時刻ｔ６）までゲート駆動信号ＳGLをＨレベルにする。上述したＶｆ制御により、ＰＷＭ信号ＦＬの立ち下がり時点では、ゲート駆動信号ＳGLはＬレベルになっている。 In FIG. 5, the pulse control unit 27 causes a current to flow through the diode element 6 of the semiconductor element 1B when the PWM signal FL is at the H level, more preferably when the PWM signal FL falls to the L level (time t3). It is determined whether or not. When current is flowing (however, when the detected current value is equal to or greater than the specified value Im2), the second time T2 has elapsed from the time when the first time T1 has elapsed (time t4), starting from the falling time of the PWM signal FL. The gate drive signal SGL is kept at the H level until the time (time t6). By the above-described Vf control, the gate drive signal SGL is at the L level at the time of falling of the PWM signal FL.
　パルス制御部２７は、ＰＷＭ信号ＦＬがＬレベルに立ち下がった後も、半導体素子１Ｂのダイオード素子６に電流が流れているか否かを判定し続ける。パルス制御部２７は、電流検出値が規定値Ｉm2を下回ると、第１時間Ｔ１が経過した後、第２時間Ｔ２が経過する前であっても、直ちにゲート駆動信号ＳGLをＬレベルに戻す。 The pulse control unit 27 continues to determine whether or not a current is flowing through the diode element 6 of the semiconductor element 1B even after the PWM signal FL falls to the L level. When the current detection value falls below the specified value Im2, the pulse control unit 27 immediately returns the gate drive signal SGL to the L level even after the first time T1 has elapsed and before the second time T2 has elapsed.
　一方、パルス制御部２７は、ＰＷＭ信号ＦＬがＬレベルに立ち下がったときにダイオード素子６に電流が流れていないと判定すると、直ちにゲート駆動信号ＳGLをＬレベルにして維持する。すなわち、ゲート駆動パルスを印加しない。 On the other hand, when the pulse control unit 27 determines that no current flows through the diode element 6 when the PWM signal FL falls to the L level, the pulse control unit 27 immediately maintains the gate drive signal SGL at the L level. That is, no gate drive pulse is applied.
　第１時間Ｔ１と第２時間Ｔ２は、アーム短絡が生じないように予め設定されている。ＰＷＭ信号ＦＬがＬレベルの期間にダイオード素子６に電流が流れている場合と、トランジスタ素子５に電流が流れている場合とでは、ゲート駆動パルスを与えたときのゲート駆動電圧ＶGLの波形が異なる。 The first time T1 and the second time T2 are set in advance so as not to cause an arm short circuit. The waveform of the gate drive voltage VGL when a gate drive pulse is applied differs between when the current flows through the diode element 6 and when the current flows through the transistor element 5 while the PWM signal FL is at the L level. .
　ダイオード素子６に電流が流れている場合には、半導体素子１Ｂのコレクタ・エミッタ間電圧が変化しないのでミラー期間が生じない。また、半導体素子１Ｂに急峻な電流変化、電圧変化が生じない。このため、ドライブ回路２８は、ゲート駆動電圧ＶGLの立ち上げ時および立ち下げ時に、通常よりも高いゲート駆動能力でゲート駆動電圧ＶGLを出力できる。さらに、ダイオード素子６に電流が流れているときには、半導体素子１Ａ、１Ｂを介した経路で短絡する可能性がない。このため、ゲート駆動電圧ＶGLの増加過程で、ゲート駆動電圧ＶGLを一時的に中間電圧に留め、他方サイドの半導体素子１Ａが短絡故障している時の短絡電流を低減する２段階駆動を行う必要がない。 When a current flows through the diode element 6, the collector-emitter voltage of the semiconductor element 1B does not change, so that no mirror period occurs. In addition, no steep current change or voltage change occurs in the semiconductor element 1B. Therefore, the drive circuit 28 can output the gate drive voltage VGL with a higher gate drive capability than usual when the gate drive voltage VGL rises and falls. Further, when a current flows through the diode element 6, there is no possibility of short-circuiting along a path through the semiconductor elements 1A and 1B. For this reason, in the process of increasing the gate drive voltage VGL, it is necessary to perform the two-stage drive for temporarily holding the gate drive voltage VGL at the intermediate voltage and reducing the short-circuit current when the semiconductor element 1A on the other side is short-circuited. There is no.
　第１時間Ｔ１と第２時間Ｔ２は、ゲート駆動パルスの印加時におけるゲート駆動電圧ＶGLの波形およびドライブ回路２８の駆動態様を考慮して、ゲート駆動電圧ＶGLがドライブ回路２８のゲート駆動能力に従って単調に増加または単調に減少するものとして設定されている。その際、ゲート駆動パルスの印加終了時点から逆回復電流が流れ始めるまでの時間Ｔｃ（キャリアの再注入時間）が、ゼロよりも長く且つ注入許容時間以下となるように設定される。注入許容時間は、許容される逆回復電流の大きさに応じて規定されている。 The first time T1 and the second time T2 are monotonous according to the gate drive capability of the drive circuit 28 in consideration of the waveform of the gate drive voltage VGL when the gate drive pulse is applied and the drive mode of the drive circuit 28. Set to increase or decrease monotonically. At this time, the time Tc (carrier reinjection time) from the end of application of the gate drive pulse until the reverse recovery current starts to flow is set to be longer than zero and shorter than the allowable injection time. The allowable injection time is specified according to the allowable reverse recovery current.
　具体的には、第１時間Ｔ１と第２時間Ｔ２は、ダイオード素子６に流れる電流を種々に変えながら、ＰＷＭ信号ＦＬの立ち下がり時点を起点として、ゲート駆動信号ＳGLの印加タイミング、実際にゲート駆動電圧ＶGLが印加されるタイミング、および逆回復電流が流れ始めるタイミングを予め測定して設定されている。この第１時間Ｔ１と第２時間Ｔ２は、本実施形態では電流と対応付けてパルス制御部２７内のメモリ等に記憶されている。なお、この第１時間Ｔ１と第２時間Ｔ２は１又は数パターンのロジック回路又はアナログ遅延回路などを用いて生成することもできる。 Specifically, the first time T1 and the second time T2 vary the current flowing through the diode element 6 while changing the current flowing through the diode element 6 and starting from the falling point of the PWM signal FL. The timing at which the drive voltage VGL is applied and the timing at which the reverse recovery current starts to flow are set in advance by measurement. In this embodiment, the first time T1 and the second time T2 are stored in a memory or the like in the pulse control unit 27 in association with the current. The first time T1 and the second time T2 can also be generated using one or several patterns of logic circuits or analog delay circuits.
　パルス制御部２７は、ゲート駆動パルスを印加する場合、電流検出信号を参照してダイオード素子６に流れている電流を求め、その電流値に応じた第１時間Ｔ１と第２時間Ｔ２をメモリから読み出す。パルス制御部２７は、ＰＷＭ信号ＦＬの立ち下がり時点を起点として、第１時間Ｔ１の経過時点でゲート駆動信号ＳGLの立ち上げ、第２時間Ｔ２の経過時点でゲート駆動信号ＳGLを立ち下げる。 When applying the gate drive pulse, the pulse control unit 27 refers to the current detection signal to obtain the current flowing in the diode element 6 and calculates the first time T1 and the second time T2 corresponding to the current value from the memory. read out. The pulse control unit 27 starts from the falling point of the PWM signal FL, and raises the gate driving signal SGL when the first time T1 has elapsed, and lowers the gate driving signal SGL when the second time T2 has elapsed.
　以上説明したように、本実施形態の駆動制御装置３２Ａ、３２Ｂは、それぞれＰＷＭ信号ＦＨ、ＦＬがＨレベルの期間に、ダイオード素子６の順方向の向きに流れる半導体素子１Ａ、１Ｂの電流（ダイオード電流）が電流しきい値Ｉｔ（本実施形態では０）以上であると判定すると、ゲート駆動信号ＳGH、ＳGLをＬレベルにする。電流しきい値Ｉｔは、ゲート駆動電圧ＶGH、ＶGLが遮断されている時における半導体素子１Ａ、１Ｂの導通損失と、ゲート駆動電圧ＶGH、ＶGLが印加されている時における半導体素子１Ａ、１Ｂの導通損失とが等しくなる電流値である。このＶｆ制御により、半導体素子１Ａ、１Ｂの種類や耐圧にかかわらず、ダイオード素子６の導通損失を低減することができる。 As described above, the drive control devices 32A and 32B according to the present embodiment have the currents (diodes of the semiconductor elements 1A and 1B flowing in the forward direction of the diode element 6 during the period in which the PWM signals FH and FL are at the H level, respectively. If it is determined that (current) is equal to or greater than the current threshold It (0 in this embodiment), the gate drive signals SGH and SGL are set to the L level. The current threshold It is the conduction loss of the semiconductor elements 1A and 1B when the gate drive voltages VGH and VGL are cut off, and the conduction of the semiconductor elements 1A and 1B when the gate drive voltages VGH and VGL are applied. This is the current value at which the loss becomes equal. With this Vf control, the conduction loss of the diode element 6 can be reduced regardless of the type and breakdown voltage of the semiconductor elements 1A and 1B.
　駆動制御装置３２Ａ、３２Ｂは、上下アーム間で通電が切り替わるとき、それぞれＰＷＭ信号ＦＨ、ＦＬがＨレベルの期間に半導体素子１Ａ、１Ｂにダイオード素子６の順方向の向きに電流が流れていると判定すると、ゲート駆動パルスの印加を指令するゲート駆動信号ＳGH、ＳGLを出力する。このパルス制御により、ダイオード素子６に蓄積されるホールが減少して逆回復電流が低減するので、スイッチング損失を低減できる。 In the drive control devices 32A and 32B, when energization is switched between the upper and lower arms, current flows in the forward direction of the diode element 6 in the semiconductor elements 1A and 1B during the period in which the PWM signals FH and FL are at the H level, respectively. When it is determined, gate drive signals SGH and SGL for instructing application of the gate drive pulse are output. By this pulse control, the holes accumulated in the diode element 6 are reduced and the reverse recovery current is reduced, so that the switching loss can be reduced.
　駆動ＩＣ２４Ａ、２４Ｂのパルス制御部２７は、ＰＷＭ信号ＦＨ、ＦＬの立ち下がり時点を起点として、第１時間Ｔ１の経過時点から第２時間Ｔ２の経過時点までゲート駆動信号ＳGH、ＳGLをＨレベルにする。ＰＷＭ信号ＦＨ、ＦＬの立ち下がり時点はデッドタイムＴｄの起点でもあるので、一定の時間を持つデッドタイムＴｄを有効に利用して、アーム短絡を防止しながらゲート駆動パルスを印加することができる。 The pulse control unit 27 of the drive ICs 24A and 24B sets the gate drive signals SGH and SGL to the H level from the time when the first time T1 has elapsed to the time when the second time T2 has elapsed, starting from the falling time of the PWM signals FH and FL. To do. Since the falling point of the PWM signals FH and FL is also the starting point of the dead time Td, the gate driving pulse can be applied while effectively preventing the arm short circuit by effectively using the dead time Td having a certain time.
　第１時間Ｔ１と第２時間Ｔ２は、デッドタイムＴｄ、素子電流に対応させて予め測定されたゲート駆動電圧ＶGH、ＶGLの遅延やばらつきおよび逆回復電流が流れ始めるまでの時間に基づいて設定されている。また、第１時間Ｔ１と第２時間Ｔ２は、ゲート駆動パルスの印加時におけるゲート駆動電圧の波形およびドライブ回路２８の駆動態様を考慮して設定されている。これにより、ゲート駆動パルスのパルス幅Ｔｗを広く確保できる。また、ゲート駆動パルスの印加タイミングの精度を高めることができ、再注入時間Ｔｃを正確に制御可能となる。その結果、アーム短絡を防止しつつ再注入時間Ｔｃを短く制御することが可能となり、スイッチング損失を一層低減できる。 The first time T1 and the second time T2 are set based on the dead time Td, the delay and variation of the gate drive voltages VGH and VGL measured in advance corresponding to the element current, and the time until the reverse recovery current starts to flow. ing. The first time T1 and the second time T2 are set in consideration of the waveform of the gate drive voltage and the drive mode of the drive circuit 28 when the gate drive pulse is applied. Thereby, a wide pulse width Tw of the gate drive pulse can be secured. In addition, the accuracy of the application timing of the gate drive pulse can be increased, and the reinjection time Tc can be accurately controlled. As a result, the reinjection time Tc can be controlled to be short while preventing an arm short circuit, and the switching loss can be further reduced.
　パルス制御部２７は、パルス制御に基づきゲート駆動パルスを印加している期間（時刻ｔ４～ｔ６）であっても、ダイオード素子６に電流が流れなくなる（電流検出値が規定値Ｉm2未満となる）可能性があるまたは電流が流れていないと判定すると、直ちにゲート駆動パルスの印加を停止する。これにより、負荷電流が急変した場合でもアーム短絡を確実に防止できる。さらに、負荷電流の急変に備えて規定値Ｉm2を高めに設定する必要がなくなるので、パルス制御を実行する電流範囲を広く確保でき、スイッチング損失を一層低減できる。 The pulse control unit 27 stops the current from flowing through the diode element 6 even during the period (time t4 to t6) in which the gate drive pulse is applied based on the pulse control (the detected current value is less than the specified value Im2). If it is determined that there is a possibility or no current is flowing, the application of the gate drive pulse is immediately stopped. Thereby, even when the load current changes suddenly, an arm short circuit can be reliably prevented. Furthermore, since it is not necessary to set the specified value Im2 higher in preparation for a sudden change in the load current, a wide current range for performing the pulse control can be secured, and the switching loss can be further reduced.
　パルス制御部２７は、ＰＷＭ信号ＦＨ、ＦＬの立ち下がり時点を起点としてゲート駆動信号を印加するので、別のタイミング信号が不要となり、従来から使用している駆動制御装置からの置き替えが容易になる。駆動制御装置３２Ａ、３２Ｂは、制御ループが短いので高応答が得られる。駆動ＩＣ２４Ａ、２４Ｂは、フォトカプラ２３Ａ、２３Ｂを介してハーフブリッジ回路４側に設けられているので、電流検出部２５に絶縁機能が不要となる。 Since the pulse control unit 27 applies the gate drive signal starting from the falling point of the PWM signals FH and FL, no separate timing signal is required, and the replacement from the conventionally used drive control device is easy. Become. The drive control devices 32A and 32B have high response because the control loop is short. Since the drive ICs 24A and 24B are provided on the half bridge circuit 4 side via the photocouplers 23A and 23B, the current detection unit 25 does not need an insulating function.
　Ｖｆ制御部２６、パルス制御部２７は、それぞれ負荷電流の大きさが規定値Ｉm1、Ｉm2よりも小さくなるとＶｆ制御、パルス制御を停止して通常制御を行う。通常制御とは、ダイオード素子６に流れる電流にかかわらず、ＰＷＭ信号が立ち上がるとゲート駆動信号を立ち上げ、ＰＷＭ信号が立ち下がるとゲート駆動信号を立ち下げる制御である。これにより、電流検出精度の低下による誤制御を防止することができる。 The Vf control unit 26 and the pulse control unit 27 stop the Vf control and the pulse control and perform the normal control when the magnitude of the load current becomes smaller than the specified values Im1 and Im2, respectively. The normal control is control that raises the gate drive signal when the PWM signal rises and lowers the gate drive signal when the PWM signal falls regardless of the current flowing through the diode element 6. Thereby, erroneous control due to a decrease in current detection accuracy can be prevented.
　（第２の実施形態）
　半導体素子１Ａ、１ＢにＭＯＳトランジスタを用いた第２の実施形態について、図６および図７を参照しながら説明する。駆動制御装置３２Ａ、３２Ｂの構成は、図１に示した通りである。ここでは、主としてローサイド側の駆動制御装置３２Ｂの作用について説明する。ハイサイド側の駆動制御装置３２Ａの作用も同様となる。 (Second Embodiment)
A second embodiment using MOS transistors for the semiconductor elements 1A and 1B will be described with reference to FIGS. The configuration of the drive control devices 32A and 32B is as shown in FIG. Here, the operation of the drive control device 32B on the low side will be mainly described. The operation of the drive control device 32A on the high side is the same.
　半導体素子１Ａ、１ＢとしてＭＯＳトランジスタを用いる場合、切替信号Ｓｋが例えばＨレベルに切り替えられる。駆動制御装置３２Ｂは、しきい値設定回路２９Ｂから入力したしきい値電圧Ｖｔに応じて電流しきい値Ｉｔを設定し、Ｖｆ制御を実行する。 When MOS transistors are used as the semiconductor elements 1A and 1B, the switching signal Sk is switched to, for example, the H level. Drive control device 32B sets current threshold It according to threshold voltage Vt input from threshold setting circuit 29B, and executes Vf control.
　図６は、ＭＯＳトランジスタにダイオード素子６の順方向の向きに電流が流れる場合の電圧電流特性図である。電流しきい値Ｉｔを境界として、ゲート駆動電圧が遮断されている時のダイオード素子６の順方向電圧Ｖｆと、ゲート駆動電圧が印加されている時のトランジスタ素子５のドレイン・ソース間電圧ＶDSとの大小関係が反転する。電圧ＶDS＜電圧Ｖｆとなる領域１では、ゲート駆動電圧を印加することにより導通損失を低減できる。電圧ＶDS≧電圧Ｖｆとなる領域２では、ゲート駆動電圧を遮断することにより導通損失を低減できる。 FIG. 6 is a voltage-current characteristic diagram when a current flows through the MOS transistor in the forward direction of the diode element 6. With the current threshold It as a boundary, the forward voltage Vf of the diode element 6 when the gate drive voltage is cut off, and the drain-source voltage VDS of the transistor element 5 when the gate drive voltage is applied The magnitude relationship of is reversed. In region 1 where voltage VDS <voltage Vf, conduction loss can be reduced by applying a gate drive voltage. In region 2 where voltage VDS ≧ voltage Vf, conduction loss can be reduced by cutting off the gate drive voltage.
　ＰＷＭ信号ＦＬがＨレベルの期間において、半導体素子１Ｂに領域１の範囲内の電流が流れている場合、Ｖｆ制御部２６は、ゲート駆動電圧ＶGLを印加する通常制御（同期整流）を実行する。その後ＰＷＭ信号ＦＬがＬレベルになると、半導体素子１Ｂにゲート駆動パルスを印加する必要がある。 When the current in the region 1 flows through the semiconductor element 1B during the period when the PWM signal FL is at the H level, the Vf control unit 26 performs normal control (synchronous rectification) to apply the gate drive voltage VGL. Thereafter, when the PWM signal FL becomes L level, it is necessary to apply a gate drive pulse to the semiconductor element 1B.
　この場合、Ｖｆ制御部２６がゲート駆動信号ＳGLをＬレベルにした後、パルス制御部２７が、ＰＷＭ信号ＦＬの立ち下がり時点を起点として、第１時間Ｔ１の経過時点から第２時間Ｔ２の経過時点までゲート駆動信号ＳGLをＨレベルにすればよい。しかし、ゲート駆動電圧ＶGLを一旦遮断するよりも、第２時間Ｔ２の経過時点までゲート駆動電圧ＶGLを連続して印加する方が導通損失を低減することができる。そこで、Ｖｆ制御部２６は、Ｖｆ制御に続きパルス制御を行うため、Ｈレベルのゲート駆動信号ＳGLを、時刻ｔ３を越えて第２時間Ｔ２の経過時点（時刻ｔ６）まで延長して出力する（パルスの拡張）。 In this case, after the Vf control unit 26 sets the gate drive signal SGL to the L level, the pulse control unit 27 starts from the time when the PWM signal FL falls and the second time T2 elapses from the time when the first time T1 elapses. The gate drive signal SGL may be kept at the H level until the time point. However, the conduction loss can be reduced by continuously applying the gate drive voltage VGL until the second time T2 elapses, rather than once interrupting the gate drive voltage VGL. Therefore, the Vf control unit 26 performs pulse control following the Vf control, and outputs the H-level gate drive signal SGL by extending it beyond the time t3 until the elapse of the second time T2 (time t6) ( Pulse expansion).
　ＰＷＭ信号ＦＬがＨレベルの期間において、半導体素子１Ｂに領域２の範囲内の電流が流れている場合、Ｖｆ制御部２６とパルス制御部２７は、図５に示したＲＣ－ＩＧＢＴの制御と同様のゲート駆動信号ＳGLを出力する。また、ＰＷＭ信号ＦＬがＨレベルの期間において、半導体素子１Ｂに領域１、２の範囲内の電流が流れていない場合、つまりＭＯＳトランジスタの順方向（ダイオード素子６の逆方向）の向きの電流が流れる場合には、Ｖｆ制御部２６とパルス制御部２７は通常制御を行う。本実施形態によっても第１の実施形態と同様の効果が得られる。 When the current in the region 2 flows through the semiconductor element 1B during the period in which the PWM signal FL is at the H level, the Vf control unit 26 and the pulse control unit 27 are the same as the RC-IGBT control shown in FIG. The gate drive signal SGL is output. Further, when the current in the range of the regions 1 and 2 does not flow through the semiconductor element 1B during the period in which the PWM signal FL is at the H level, that is, the current in the forward direction of the MOS transistor (the reverse direction of the diode element 6). When flowing, the Vf control unit 26 and the pulse control unit 27 perform normal control. According to this embodiment, the same effect as that of the first embodiment can be obtained.
　（第３、第４、第５の実施形態）
　図８、図９、図１０は、何れも高耐圧を持つ駆動ＩＣ５１、５３、５５を用いた駆動制御装置５２、５４、５６である。高耐圧とは、ハーフブリッジ回路４に印加される電源電圧に応じた耐圧である。駆動制御装置５２、５４、５６は、ハーフブリッジ回路４を構成する２つの半導体素子１Ａ、１Ｂを駆動制御する。 (Third, fourth and fifth embodiments)
8, 9, and 10 show drive control devices 52, 54, and 56 using drive ICs 51, 53, and 55 that have a high breakdown voltage. The high breakdown voltage is a breakdown voltage according to the power supply voltage applied to the half bridge circuit 4. The drive control devices 52, 54, and 56 drive and control the two semiconductor elements 1 </ b> A and 1 </ b> B that constitute the half-bridge circuit 4.
　駆動ＩＣ５１、５３、５５は、半導体素子１Ａ、１Ｂに対し共通のＶｆ制御部２６と共通のパルス制御部２７を備えており、電源電圧ＶDD（例えば１５Ｖ）が供給されることで動作する。ゲート駆動信号ＳGHは、レベルシフト回路５７とドライブ回路２８を介して半導体素子１Ａに与えられ、ゲート駆動信号ＳGLは、ドライブ回路２８を介して半導体素子１Ｂに与えられる。 The driving ICs 51, 53, and 55 are provided with a common Vf control unit 26 and a common pulse control unit 27 for the semiconductor elements 1A and 1B, and operate when supplied with a power supply voltage VDD (for example, 15 V). The gate drive signal SGH is given to the semiconductor element 1A via the level shift circuit 57 and the drive circuit 28, and the gate drive signal SGL is given to the semiconductor element 1B via the drive circuit 28.
　駆動ＩＣ５１は、センス抵抗７Ａ、７Ｂに生じるセンス電圧ＶSH、ＶSLに基づいて電流検出信号を出力する電流検出部２５を備えている。ハイサイド側の電流検出部２５は、レベルシフト回路５８を介して電流検出信号を出力する。駆動ＩＣ５３は、ハイサイド側の電流検出部２５とレベルシフト回路５８を省いた構成を備えている。駆動ＩＣ５５は、電流検出回路６０を備え、センス電圧ＶSLに替えてホールセンサ５９等のセンス信号を入力する。駆動ＩＣ５３の電流検出部２５および駆動ＩＣ５５の電流検出回路６０は、いずれか一方（例えば半導体素子１Ｂ）に流れる電流検出信号に基づいて、他方（例えば半導体素子１Ａ）に流れる電流を推定する。その他の構成は、第１の実施形態と同様である。 The drive IC 51 includes a current detection unit 25 that outputs a current detection signal based on the sense voltages VSH and VSL generated in the sense resistors 7A and 7B. The high-side current detection unit 25 outputs a current detection signal via the level shift circuit 58. The drive IC 53 has a configuration in which the high-side current detection unit 25 and the level shift circuit 58 are omitted. The drive IC 55 includes a current detection circuit 60 and inputs a sense signal from the hall sensor 59 or the like instead of the sense voltage VSL. The current detection unit 25 of the drive IC 53 and the current detection circuit 60 of the drive IC 55 estimate the current flowing to the other (for example, the semiconductor element 1A) based on the current detection signal flowing to either one (for example, the semiconductor element 1B). Other configurations are the same as those of the first embodiment.
　パルス制御部２７は、ゲート駆動信号ＳGH、ＳGLを生成するので、２つの半導体素子１Ａ、１Ｂのうち一方の半導体素子にゲート駆動電圧を印加している期間、他方の半導体素子へのゲート駆動電圧の印加を禁止できる。これにより、ＰＷＭ信号ＦＨ、ＦＬが制御ＩＣ６３のＶｆ制御部２６に入力されているため、Ｖｆ制御部２６およびパルス制御部２７は、一方及び他方のアームの制御を統括的に実行することができ、アーム短絡を確実に防止できる。また、ハイサイド側とローサイド側とで電流検出部２５または電流検出回路６０を共用化できるので、回路構成を簡単化できる（図９、図１０）。共用化する場合には、しきい値設定回路３０、３１で生成される規定電圧Ｖm1、Ｖm2に基づいて、ハイサイド側の規定値Ｉm1、Ｉm2を第１の実施形態よりも大きく設定することが好ましい。その他、第１、第２の実施形態と同様の作用および効果が得られる。 Since the pulse control unit 27 generates the gate drive signals SGH and SGL, the gate drive voltage applied to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements 1A and 1B. Can be prohibited. As a result, since the PWM signals FH and FL are input to the Vf control unit 26 of the control IC 63, the Vf control unit 26 and the pulse control unit 27 can collectively control the one and the other arms. , Arm short circuit can be surely prevented. Further, since the current detection unit 25 or the current detection circuit 60 can be shared between the high side and the low side, the circuit configuration can be simplified (FIGS. 9 and 10). In the case of sharing, the high-side specified values Im1 and Im2 may be set larger than in the first embodiment based on the specified voltages Vm1 and Vm2 generated by the threshold setting circuits 30 and 31. preferable. In addition, operations and effects similar to those of the first and second embodiments can be obtained.
　（第６、第７の実施形態）
　図１１、図１２は、制御部とドライブ回路とを分離して構成した駆動制御装置６１、６２を示している。駆動制御装置６１、６２は、ハーフブリッジ回路４を構成する２つの半導体素子１Ａ、１Ｂを駆動制御する。駆動制御装置６１は、制御ＩＣ６３、フォトカプラ６４Ａ、６４Ｂ、駆動ＩＣ６５Ａ、６５Ｂ、電流検出回路６０などから構成されている。 (Sixth and seventh embodiments)
11 and 12 show drive control devices 61 and 62 configured by separating the control unit and the drive circuit. The drive control devices 61 and 62 drive and control the two semiconductor elements 1A and 1B constituting the half bridge circuit 4. The drive control device 61 includes a control IC 63, photocouplers 64A and 64B, drive ICs 65A and 65B, a current detection circuit 60, and the like.
　制御ＩＣ６３は、専用ＡＳＩＣ、マイコンのハードＩＰ（Intellectual Property）、ＦＰＧＡなどから構成されており、上述したＶｆ制御部２６とパルス制御部２７が実装されている。フォトカプラ６４Ａ、６４Ｂは、ゲート駆動信号ＳGH、ＳGLを電気的に絶縁して駆動ＩＣ６５Ａ、６５Ｂに伝送する絶縁回路である。駆動ＩＣ６５Ａ、６５Ｂは、ドライブ回路２８を備えており、ゲート駆動信号ＳGH、ＳGLを入力してゲート駆動電圧ＶGH、ＶGLを出力する。電流検出回路６０は、ホールセンサ５９等で負荷電流を検出し、制御ＩＣ６３に対し電流検出信号を出力する。 The control IC 63 includes a dedicated ASIC, a microcomputer hardware IP (Intellectual Property), an FPGA, and the like, and the Vf control unit 26 and the pulse control unit 27 described above are mounted thereon. The photocouplers 64A and 64B are insulation circuits that electrically insulate the gate drive signals SGH and SGL and transmit them to the drive ICs 65A and 65B. The drive ICs 65A and 65B include a drive circuit 28, which receives gate drive signals SGH and SGL and outputs gate drive voltages VGH and VGL. The current detection circuit 60 detects a load current with the hall sensor 59 or the like, and outputs a current detection signal to the control IC 63.
　駆動制御装置６２は、ホールセンサ５９と電流検出回路６０に替えて、センス電圧ＶSH、ＶSLを入力とするフォトカプラ６７Ａ、６７Ｂと電流極性検出回路６８を備えている。電流極性検出回路６８は、半導体素子１Ａ、１Ｂに流れる電流値または電流の向き（極性）を検出する。つまり、電流の大きさを検出してもよいし、電流の極性を検出するだけでもよい。これにより、パルス制御およびＲＣ－ＩＧＢＴに対するＶｆ制御を実行できる。 The drive control device 62 includes photocouplers 67A and 67B that receive the sense voltages VSH and VSL and a current polarity detection circuit 68 in place of the hall sensor 59 and the current detection circuit 60. The current polarity detection circuit 68 detects the value of current flowing in the semiconductor elements 1A and 1B or the direction (polarity) of the current. That is, the magnitude of the current may be detected or only the polarity of the current may be detected. Thereby, pulse control and Vf control for RC-IGBT can be executed.
　本実施形態によっても、パルス制御部２７は、２つの半導体素子１Ａ、１Ｂのうち一方の半導体素子にゲート駆動電圧を印加している期間、他方の半導体素子へのゲート駆動電圧の印加を禁止できる。これにより、アーム短絡を確実に防止できる。 Also in this embodiment, the pulse control unit 27 can prohibit the application of the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements 1A and 1B. . Thereby, an arm short circuit can be prevented reliably.
　ＰＷＭ信号ＦＨ、ＦＬが制御ＩＣ６３のＶｆ制御部２６に入力されているため、Ｖｆ制御部２６およびパルス制御部２７は、一方及び他方のアームの制御を統括的に実行することができる。この実施形態によっても、第１、第２の実施形態と同様の作用および効果が得られる。また実施例７において、第４の実施形態と同様にフォトカプラ６７Ａ、６７Ｂの何れか一方を省略してもよい。このとき、省略したフォトカプラ６７Ａ，６７Ｂに対応したセンス素子（５ｓ、６ｓ）およびセンス抵抗（７）を省略しても良い。この場合には、電流極性検出部６８はいずれか一方（例えば半導体素子１Ｂ）に流れる電流の極性検出信号に基づいて、他方（例えば半導体素子１Ａ）に流れる電流の極性を推定する。電流極性検出部６８の前段ではなく電流極性検出部６８の後段にフォトカプラ６７Ａ、６７Ｂと同様の構成のフォトカプラを設けても良い。電流検出回路６０、電流極性検出回路６８を制御ＩＣ６３もしくは駆動ＩＣ６５内に形成してもよい。 Since the PWM signals FH and FL are input to the Vf control unit 26 of the control IC 63, the Vf control unit 26 and the pulse control unit 27 can collectively control the one and the other arms. According to this embodiment, the same operation and effect as those of the first and second embodiments can be obtained. In Example 7, as in the fourth embodiment, either one of the photocouplers 67A and 67B may be omitted. At this time, the sense elements (5s, 6s) and the sense resistor (7) corresponding to the omitted photocouplers 67A and 67B may be omitted. In this case, the current polarity detection unit 68 estimates the polarity of the current flowing in the other (for example, the semiconductor element 1A) based on the polarity detection signal of the current flowing in one (for example, the semiconductor element 1B). A photocoupler having the same configuration as that of the photocouplers 67A and 67B may be provided not in the previous stage of the current polarity detection unit 68 but in the subsequent stage of the current polarity detection unit 68. The current detection circuit 60 and the current polarity detection circuit 68 may be formed in the control IC 63 or the drive IC 65.
　（第８、第９の実施形態）
　図１３、図１４は、制御部とドライブ回路とを分離するとともに、Ｖｆ制御部２６、パルス制御部２７および電流検出部２５をマイコン２１に取り込んだ構成の駆動制御装置７１、７２を示している。駆動制御装置７１、７２は、ハーフブリッジ回路４を構成する２つの半導体素子１Ａ、１Ｂを駆動制御する。駆動制御装置７１は、マイコン２１、フォトカプラ６４Ａ、６４Ｂ、駆動ＩＣ６５Ａ、６５Ｂなどから構成されている。駆動制御装置７２は、センス電圧ＶSH、ＶSLを入力とするフォトカプラ６７Ａ、６７Ｂを備えている。 (Eighth and ninth embodiments)
13 and 14 show drive control devices 71 and 72 having a configuration in which the control unit and the drive circuit are separated and the Vf control unit 26, the pulse control unit 27, and the current detection unit 25 are incorporated in the microcomputer 21. . The drive control devices 71 and 72 drive and control the two semiconductor elements 1A and 1B constituting the half bridge circuit 4. The drive control device 71 includes the microcomputer 21, photocouplers 64A and 64B, drive ICs 65A and 65B, and the like. The drive control device 72 includes photocouplers 67A and 67B that receive the sense voltages VSH and VSL.
　マイコン２１は、メモリ７３に予め記憶された制御プログラムを実行することにより、上述したＶｆ制御部２６、パルス制御部２７および電流検出部２５の機能を実現する。駆動制御装置７１のマイコン２１は、ホールセンサ５９のセンス信号を入力して電流検出信号を得る。駆動制御装置７２のマイコン２１は、フォトカプラ６７Ａ、６７Ｂの出力信号を介して電流検出信号を得る。メモリ７３には、制御プログラムの他に、第１時間Ｔ１と第２時間Ｔ２、しきい値なども記憶されている。
本実施形態によっても、パルス制御部２７は、２つの半導体素子１Ａ、１Ｂのうち一方の半導体素子にゲート駆動電圧を印加している期間、他方の半導体素子へのゲート駆動電圧の印加を禁止できる。これにより、アーム短絡を確実に防止できる。 The microcomputer 21 implements the functions of the Vf control unit 26, the pulse control unit 27, and the current detection unit 25 described above by executing a control program stored in advance in the memory 73. The microcomputer 21 of the drive control device 71 receives a sense signal from the hall sensor 59 and obtains a current detection signal. The microcomputer 21 of the drive control device 72 obtains a current detection signal via the output signals of the photocouplers 67A and 67B. In addition to the control program, the memory 73 also stores a first time T1, a second time T2, a threshold value, and the like.
Also in this embodiment, the pulse control unit 27 can prohibit the application of the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements 1A and 1B. . Thereby, an arm short circuit can be prevented reliably.
　ＰＷＭ信号ＦＨ、ＦＬがマイコン２１のＶｆ制御部２６に入力されているため、Ｖｆ制御部２６およびパルス制御部２７は、一方及び他方のアームの制御を統括的に実行することができる。この実施形態によっても、第１、第２の実施形態と同様の作用および効果が得られる。また実施例９において、第４の実施形態と同様にフォトカプラ６７Ａ、６７Ｂの何れか一方を省略してもよい。このとき、省略したフォトカプラ６７Ａ，６７Ｂに対応したセンス素子（５ｓ、６ｓ）およびセンス抵抗（７）を省略しても良い。この場合には、電流極性検出部６８はいずれか一方（例えば半導体素子１Ｂ）に流れる電流の極性検出信号に基づいて、他方（例えば半導体素子１Ａ）に流れる電流の極性を推定する。 Since the PWM signals FH and FL are input to the Vf control unit 26 of the microcomputer 21, the Vf control unit 26 and the pulse control unit 27 can collectively control the one and other arms. According to this embodiment, the same operation and effect as those of the first and second embodiments can be obtained. In Example 9, as in the fourth embodiment, either one of the photocouplers 67A and 67B may be omitted. At this time, the sense elements (5s, 6s) and the sense resistor (7) corresponding to the omitted photocouplers 67A and 67B may be omitted. In this case, the current polarity detection unit 68 estimates the polarity of the current flowing in the other (for example, the semiconductor element 1A) based on the polarity detection signal of the current flowing in one (for example, the semiconductor element 1B).
　（第１～第９実施形態についての他の実施形態）
　以上、第１～第９の実施形態について説明したが、以下のように開示の要旨を逸脱しない範囲内で種々の変形、拡張を行うことができる。 (Other embodiments of the first to ninth embodiments)
While the first to ninth embodiments have been described above, various modifications and extensions can be made without departing from the scope of the disclosure as follows.
　各実施形態は、Ｖｆ制御部２６によるＶｆ制御とパルス制御部２７によるパルス制御のうちＶｆ制御だけを行う構成またはパルス制御だけを行う構成に変更してもよい。第３から第７の実施形態においてＶｆ制御だけを行う構成の場合、Ｖｆ制御部２６が、半導体素子１Ａ、１Ｂのうち一方の半導体素子にゲート駆動電圧を印加している期間、他方の半導体素子へのゲート駆動電圧の印加が禁止されることは勿論である。 Each embodiment may be changed to a configuration in which only the Vf control is performed among the Vf control by the Vf control unit 26 and the pulse control by the pulse control unit 27, or a configuration in which only the pulse control is performed. In the case where only the Vf control is performed in the third to seventh embodiments, the Vf control unit 26 applies the gate drive voltage to one of the semiconductor elements 1A and 1B during the other semiconductor element. Of course, the application of the gate drive voltage to is prohibited.
　切替信号Ｓｋとしきい値電圧Ｖｔ（電流しきい値Ｉｔの設定）を入力する構成は、必要に応じて備えればよい。 The configuration for inputting the switching signal Sk and the threshold voltage Vt (setting of the current threshold value It) may be provided as necessary.
　Ｖｆ制御部２６、パルス制御部２７は、それぞれ負荷電流の大きさが規定値Ｉm1、Ｉm2よりも小さくなるとＶｆ制御、パルス制御を停止して通常制御を行うようにしたが、この通常制御への切り替え制御は必要に応じて実行すればよい。 The Vf control unit 26 and the pulse control unit 27 stop the Vf control and the pulse control and perform the normal control when the magnitude of the load current becomes smaller than the specified values Im1 and Im2, respectively. The switching control may be executed as necessary.
　第１、第２の実施形態においても、電流検出部２５は、センス電圧ＶSH、ＶSLに替えてホールセンサ５９のセンス信号を入力して電流検出信号を得てもよい。 Also in the first and second embodiments, the current detection unit 25 may obtain a current detection signal by inputting a sense signal of the Hall sensor 59 instead of the sense voltages VSH and VSL.
　第２の実施形態においても、負荷電流の大きさが規定値Ｉm1、Ｉm2よりも小さくなると、それぞれＶｆ制御、パルス制御を停止して通常制御を行う構成としてもよい。また、駆動制御システムの運転領域が常に図６に示す領域１にある場合には、Ｖｆ制御部２６から、領域１と領域２との間での制御切替機能を省いてもよい。すなわち、Ｖｆ制御部２６は、ＰＷＭ信号ＦＬがＨレベルの期間、常にゲート駆動電圧ＶGLを半導体素子１Ｂのゲートに印加する。Ｖｆ制御部２６は、当該期間において半導体素子１Ｂにダイオード素子６の順方向の向きに電流が流れていると判定すると、第２の実施形態と同様にして第２時間Ｔ２の経過時点（時刻ｔ６）までパルスの拡張を行う。 Also in the second embodiment, when the magnitude of the load current becomes smaller than the specified values Im1 and Im2, the Vf control and the pulse control may be stopped and the normal control may be performed, respectively. Further, when the operation region of the drive control system is always in the region 1 shown in FIG. 6, the control switching function between the region 1 and the region 2 may be omitted from the Vf control unit 26. That is, the Vf control unit 26 always applies the gate drive voltage VGL to the gate of the semiconductor element 1B while the PWM signal FL is at the H level. When the Vf control unit 26 determines that the current flows in the forward direction of the diode element 6 in the semiconductor element 1B during the period, the Vf control unit 26 determines that the second time T2 has elapsed (time t6) as in the second embodiment. ) To extend the pulse.
　第８、第９の実施形態においても、外部から電流しきい値Ｉｔを特定するしきい値特定信号（切替信号Ｓｋ）を入力可能に構成し、しきい値設定回路２９Ａ、２９Ｂを備えてもよい。また、しきい値設定回路３０Ａ、３０Ｂ、３１Ａ、３１Ｂを備え、負荷電流の大きさが規定値Ｉm1、Ｉm2よりも小さくなるとＶｆ制御、パルス制御を停止して通常制御を行う構成としてもよい。 Also in the eighth and ninth embodiments, a threshold value specifying signal (switching signal Sk) for specifying the current threshold value It can be input from the outside, and threshold setting circuits 29A and 29B are provided. Good. Further, the threshold setting circuits 30A, 30B, 31A and 31B may be provided, and when the magnitude of the load current becomes smaller than the specified values Im1 and Im2, the Vf control and the pulse control are stopped and the normal control is performed.
　第３から第９の実施形態は、半導体素子１Ａ、１ＢにＭＯＳトランジスタを用いた構成に対しても、第２の実施形態と同様にして適用できる。半導体素子１Ａ、１Ｂは、コントロール用のゲートを有し寄生ダイオードが形成された素子、例えばＭＯＳゲートを備えたダイオードであってもよい。ＲＣ－ＩＧＢＴは、トレンチゲート型に限らずプレーナゲート型などであってもよい。ＭＯＳトランジスタは、トレンチゲート型に限らずプレーナゲート型などであってもよい。ＭＯＳトランジスタは、ＳＪ（Super Junction）構造であってもよい。 The third to ninth embodiments can be applied to the configuration using MOS transistors for the semiconductor elements 1A and 1B in the same manner as the second embodiment. The semiconductor elements 1A and 1B may be elements having a control gate and having a parasitic diode formed thereon, for example, diodes having MOS gates. The RC-IGBT is not limited to the trench gate type but may be a planar gate type. The MOS transistor is not limited to a trench gate type but may be a planar gate type. The MOS transistor may have an SJ (Super Junction) structure.
　上記実施形態では、電流検出手段として、半導体素子１Ａ、１Ｂにセンス素子を形成した上でセンス抵抗７Ａ、７Ｂを備えた。或いは、ホールセンサ５９を備えた。これらに替えて、図１５に示すように、センス素子を除いた半導体素子１Ａ、１Ｂと直列にセンス抵抗７Ａ、７Ｂを設けてもよい。センス抵抗７Ａ、７Ｂとメイン素子とが直接接続されているので、高応答が可能となる。また、図１６に示すように、半導体素子１Ａ、１Ｂに対しホールセンサ５９Ａ、５９Ｂを設けてもよい。何れの構成でも、電流を高精度に検出できる。これらの変形例は、第１、第２の実施形態のみならず、第３から第９の実施形態についても適用できる。さらに、ホールセンサに替えてＧＭＲ（Giant Magneto Resistance）センサなどの絶縁型電流センサを用いてもよい。 In the above embodiment, the sense resistors 7A and 7B are provided as the current detection means after forming the sense elements in the semiconductor elements 1A and 1B. Alternatively, a hall sensor 59 is provided. Instead of these, as shown in FIG. 15, sense resistors 7A and 7B may be provided in series with the semiconductor elements 1A and 1B excluding the sense elements. Since the sense resistors 7A and 7B and the main element are directly connected, high response is possible. Further, as shown in FIG. 16, Hall sensors 59A and 59B may be provided for the semiconductor elements 1A and 1B. In any configuration, the current can be detected with high accuracy. These modifications can be applied not only to the first and second embodiments but also to the third to ninth embodiments. Further, an insulated current sensor such as a GMR (Giant Magneto Resistance) sensor may be used instead of the Hall sensor.
　第１、第３、第４、第９の実施形態、第２の実施形態で駆動制御システムの運転領域が常に領域１のため制御切替機能を省いた構成の場合、および図１５に示す構成においても、電流検出部２５または電流検出回路６０を電流極性検出回路６８に置き替え、第７の実施形態と同様にパルス制御およびＶｆ制御を実行してもよい。これらの場合、第７の実施形態と同様に、半導体素子１Ａ、１Ｂのうち一方の半導体素子にゲート駆動電圧を印加している期間、他方の半導体素子へのゲート駆動電圧の印加を禁止できる。また、電流極性検出回路６８は、一方の半導体素子に流れる電流の極性検出信号に基づいて、他方の半導体素子に流れる電流の極性を推定できる。 In the first, third, fourth, ninth, and second embodiments, the operation region of the drive control system is always region 1, so that the control switching function is omitted, and in the configuration shown in FIG. Alternatively, the current detection unit 25 or the current detection circuit 60 may be replaced with the current polarity detection circuit 68, and the pulse control and the Vf control may be executed similarly to the seventh embodiment. In these cases, as in the seventh embodiment, application of the gate drive voltage to the other semiconductor element can be prohibited while the gate drive voltage is applied to one of the semiconductor elements 1A and 1B. Further, the current polarity detection circuit 68 can estimate the polarity of the current flowing through the other semiconductor element based on the polarity detection signal of the current flowing through the one semiconductor element.
　電流極性検出回路６８は、センス抵抗７Ａ、７Ｂに生じるセンス電圧ＶSH、ＶSLに替えて、トランジスタ素子５のコレクタ・エミッタ間電圧（またはドレイン・ソース間電圧）またはゲート駆動電圧ＶGH、ＶGLに基づいて半導体素子１Ａ、１Ｂに流れる電流の極性を検出できる。 The current polarity detection circuit 68 is based on the collector-emitter voltage (or drain-source voltage) or the gate drive voltages VGH, VGL of the transistor element 5 instead of the sense voltages VSH, VSL generated in the sense resistors 7A, 7B. The polarity of the current flowing through the semiconductor elements 1A and 1B can be detected.
　（第１０の実施形態）
　図１７～図１８は第１０の実施形態を示すもので、半導体素子１Ａ，１Ｂに替えて半導体素子１０１Ａ，１０１Ｂを使用すると共に電流検出部２５に替えて電圧検出部１２５を使用した形態を示す。同一または類似の構成については同一または類似の符号を付して説明を省略する。 (Tenth embodiment)
FIGS. 17 to 18 show a tenth embodiment, in which semiconductor elements 101A and 101B are used instead of the semiconductor elements 1A and 1B, and a voltage detector 125 is used instead of the current detector 25. FIG. . The same or similar components are denoted by the same or similar reference numerals and description thereof is omitted.
　半導体素子１０１Ａ、１０１Ｂは、絶縁ゲート型のトランジスタ素子１０５と、ダイオード素子１０６とが同一の半導体基板８に形成された逆導通型ＩＧＢＴ（ＲＣ－ＩＧＢＴ）であり、前述実施形態のトランジスタ素子５とダイオード素子６とにそれぞれ対応したメイン素子（トランジスタ素子１０５、ダイオード素子１０６）を示している。トランジスタ素子１０５の通電電極（コレクタ、エミッタ）とダイオード素子１０６の通電電極（カソード、アノード）とはそれぞれ共通の電極とされている。 The semiconductor elements 101A and 101B are reverse conducting IGBTs (RC-IGBTs) in which the insulated gate transistor element 105 and the diode element 106 are formed on the same semiconductor substrate 8, and the transistor elements 5 of the above-described embodiment Main elements (transistor element 105 and diode element 106) respectively corresponding to the diode element 6 are shown. The current-carrying electrodes (collector and emitter) of the transistor element 105 and the current-carrying electrodes (cathode and anode) of the diode element 106 are common electrodes.
　また、このメイン素子に加えて、半導体基板にはメイン素子のコレクタ電位（電極電位相当）を検出するためのセンス素子（センストランジスタ１０５ｓ、センスダイオード１０６ｓ）が構成されている。センストランジスタ１０５ｓの通電電極（コレクタ、エミッタ）とセンスダイオード１０６ｓの通電電極（カソード、アノード）とはそれぞれ共通の電極とされている。絶縁ゲート型のセンストランジスタ１０５ｓのゲートエミッタ間は共通接続されている。センストランジスタ１０５ｓのエミッタ電極とトランジスタ素子１０５のエミッタ電極との間にはセンス抵抗１０７Ａ、１０７Ｂが接続されている。センス抵抗１０７Ａ、１０７Ｂは、電圧検出部１２５と共に電圧検出手段を構成している。 In addition to the main element, a sense element (sense transistor 105s, sense diode 106s) for detecting the collector potential (corresponding to the electrode potential) of the main element is configured on the semiconductor substrate. The conducting electrodes (collector and emitter) of the sense transistor 105s and the conducting electrodes (cathode and anode) of the sense diode 106s are common electrodes. The gate and emitter of the insulated gate type sense transistor 105s are connected in common. Sense resistors 107A and 107B are connected between the emitter electrode of the sense transistor 105s and the emitter electrode of the transistor element 105. The sense resistors 107A and 107B constitute a voltage detection unit together with the voltage detection unit 125.
　駆動ＩＣ２４Ａ、２４Ｂに替わる駆動ＩＣ１２４Ａ、１２４Ｂには、電圧検出部１２５が構成されている。駆動ＩＣ１２４Ａ、１２４Ｂには、Ｖｆ制御部２６、パルス制御部２７、ドライブ回路２８が構成されている。これらのＶｆ制御部２６、パルス制御部２７、ドライブ回路２８の構成は、前述の実施形態と制御手法が類似するため図中には同一符号を付している。駆動ＩＣ１２４Ａ、１２４Ｂは互いに同一構成であるため、駆動ＩＣ１２４Ｂ内の異なる部分となる電圧検出部１２５の構成のみを説明する。 The voltage detection part 125 is comprised in drive IC124A, 124B replaced with drive IC24A, 24B. The drive ICs 124A and 124B are configured with a Vf control unit 26, a pulse control unit 27, and a drive circuit 28. The configurations of the Vf control unit 26, the pulse control unit 27, and the drive circuit 28 are denoted by the same reference numerals in the drawing because the control method is similar to that of the above-described embodiment. Since the drive ICs 124A and 124B have the same configuration, only the configuration of the voltage detection unit 125, which is a different part in the drive IC 124B, will be described.
　電圧検出部１２５は、センス抵抗１０７Ｂに生じるセンス電圧ＶSLに基づいて、半導体素子１０１Ｂの電圧検出信号を出力する電圧検出手段である。電圧検出部１２５は、センス素子（１０５ｓ、１０６ｓ）を用いると、センスダイオード１０６ｓの端子間電圧とセンス抵抗１０７Ａ、１０７Ｂとで分圧された分圧電圧を検出する。Ｖｆ制御部２６とパルス制御部２７は、ＰＷＭ信号ＦＬに基づいてゲート駆動信号ＳGLを生成する。ドライブ回路２８は、ゲート駆動信号ＳGLを入力してゲート駆動電圧ＶGLを出力する。その他の構成は前述実施形態と同様であるため詳細説明を省略する。また、作用についてもほぼ第１の実施形態の説明とほぼ同様であるが、第１の実施形態と異なる部分となるパルス制御について、図１８を参照して説明する。 The voltage detector 125 is a voltage detector that outputs a voltage detection signal of the semiconductor element 101B based on the sense voltage VSL generated in the sense resistor 107B. When the sense element (105s, 106s) is used, the voltage detector 125 detects a divided voltage divided by the voltage across the sense diode 106s and the sense resistors 107A, 107B. The Vf control unit 26 and the pulse control unit 27 generate the gate drive signal SGL based on the PWM signal FL. The drive circuit 28 receives the gate drive signal SGL and outputs a gate drive voltage VGL. Since other configurations are the same as those of the above-described embodiment, detailed description thereof is omitted. Further, although the operation is almost the same as that of the first embodiment, the pulse control which is different from the first embodiment will be described with reference to FIG.
　図１８に示すように、本実施形態のパルス制御でも第１の実施形態と同様に、ＰＷＭ信号ＦＬがＬレベルに立ち下がった後、逆回復電流が流れ始める前までに、半導体素子１０１Ｂにゲート駆動パルスを印加する点では同じである。しかし、このゲート駆動パルスを印加する条件判定が第１の実施形態とは異なる。 As shown in FIG. 18, in the pulse control of this embodiment as well as in the first embodiment, after the PWM signal FL falls to the L level, before the reverse recovery current starts to flow, the semiconductor element 101B is gated. It is the same in that a drive pulse is applied. However, the condition determination for applying the gate drive pulse is different from that in the first embodiment.
　すなわち、図１８において、ＰＷＭ信号ＦＨがＨレベルからＬレベルに立ち下がると、半導体素子１０１Ａのコレクタエミッタ間電圧が増加し、このとき同時に半導体素子１０１Ｂのコレクタ電極電位Ｖco（トランジスタ素子１０５Ｂのコレクタ電極電位）が低下する。このとき、電圧検出部１２５はセンス素子（１０５ｓ、１０６ｓ）により電極電位Ｖcoの低下タイミングを検出できる。なお、半導体素子１０１Ａのコレクタエミッタ間電圧はミラー期間において徐々に増加しその後に急速増加する。このため、ミラー期間中にはコレクタ電極電位Ｖcoは徐々に低下し、その後、急速低下する。 That is, in FIG. 18, when the PWM signal FH falls from the H level to the L level, the collector-emitter voltage of the semiconductor element 101A increases. At the same time, the collector electrode potential Vco of the semiconductor element 101B (the collector electrode of the transistor element 105B) (Potential) decreases. At this time, the voltage detector 125 can detect the decrease timing of the electrode potential Vco by the sense elements (105s, 106s). Note that the collector-emitter voltage of the semiconductor element 101A gradually increases in the mirror period and then rapidly increases. For this reason, the collector electrode potential Vco gradually decreases during the mirror period, and then rapidly decreases.
　電圧検出部１２５は、前述のミラー期間中にコレクタ電極電位Ｖcoの低下タイミングを検出する（時刻ｔ１ａ）。Ｖｆ制御部２６は、電圧検出部１２５により電極電位Ｖcoの低下を検出し、入力されるＰＷＭ信号ＦＬのオンオフ指令信号とコレクタ電極電位Ｖcoとの関係に応じて極性を推定できる。 The voltage detector 125 detects the decrease timing of the collector electrode potential Vco during the above-described mirror period (time t1a). The Vf control unit 26 can detect a decrease in the electrode potential Vco by the voltage detection unit 125 and estimate the polarity according to the relationship between the on / off command signal of the input PWM signal FL and the collector electrode potential Vco.
　駆動ＩＣ１２４ＢのＶｆ制御部２６は、コレクタ電極電位Ｖcoが低下したことを検出した時点（ｔ１ａ）からＰＷＭ信号ＦＬのオン指令信号を入力するか否かを判定し、オン指令信号が入力されたときにＬレベルのゲート駆動信号ＳGLを出力する（時刻ｔ２～ｔ３）。このとき、このゲート駆動信号ＳGLに応じたゲート駆動電圧ＶGLが半導体素子１０１Ｂのゲートに印加される。これによりゲート駆動電圧ＶGLが遮断される。この間、極性判定をし続ける。 The Vf control unit 26 of the driving IC 124B determines whether or not to input the ON command signal of the PWM signal FL from the time (t1a) when it is detected that the collector electrode potential Vco has decreased, and when the ON command signal is input The L level gate drive signal SGL is output to (time t2 to t3). At this time, a gate drive voltage VGL corresponding to the gate drive signal SGL is applied to the gate of the semiconductor element 101B. As a result, the gate drive voltage VGL is cut off. During this time, the polarity determination is continued.
　図２５および図２６は負荷電流の方向、大きさに応じたコレクタ電極電位の変化特性の参考図を示す。図１７に示すノードＮｔに負荷から電流が流れ込む方向について負荷電流を負とし（図２５（ａ）左欄）、図１７のノードＮｔから負荷側に流れ出す方向について負荷電流を正と定義する（図２５（ａ）右欄）。 FIG. 25 and FIG. 26 show reference diagrams of the change characteristics of the collector electrode potential according to the direction and magnitude of the load current. The load current is defined as negative in the direction in which current flows from the load to the node Nt shown in FIG. 17 (left column in FIG. 25A), and the load current is defined as positive in the direction flowing out from the node Nt in FIG. 25 (a) right column).
　負荷電流が負となっているときにはノードＮｔには電流が流れ込む。このため、図２５（ａ）の部分ＮＭの拡大図を図２５（ｂ）に示すように、原理的にコレクタ電極電位Ｖcoは高くなる。負荷電流が正となっているときにはノードＮｔから電流が負荷側に流出することになるため、図２５（ａ）の部分ＮＰの拡大図を図２５（ｃ）に示すようにコレクタ電極電位Ｖcoは低くなる。 When the load current is negative, current flows into the node Nt. For this reason, as shown in FIG. 25B, which is an enlarged view of the portion NM in FIG. 25A, the collector electrode potential Vco increases in principle. Since the current flows out from the node Nt to the load side when the load current is positive, an enlarged view of the portion NP in FIG. 25A is shown in FIG. Lower.
　したがって、負荷電流が０付近となる条件で負荷電流の極性が反転するとき、半導体素子１０１Ａ、１０１Ｂのオン抵抗のバランスに応じて電圧検出部１２５による検出電圧が決定される。負荷電流の極性が反転すると、図２６に示すように、コレクタ電極電位Ｖcoが大きく変動したり、チャタリングを引き起こす。このため、前述したように、電圧検出部１２５の検出電圧が大きく変動したか否かを判定することで、負荷電流、ダイオード素子１０６の電流が０付近の所定範囲であるか否かを判定し、この条件を満たし負荷電流が０付近となりほとんど流れていないと判定した場合には、Ｖｆ制御部２６はＬレベルのゲート駆動信号ＳGLを出力し続ける。これにより、制御の信頼性、安定性を高めることができる。 Therefore, when the polarity of the load current is reversed under the condition that the load current is close to 0, the detection voltage by the voltage detection unit 125 is determined according to the balance of the on-resistance of the semiconductor elements 101A and 101B. When the polarity of the load current is reversed, as shown in FIG. 26, the collector electrode potential Vco largely fluctuates or causes chattering. For this reason, as described above, it is determined whether or not the load current and the current of the diode element 106 are within a predetermined range near 0 by determining whether or not the detection voltage of the voltage detection unit 125 has greatly fluctuated. When it is determined that this condition is satisfied and the load current is near 0 and hardly flows, the Vf control unit 26 continues to output the L level gate drive signal SGL. Thereby, the reliability and stability of control can be improved.
　逆に、極性を判定してゲート駆動信号ＳGLをＬレベルに出力し続けている間に、その途中でコレクタ電極電位Ｖcoが大きく変動したことを検出すると、Ｖｆ制御部２６はＰＷＭ信号ＦＬの指令信号に合わせたゲート駆動信号ＳGLを出力する。この場合、制御の応答性能を高めることができる。 Conversely, while the polarity is determined and the gate drive signal SGL continues to be output to the L level, if it is detected that the collector electrode potential Vco fluctuates significantly during the process, the Vf control unit 26 instructs the PWM signal FL to A gate drive signal SGL that matches the signal is output. In this case, control response performance can be improved.
　また、時点ｔ１と時点ｔ２との間のデッドタイムＴｄが短くなったり、ＰＷＭ信号ＦＨのオフ指令信号の発生タイミングからゲート駆動電圧ＶGHの立下りの遅延時間が長くなったりすると、コレクタ電極電位Ｖcoが急激に低下するタイミングよりも前にＰＷＭ信号ＦＬのオン指令信号が入力されることもある。この場合、ＰＷＭ信号ＦＬのオン指令信号の入力時点から所定時間以内に電圧検出部１２５によりコレクタ電極電位Ｖcoが急激に低下することを検出したことを条件として、Ｖｆ制御部２６が前述同様の制御手法によりゲート駆動信号ＳGLを出力すると良い。 Further, when the dead time Td between the time point t1 and the time point t2 is shortened or the delay time of the fall of the gate drive voltage VGH is increased from the generation timing of the OFF command signal of the PWM signal FH, the collector electrode potential Vco The ON command signal for the PWM signal FL may be input before the timing at which the voltage rapidly decreases. In this case, the Vf control unit 26 performs the same control as described above on the condition that the voltage detection unit 125 detects that the collector electrode potential Vco rapidly decreases within a predetermined time from the input time point of the ON command signal of the PWM signal FL. The gate drive signal SGL may be output by a technique.
　他方、図１８において、ＰＷＭ信号ＦＨがＬレベルからＨレベルに立ち上がると（時刻ｔ７）、その後、半導体素子１０１Ｂのコレクタエミッタ間電圧が増加し、半導体素子１０１Ｂの電極電位Ｖco（トランジスタ素子１０５Ｂのコレクタ電位）が増加する。このとき、電圧検出部１２５は、センス素子（１０５ｓ、１０６ｓ）によりダイオード６の電圧と抵抗１０７Ａの電圧との分圧電圧により電極電位Ｖcoの増加タイミングを検出できる。 On the other hand, in FIG. 18, when the PWM signal FH rises from the L level to the H level (time t7), the collector-emitter voltage of the semiconductor element 101B increases thereafter, and the electrode potential Vco of the semiconductor element 101B (the collector of the transistor element 105B). Potential) increases. At this time, the voltage detection unit 125 can detect the increase timing of the electrode potential Vco by the divided voltage of the voltage of the diode 6 and the voltage of the resistor 107A by the sense elements (105s, 106s).
　Ｖｆ制御部２６による極性判定を受けて、ダイオード素子１０６に対し順方向に電流が流れていると判定したときには、パルス制御部２７が、ＰＷＭ信号ＦＬのオフ指令信号の入力された時点（時刻ｔ３）を起点として第１時間Ｔ１の経過時点（時刻ｔ４）から第２時間Ｔ２の経過時点（時刻ｔ６）までゲート駆動信号ＳGLをＨレベルにする。このゲート駆動信号ＳGLにより、半導体素子１０１Ｂのゲートにゲート駆動パルスＶGLが印加される。 In response to the polarity determination by the Vf control unit 26, when it is determined that a current is flowing in the forward direction with respect to the diode element 106, the pulse control unit 27 receives the OFF command signal of the PWM signal FL (time t3). ) As a starting point, the gate drive signal SGL is set to the H level from the elapsed time (time t4) of the first time T1 to the elapsed time (time t6) of the second time T2. By this gate drive signal SGL, a gate drive pulse VGL is applied to the gate of the semiconductor element 101B.
　また、パルス制御部２７はＰＷＭ信号ＦＬがＬレベルに立ち下がった後も、電圧検出部１２５の電圧が変動したか否かを判定することで、半導体素子１０１Ｂのダイオード素子１０６に電流が流れているか否かを判定し続ける。一方、パルス制御部２７は、ＰＷＭ信号ＦＬがＬレベルに立ち下がったときにダイオード素子６に電流が流れていないと判定すると、直ちにゲート駆動信号ＳGLをＬレベルにして維持する。すなわち、ゲート駆動パルスを印加しない。 Further, even after the PWM signal FL falls to the L level, the pulse control unit 27 determines whether or not the voltage of the voltage detection unit 125 has changed, so that a current flows through the diode element 106 of the semiconductor element 101B. Continue to determine whether or not. On the other hand, if the pulse control unit 27 determines that no current flows through the diode element 6 when the PWM signal FL falls to the L level, the pulse control unit 27 immediately maintains the gate drive signal SGL at the L level. That is, no gate drive pulse is applied.
　図１８に示す第１時間Ｔ１と第２時間Ｔ２は、アーム短絡が生じないように予め設定されている。ＰＷＭ信号ＦＬがＬレベルの期間にダイオード素子１０６に電流が流れている場合と、トランジスタ素子１０５に電流が流れている場合とでは、ゲート駆動パルスを与えたときのゲート駆動電圧ＶGLの波形が異なる。 The first time T1 and the second time T2 shown in FIG. 18 are set in advance so as not to cause an arm short circuit. The waveform of the gate drive voltage VGL when a gate drive pulse is applied differs between when the current flows through the diode element 106 and when the current flows through the transistor element 105 while the PWM signal FL is at the L level. .
　ダイオード素子１０６に電流が流れている場合には、半導体素子１０１Ｂのコレクタ・エミッタ間電圧が変化しない。また、半導体素子１０１Ｂに急峻な電流変化、電圧変化が生じない。このため、ドライブ回路２８は、ゲート駆動電圧ＶGLの立ち上げ時および立ち下げ時に、通常よりも高いゲート駆動能力でゲート駆動電圧ＶGLを出力できる。 When a current flows through the diode element 106, the collector-emitter voltage of the semiconductor element 101B does not change. Further, no steep current change or voltage change occurs in the semiconductor element 101B. Therefore, the drive circuit 28 can output the gate drive voltage VGL with a higher gate drive capability than usual when the gate drive voltage VGL rises and falls.
　第１時間Ｔ１と第２時間Ｔ２は、ゲート駆動パルスの印加時におけるゲート駆動電圧ＶGLの波形およびドライブ回路２８の駆動態様を考慮し、ゲート駆動電圧ＶGLがドライブ回路２８のゲート駆動能力に従って単調に増加または単調に減少するものとして設定されている。その際、ゲート駆動パルスの印加終了時点から逆回復電流が流れ始めるまでの時間Ｔｃ（キャリアの再注入時間）が、ゼロよりも長く且つ注入許容時間以下となるように設定される。注入許容時間は、許容される逆回復電流の大きさに応じて規定されている。 The first time T1 and the second time T2 take into account the waveform of the gate drive voltage VGL when the gate drive pulse is applied and the drive mode of the drive circuit 28, and the gate drive voltage VGL is monotonous according to the gate drive capability of the drive circuit 28. It is set to increase or decrease monotonically. At this time, the time Tc (carrier reinjection time) from the end of application of the gate drive pulse until the reverse recovery current starts to flow is set to be longer than zero and shorter than the allowable injection time. The allowable injection time is specified according to the allowable reverse recovery current.
　具体的には、第１時間Ｔ１と第２時間Ｔ２は、ダイオード素子１０６に流れる電流を種々に変えながら、ＰＷＭ信号ＦＬの立下り時点を起点とし、ゲート駆動信号ＳGLの印加タイミング、実際にゲート駆動電圧ＶGLが印加されるタイミング、および逆回復電流が流れ始めるタイミングを予め測定して設定されている。この第１時間Ｔ１と第２時間Ｔ２は、本実施形態ではパルス制御部２７内のメモリ等に記憶されている。なお、この第１時間Ｔ１と第２時間Ｔ２は１又は数パターンのロジック回路又はアナログ遅延回路などを用いて構成することもできる。 Specifically, the first time T1 and the second time T2 change the current flowing through the diode element 106 in various ways, starting from the falling point of the PWM signal FL, and the application timing of the gate drive signal SGL, actually the gate The timing at which the drive voltage VGL is applied and the timing at which the reverse recovery current starts to flow are set in advance by measurement. The first time T1 and the second time T2 are stored in a memory or the like in the pulse control unit 27 in this embodiment. The first time T1 and the second time T2 can also be configured using one or several patterns of logic circuits or analog delay circuits.
　パルス制御部２７は、ゲート駆動パルスを印加する場合、第１時間Ｔ１と第２時間Ｔ２をメモリから読み出す。パルス制御部２７は、コレクタ電極電位Ｖcoの低下検出タイミングを起点として、第１時間Ｔ１の経過時点でゲート駆動信号ＳGLの立ち上げ、第２時間Ｔ２の経過時点でゲート駆動信号ＳGLを立ち下げる。 The pulse control unit 27 reads the first time T1 and the second time T2 from the memory when applying the gate drive pulse. The pulse control unit 27 starts the gate drive signal SGL at the time when the first time T1 has elapsed, and lowers the gate drive signal SGL at the time when the second time T2 has elapsed, starting from the detection timing of the decrease in the collector electrode potential Vco.
　以上説明したように、第１０の実施形態の構成においても第１の実施形態が制御不可能な電流閾値以下でもほぼ同様の効果を奏する可能性がある。 As described above, even in the configuration of the tenth embodiment, there is a possibility that the same effect can be obtained even when the first embodiment is below the current threshold that cannot be controlled.
　（第１１の実施形態）
　図１９は第１１の実施形態を示すもので、半導体素子１０１Ａ、１０１ＢにＭＯＳトランジスタなどを使用し同期整流を行った方が導通損失を低減できる場合のタイミングチャートを示している。駆動制御装置１３２Ａ、１３２Ｂの構成は、図１７に示した通りである。ここでは、主としてローサイド側の駆動制御装置１３２Ｂの作用について説明する。ハイサイド側の駆動制御装置１３２Ａの作用も同様となる。ＭＯＳトランジスタの場合で説明すると、その特性は図６に示したように、電圧ＶDS＜電圧Ｖｆとなる領域１では、ゲート駆動電圧を印加することにより導通損失を低減できる。電圧ＶDS≧電圧Ｖｆとなる領域２では、ゲート駆動電圧を遮断することにより導通損失を低減できる。前述実施形態と動作が同一部分については説明を省略する。電圧検出部１２５は、前述のミラー期間中にコレクタ電極電位Ｖcoの低下タイミングを検出する（時刻ｔ１ａ）。Ｖｆ制御部２６は、電圧検出部１２５により電極電位Ｖcoの低下を検出し、入力されるＰＷＭ信号ＦＬのオンオフ指令信号とコレクタ電極電位Ｖcoとの関係に応じて極性を推定できる。 (Eleventh embodiment)
FIG. 19 shows an eleventh embodiment, and shows a timing chart when conduction loss can be reduced by performing synchronous rectification using MOS transistors or the like for the semiconductor elements 101A and 101B. The configuration of the drive control devices 132A and 132B is as shown in FIG. Here, the operation of the drive control device 132B on the low side will be mainly described. The operation of the drive control device 132A on the high side is the same. In the case of the MOS transistor, as shown in FIG. 6, in the region 1 where the voltage VDS <the voltage Vf, the conduction loss can be reduced by applying the gate drive voltage. In region 2 where voltage VDS ≧ voltage Vf, conduction loss can be reduced by cutting off the gate drive voltage. The description of the same operation as that in the above embodiment is omitted. The voltage detector 125 detects the decrease timing of the collector electrode potential Vco during the above-described mirror period (time t1a). The Vf control unit 26 can detect a decrease in the electrode potential Vco by the voltage detection unit 125 and estimate the polarity according to the relationship between the on / off command signal of the input PWM signal FL and the collector electrode potential Vco.
　駆動ＩＣ１２４ＢのＶｆ制御部２６は、コレクタ電極電位Ｖcoが低下したことを検出した時点（ｔ１ａ）からＰＷＭ信号ＦＬのオン指令信号を入力するか否かを判定し、オン指令信号が入力されたときにＨレベルのゲート駆動信号ＳGLを出力する（時刻ｔ２～ｔ３）。このとき、このゲート駆動信号ＳGLに応じたゲート駆動電圧ＶGLが半導体素子１０１Ｂのゲートに印加される。 The Vf control unit 26 of the driving IC 124B determines whether or not to input the ON command signal of the PWM signal FL from the time (t1a) when it is detected that the collector electrode potential Vco has decreased, and when the ON command signal is input H level gate drive signal SGL is output at time t2 to t3. At this time, a gate drive voltage VGL corresponding to the gate drive signal SGL is applied to the gate of the semiconductor element 101B.
　また、ＰＷＭ信号ＦＬがＨレベルの期間においては、半導体素子１０１Ｂに領域１の範囲内の電流が流れている場合、Ｖｆ制御部２６は、ゲート駆動電圧ＶGLを印加する通常制御（同期整流）を実行する。その後ＰＷＭ信号ＦＬがＬレベルになると、Ｖｆ制御部２６は、半導体素子１０１Ｂにゲート駆動パルスを印加する。 Further, in the period in which the PWM signal FL is at the H level, when a current in the range of the region 1 flows through the semiconductor element 101B, the Vf control unit 26 performs normal control (synchronous rectification) for applying the gate drive voltage VGL. Execute. Thereafter, when the PWM signal FL becomes L level, the Vf control unit 26 applies a gate drive pulse to the semiconductor element 101B.
　この場合、パルス制御部２７が、オフ指令信号の入力時点を起点として、第１時間Ｔ１の経過時点から第２時間Ｔ２の経過時点までゲート駆動信号ＳGLをＨレベルにすればよい。しかし、ゲート駆動電圧ＶGLを一旦遮断するよりも、第２時間Ｔ２の経過時点までゲート駆動電圧ＶGLを連続して印加する方が導通損失を低減できる。そこで、Ｖｆ制御部２６は、Ｖｆ制御に続きパルス制御を行うため、Ｈレベルのゲート駆動信号ＳGLを、時刻ｔ３を越えて第２時間Ｔ２の経過時点（時刻ｔ６）まで延長して出力すると良い（パルスの拡張）。 In this case, the pulse control unit 27 may set the gate drive signal SGL to the H level from the time when the first time T1 has elapsed to the time when the second time T2 has elapsed, starting from the input time of the off command signal. However, the conduction loss can be reduced by continuously applying the gate drive voltage VGL until the second time T2 elapses, rather than once interrupting the gate drive voltage VGL. Therefore, since the Vf control unit 26 performs pulse control following the Vf control, the Vf control unit 26 may output the H-level gate drive signal SGL by extending it beyond the time t3 to the lapse of the second time T2 (time t6). (Pulse extension).
　ＰＷＭ信号ＦＬがＨレベルの期間において、半導体素子１０１Ｂに図６に示す領域２の範囲内の電流が流れている場合、Ｖｆ制御部２６とパルス制御部２７は、図５に示したＲＣ－ＩＧＢＴの制御と同様のゲート駆動信号ＳGLを出力する。 When the current within the range of the region 2 shown in FIG. 6 flows through the semiconductor element 101B during the period in which the PWM signal FL is at the H level, the Vf control unit 26 and the pulse control unit 27 perform the RC-IGBT shown in FIG. A gate drive signal SGL similar to the control in step S3 is output.
　さて、ＰＷＭ信号ＦＬがＬレベルの期間においても、第１０の実施形態で説明したように、電圧検出部１２５がセンス素子（１０５ｓ、１０６ｓ）によりコレクタ電極電位Ｖcoの立ち下がりを検出した時点（時刻ｔ１ａ）よりも後において、Ｖｆ制御部２６による通常のＶｆ制御に続くように、制御手段（Ｖｆ制御部２６又はパルス制御部２７）はオン指令信号の入力時点（ｔ２）を遡って出力するようにパルス制御を行っても良い（時刻ｔ１ｂ→ｔ２の区間のパルスの拡張参照）。 Even when the PWM signal FL is at the L level, as described in the tenth embodiment, the time point (time) when the voltage detection unit 125 detects the falling edge of the collector electrode potential Vco by the sense elements (105s, 106s). After t1a), the control means (Vf control unit 26 or pulse control unit 27) outputs the ON command signal input time (t2) retroactively so as to follow the normal Vf control by the Vf control unit 26. Alternatively, pulse control may be performed (refer to the expansion of the pulse in the interval from time t1b → t2).
　アーム短絡を防ぐためには、ゲート駆動電圧ＶGHが閾値電圧Ｖth未満となる時点（すなわち流が流れなくなる時点）から再度閾値電圧Ｖthに達する時点（すなわち電流が流れ出す時点）までの間、ゲート駆動電圧ＶGLを上昇させることができる。 In order to prevent an arm short circuit, the gate drive voltage VGL is from the time when the gate drive voltage VGH becomes less than the threshold voltage Vth (ie, when the current stops flowing) to the time when the threshold voltage Vth is reached again (ie when the current starts flowing). Can be raised.
　ゲート駆動信号ＳGLが与えられてからゲート駆動電圧ＶGLを上昇させるまで、Ｖｆ制御部２６及びパルス制御部２７は、信号生成処理などの各種処理を行うための遅延時間を生じる。この遅延時間を実験、シミュレーションなどを用いて予め測定しておき、このゲート駆動電圧ＶGLを上昇させている期間中にアーム短絡が生じないように、Ｖｆ制御部２６およびパルス制御部２７がゲート駆動信号ＳGLのパルス拡張すると良い。 From the time when the gate drive signal SGL is given until the gate drive voltage VGL is raised, the Vf control unit 26 and the pulse control unit 27 generate delay times for performing various processes such as a signal generation process. This delay time is measured in advance using experiments, simulations, and the like, and the Vf control unit 26 and the pulse control unit 27 drive the gate so that no arm short circuit occurs during the period when the gate drive voltage VGL is increased. It is preferable to extend the pulse of the signal SGL.
　このとき、ゲート駆動電圧ＶGHの閾値電圧Ｖth未満となるタイミング（すなわち電流が流れなくなる時点）とゲート駆動電圧ＶGLが閾値電圧Ｖth以上となるタイミングとの間に余裕時間（図１９のマージン時間Ｍａ）を設けると良い。ゲート駆動電圧ＶGLが閾値電圧Ｖth未満となるタイミングと、ゲート駆動電圧ＶGHが閾値電圧Ｖth以上となるタイミング（すなわち電流が流れ出す時点）との間に余裕時間（図１９のマージン時間Ｍｂ）を設けると良い。 At this time, a margin time (margin time Ma in FIG. 19) between the timing when the gate driving voltage VGH becomes less than the threshold voltage Vth (that is, when the current stops flowing) and the timing when the gate driving voltage VGL becomes equal to or higher than the threshold voltage Vth. It is good to provide. When a margin time (margin time Mb in FIG. 19) is provided between the timing when the gate drive voltage VGL becomes lower than the threshold voltage Vth and the timing when the gate drive voltage VGH becomes equal to or higher than the threshold voltage Vth (that is, when current flows). good.
　すなわち、電圧検出部１２５により電圧が検出されてから実際に制御が実施されるまでの遅延バラつき（電圧検出部１２５のバラつき、半導体素子１０１Ａ等の構成バラつき、温度特性の変化、経年劣化等による遅延バラつき、等）を生じるが、これらの遅延バラつきをマージンとして考慮した遅延時間を見込んでパルス拡張すると良い。 That is, delay variation from when the voltage is detected by the voltage detection unit 125 until actual control is performed (variation of the voltage detection unit 125, configuration variation of the semiconductor element 101A, etc., change in temperature characteristics, aging deterioration, etc. However, it is preferable to extend the pulse in consideration of the delay time considering the delay variation as a margin.
　電圧検出部１２５は、前述のミラー期間中にコレクタ電極電位Ｖcoの低下タイミングを検出する（時刻ｔ１ａ）。Ｖｆ制御部２６は、電圧検出部１２５により電極電位Ｖcoの低下を検出し、入力されるＰＷＭ信号ＦＬのオンオフ指令信号とコレクタ電極電位Ｖcoとの関係に応じて極性を推定できる。この極性の推定方法は第１０の実施形態に示した方法と同様である。 The voltage detector 125 detects the decrease timing of the collector electrode potential Vco during the above-described mirror period (time t1a). The Vf control unit 26 can detect a decrease in the electrode potential Vco by the voltage detection unit 125 and estimate the polarity according to the relationship between the on / off command signal of the input PWM signal FL and the collector electrode potential Vco. This polarity estimation method is the same as the method shown in the tenth embodiment.
　実験的又はシミュレーションなどにより領域１または領域２の範囲内の電流が流れているか否かを判定し、領域１が支配的（制御時間が所定割合以上）であると判定されたときには、Ｖｆ制御部２６は、ゲート駆動電圧ＶGLを印加する通常制御（同期整流）を実行する。その後ＰＷＭ信号ＦＬがＬレベルになると、半導体素子１０１Ｂにゲート駆動パルスを印加する必要がある。 It is determined whether a current in the range of the region 1 or the region 2 is flowing experimentally or by simulation, and when it is determined that the region 1 is dominant (control time is a predetermined ratio or more), the Vf control unit 26 executes normal control (synchronous rectification) in which the gate drive voltage VGL is applied. Thereafter, when the PWM signal FL becomes L level, it is necessary to apply a gate drive pulse to the semiconductor element 101B.
　この場合、Ｖｆ制御部２６がゲート駆動信号ＳGLをＬレベルにした後、パルス制御部２７が、ＰＷＭ信号ＦＬの立ち下がり時点を起点として、第１時間Ｔ１の経過時点から第２時間Ｔ２の経過時点までゲート駆動信号ＳGLをＨレベルにすればよい。しかし、ゲート駆動電圧ＶGLを一旦遮断するよりも、第２時間Ｔ２の経過時点までゲート駆動電圧ＶGLを連続して印加する方が導通損失を低減することができる。そこで、Ｖｆ制御部２６は、Ｖｆ制御に続きパルス制御を行うため、Ｈレベルのゲート駆動信号ＳGLを、時刻ｔ３を越えて第２時間Ｔ２の経過時点（時刻ｔ６）まで延長して出力する（パルスの拡張）。 In this case, after the Vf control unit 26 sets the gate drive signal SGL to the L level, the pulse control unit 27 starts from the time when the PWM signal FL falls and the second time T2 elapses from the time when the first time T1 elapses. The gate drive signal SGL may be kept at the H level until the time point. However, the conduction loss can be reduced by continuously applying the gate drive voltage VGL until the second time T2 elapses, rather than once interrupting the gate drive voltage VGL. Therefore, the Vf control unit 26 performs pulse control following the Vf control, and outputs the H-level gate drive signal SGL by extending it beyond the time t3 until the elapse of the second time T2 (time t6) ( Pulse expansion).
　時点ｔ１ａからｔ２までの検出処理は第１０の実施形態と同様の方法で行うが、時点ｔ２以降についてＶｆ制御部２６がゲート駆動信号ＳGLをＨレベルとしているため、負荷電流が０付近となる条件で負荷電流の極性が反転するときにも、第１０の実施形態で説明したチャタリングが引き起こされることはない。したがって、Ｖｆ制御部２６は、そのままＨレベルのゲート駆動信号ＳGLを、時点ｔ２以降、時点ｔ６まで出力し続ければ良い。 The detection process from the time point t1a to the time point t2 is performed by the same method as in the tenth embodiment. However, since the Vf control unit 26 keeps the gate drive signal SGL at the H level after the time point t2, the condition that the load current is close to zero. Even when the polarity of the load current is reversed, the chattering described in the tenth embodiment is not caused. Therefore, the Vf control unit 26 may continue to output the H level gate drive signal SGL as it is from time t2 to time t6.
　本実施形態によっても第２または第１０の実施形態と同様の効果が得られる。 Also in this embodiment, the same effect as that of the second or tenth embodiment can be obtained.
　（第１２、第１３の実施形態）
　図２０は第１２の実施形態を示し、図２１は第１３の実施形態を示すもので、何れも高耐圧を持つ駆動ＩＣ１５１、１５３を用いた駆動制御装置１５２、１５４を示している。高耐圧とは、ハーフブリッジ回路４に印加される電源電圧に応じた耐圧である。駆動制御装置１５２、１５４は、ハーフブリッジ回路４を構成する２つの半導体素子１０１Ａ、１０１Ｂを駆動制御する。 (Twelfth and thirteenth embodiments)
FIG. 20 shows a twelfth embodiment, and FIG. 21 shows a thirteenth embodiment, both of which show drive control devices 152 and 154 using drive ICs 151 and 153 having a high breakdown voltage. The high breakdown voltage is a breakdown voltage according to the power supply voltage applied to the half bridge circuit 4. The drive control devices 152 and 154 drive and control the two semiconductor elements 101A and 101B constituting the half bridge circuit 4.
　駆動ＩＣ１５１、１５３は、半導体素子１０１Ａ、１０１Ｂに対し共通のＶｆ制御部２６と共通のパルス制御部２７を備えており、電源電圧ＶDD（例えば１５Ｖ）が供給されることで動作する。ゲート駆動信号ＳGHは、レベルシフト部５７とドライブ回路２８を介して半導体素子１０１Ａに与えられ、ゲート駆動信号ＳGLは、ドライブ回路２８を介して半導体素子１０１Ｂに与えられる。 The drive ICs 151 and 153 are provided with a common Vf control unit 26 and a common pulse control unit 27 for the semiconductor elements 101A and 101B, and operate when supplied with a power supply voltage VDD (for example, 15V). The gate drive signal SGH is given to the semiconductor element 101A via the level shift unit 57 and the drive circuit 28, and the gate drive signal SGL is given to the semiconductor element 101B via the drive circuit 28.
　駆動ＩＣ１５１は、センス抵抗１０７Ａ、１０７Ｂに生じるセンス電圧ＶSH、ＶSLに基づいて電圧検出信号を出力する電圧検出部１２５を備えている。ハイサイド側の電圧検出部１２５は、レベルシフト回路５８を介して電圧検出信号を出力する。駆動ＩＣ１５３は、ハイサイド側の電圧検出部１２５とレベルシフト回路５８を省いた構成を備えている。 The drive IC 151 includes a voltage detection unit 125 that outputs a voltage detection signal based on the sense voltages VSH and VSL generated in the sense resistors 107A and 107B. The high-side voltage detection unit 125 outputs a voltage detection signal via the level shift circuit 58. The drive IC 153 has a configuration in which the high-side voltage detection unit 125 and the level shift circuit 58 are omitted.
　パルス制御部２７は、ゲート駆動信号ＳGH、ＳGLを生成するので、２つの半導体素子１０１Ａ、１０１Ｂのうち一方の半導体素子にゲート駆動電圧を印加している期間、他方の半導体素子へのゲート駆動電圧の印加を禁止できる。これにより、アーム短絡を確実に防止できる。 Since the pulse control unit 27 generates the gate drive signals SGH and SGL, the gate drive voltage applied to the other semiconductor element during the period when the gate drive voltage is applied to one of the two semiconductor elements 101A and 101B. Can be prohibited. Thereby, an arm short circuit can be prevented reliably.
　また、第１３の実施形態を示す図２１に示すように、ハイサイド側とローサイド側とで電圧検出部１２５を共用化できるので、回路構成を簡単化できる。この場合、共用化することで省略した電圧検出部１２５に対応したセンス素子（１０５ｓ、１０６ｓ）およびセンス抵抗（１０７）を省略しても良い。共用化する場合には、しきい値設定回路３０、３１で生成される規定電圧Ｖm1、Ｖm2に基づいて、ハイサイド側の規定電圧を第１０の実施形態よりも大きく設定することが好ましい。その他、第１０、第１１の実施形態と同様の作用および効果が得られる。 Further, as shown in FIG. 21 showing the thirteenth embodiment, since the voltage detection unit 125 can be shared between the high side and the low side, the circuit configuration can be simplified. In this case, the sense elements (105s, 106s) and the sense resistor (107) corresponding to the voltage detection unit 125 omitted by sharing may be omitted. In the case of sharing, it is preferable to set the specified voltage on the high side larger than that in the tenth embodiment based on the specified voltages Vm1 and Vm2 generated by the threshold setting circuits 30 and 31. In addition, operations and effects similar to those of the tenth and eleventh embodiments can be obtained.
　（第１４の実施形態）
　図２２は第１４の実施形態を示すもので、制御部とドライブ回路とを分離して構成した駆動制御装置１６２を示している。駆動制御装置１６２は、ハーフブリッジ回路４を構成する２つの半導体素子１０１Ａ、１０１Ｂを駆動制御する。駆動制御装置１６２は、制御ＩＣ１６３、フォトカプラ６４Ａ、６４Ｂ、６７Ａ、６７Ｂ、駆動ＩＣ６５Ａ、６５Ｂ、電圧検出部１６８などから構成されている。 (Fourteenth embodiment)
FIG. 22 shows a fourteenth embodiment and shows a drive control device 162 configured by separating a control unit and a drive circuit. The drive control device 162 controls the drive of the two semiconductor elements 101A and 101B constituting the half bridge circuit 4. The drive control device 162 includes a control IC 163, photocouplers 64A, 64B, 67A, 67B, drive ICs 65A, 65B, a voltage detection unit 168, and the like.
　制御ＩＣ１６３は、専用ＡＳＩＣ、マイコンのハードＩＰ（Intellectual Property）、ＦＰＧＡなどから構成されており、上述したＶｆ制御部２６とパルス制御部２７が実装されている。フォトカプラ６４Ａ、６４Ｂは、ゲート駆動信号ＳGH、ＳGLを電気的に絶縁して駆動ＩＣ６５Ａ、６５Ｂに伝送する絶縁回路である。駆動ＩＣ６５Ａ、６５Ｂは、ドライブ回路２８を備えており、ゲート駆動信号ＳGH、ＳGLを入力してゲート駆動電圧ＶGH、ＶGLを出力する。 The control IC 163 includes a dedicated ASIC, a microcomputer hardware IP (Intellectual Property), an FPGA, and the like, and the Vf control unit 26 and the pulse control unit 27 described above are mounted thereon. The photocouplers 64A and 64B are insulation circuits that electrically insulate the gate drive signals SGH and SGL and transmit them to the drive ICs 65A and 65B. The drive ICs 65A and 65B include a drive circuit 28, which receives gate drive signals SGH and SGL and outputs gate drive voltages VGH and VGL.
　電圧検出部１６８は、フォトカプラ６７Ａ、６７Ｂを通じてセンス電圧ＶSH、ＶSLを検出する。電圧検出部１６８は、半導体素子１０１Ａ、１０１Ｂに流れる電流値または電流の向き（極性）をセンス素子１０５ｓ、１０６ｓにかかる電圧と抵抗１０７Ａ、１０７Ｂにかかる電圧の分圧電圧により検出できる。これにより、パルス制御およびＲＣ－ＩＧＢＴに対するＶｆ制御を実行できる。 The voltage detector 168 detects the sense voltages VSH and VSL through the photocouplers 67A and 67B. The voltage detection unit 168 can detect the value of the current flowing in the semiconductor elements 101A and 101B or the direction (polarity) of the current based on the divided voltage of the voltage applied to the sense elements 105s and 106s and the voltage applied to the resistors 107A and 107B. Thereby, pulse control and Vf control for RC-IGBT can be executed.
　本実施形態によっても、パルス制御部２７は、２つの半導体素子１０１Ａ、１０１Ｂのうち一方の半導体素子にゲート駆動電圧を印加している期間、他方の半導体素子へのゲート駆動電圧の印加を禁止できる。これにより、アーム短絡を確実に防止できる。また、フォトカプラ６７Ａ、６７Ｂの何れか一方を省略してもよい。このとき、省略したフォトカプラ６７Ａ，６７Ｂに対応したセンス素子（１０５ｓ、１０６ｓ）およびセンス抵抗（１０７）を省略しても良い。この場合には、電圧検出部１６８は、半導体素子１０１Ｂに流れる電流の極性検出信号に基づいて、他方の半導体素子１０１Ａに流れる電流の極性を推定する。電圧検出部１６８の前段ではなく電圧検出部１６８の後段にフォトカプラ６７Ａ、６７Ｂと同様の構成のフォトカプラを設けても良い。電圧検出部１６８を制御ＩＣ６３もしくは駆動ＩＣ６５内に形成してもよい。 Also in this embodiment, the pulse control unit 27 can prohibit the application of the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements 101A and 101B. . Thereby, an arm short circuit can be prevented reliably. Further, either one of the photocouplers 67A and 67B may be omitted. At this time, the sense elements (105s, 106s) and the sense resistor (107) corresponding to the omitted photocouplers 67A and 67B may be omitted. In this case, the voltage detection unit 168 estimates the polarity of the current flowing through the other semiconductor element 101A based on the polarity detection signal of the current flowing through the semiconductor element 101B. A photocoupler having a configuration similar to that of the photocouplers 67A and 67B may be provided not in the previous stage of the voltage detection unit 168 but in the subsequent stage of the voltage detection unit 168. The voltage detection unit 168 may be formed in the control IC 63 or the drive IC 65.
　ＰＷＭ信号ＦＨ、ＦＬが制御ＩＣ１６３のＶｆ制御部２６に入力されているため、Ｖｆ制御部２６およびパルス制御部２７は、一方及び他方のアームの制御を統括的に実行することができる。この実施形態によっても、第１０、第１１の実施形態と同様の作用および効果が得られる。 Since the PWM signals FH and FL are input to the Vf control unit 26 of the control IC 163, the Vf control unit 26 and the pulse control unit 27 can collectively control the one and the other arms. Also according to this embodiment, the same operation and effect as those of the tenth and eleventh embodiments can be obtained.
　（第１５の実施形態）
　図２３は第１５の実施形態を示すもので、制御部とドライブ回路とを分離するとともに、Ｖｆ制御部２６、パルス制御部２７および電圧検出部１２５をマイコン１２１に取り込んだ構成の駆動制御装置１７２を示している。駆動制御装置１７２は、ハーフブリッジ回路４を構成する２つの半導体素子１０１Ａ、１０１Ｂを駆動制御する。駆動制御装置１７２は、マイコン１２１、フォトカプラ６４Ａ、６４Ｂ、駆動ＩＣ６５Ａ、６５Ｂなどから構成されている。駆動制御装置１７２は、センス電圧ＶSH、ＶSLを入力とするフォトカプラ６７Ａ、６７Ｂを備えている。 (Fifteenth embodiment)
FIG. 23 shows a fifteenth embodiment, in which a controller and a drive circuit are separated, and a drive controller 172 having a configuration in which a Vf controller 26, a pulse controller 27, and a voltage detector 125 are incorporated in a microcomputer 121. Is shown. The drive control device 172 controls the drive of the two semiconductor elements 101A and 101B constituting the half bridge circuit 4. The drive control device 172 includes a microcomputer 121, photocouplers 64A and 64B, drive ICs 65A and 65B, and the like. The drive controller 172 includes photocouplers 67A and 67B that receive the sense voltages VSH and VSL.
　マイコン１２１は、メモリ７３に予め記憶された制御プログラムを実行することにより、上述したＶｆ制御部２６、パルス制御部２７および電圧検出部１２５の機能を実現する。駆動制御装置１７２のマイコン１２１は、フォトカプラ６７Ａ、６７Ｂの出力信号を介して電圧検出信号を得る。メモリ７３には、制御プログラムの他に、第１時間Ｔ１と第２時間Ｔ２、しきい値なども記憶されている。 The microcomputer 121 implements the functions of the Vf control unit 26, the pulse control unit 27, and the voltage detection unit 125 described above by executing a control program stored in advance in the memory 73. The microcomputer 121 of the drive control device 172 obtains a voltage detection signal via the output signals of the photocouplers 67A and 67B. In addition to the control program, the memory 73 also stores a first time T1, a second time T2, a threshold value, and the like.
　本実施形態によっても、マイコン１２１は、２つの半導体素子１０１Ａ、１０１Ｂのうち一方の半導体素子にゲート駆動電圧を印加している期間、他方の半導体素子へのゲート駆動電圧の印加を禁止できる。これにより、アーム短絡を確実に防止できる。また、フォトカプラ６７Ａ、６７Ｂの何れか一方を省略してもよい。このとき、省略したフォトカプラ６７Ａ，６７Ｂに対応したセンス素子（１０５ｓ、１０６ｓ）およびセンス抵抗（１０７）を省略しても良い。共用化する場合には、しきい値設定回路３０、３１で生成される規定電圧Ｖm1、Ｖm2に基づいて、ハイサイド側の規定電圧を第１０の実施形態よりも大きく設定することが好ましい。その他、第１０、第１１の実施形態と同様の作用および効果が得られる。 Also in the present embodiment, the microcomputer 121 can prohibit the application of the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements 101A and 101B. Thereby, an arm short circuit can be prevented reliably. Further, either one of the photocouplers 67A and 67B may be omitted. At this time, the sense elements (105s, 106s) and the sense resistor (107) corresponding to the omitted photocouplers 67A and 67B may be omitted. In the case of sharing, it is preferable to set the specified voltage on the high side larger than that in the tenth embodiment based on the specified voltages Vm1 and Vm2 generated by the threshold setting circuits 30 and 31. In addition, operations and effects similar to those of the tenth and eleventh embodiments can be obtained.
　ＰＷＭ信号ＦＨ、ＦＬが制御ＩＣ１６３のＶｆ制御部２６に入力されているため、Ｖｆ制御部２６およびパルス制御部２７は、一方及び他方のアームの制御を統括的に実行することができる。第１４の実施形態と同様に、フォトカプラ６７Ａを省略してもよい。これらの実施形態によっても、第１０、第１１の実施形態と同様の作用および効果が得られる。 Since the PWM signals FH and FL are input to the Vf control unit 26 of the control IC 163, the Vf control unit 26 and the pulse control unit 27 can collectively control the one and the other arms. As in the fourteenth embodiment, the photocoupler 67A may be omitted. Also in these embodiments, the same operations and effects as those in the tenth and eleventh embodiments can be obtained.
　（第１６の実施形態）
　図２４は第１６の実施形態を示すもので、中間電位を電圧検出する電圧検出手段としての電圧検出部１８０を設けた形態を示す。図２４に示す電圧検出部１８０は、トランジスタ素子１０５、ダイオード構造１０６の素子形成領域１００の外周側の半導体基板８に設けられるガードリング８ａの電位を検出するように設けられる。半導体基板８の下面側表層部には、ダイオード構造６のカソード領域１７、トランジスタ構造５のコレクタ電極１８が形成されているが、これらの素子形成領域１００だけでなくそのまま外周縁側に連通され耐圧保持領域１０１に及んでいる。 (Sixteenth embodiment)
FIG. 24 shows a sixteenth embodiment and shows a mode in which a voltage detection unit 180 is provided as voltage detection means for detecting a voltage of an intermediate potential. 24 is provided so as to detect the potential of the guard ring 8a provided on the semiconductor substrate 8 on the outer peripheral side of the element formation region 100 of the transistor element 105 and the diode structure 106. The voltage detector 180 shown in FIG. The cathode region 17 of the diode structure 6 and the collector electrode 18 of the transistor structure 5 are formed on the lower surface side layer portion of the semiconductor substrate 8. The region 101 is reached.
　この耐圧保持領域１０１にはガードリング８ａが形成される。このガードリング８ａは複数形成されている。このガードリング８ａは、半導体層８とは異なる導電型（この場合、ｐ＋（逆導電型））に形成されており、素子形成領域１００の外周を囲むように平面的には例えば同心円状に形成されている。 A guard ring 8a is formed in the pressure resistant holding region 101. A plurality of guard rings 8a are formed. The guard ring 8a is formed in a conductivity type different from that of the semiconductor layer 8 (in this case, p + (reverse conductivity type)), and is formed concentrically in a plan view so as to surround the outer periphery of the element formation region 100. Has been.
　そして、半導体基板８のガードリング８ａよりも外周領域となる最外周領域には、通常半導体基板８と同一導電型となるｎ＋の等価電位リング（ＥＱＲ：Equivalent Potential ing）８ｂがチャネルストッパ領域として形成され、ドレイン電位を固定するために設けられる。ガードリング８ａは、半導体基板８の外周縁側において互いに離間して形成され、最外周の等価電位リング８ｂと素子形成領域１００側に設けられるソース電極との間に発生する電界緩和のために設けられている。 Then, an n + equivalent potential ring (EQR) 8b having the same conductivity type as that of the semiconductor substrate 8 is formed as a channel stopper region in the outermost peripheral region which is the outer peripheral region of the guard ring 8a of the semiconductor substrate 8. Provided to fix the drain potential. The guard rings 8a are formed to be separated from each other on the outer peripheral edge side of the semiconductor substrate 8, and are provided to alleviate the electric field generated between the outermost equivalent potential ring 8b and the source electrode provided on the element forming region 100 side. ing.
　これらのガードリング８ａは外周側から順に段階的に電位が低くなり耐圧を保持できる。電圧検出部１８０は、このうち何れか一つのガードリング８ａの層の上部から電圧を検出することでコレクタエミッタ間の中間電位を検出できる。この中間電位の変化は、前述の実施形態で説明したコレクタ電極電位ＶCOの変化と同様の変化であり、このように電圧検出部１８０がこの中間電位を検出したとしても同様に制御できる。 The potential of these guard rings 8a decreases step by step from the outer peripheral side and can maintain a withstand voltage. The voltage detector 180 can detect the intermediate potential between the collector and emitter by detecting the voltage from the upper part of any one of the guard ring 8a layers. The change in the intermediate potential is the same change as the change in the collector electrode potential VCO described in the above-described embodiment, and even if the voltage detection unit 180 detects the intermediate potential as described above, it can be controlled similarly.
　この実施形態に示した電圧検出部１８０は、第１０～第１５の実施形態の電圧検出部１２５に替えて用いることができるし、電圧検出部１２５と共に用いても良い。また、前述した第１～第９の実施形態の各実施形態に示した電流検出手段（７Ａ、７Ｂ、２５、５９、６０、６８）の構成と組み合わせて用いても良い。 The voltage detection unit 180 shown in this embodiment can be used in place of the voltage detection unit 125 of the tenth to fifteenth embodiments, or may be used together with the voltage detection unit 125. Further, it may be used in combination with the configuration of the current detection means (7A, 7B, 25, 59, 60, 68) shown in the respective embodiments of the first to ninth embodiments.
　また電圧検出部１８０から検出した中間電位は必要に応じて抵抗分圧等によりさらに降圧して用いてもよい。 Further, the intermediate potential detected from the voltage detection unit 180 may be further stepped down by resistance division or the like as necessary.
　（第１～第１６の実施形態についての他の実施形態）
　以上、第１～第１６の実施形態について説明したが、以下のように開示の要旨を逸脱しない範囲内で種々の変形、拡張を行うことができる。 (Other embodiments of the first to sixteenth embodiments)
Although the first to sixteenth embodiments have been described above, various modifications and extensions can be made without departing from the scope of the disclosure as follows.
　各実施形態は、Ｖｆ制御部２６によるＶｆ制御とパルス制御部２７によるパルス制御のうちＶｆ制御だけを行う構成またはパルス制御だけを行う構成に変更してもよい。第３から第７の実施形態においてＶｆ制御だけを行う構成の場合、Ｖｆ制御部２６が、半導体素子１Ａ、１Ｂのうち一方の半導体素子にゲート駆動電圧を印加している期間、他方の半導体素子へのゲート駆動電圧の印加が禁止されることは勿論である。 Each embodiment may be changed to a configuration in which only the Vf control is performed among the Vf control by the Vf control unit 26 and the pulse control by the pulse control unit 27, or a configuration in which only the pulse control is performed. In the case where only the Vf control is performed in the third to seventh embodiments, the Vf control unit 26 applies the gate drive voltage to one of the semiconductor elements 1A and 1B during the other semiconductor element. Of course, the application of the gate drive voltage to is prohibited.
　Ｖｆ制御部２６、パルス制御部２７は、それぞれ検出電圧の大きさが規定値よりも小さくなるとＶｆ制御、パルス制御を停止して通常制御を行うようにしたが、この通常制御への切り替え制御は必要に応じて実行すればよい。 The Vf control unit 26 and the pulse control unit 27 stop the Vf control and the pulse control and perform the normal control when the magnitude of the detected voltage becomes smaller than the specified value, respectively. What is necessary is just to perform as needed.
　第１１の実施形態においても、負荷電流の大きさが規定値Ｉm1、Ｉm2よりも小さくなると、それぞれＶｆ制御、パルス制御を停止して通常制御を行う構成としてもよい。また、駆動制御システムの運転領域が常に図６に示す領域１にある場合には、Ｖｆ制御部２６から、領域１と領域２との間での制御切替機能を省いてもよい。すなわち、Ｖｆ制御部２６は、ＰＷＭ信号ＦＬがＨレベルの期間、常にゲート駆動電圧ＶGLを半導体素子１Ｂのゲートに印加する。Ｖｆ制御部２６は、当該期間において半導体素子１Ｂにダイオード素子６の順方向の向きに電流が流れていると判定すると、第１１の実施形態と同様にして、時刻ｔ２から第２時間Ｔ２の経過時点（時刻ｔ６）までパルスの拡張を行う。 Also in the eleventh embodiment, when the magnitude of the load current becomes smaller than the specified values Im1 and Im2, the Vf control and the pulse control may be stopped and the normal control may be performed, respectively. Further, when the operation region of the drive control system is always in the region 1 shown in FIG. 6, the control switching function between the region 1 and the region 2 may be omitted from the Vf control unit 26. That is, the Vf control unit 26 always applies the gate drive voltage VGL to the gate of the semiconductor element 1B while the PWM signal FL is at the H level. If the Vf control unit 26 determines that a current flows in the forward direction of the diode element 6 in the semiconductor element 1B during the period, the second time T2 elapses from the time t2 as in the eleventh embodiment. The pulse is expanded until the time (time t6).
　第１２から第１６の実施形態は、半導体素子１０１Ａ、１０１ＢにＭＯＳトランジスタを用いた構成に対しても、第１１の実施形態と同様にして適用できる。半導体素子１０１Ａ、１０１Ｂは、コントロール用のゲートを有し寄生ダイオードが形成された素子、例えばＭＯＳゲートを備えたダイオードであってもよい。ＲＣ－ＩＧＢＴは、トレンチゲート型に限らずプレーナゲート型などであってもよい。ＭＯＳトランジスタは、トレンチゲート型に限らずプレーナゲート型などであってもよい。ＭＯＳトランジスタは、ＳＪ（Super Junction）構造であってもよい。 The twelfth to sixteenth embodiments can be applied to a configuration using MOS transistors for the semiconductor elements 101A and 101B in the same manner as the eleventh embodiment. The semiconductor elements 101A and 101B may be elements having a control gate and formed with a parasitic diode, for example, a diode having a MOS gate. The RC-IGBT is not limited to the trench gate type but may be a planar gate type. The MOS transistor is not limited to a trench gate type but may be a planar gate type. The MOS transistor may have an SJ (Super Junction) structure.
　センス素子１０５ｓ、１０６ｓを並列接続した構成を用いて説明したが、これに替えて、センスダイオード１０６ｓ、を単独でセンス素子として構成し、電圧検出部１２５がこのセンス素子の両端にかかる直流電圧（ＤＣ電圧）を検出するようにしても良い。これらの構成の場合、電圧検出だけでなく電流検出用としても共用できる。また、センスダイオード１０６ｓに替えて抵抗を使用して直流電圧（ＤＣ電圧）を検出するようにしても良い。あるいは、センストランジスタ１０５ｓを単独でセンス素子として使用しても良い。この場合、センストランジスタ１０５ｓはトランジスタ容量として機能するため電圧変化をパルス電圧／電流として検出できる。 Although the description has been given using the configuration in which the sense elements 105s and 106s are connected in parallel, instead of this, the sense diode 106s is configured alone as a sense element, and the voltage detection unit 125 has a direct current voltage applied to both ends of the sense element ( DC voltage) may be detected. These configurations can be used not only for voltage detection but also for current detection. Further, a DC voltage (DC voltage) may be detected using a resistor instead of the sense diode 106s. Alternatively, the sense transistor 105s may be used alone as a sense element. In this case, since the sense transistor 105s functions as a transistor capacitance, a voltage change can be detected as a pulse voltage / current.
　図１の構成を採用した場合、図２７に示すように、電流検出部２５が半導体素子１Ａの電流を検出し、この電流の変動を検出した時点ｔ１ｃで、Ｖｆ制御部２６がｔ２よりも前にパルスを拡張してゲート駆動信号ＳGLをＨレベルとして出力しても良い。図１の電流検出部２５に替えてその他の形態の電流検出部２５を設けても良く、第７の実施形態の電流極性検出回路６８を設けても良い。 When the configuration of FIG. 1 is adopted, as shown in FIG. 27, the current detection unit 25 detects the current of the semiconductor element 1A, and at the time t1c when the fluctuation of this current is detected, the Vf control unit 26 precedes t2. Alternatively, the pulse may be extended to output the gate drive signal SGL as the H level. Instead of the current detection unit 25 of FIG. 1, another form of the current detection unit 25 may be provided, or the current polarity detection circuit 68 of the seventh embodiment may be provided.
　また、図２８に示すように、図１７に示す形態を基本構成として逆アーム側のゲート駆動電圧ＶGHを検出する電圧検出部２２５を制御電圧検出手段として設け、この電圧検出部２２５により検出されるゲート駆動電圧ＶGHがしきい値電圧Ｖth未満になることが検出された時点で、Ｖｆ制御部２６（制御手段）がｔ２よりも前にパルスを拡張してゲート駆動信号ＳGLをＨレベルとして出力するようにしても良い。Ｖｆ制御、パルス制御に係る各ノードの制御信号、駆動信号等の波形は図２７と同じであるため省略する。電圧検出部２２５は駆動ＩＣ１２４Ａ、１２４Ｂ内に組み込んでも駆動ＩＣ１２４Ａ、１２４Ｂとは独立に構成しても良い。 Further, as shown in FIG. 28, a voltage detector 225 for detecting the gate drive voltage VGH on the reverse arm side is provided as a control voltage detector based on the configuration shown in FIG. 17 and is detected by this voltage detector 225. When it is detected that the gate drive voltage VGH is lower than the threshold voltage Vth, the Vf control unit 26 (control means) extends the pulse before t2 and outputs the gate drive signal SGL as the H level. You may do it. Waveforms of control signals, drive signals, and the like at each node relating to Vf control and pulse control are the same as those in FIG. The voltage detection unit 225 may be incorporated in the drive ICs 124A and 124B or may be configured independently of the drive ICs 124A and 124B.
　同様に、図１２に対応して表す図２９に示すように、フォトカプラ２６７Ａ、２６７Ｂを介して逆アーム側のゲート駆動電圧ＶGHを検出する電圧検出部２２５をそれぞれ設け、この電圧検出部２２５によりゲート駆動電圧ＶGHがしきい値電圧Ｖth未満になることが検出された時点で、Ｖｆ制御部２６（制御手段）がｔ２よりも前にパルスを拡張してゲート駆動信号ＳGLをＨレベルとして出力するようにしても良い。各ノードの制御信号、駆動信号等の波形は図２７と同じであるため図示を省略している。同様に、図２９に示す電圧検出部２２５もまた、制御ＩＣ６３内に組み込んでも制御ＩＣ６３とは独立に構成しても良い。 Similarly, as shown in FIG. 29 corresponding to FIG. 12, a voltage detection unit 225 for detecting the gate drive voltage VGH on the reverse arm side is provided via the photocouplers 267A and 267B, respectively. When it is detected that the gate drive voltage VGH is lower than the threshold voltage Vth, the Vf control unit 26 (control means) extends the pulse before t2 and outputs the gate drive signal SGL as the H level. You may do it. The waveforms of control signals, drive signals, etc. at each node are the same as in FIG. Similarly, the voltage detection unit 225 shown in FIG. 29 may be incorporated in the control IC 63 or may be configured independently of the control IC 63.
　また、図３０に示すように、自アーム側の駆動ＩＣ２４Ａ、２４Ｂが、逆アーム側のＰＷＭ信号ＦＬ又はＦＨをＶｆ制御部２６（又はパルス制御部２７）に入力し、Ｖｆ制御部２６（又はパルス制御部２７）がこのＰＷＭ信号の立下りを検出した時点から所定時間経過したタイミングにおいて、Ｖｆ制御部２６がｔ２よりも前にパルス拡張してゲート駆動信号ＳGLをＨレベルとして出力するようにしても良い。この所定時間は予めアーム間短絡しないように予め定められた時間に設定すると良い。 Further, as shown in FIG. 30, the drive ICs 24A and 24B on the own arm side input the PWM signal FL or FH on the opposite arm side to the Vf control unit 26 (or pulse control unit 27), and the Vf control unit 26 (or At a timing when a predetermined time has elapsed since the pulse control unit 27) detected the fall of the PWM signal, the Vf control unit 26 performs pulse expansion before t2 and outputs the gate drive signal SGL as the H level. May be. The predetermined time may be set to a predetermined time so as not to short-circuit between the arms in advance.
　また、図３１に示すように、自アーム側の駆動ＩＣ１２４Ａ、１２４Ｂが、逆アーム側のＰＷＭ信号ＦＬ又はＦＨをＶｆ制御部２６（又はパルス制御部２７）に入力し、Ｖｆ制御部２６（又はパルス制御部２７）がこのＰＷＭ信号の立下りを検出した時点から所定時間経過したタイミングにおいて、Ｖｆ制御部２６がｔ２よりも前にパルス拡張してゲート駆動信号ＳGLをＨレベルとして出力するようにしても良い。この所定時間は予めアーム間短絡しないように予め定められた時間に設定すると良い。 Further, as shown in FIG. 31, the drive ICs 124A and 124B on the own arm side input the PWM signal FL or FH on the opposite arm side to the Vf control unit 26 (or pulse control unit 27), and the Vf control unit 26 (or At a timing when a predetermined time has elapsed since the pulse control unit 27) detected the fall of the PWM signal, the Vf control unit 26 performs pulse expansion before t2 and outputs the gate drive signal SGL as the H level. May be. The predetermined time may be set to a predetermined time so as not to short-circuit between the arms in advance.
　図２８～図３１には一例を示したが、その他にも、第１～第９実施形態に示した電流検出手段（電流検出部２５、ホールセンサ５９、電流検出回路６０、電流極性検出回路６８など）、第１０～第１５の実施形態に示した電圧検出手段（電圧検出部１２５、電圧検出部１６８など）、制御電圧検出手段（電圧検出部２２５）、の何れか２つを組み合わせて構成しても良い。 FIGS. 28 to 31 show an example. In addition, the current detection means (current detection unit 25, hall sensor 59, current detection circuit 60, current polarity detection circuit 68 shown in the first to ninth embodiments is shown. Etc.), a combination of any two of the voltage detection means (voltage detection section 125, voltage detection section 168, etc.) and control voltage detection means (voltage detection section 225) shown in the tenth to fifteenth embodiments. You may do it.
　特に、電流検出手段と電圧検出手段を組み合わせて構成すると、図３２に示すように、アーム短絡を生じない程度で、Ｖｆ制御部２６が時点ｔ２よりも前の時点ｔ１ｂからパルス拡張してゲート駆動信号ＳGLをＨレベルとして出力できる。この図３２に示す例の場合、ゲート駆動電圧ＶGLのマージン期間Ｍａ（図１９参照）を最短（≒０）にできる。 In particular, when the current detection unit and the voltage detection unit are combined, as shown in FIG. 32, the Vf control unit 26 expands the pulse from the time point t1b before the time point t2 to drive the gate without causing an arm short circuit. The signal SGL can be output as an H level. In the example shown in FIG. 32, the margin period Ma (see FIG. 19) of the gate drive voltage VGL can be made the shortest (≈0).
　逆アーム側のＰＷＭ信号ＦＨ、ＦＬを自アーム側の駆動ＩＣ２４Ａ、２４ＢのＶｆ制御部２６又はパルス制御部２７に入力する形態を、電流検出部２５、電圧検出部１２５、電圧検出部２２５により電流または電圧を検出して制御する形態に組み合わせても良い。 The form in which the PWM signals FH and FL on the reverse arm side are input to the Vf control unit 26 or the pulse control unit 27 of the drive ICs 24A and 24B on the own arm side is determined by the current detection unit 25, the voltage detection unit 125, and the voltage detection unit 225. Or you may combine with the form which detects and controls a voltage.
　例えば、図１８、図１９に示したように、半導体素子１０１Ａの電流の立下り時点とコレクタ電極電位Ｖcoの立下り検出時点とを比較すると、コレクタ電極電位Ｖcoの立下り検出時点が半導体素子１０１Ａの電流の立下り時点よりも速いことがわかる。 For example, as shown in FIG. 18 and FIG. 19, when the falling time of the current of the semiconductor element 101A and the falling detection time of the collector electrode potential Vco are compared, the falling detection time of the collector electrode potential Vco is the semiconductor element 101A. It can be seen that it is faster than the current falling point.
　したがって、例えば第１０の実施形態等で説明した電圧検出手段を用い、Ｖｆ制御部２６にＰＷＭ信号ＦＬのオフ指令信号が入力されているときに、電圧検出信号に基づいてダイオード構造６の順方向の向きに電流が流れていると判定した場合、図３２に示すように、ゲート駆動電圧ＶGLが上昇するタイミングが、半導体素子１０１Ａに電流が流れなくなり始めるタイミングｔ１ｃ（例えば、半導体素子１０１Ｂに電流が流れ出すタイミング）よりも後となるように、ゲート駆動信号ＳGLをタイミングｔ２よりも前の時点ｔ１ｂからパルス拡張すると良い。 Therefore, for example, when the voltage detection means described in the tenth embodiment or the like is used and the OFF command signal of the PWM signal FL is input to the Vf control unit 26, the forward direction of the diode structure 6 is based on the voltage detection signal. 32, when the gate drive voltage VGL rises, the timing at which the current starts to flow to the semiconductor element 101A t1c (for example, the current flows to the semiconductor element 101B), as shown in FIG. The gate drive signal SGL may be pulse-expanded from the time point t1b before the timing t2 so as to be later than the timing at which it flows out.
　なお、パルス拡張してゲート駆動信号ＳGLを出力してからゲート駆動電圧ＶGLを生成するまでに所定の遅延時間を要する。このため、この遅延時間を予め測定し、この測定時間を見込んで時点ｔ２よりも前にパルス拡張開始するタイミングｔ１ｂを予め設定しても良い。第１１の実施形態で説明したように、電圧検出部１２５、ドライバ２８、半導体素子１０１Ａ、１０１Ｂなどには各種の遅延バラつきを生じるが、この遅延バラつきを予め測定しておきマージンを見込んでおくと良い。しかし、電圧検出部１２５及び電流検出部２５などを用いて電圧検出制御及び電流検出制御を組み合わせれば、電圧変動を検出した時点（ｔ１ａ）においてパルス拡張開始のタイミングを決定できるため、遅延バラつきを予め測定し時点ｔ２よりも前にパルス拡張開始するタイミングを設定しなくても良くなる。 It should be noted that a predetermined delay time is required until the gate drive voltage VGL is generated after the pulse is extended and the gate drive signal SGL is output. For this reason, the delay time may be measured in advance, and the timing t1b at which the pulse expansion starts may be set in advance before the time t2 in anticipation of the measurement time. As described in the eleventh embodiment, various delay variations occur in the voltage detection unit 125, the driver 28, the semiconductor elements 101A and 101B, and the delay variation is measured in advance to allow for a margin. good. However, if voltage detection control and current detection control are combined using the voltage detection unit 125, the current detection unit 25, etc., the timing of the pulse expansion start can be determined at the time when the voltage fluctuation is detected (t1a). It is not necessary to set the timing for starting the pulse expansion before the time t2 after measurement in advance.
　このような制御を行うと、第１～第９の実施形態で説明した電流検出手段のみを用いて制御を行うよりもＶｆ制御部２６が行う第１１の実施形態のパルス拡張をより速い時点から行うことができ、ゲート駆動処理に要する時間の確保と同期整流期間の拡張ができ、最大限の効果が得られる。 When such control is performed, the pulse expansion of the eleventh embodiment performed by the Vf control unit 26 is performed at a faster time point than when the control is performed using only the current detection means described in the first to ninth embodiments. The time required for the gate driving process can be secured and the synchronous rectification period can be extended, and the maximum effect can be obtained.
　図面中、１Ａ、１Ｂ、１０１Ａ、１０１Ｂは半導体素子、４はハーフブリッジ回路、５、１０５はトランジスタ素子（トランジスタ構造）、６、１０６はダイオード素子（ダイオード構造）、７Ａ、７Ｂ、１０７Ａ、１０７Ｂはセンス抵抗（電流検出手段）、８は半導体基板、８ａはガードリング（電界制限リング）、１５はエミッタ電極（通電電極）、１８はコレクタ電極（通電電極）、２１、１２１はマイコン（制御ＩＣ）、２４Ａ、２４Ｂ、１２４Ａ、１２４Ｂ、５１、５３、５５、１５１、１５３は駆動ＩＣ（ＩＣ）、２５は電流検出部（電流検出手段）、１２５、１６８は電圧検出部（電圧検出手段）、２６はＶｆ制御部（制御手段，第２の制御手段，入力手段）、２７はパルス制御部（制御手段，第１の制御手段，入力手段）、２８はドライブ回路、３２Ａ、３２Ｂ、１３２Ａ、１３２Ｂ、５２、５４、５６、１５２、１５４、６１、６２、１６２、７１、７２、１７２は駆動制御装置、５９はホールセンサ（電流検出手段）、６０は電流検出回路（電流検出手段）、６３は制御ＩＣ、６４Ａ、６４Ｂ、６７Ａ、６７Ｂはフォトカプラ（絶縁回路）、６５Ａ、６５Ｂは駆動ＩＣ、６８は電流極性検出回路（電流検出手段）、１８０は電圧検出部（電圧検出手段）、２２５は電圧検出部（制御電圧検出手段）である。 In the drawings, 1A, 1B, 101A and 101B are semiconductor elements, 4 is a half-bridge circuit, 5 and 105 are transistor elements (transistor structure), 6 and 106 are diode elements (diode structure), 7A, 7B, 107A and 107B are Sense resistor (current detection means), 8 is a semiconductor substrate, 8a is a guard ring (electric field limiting ring), 15 is an emitter electrode (energized electrode), 18 is a collector electrode (energized electrode), and 21 and 121 are microcomputers (control IC) 24A, 24B, 124A, 124B, 51, 53, 55, 151, and 153 are drive ICs (ICs), 25 is a current detector (current detector), 125 and 168 are voltage detectors (voltage detector), 26 Is a Vf control section (control means, second control means, input means), 27 is a pulse control section (control means, first control means, input means) 28 is a drive circuit, 32A, 32B, 132A, 132B, 52, 54, 56, 152, 154, 61, 62, 162, 71, 72, and 172 are drive control devices, 59 is a hall sensor (current detection means), 60 Is a current detection circuit (current detection means), 63 is a control IC, 64A, 64B, 67A and 67B are photocouplers (insulation circuit), 65A and 65B are drive ICs, 68 is a current polarity detection circuit (current detection means), 180 Is a voltage detector (voltage detector), and 225 is a voltage detector (control voltage detector).
　（第１７の実施形態）
　以下、本開示の第１７の実施形態について図面を参照しながら説明する。上述した全ての実施形態に適用可能であるが、基本構成である図３３（第１の実施形態の図１に相当）の駆動制御システムを用いて説明する。図３３に示す駆動制御システムは、モータ等の誘導性負荷を駆動するインバータ装置、インダクタを備えて直流電圧を昇圧／降圧するコンバータ装置などの電力変換装置に用いられる。スイッチング素子である半導体素子１００１Ａ、１００１Ｂは、高電位側の直流電源線１００２と低電位側の直流電源線１００３との間に出力端子Ｎｔを挟んで直列に配されて、ハーフブリッジ回路１００４を構成している。 (Seventeenth embodiment)
Hereinafter, a seventeenth embodiment of the present disclosure will be described with reference to the drawings. Although applicable to all the embodiments described above, description will be made using the drive control system of FIG. 33 (corresponding to FIG. 1 of the first embodiment) which is a basic configuration. The drive control system shown in FIG. 33 is used in a power conversion device such as an inverter device that drives an inductive load such as a motor or a converter device that includes an inductor and boosts / steps down a DC voltage. The semiconductor elements 1001A and 1001B, which are switching elements, are arranged in series with the output terminal Nt sandwiched between the high potential side DC power supply line 1002 and the low potential side DC power supply line 1003 to form a half-bridge circuit 1004. is doing.
　Ｖｆ制御部１０２６とパルス制御部１０２７とで生成されたゲート駆動信号ＳGLは、ドライブ回路１０２８を介して半導体素子１００１Ｂのゲートに与えられる。ドライブ回路１０２８は、図３４に示すようにゲート駆動能力を複数通りに切り替えることができる。 The gate drive signal SGL generated by the Vf control unit 1026 and the pulse control unit 1027 is given to the gate of the semiconductor element 1001B through the drive circuit 1028. The drive circuit 1028 can switch the gate drive capability in a plurality of ways as shown in FIG.
　ドライブ回路１０２８は、ターンオン時に、ＭＯＳトランジスタ１０２９によりゲートを駆動する。ＭＯＳトランジスタ１０２９のゲートには、切替スイッチ１０３０を介して定電流駆動アンプ１０３１の出力電圧（Ａ側）またはフローティンググランドＦＧの電圧（Ｂ側）が与えられる。前者の場合に通常の駆動能力となり、後者の場合に高い駆動能力となる。また、ドライブ回路１０２８は、通常の駆動能力の場合に、駆動途中で短絡電流に対する保護動作を行う。このため、定電流駆動アンプ１０３１は、ゲート駆動電圧ＶGLの増加過程で、ゲート駆動電圧ＶGLを一時的に中間電圧に留める。 The drive circuit 1028 drives the gate by the MOS transistor 1029 when it is turned on. The output voltage (A side) of the constant current drive amplifier 1031 or the voltage of the floating ground FG (B side) is applied to the gate of the MOS transistor 1029 via the changeover switch 1030. In the former case, the normal driving capability is obtained, and in the latter case, the driving capability is high. Further, the drive circuit 1028 performs a protection operation against a short-circuit current during driving in the case of normal driving capability. Therefore, the constant current drive amplifier 1031 temporarily keeps the gate drive voltage VGL at the intermediate voltage in the process of increasing the gate drive voltage VGL.
　ドライブ回路１０２８は、ターンオフ時に、ＭＯＳトランジスタ１０３２、１０３３によりゲートを駆動する。切替スイッチ１０３４をＡ側に切り替えてＭＯＳトランジスタ１０３２のみで駆動すると通常の駆動能力となり、切替スイッチ１０３４をＢ側に切り替えてＭＯＳトランジスタ１０３２、１０３３で駆動すると高い駆動能力となる。ＭＯＳトランジスタ１０３３は、ＭＯＳトランジスタ１０３２よりも低いオン抵抗を持つ。なお、ＭＯＳトランジスタ１０３３は、半導体素子１００１Ｂをオフ状態に保持するときにも用いられる。 The drive circuit 1028 drives the gate by the MOS transistors 1032 and 1033 when turned off. When the changeover switch 1034 is switched to the A side and driven only by the MOS transistor 1032, normal driving capability is obtained, and when the changeover switch 1034 is switched to the B side and driven by the MOS transistors 1032, 1033, high driving capability is obtained. The MOS transistor 1033 has a lower on-resistance than the MOS transistor 1032. Note that the MOS transistor 1033 is also used when the semiconductor element 1001B is held in an off state.
　ＰＷＭ信号ＦＬの立ち上がり時、トランジスタ素子１００５に電流が流れている状態からのＰＷＭ信号ＦＬの立ち下がり時など、半導体素子１００１Ｂに流れる電流（素子電流）、電圧に急峻な変化が生じるときには、電圧サージの発生を抑制するため通常の駆動能力に切り替えられる。これに対し、パルス制御のように素子電流や電圧に急峻な変化が生じないときには、高い駆動能力に切り替えられる。 When a sharp change occurs in the current (element current) and voltage flowing through the semiconductor element 1001B, such as when the PWM signal FL rises, when the PWM signal FL falls from the state where the current flows in the transistor element 1005, a voltage surge occurs. In order to suppress the occurrence of this, it is switched to a normal driving capability. On the other hand, when there is no steep change in the device current or voltage as in pulse control, the driving capability is switched to high.
　駆動ＩＣ１０２４Ａには、しきい値設定回路１０３５Ａ、１０３６Ａ、１０３７Ａが外付けされている。駆動ＩＣ１０２４Ｂには、しきい値設定回路１０３５Ｂ、１０３６Ｂ、１０３７Ｂが外付けされている。しきい値設定回路１０２９Ａ、１０３０Ａ、１０３１Ａは、半導体素子１００１Ａのエミッタ電位に等しいフローティンググランドＦＧを基準電位として構成されている。しきい値設定回路１０３５Ａ、１０３５Ｂは、電圧ＶDDA、ＶDDBを抵抗Ｒ１、Ｒ２で分圧してしきい値電圧Ｖｔを生成する。しきい値設定回路１０３６Ａ、１０３６Ｂは、電圧ＶDDA、ＶDDBを抵抗Ｒ３、Ｒ４で分圧して規定電圧Ｖm1を生成する。しきい値設定回路１０３７Ａ、１０３７Ｂは、電圧ＶDDA、ＶDDBを抵抗Ｒ５、Ｒ６で分圧して規定電圧Ｖm2を生成する。 Threshold value setting circuits 1035A, 1036A, and 1037A are externally attached to the driving IC 1024A. Threshold setting circuits 1035B, 1036B, and 1037B are externally attached to the driving IC 1024B. The threshold setting circuits 1029A, 1030A, 1031A are configured with a floating ground FG equal to the emitter potential of the semiconductor element 1001A as a reference potential. The threshold setting circuits 1035A and 1035B divide the voltages VDDA and VDDB by the resistors R1 and R2 to generate the threshold voltage Vt. The threshold setting circuits 1036A and 1036B divide the voltages VDDA and VDDB by the resistors R3 and R4 to generate the specified voltage Vm1. The threshold setting circuits 1037A and 1037B divide the voltages VDDA and VDDB by the resistors R5 and R6 to generate a specified voltage Vm2.
　しきい値電圧Ｖｔは、Ｖｆ制御部１０２６で用いられる電流しきい値Ｉｔの大きさを決定する。ダイオード素子１００６の順方向電流Ｉｆに対する順方向電圧Ｖｆの特性は、素子の種類（ＲＣ－ＩＧＢＴ、ＭＯＳトランジスタ等）や素子の耐圧によって異なる。そこで、Ｖｆ制御部１０２６は、外部から与えられる切替信号Ｓｋとしきい値電圧Ｖｔとに基づいて、適切な電流しきい値Ｉｔを選択する。 The threshold voltage Vt determines the magnitude of the current threshold It used in the Vf control unit 1026. The characteristic of the forward voltage Vf with respect to the forward current If of the diode element 1006 varies depending on the type of element (RC-IGBT, MOS transistor, etc.) and the breakdown voltage of the element. Therefore, the Vf control unit 1026 selects an appropriate current threshold It based on the switching signal Sk and the threshold voltage Vt given from the outside.
　規定電圧Ｖm1は、Ｖｆ制御を停止するか否かの判定に用いる規定値Ｉm1の大きさを決定する。規定電圧Ｖm2は、パルス制御を停止するか否かの判定に用いる規定値Ｉm2の大きさを決定する。電流検出時と、その検出電流の極性に基づいてゲート駆動電圧ＶGH、ＶGLを印加した時とでは、制御の遅れにより電流極性が反転している虞もある。このため、Ｖｆ制御部１０２６は、電流検出値が規定値Ｉm1を下回るとＶｆ制御を停止し、パルス制御部１０２７は、電流検出値が規定値Ｉm2を下回るとパルス制御を停止する。 The specified voltage Vm1 determines the magnitude of the specified value Im1 used for determining whether or not to stop the Vf control. The specified voltage Vm2 determines the magnitude of the specified value Im2 used for determining whether or not to stop the pulse control. When the current is detected and when the gate drive voltages VGH and VGL are applied based on the polarity of the detected current, there is a possibility that the current polarity is reversed due to a delay in control. Therefore, the Vf control unit 1026 stops the Vf control when the current detection value falls below the specified value Im1, and the pulse control unit 1027 stops the pulse control when the current detection value falls below the specified value Im2.
　以上説明した駆動ＩＣ１０２４Ａとセンス抵抗１００７Ａにより駆動制御装置１０３８Ａが構成され、駆動ＩＣ１０２４Ｂとセンス抵抗１００７Ｂにより駆動制御装置１０３８Ｂが構成されている。 The drive control device 1038A is configured by the drive IC 1024A and the sense resistor 1007A described above, and the drive control device 1038B is configured by the drive IC 1024B and the sense resistor 1007B.
　次に、図３５から図４６を参照しながら、主としてローサイド側の駆動制御装置１０３８Ｂの作用について説明する。ハイサイド側の駆動制御装置１０３８Ａの作用も同様となる。はじめにＶｆ制御について簡単に説明する。ＲＣ－ＩＧＢＴである半導体素子１００１Ａ、１００１Ｂは、ダイオード素子１００６に電流が流れている状態でゲート駆動電圧が印加されると、第１領域１０１２にチャネルが形成されてホールの注入が抑制される。このため、図３７に示すように、順方向電流Ｉｆが流れているダイオード素子１００６の順方向電圧Ｖｆが高くなり、ダイオード素子１００６の導通損失（Ｖｆ×Ｉｆ）が増大する。 Next, the operation of the drive control device 1038B on the low side will be mainly described with reference to FIGS. The operation of the drive control device 1038A on the high side is the same. First, Vf control will be briefly described. When a gate drive voltage is applied to the semiconductor elements 1001A and 1001B that are RC-IGBTs while a current is flowing through the diode element 1006, a channel is formed in the first region 1012 and hole injection is suppressed. For this reason, as shown in FIG. 37, the forward voltage Vf of the diode element 1006 through which the forward current If flows increases, and the conduction loss (Vf × If) of the diode element 1006 increases.
　そこで、ダイオード素子１００６に電流しきい値Ｉｔ以上の電流が流れている場合には、ゲート駆動電圧を遮断することにより導通損失を低減できる。電流しきい値Ｉｔは、ＲＣ－ＩＧＢＴの場合にはほぼゼロであり、ＭＯＳトランジスタの場合には耐圧等に応じてゼロよりも大きい値になる。ＲＣ－ＩＧＢＴを駆動する場合には切替信号Ｓｋが例えばＬレベルに切り替えられ、ＭＯＳトランジスタを駆動する場合には切替信号Ｓｋが例えばＨレベルに切り替えられる。Ｖｆ制御部１０２６は、切替信号ＳｋがＨレベルのときに、しきい値電圧Ｖｔに応じた電流しきい値Ｉｔを設定してＶｆ制御を実行する。 Therefore, when a current greater than or equal to the current threshold It flows through the diode element 1006, the conduction loss can be reduced by cutting off the gate drive voltage. The current threshold It is substantially zero in the case of RC-IGBT, and is greater than zero in the case of a MOS transistor depending on the breakdown voltage or the like. When the RC-IGBT is driven, the switching signal Sk is switched to L level, for example, and when the MOS transistor is driven, the switching signal Sk is switched to H level, for example. When the switching signal Sk is at the H level, the Vf control unit 1026 sets the current threshold It according to the threshold voltage Vt and executes Vf control.
　図３８は、出力端子Ｎｔから負荷に向かって電流が流れている場合に、半導体素子１００１Ａをオフして半導体素子１００１Ｂをオンした後、半導体素子１００１Ｂをオフして再度半導体素子１００１Ａをオンしたときの波形である。上から順に、半導体素子１００１Ａの電流、ゲート駆動電圧ＶGH、ＶGL、ＰＷＭ信号ＦＨ、ゲート駆動信号ＳGL、ＰＷＭ信号ＦＬを示している。Ｖthは、半導体素子１００１Ａのしきい値電圧である。 FIG. 38 shows a case where the semiconductor element 1001A is turned off and the semiconductor element 1001B is turned on and then the semiconductor element 1001B is turned off and the semiconductor element 1001A is turned on again when a current flows from the output terminal Nt toward the load. It is a waveform. In order from the top, the current of the semiconductor element 1001A, the gate drive voltages VGH and VGL, the PWM signal FH, the gate drive signal SGL, and the PWM signal FL are shown. Vth is a threshold voltage of the semiconductor element 1001A.
　駆動ＩＣ１０２４ＢのＶｆ制御部１０２６は、ＰＷＭ信号ＦＬがＨレベルの期間（時刻ｔ２～ｔ３）、ダイオード素子１００６の検出電流がその順方向において電流しきい値Ｉｔ以上であるか否かを判定する。ここで、検出電流が電流しきい値Ｉｔ以上であると判定すると、図３８に示すようにＬレベルのゲート駆動信号ＳGLを出力する。これにより、ゲート駆動電圧ＶGLが遮断され、導通損失が低減する。 The Vf control unit 1026 of the driving IC 1024B determines whether or not the detected current of the diode element 1006 is equal to or higher than the current threshold It in the forward direction during the period when the PWM signal FL is at the H level (time t2 to t3). If it is determined that the detected current is greater than or equal to the current threshold It, an L level gate drive signal SGL is output as shown in FIG. As a result, the gate drive voltage VGL is cut off and the conduction loss is reduced.
　次に、パルス制御について説明する。パルス制御は、ＰＷＭ信号ＦＬがＨレベルの期間に半導体素子１００１Ｂのダイオード素子１００６に電流が流れている場合、ＰＷＭ信号ＦＬがＬレベルに立ち下がった後、逆回復電流が流れ始める前までに、半導体素子１００１Ｂにゲート駆動パルスを印加する制御である。ＰＷＭ信号ＦＨがＨレベルの期間に半導体素子１００１Ａのダイオード素子１００６に電流が流れている場合であって、ＰＷＭ信号ＦＨがＬレベルに立ち下がった後も同様である。これにより、ダイオード素子１００６に蓄積されるキャリア（ホール）が減少するので、逆回復電流を低減する作用が得られる。 Next, pulse control will be described. In the pulse control, when the current flows through the diode element 1006 of the semiconductor element 1001B during the period in which the PWM signal FL is at the H level, after the PWM signal FL falls to the L level and before the reverse recovery current starts to flow, This is control for applying a gate drive pulse to the semiconductor element 1001B. The same applies to the case where a current flows through the diode element 1006 of the semiconductor element 1001A during the period in which the PWM signal FH is at the H level, and after the PWM signal FH falls to the L level. As a result, carriers (holes) accumulated in the diode element 1006 are reduced, so that an effect of reducing the reverse recovery current can be obtained.
　図３８において、パルス制御部１０２７は、ＰＷＭ信号ＦＬがＬレベルに立ち下がったとき（時刻ｔ３）に半導体素子１００１Ｂのダイオード素子１００６に電流が流れている（電流検出値が規定値Ｉm2以上）と判定すると、その立ち下がり時点を起点として、第１時間Ｔ１の経過時点（時刻ｔ４）から第２時間Ｔ２の経過時点（時刻ｔ６）までゲート駆動信号ＳGLをＨレベルにする。上述したＶｆ制御により、ＰＷＭ信号ＦＬの立ち下がり時点では、ゲート駆動信号ＳGLはＬレベルになっている。 In FIG. 38, when the PWM signal FL falls to the L level (time t3), the pulse control unit 1027 has a current flowing through the diode element 1006 of the semiconductor element 1001B (the current detection value is equal to or greater than the specified value Im2). When the determination is made, the gate drive signal SGL is set to the H level from the time when the first time T1 has elapsed (time t4) to the time when the second time T2 has elapsed (time t6). By the above-described Vf control, the gate drive signal SGL is at the L level at the time of falling of the PWM signal FL.
　パルス制御部１０２７は、ＰＷＭ信号ＦＬがＬレベルに立ち下がった後も、半導体素子１００１Ｂのダイオード素子１００６に電流が流れているか否かを判定し続ける。パルス制御部１０２７は、電流検出値が規定値Ｉm2を下回ると、第１時間Ｔ１が経過した後、第２時間Ｔ２が経過する前であっても、直ちにゲート駆動信号ＳGLをＬレベルに戻す。 The pulse control unit 1027 continues to determine whether or not a current is flowing through the diode element 1006 of the semiconductor element 1001B even after the PWM signal FL falls to the L level. When the detected current value falls below the specified value Im2, the pulse controller 1027 immediately returns the gate drive signal SGL to the L level even after the first time T1 has elapsed and before the second time T2 has elapsed.
　一方、パルス制御部１０２７は、ＰＷＭ信号ＦＬがＬレベルに立ち下がったときにダイオード素子１００６に電流が流れていないと判定すると、直ちにゲート駆動信号ＳGLをＬレベルにして維持する。すなわち、ゲート駆動パルスを印加しない。 On the other hand, if the pulse control unit 1027 determines that no current flows through the diode element 1006 when the PWM signal FL falls to the L level, the pulse control unit 1027 immediately maintains the gate drive signal SGL at the L level. That is, no gate drive pulse is applied.
　図３８に示すように、上下アーム間で通電が切り替わるとき、ゲート駆動電圧ＶGHがしきい値電圧Ｖth以上になると（時刻ｔ９）、半導体素子１００１Ａのトランジスタ素子１００５に流れる電流が増加する。このトランジスタ素子１００５に流れる電流のうち、半導体素子１００１Ｂのダイオード素子１００６に流れていた電流を超える電流が逆回復電流である。図面ではハッチングで示している（時刻ｔ１０～ｔ１１）。図３９、図４０には、負荷電流（半導体素子１００１Ａ、１００１Ｂに流れる電流）が１００Ａの場合と２００Ａの場合を併せて示している。 As shown in FIG. 38, when the energization is switched between the upper and lower arms, when the gate drive voltage VGH becomes equal to or higher than the threshold voltage Vth (time t9), the current flowing through the transistor element 1005 of the semiconductor element 1001A increases. Of the current flowing through the transistor element 1005, the current exceeding the current flowing through the diode element 1006 of the semiconductor element 1001B is the reverse recovery current. In the drawing, hatching is indicated (time t10 to t11). 39 and 40 show the case where the load current (current flowing through the semiconductor elements 1001A and 1001B) is 100A and 200A.
　図３９に示すように、ゲート駆動電圧ＶGL（ゲート駆動パルス）が印加されると、半導体素子１００１Ｂのダイオード素子１００６内のキャリアが減少するのでキャリア濃度が低下する（時刻ｔ５～ｔ８）。ゲート駆動パルスの印加が終了すると、ダイオード素子１００６に再びキャリアが注入されるのでキャリア濃度が上昇する。このゲート駆動パルスの印加終了時点（時刻ｔ８）から逆回復電流が流れ始めるまで（時刻ｔ１０）の時間Ｔｃ（Ｔc1、Ｔc2）は、キャリアの再注入時間である。 As shown in FIG. 39, when a gate drive voltage VGL (gate drive pulse) is applied, carriers in the diode element 1006 of the semiconductor element 1001B decrease, so that the carrier concentration decreases (time t5 to t8). When the application of the gate drive pulse is completed, carriers are injected again into the diode element 1006, so that the carrier concentration increases. The time Tc (Tc1, Tc2) from the end of application of the gate drive pulse (time t8) until the reverse recovery current starts to flow (time t10) is the carrier reinjection time.
　再注入時間Ｔｃが短いほど、ダイオード素子１００６に蓄積されるキャリア濃度が低いので、逆回復電流が小さくなる。図４１に示すように、再注入時間Ｔｃが短いほどスイッチング損失が減少する。従って、再注入時間Ｔｃは、許容される逆回復電流の大きさに対応する注入許容時間以下となるように制御される。図４０は、再注入時間Ｔｃがゼロとなる場合を示している。実際には、アーム短絡を防止するため、再注入時間Ｔｃが短絡余裕時間Ｔｍ（＞０）以上となるように制御される。 As the reinjection time Tc is shorter, the carrier concentration accumulated in the diode element 1006 is lower, so the reverse recovery current is smaller. As shown in FIG. 41, the switching loss decreases as the reinjection time Tc is shorter. Therefore, the reinjection time Tc is controlled to be equal to or less than the allowable injection time corresponding to the allowable reverse recovery current. FIG. 40 shows a case where the reinjection time Tc becomes zero. Actually, in order to prevent an arm short circuit, the reinjection time Tc is controlled to be equal to or longer than the short circuit margin time Tm (> 0).
　図３９に示すように、負荷電流が大きいほど逆回復電流が流れ始める時点（時刻ｔ１０）が遅れる。このため、ＰＷＭ信号ＦＬの立ち下がり時点を起点としてゲート駆動電圧ＶGLの印加終了時点を固定すると（時刻ｔ８）、負荷電流が１００Ａのときには再注入時間がＴc1となり、負荷電流が２００Ａのときには再注入時間がＴc2（＞Ｔc1）となる。つまり、負荷電流が大きいほど再注入時間が長くなり、逆回復電流が大きくなってしまう。また、負荷電流が大きいほどダイオード素子１００６に蓄積されるキャリア濃度自体が高いので、キャリア濃度を十分に下げてスイッチング損失を低減するには、図４２に示すようにゲート駆動パルスの幅をある程度確保して、キャリア減少のための時間を十分に確保することが必要である。 39, as the load current increases, the time (time t10) at which reverse recovery current begins to flow is delayed. For this reason, when the application end point of the gate drive voltage VGL is fixed starting from the falling point of the PWM signal FL (time t8), the reinjection time becomes Tc1 when the load current is 100A, and reinjection when the load current is 200A. Time becomes Tc2 (> Tc1). That is, the larger the load current, the longer the reinjection time, and the reverse recovery current increases. Further, since the carrier concentration itself stored in the diode element 1006 is higher as the load current is larger, in order to sufficiently reduce the carrier concentration and reduce the switching loss, the gate drive pulse width is ensured to some extent as shown in FIG. Therefore, it is necessary to secure a sufficient time for carrier reduction.
　こうした理由により、パルス制御部１０２７は、負荷電流に応じてゲート駆動電圧ＶGLの印加タイミングを制御する。パルス制御部１０２７は、ＰＷＭ信号ＦＬの立ち下がり時点を起点として、ゲート駆動信号ＳGLをＨレベルにする第１時間Ｔ１とＬレベルに戻す第２時間Ｔ２との時間幅Ｔｗを、ＰＷＭ信号ＦＬがＨレベルの期間にダイオード素子１００６に流れていた電流の大きさに応じた値に設定する。具体的には、ＰＷＭ信号ＦＬがＨレベルの期間にダイオード素子１００６に流れていた電流が大きいほど、長い時間幅を設定する。 For these reasons, the pulse controller 1027 controls the application timing of the gate drive voltage VGL according to the load current. The pulse control unit 1027 starts from the falling point of the PWM signal FL, and sets the time width Tw between the first time T1 when the gate drive signal SGL is set to the H level and the second time T2 when the gate drive signal SGL is returned to the L level. The value is set according to the magnitude of the current flowing in the diode element 1006 during the H level period. Specifically, the longer time width is set as the current flowing through the diode element 1006 during the period when the PWM signal FL is at the H level is larger.
　第１時間Ｔ１と第２時間Ｔ２は、ダイオード素子６に流れる電流を種々に変えながら、ＰＷＭ信号ＦＬの立ち下がり時点を起点として、ゲート駆動信号ＳGLの印加タイミング、実際にゲート駆動電圧ＶGLが印加されるタイミング、および逆回復電流が流れ始めるタイミングを予め測定して設定されている。この第１時間Ｔ１と第２時間Ｔ２は、電流と対応付けて後述するメモリ１０３９等（アナログ回路等で設計してもよい）に記憶されている。第１時間Ｔ１と第２時間Ｔ２に替えて、第１時間Ｔ１とパルス幅Ｔｗ（＝Ｔ２－Ｔ１）を記憶してもよい。 In the first time T1 and the second time T2, the application timing of the gate drive signal SGL and the actual gate drive voltage VGL are applied starting from the falling point of the PWM signal FL while changing the current flowing through the diode element 6 in various ways. The timing at which the reverse recovery current starts to flow and the timing at which the reverse recovery current starts to flow are set in advance. The first time T1 and the second time T2 are stored in a memory 1039 or the like (which may be designed with an analog circuit or the like) described later in association with the current. Instead of the first time T1 and the second time T2, the first time T1 and the pulse width Tw (= T2-T1) may be stored.
　図３５は、駆動ＩＣ１０２４Ｂについてのパルス制御部１０２７のブロック構成図である。メモリ１０３９は、電流検出信号を入力し、パルス制御に必要な第１時間Ｔ１と第２時間Ｔ２（または第１時間Ｔ１とパルス幅Ｔｗ）を出力する。パルス開始決定部１０４０は、図４３に示すように、ＰＷＭ信号ＦＬと第１時間Ｔ１から、ゲート駆動信号ＳGLの立ち上がりのタイミング信号を生成する。パルス幅決定部１０４１は、ＰＷＭ信号ＦＬと第２時間Ｔ２（またはパルス幅Ｔｗ）から、ゲート駆動信号ＳGLの立ち下がりタイミング信号を生成する。パルス生成部１０４２は、これらのタイミング信号に基づいてゲート駆動信号ＳGLを生成し、ドライブ回路１０２８に出力する。 FIG. 35 is a block diagram of the pulse control unit 1027 for the drive IC 1024B. The memory 1039 receives the current detection signal and outputs the first time T1 and the second time T2 (or the first time T1 and the pulse width Tw) necessary for the pulse control. As shown in FIG. 43, the pulse start determining unit 1040 generates a rising timing signal of the gate drive signal SGL from the PWM signal FL and the first time T1. The pulse width determination unit 1041 generates a falling timing signal of the gate drive signal SGL from the PWM signal FL and the second time T2 (or pulse width Tw). The pulse generation unit 1042 generates a gate drive signal SGL based on these timing signals and outputs it to the drive circuit 1028.
　パルス開始決定部１０４０は、例えば図３６に示す構成を備えている。ＰＷＭ信号ＦＬがＨレベルの期間は、バッファ１０４３を介したゲート電圧によりＭＯＳトランジスタ１０４４がオンするので、コンデンサ１０４５の電圧はゼロとなる。ＰＷＭ信号ＦＬがＬレベルに立ち下がると、ＭＯＳトランジスタ１０４４がオフし、定電流回路１０４６によりコンデンサ１０４５が充電される。コンパレータ１０４７は、コンデンサ１０４５の電圧と、第１時間Ｔ１に応じた基準電圧とを比較してタイミング信号を出力する。パルス幅決定部１０４１も、同様の構成を備えている。 The pulse start determination unit 1040 has a configuration shown in FIG. 36, for example. During the period when the PWM signal FL is at the H level, the MOS transistor 1044 is turned on by the gate voltage via the buffer 1043, so the voltage of the capacitor 1045 is zero. When the PWM signal FL falls to the L level, the MOS transistor 1044 is turned off, and the capacitor 1045 is charged by the constant current circuit 1046. The comparator 1047 compares the voltage of the capacitor 1045 with a reference voltage corresponding to the first time T1, and outputs a timing signal. The pulse width determination unit 1041 has the same configuration.
　図４４は、ＰＷＭ信号ＦＬがＨレベルの期間にダイオード素子１００６に流れていた電流に応じて、メモリ１０３９から出力される第１時間Ｔ１すなわち基準電圧が変化し、それによりゲート駆動信号ＳGLの立ち上がりのタイミング信号が変化する様子を示している。なお、メモリ１０３９に第１時間Ｔ１を記憶させ、読み出した値を素子電流に応じて変化させてもよい。 In FIG. 44, the first time T1, that is, the reference voltage output from the memory 1039 changes according to the current flowing in the diode element 1006 during the period in which the PWM signal FL is at the H level, and thereby the rise of the gate drive signal SGL. This shows how the timing signal changes. The first time T1 may be stored in the memory 1039, and the read value may be changed according to the element current.
　ＰＷＭ信号ＦＬがＬレベルの期間にダイオード素子１００６に電流が流れている場合と、トランジスタ素子１００５に電流が流れている場合とでは、ゲート駆動パルスを与えたときのゲート駆動電圧ＶGLの波形が異なる。そこで、以下の述べる（１）から（３）に示す事項を考慮した上で、ゲート駆動電圧ＶGLがドライブ回路１０２８のゲート駆動能力に従って単調に増加または単調に減少するものとして、第１時間Ｔ１と第２時間Ｔ２（または第１時間Ｔ１とパルス幅Ｔｗ）が設定されている。
（１）デッドタイムＴｄ
　ＰＷＭ信号ＦＨ、ＦＬのデッドタイムＴｄは一定時間である。このため、ＰＷＭ信号ＦＬがＬレベルなってからＰＷＭ信号ＦＨがＨレベルになるまでの時間、およびＰＷＭ信号ＦＨがＬレベルなってからＰＷＭ信号ＦＬがＨレベルになるまでの時間が正確に保証されている。このデッドタイムＴｄを利用することにより、アーム短絡を防止しつつゲート駆動パルスを印加することができる。
（２）ミラー期間
　トランジスタ素子１００５に電流が流れる場合には、ゲート駆動電圧ＶGLの印加時および遮断時にコレクタ・エミッタ間電圧の変化が生じるので、ミラー期間が生じる。このミラー期間は長く、例えば条件によっては数μｓｅｃの時間となる場合がある。これに対し、ダイオード素子１００６に電流が流れる場合には、コレクタ・エミッタ間電圧は変化しないので、ミラー期間は生じない。 The waveform of the gate drive voltage VGL when a gate drive pulse is applied differs between when the current flows through the diode element 1006 and when the current flows through the transistor element 1005 while the PWM signal FL is at the L level. . Therefore, in consideration of the following items (1) to (3), it is assumed that the gate drive voltage VGL monotonously increases or monotonously decreases according to the gate drive capability of the drive circuit 1028. The second time T2 (or the first time T1 and the pulse width Tw) is set.
(1) Dead time Td
The dead time Td of the PWM signals FH and FL is a fixed time. Therefore, the time from when the PWM signal FL becomes L level until the PWM signal FH becomes H level and the time from when the PWM signal FH becomes L level until the PWM signal FL becomes H level are accurately guaranteed. ing. By utilizing this dead time Td, a gate drive pulse can be applied while preventing an arm short circuit.
(2) Mirror period When a current flows through the transistor element 1005, the collector-emitter voltage changes when the gate drive voltage VGL is applied and when the gate drive voltage VGL is applied. This mirror period is long, and may be several μsec depending on conditions, for example. On the other hand, when a current flows through the diode element 1006, the collector-emitter voltage does not change, so that no mirror period occurs.
　図４５は、ミラー期間が存在するものとしてゲート駆動パルスのタイミングを設定する場合と、ミラー期間が存在しないものとしてゲート駆動パルスのタイミングを設定する場合の再注入時間を示している。前者の場合、ミラー期間を想定して再注入時間Ｔｃを設定すると、実際にはミラー期間が生じないため、実際の再注入時間はＴｃよりも長くなる。これに対し、当初からミラー期間が生じないものとして設定すれば、目標通りの再注入時間Ｔｃを設定することができる。従って、ミラー期間を除いた時間を用いてゲート駆動パルスのタイミングを設定する。これにより、ゲート駆動パルスのパルス幅Ｔｗをより長く確保できる効果もある。
（３）ドライブ回路１０２８の駆動能力
　ゲート駆動パルスを出力する場合、ドライブ回路１０２８は、ゲート駆動電圧ＶGLの立ち上げ時および立ち下げ時に、切替スイッチ１０３０、１０３４（図３４参照）をＢ側に切り替えて、高いゲート駆動能力（ここでは最大のゲート駆動能力）でゲート駆動電圧ＶGLを出力する。ゲート駆動パルスの印加期間では、ダイオード素子１００６に電流が流れ続けているので、急峻な電流変化によるサージが発生しないからである。 FIG. 45 shows the reinjection time when the gate drive pulse timing is set assuming that the mirror period exists, and when the gate drive pulse timing is set assuming that the mirror period does not exist. In the former case, when the reinjection time Tc is set assuming the mirror period, the actual reinjection time becomes longer than Tc because the mirror period does not actually occur. On the other hand, if it is set from the beginning that the mirror period does not occur, the target reinjection time Tc can be set. Therefore, the timing of the gate drive pulse is set using the time excluding the mirror period. This also has an effect of ensuring a longer pulse width Tw of the gate drive pulse.
(3) Drive capability of drive circuit 1028 When a gate drive pulse is output, the drive circuit 1028 switches the changeover switches 1030 and 1034 (see FIG. 34) to the B side when the gate drive voltage VGL rises and falls. Thus, the gate drive voltage VGL is output with a high gate drive capability (here, the maximum gate drive capability). This is because, during the application period of the gate drive pulse, current continues to flow through the diode element 1006, so that a surge due to a steep current change does not occur.
　また、ドライブ回路１０２８は、ゲート駆動電圧ＶGLの立ち上げ時に、一定のゲート駆動能力を維持してゲート駆動電圧ＶGLを出力する。トランジスタ素子１００５に電流が流れる場合には、ゲート駆動電圧ＶGLの増加過程でゲート駆動電圧ＶGLを一時的に中間電圧Ｖｍ（例えば１２Ｖ）に留めることで、他方の半導体素子１００１Ａが短絡故障している時の短絡電流を低減する方法が用いられている。しかし、半導体素子１００１Ｂのダイオード素子１００６に順方向電流が流れているときには、半導体素子１００１Ａ、１００１Ｂを介した経路で短絡する可能性がない。このため、中間電圧Ｖｍを用いた２段階駆動は不要となる。 Further, the drive circuit 1028 outputs a gate drive voltage VGL while maintaining a certain gate drive capability when the gate drive voltage VGL is raised. When a current flows through the transistor element 1005, the other semiconductor element 1001A is short-circuited by temporarily holding the gate drive voltage VGL at the intermediate voltage Vm (for example, 12V) in the process of increasing the gate drive voltage VGL. A method for reducing the short-circuit current is used. However, when a forward current flows through the diode element 1006 of the semiconductor element 1001B, there is no possibility of short-circuiting along the path through the semiconductor elements 1001A and 1001B. This eliminates the need for two-step driving using the intermediate voltage Vm.
　図４６は、ドライブ回路１０２８が通常の駆動能力で且つ２段階駆動によりゲート駆動電圧ＶGLを出力する場合と、ドライブ回路１０２８が高い駆動能力を維持してゲート駆動電圧ＶGLを出力する場合の波形を対比して示している。ドライブ回路１０２８の駆動能力、半導体素子１００１Ｂのゲート容量などにはばらつきがあるため、ゲート駆動電圧ＶGLの立ち上がり時間および立ち下がり時間にもばらつきが生じる。このばらつきは、駆動能力が低いほど大きく現れる。 46 shows waveforms when the drive circuit 1028 outputs the gate drive voltage VGL with the normal drive capability and the two-stage drive, and when the drive circuit 1028 maintains the high drive capability and outputs the gate drive voltage VGL. In contrast. Since there are variations in the drive capability of the drive circuit 1028, the gate capacitance of the semiconductor element 1001B, etc., variations also occur in the rise time and fall time of the gate drive voltage VGL. This variation becomes more significant as the driving capability is lower.
　このため、再注入時間Ｔｃが常に短絡余裕時間Ｔｍ以上となるように設定した場合、ドライブ回路１０２８が高い駆動能力を維持してゲート駆動電圧ＶGLを出力することにより、再注入時間Ｔｃと短絡余裕時間Ｔｍとの乖離を小さくすることができる。すなわち、再注入時間Ｔｃを正確に制御することができる。また、ゲート駆動パルスのパルス幅Ｔｗのばらつきが低減するとともに、より長いパルス幅Ｔｗを確保できる。 For this reason, when the reinjection time Tc is always set to be equal to or longer than the short circuit margin time Tm, the drive circuit 1028 maintains a high driving capability and outputs the gate drive voltage VGL. Deviation from time Tm can be reduced. That is, the reinjection time Tc can be accurately controlled. Further, variation in the pulse width Tw of the gate drive pulse is reduced, and a longer pulse width Tw can be secured.
　以上説明したように、本実施形態の駆動制御装置１０３８Ａ、１０３８Ｂは、上下アーム間で通電が切り替わるとき、それぞれＰＷＭ信号ＦＨ、ＦＬがＨレベルの期間に半導体素子１００１Ａ、１００１Ｂにダイオード素子１００６の順方向の向きに電流が流れていると判定すると、ゲート駆動パルスの印加を指令するゲート駆動信号ＳGH、ＳGLを出力する。このパルス制御により、ダイオード素子１００６に蓄積されるホールが減少して逆回復電流が低減するので、スイッチング損失を低減できる。 As described above, in the drive control devices 1038A and 1038B according to the present embodiment, when the energization is switched between the upper and lower arms, the semiconductor elements 1001A and 1001B are in the order of the diode elements 1006 during the period when the PWM signals FH and FL are at the H level, respectively. If it is determined that the current is flowing in the direction, the gate drive signals SGH and SGL for instructing the application of the gate drive pulse are output. By this pulse control, holes accumulated in the diode element 1006 are reduced and the reverse recovery current is reduced, so that switching loss can be reduced.
　駆動ＩＣ１０２４Ａ、１０２４Ｂのパルス制御部１０２７は、ＰＷＭ信号ＦＨ、ＦＬの立ち下がり時点を起点として、第１時間Ｔ１の経過時点から第２時間Ｔ２の経過時点までゲート駆動信号ＳGH、ＳGLをＨレベルにする。ＰＷＭ信号ＦＨ、ＦＬの立ち下がり時点はデッドタイムＴｄの起点でもあるので、一定の時間を持つデッドタイムＴｄを有効に利用して、アーム短絡を防止しながらゲート駆動パルスを印加することができる。 The pulse control unit 1027 of the drive ICs 1024A and 1024B sets the gate drive signals SGH and SGL to the H level from the time when the first time T1 elapses to the time when the second time T2 elapses, starting from the falling time of the PWM signals FH and FL. To do. Since the falling point of the PWM signals FH and FL is also the starting point of the dead time Td, the gate driving pulse can be applied while effectively preventing the arm short circuit by effectively using the dead time Td having a certain time.
　第１時間Ｔ１と第２時間Ｔ２（または第１時間Ｔ１とパルス幅Ｔｗ）は、デッドタイムＴｄ、素子電流に対応させて予め測定されたゲート駆動電圧ＶGH、ＶGLの遅延やばらつきおよび逆回復電流が流れ始めるまでの時間に基づいて設定され、パルス制御部２７のメモリ１０３９に記憶されている。 The first time T1 and the second time T2 (or the first time T1 and the pulse width Tw) are the dead time Td, the delay and variation of the gate drive voltages VGH and VGL measured in advance corresponding to the element current, and the reverse recovery current. Is set based on the time until the flow starts, and is stored in the memory 1039 of the pulse control unit 27.
　上下アーム間で通電が切り替わるとき、負荷電流が大きいほど逆回復電流が流れるタイミングが遅くなる。そこで、第１時間Ｔ１と第２時間Ｔ２との時間幅（パルス幅Ｔｗ）は、ＰＷＭ信号ＦＨ、ＦＬがＨレベルの期間にダイオード素子１００６に流れていた電流が大きいほど長く設定されている。これにより、負荷電流の大きさにかかわらず、ダイオード素子１００６に対するキャリアの再注入時間Ｔｃ（ゲート駆動パルスの印加終了から逆回復電流が流れ始めるまでの時間）の増大を抑えることができ、スイッチング損失を低減することができる。 ¡When energization is switched between the upper and lower arms, the greater the load current, the slower the reverse recovery current flows. Therefore, the time width (pulse width Tw) between the first time T1 and the second time T2 is set longer as the current flowing through the diode element 1006 during the period in which the PWM signals FH and FL are at the H level is larger. Thereby, regardless of the magnitude of the load current, it is possible to suppress an increase in the carrier reinjection time Tc (the time from the end of application of the gate drive pulse until the reverse recovery current starts flowing) to the diode element 1006, and the switching loss. Can be reduced.
　第１時間Ｔ１と第２時間Ｔ２は、再注入時間Ｔｃがゼロより大きくなるように設定されている。これにより、ハーフブリッジ回路４に短絡電流が流れることを防止できる。また、パルス幅Ｔｗは、所定の注入許容時間以下となるように設定されている。これにより、逆回復電流を注入許容時間に応じた大きさ以下に制限することができ、スイッチング損失を低減できる。 The first time T1 and the second time T2 are set so that the reinjection time Tc is greater than zero. Thereby, it is possible to prevent a short-circuit current from flowing through the half bridge circuit 4. Further, the pulse width Tw is set to be equal to or shorter than a predetermined allowable injection time. As a result, the reverse recovery current can be limited to a value corresponding to the allowable injection time or less, and the switching loss can be reduced.
　さらに、第１時間Ｔ１と第２時間Ｔ２は、ゲート駆動パルスの印加時におけるゲート駆動電圧の波形およびドライブ回路１０２８の駆動態様を考慮して設定されている。すなわち、ダイオード素子１００６に電流が流れているときにゲート駆動パルスを与えると、ミラー期間が生じない。そこで、ミラー期間が生じないものとして、第１時間Ｔ１と第２時間Ｔ２が設定される。 Furthermore, the first time T1 and the second time T2 are set in consideration of the waveform of the gate drive voltage and the drive mode of the drive circuit 1028 when the gate drive pulse is applied. That is, if a gate drive pulse is applied when a current flows through the diode element 1006, the mirror period does not occur. Therefore, the first time T1 and the second time T2 are set as those in which the mirror period does not occur.
　また、ゲート駆動パルスの印加期間では、ダイオード素子１００６に電流が流れ続けているので、急峻な電流変化、電圧変化によるサージは発生しない。このため、ドライブ回路１０２８は、自ら有する最大のゲート駆動能力に従ってゲート駆動電圧ＶGH、ＶGLを出力する。さらに、ダイオード素子１００６に電流が流れているのであれば、短絡の可能性がない。このため、ドライブ回路１０２８は、ゲート駆動電圧ＶGL、ＶGHの立ち上げ時に、一定のゲート駆動能力を維持して、ゲート駆動電圧ＶGL、ＶGHを単調に増加させる。こうした駆動態様を用いた場合に合わせて、第１時間Ｔ１と第２時間Ｔ２が設定される。 In addition, during the gate drive pulse application period, current continues to flow through the diode element 1006, so that a surge due to a sudden current change or voltage change does not occur. Therefore, the drive circuit 1028 outputs the gate drive voltages VGH and VGL according to the maximum gate drive capability that the drive circuit 1028 has. Furthermore, if a current flows through the diode element 1006, there is no possibility of a short circuit. Therefore, the drive circuit 1028 monotonously increases the gate drive voltages VGL and VGH while maintaining a constant gate drive capability when the gate drive voltages VGL and VGH are raised. The first time T1 and the second time T2 are set in accordance with such a driving mode.
　こうしたゲート駆動パルスに特有の駆動態様を用いたときのゲート駆動電圧は、トランジスタ素子１００５を通断電させる駆動態様を用いたときのゲート駆動電圧に比べ、遅延やばらつきが小さくなる。そのため、駆動ＩＣ１０２４Ａ、１０２４Ｂは、ゲート駆動パルスの印加タイミングの精度を高めることができ、再注入時間Ｔｃを正確に制御可能となる。その結果、アーム短絡を防止しつつ再注入時間を短く制御することが可能となり、スイッチング損失を一層低減できる。また、ゲート駆動パルスのパルス幅Ｔｗをより広く確保できる。さらに、パルス制御部１０２７は、ＰＷＭ信号ＦＨ、ＦＬの立ち下がり時点を起点としてゲート駆動信号を印加するので、別のタイミング信号が不要となり、従来から使用している駆動制御装置からの置き替えが容易になる。 The gate driving voltage when using a driving mode peculiar to such a gate driving pulse has a smaller delay and variation than the gate driving voltage when using a driving mode that cuts off the transistor element 1005. Therefore, the drive ICs 1024A and 1024B can increase the accuracy of the application timing of the gate drive pulse, and can accurately control the reinjection time Tc. As a result, the reinjection time can be controlled to be short while preventing an arm short circuit, and the switching loss can be further reduced. Further, a wider pulse width Tw of the gate drive pulse can be secured. Further, since the pulse control unit 1027 applies the gate drive signal starting from the falling point of the PWM signals FH and FL, no separate timing signal is required, and the conventional drive control device can be replaced. It becomes easy.
　パルス制御部１０２７は、パルス制御に基づきゲート駆動パルスを印加している期間（時刻ｔ４～ｔ６）であっても、ダイオード素子１００６に電流が流れなくなる（電流検出値が規定値Ｉm2未満となる）可能性があるまたは電流が流れていないと判定すると、直ちにゲート駆動パルスの印加を停止する。これにより、負荷電流が急変した場合でもアーム短絡を確実に防止できる。さらに、負荷電流の急変に備えて規定値Ｉm2を高めに設定する必要がなくなるので、パルス制御を実行する電流範囲を広く確保でき、スイッチング損失を一層低減できる。 The pulse control unit 1027 stops the current from flowing through the diode element 1006 even during the period (time t4 to t6) in which the gate drive pulse is applied based on the pulse control (the detected current value becomes less than the specified value Im2). If it is determined that there is a possibility or no current is flowing, the application of the gate drive pulse is immediately stopped. Thereby, even when the load current changes suddenly, an arm short circuit can be reliably prevented. Furthermore, since it is not necessary to set the specified value Im2 higher in preparation for a sudden change in the load current, a wide current range for performing the pulse control can be secured, and the switching loss can be further reduced.
　また、第１７の実施形態において、第２の実施形態に記載のように半導体素子１Ａ、１ＢにＭＯＳトランジスタなどを使用し同期整流を行った方が導通損失を低減できる場合は、半導体素子にダイオード構造の順方向の向きに電流が流れていると判定すると、上記第１時間Ｔ１に代わり、図７に記載のようにゲート駆動制御信号ＳＧＬ，ＳＧＨの立ち上がり（ｔ２）と上記第２時間Ｔ２に応じて高い駆動能力でゲート駆動電圧ＶGH、ＶGLを出力するようにするとよい。 Further, in the seventeenth embodiment, if the conduction loss can be reduced by using a MOS transistor or the like for the semiconductor elements 1A and 1B as described in the second embodiment and performing the synchronous rectification, a diode is added to the semiconductor element. If it is determined that the current is flowing in the forward direction of the structure, instead of the first time T1, the rising edge (t2) of the gate drive control signals SGL and SGH and the second time T2 as shown in FIG. Accordingly, it is preferable to output the gate drive voltages VGH and VGL with a high drive capability.
　また、第１７の実施形態では第１の実施形態に相当する回路構成の駆動制御システムについて説明したが、図３３に示す回路構成（第１の実施形態に相当）に代えて、第３、４、５、６、７、８、９の実施形態に記載の駆動制御システムにも適用できる。この場合においても図８、９、１０、１１、１２、１３、１４に記載の半導体素子１Ａ、１ＢにＭＯＳトランジスタなどを使用し同期整流を行った方が導通損失を低減できる場合は、半導体素子にダイオード構造の順方向の向きに電流が流れていると判定すると、上記第１時間Ｔ１に代わり、図７に記載のようにゲート駆動制御信号ＳＧＬ，ＳＧＨの立ち上がり（ｔ２）と上記第２時間Ｔ２に応じて高い駆動能力でゲート駆動電圧ＶGH、ＶGLを出力するとよい。 In the seventeenth embodiment, the drive control system having a circuit configuration corresponding to the first embodiment has been described. However, instead of the circuit configuration (corresponding to the first embodiment) shown in FIG. The present invention can also be applied to the drive control system described in the fifth, sixth, seventh, eighth, and ninth embodiments. Also in this case, if the semiconductor element 1A, 1B described in FIGS. 8, 9, 10, 11, 12, 13, 14 can be reduced in conduction loss by performing synchronous rectification using a MOS transistor or the like, the semiconductor element If it is determined that the current flows in the forward direction of the diode structure, the rise (t2) of the gate drive control signals SGL and SGH and the second time as shown in FIG. 7 instead of the first time T1. It is preferable to output the gate drive voltages VGH and VGL with high drive capability according to T2.
　また、第１７の実施形態では第１の実施形態に相当する回路構成の駆動制御システムについて説明したが、図３３に示す回路構成（第１の実施形態に相当）に代えて、第１１、１２、１３、１４、１５の実施形態に記載の駆動制御システムにも適用できる。この場合において図１７、２０、２１、２２、２３に記載の半導体素子１０１Ａ、１０１ＢにＭＯＳトランジスタなどを使用し同期整流を行った方が導通損失を低減できる場合は、半導体素子にダイオード構造の順方向の向きに電流が流れていると判定すると、上記第１時間Ｔ１に代わり、図１９に記載のようにゲート駆動制御信号ＳＧＬ，ＳＧＨの立ち上がり（ｔ２）と上記第２時間Ｔ２に応じて高い駆動能力でゲート駆動電圧ＶGH、ＶGLを出力するとよい。
また、第１７の実施形態では第１の実施形態に相当する回路構成の駆動制御システムについて説明したが、図３３に示す回路構成（第１の実施形態に相当）に代えて、上述した図７、１９、２７、３２記載の制御を実施する第１～第１６の実施形態の変形例に記載の駆動制御システムにも適用できる。この場合において半導体素子１Ａ、１Ｂもしくは１０１Ａ、１０１ＢにＭＯＳトランジスタなどを使用し同期整流を行った方が導通損失を低減できる場合は、半導体素子にダイオード構造の順方向の向きに電流が流れていると判定すると、上記第１時間Ｔ１に代わり、図２７に記載のようにゲート駆動制御信号ＳＧＬ，ＳＧＨの立ち上がり（ｔ２、ｔ１ｃ、ｔ１ｂ）と上記第２時間Ｔ２に応じて高い駆動能力でゲート駆動電圧ＶGH、ＶGLを出力するとよい。 In the seventeenth embodiment, the drive control system having a circuit configuration corresponding to the first embodiment has been described. However, instead of the circuit configuration (corresponding to the first embodiment) shown in FIG. , 13, 14, and 15 can also be applied to the drive control system. In this case, when conducting rectification using a MOS transistor or the like for the semiconductor elements 101A and 101B shown in FIGS. 17, 20, 21, 22, and 23 can reduce conduction loss, the order of the diode structure in the semiconductor element is reduced. If it is determined that a current is flowing in the direction of the direction, instead of the first time T1, as shown in FIG. 19, it is high according to the rise (t2) of the gate drive control signals SGL and SGH and the second time T2. The gate drive voltages VGH and VGL may be output with the drive capability.
In the seventeenth embodiment, the drive control system having the circuit configuration corresponding to the first embodiment has been described. However, instead of the circuit configuration shown in FIG. 33 (corresponding to the first embodiment), FIG. , 19, 27, 32 can be applied to the drive control system described in the modified examples of the first to sixteenth embodiments. In this case, when conducting rectification can be reduced by using a MOS transistor or the like for the semiconductor elements 1A, 1B or 101A, 101B, current flows in the semiconductor element in the forward direction of the diode structure. , Instead of the first time T1, as shown in FIG. 27, gate drive is performed with high driving capability in accordance with the rise (t2, t1c, t1b) of the gate drive control signals SGL, SGH and the second time T2. The voltages VGH and VGL should be output.
　以上、本開示の好適な実施形態について説明したが、本開示は上述した実施形態に限定されるものではなく、開示の要旨を逸脱しない範囲内で種々の変形、拡張を行うことができる。 The preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above-described embodiments, and various modifications and extensions can be made without departing from the gist of the disclosure.
　ＲＣ－ＩＧＢＴは、トレンチゲート型に限らずプレーナゲート型などであってもよい。半導体素子１００１Ａ、１００１Ｂは、コントロール用のゲートを有し寄生ダイオードが形成された素子、例えばＭＯＳトランジスタ、ＭＯＳゲートを備えたダイオードであってもよい。ＭＯＳトランジスタは、トレンチゲート型に限らずプレーナゲート型などであってもよい。ＭＯＳトランジスタは、ＳＪ（Super Junction）構造であってもよい。 RC-IGBT is not limited to a trench gate type, but may be a planar gate type. The semiconductor elements 1001A and 1001B may be elements having a control gate and formed with a parasitic diode, for example, a MOS transistor and a diode having a MOS gate. The MOS transistor is not limited to a trench gate type but may be a planar gate type. The MOS transistor may have an SJ (Super Junction) structure.
　上記実施形態では、電流検出手段として、半導体素子１００１Ａ、１００１Ｂにセンス素子を形成した上でセンス抵抗１００７Ａ、１００７Ｂを備えた。これに替えて、図４７に示すように、センス素子を除いた半導体素子１００１Ａ、１００１Ｂと直列にセンス抵抗１００７Ａ、１００７Ｂを設けてもよい。センス抵抗１００７Ａ、１００７Ｂとメイン素子とが直接接続されているので、高速答が可能となる。また、図４８に示すように、半導体素子１００１Ａ、１００１Ｂに対しホールセンサ１０５９Ａ、１０５９Ｂを設けてもよい。ホールセンサ１０５９Ａ、１０５９Ｂに替えて、出力端子Ｎｔから負荷に至る出力線にホールセンサを設けてもよい。何れの構成でも、電流を高精度に検出できる。ホールセンサに替えてＧＭＲ（Giant Magneto Resistance）センサなどの絶縁型電流センサを用いてもよい。 In the above embodiment, the sense resistors 1007A and 1007B are provided as the current detection means after the sense elements are formed in the semiconductor elements 1001A and 1001B. Instead, as shown in FIG. 47, sense resistors 1007A and 1007B may be provided in series with the semiconductor elements 1001A and 1001B excluding the sense elements. Since the sense resistors 1007A and 1007B and the main element are directly connected, a high-speed answer is possible. As shown in FIG. 48, Hall sensors 1059A and 1059B may be provided for the semiconductor elements 1001A and 1001B. Instead of the Hall sensors 1059A and 1059B, Hall sensors may be provided on the output lines from the output terminal Nt to the load. In any configuration, the current can be detected with high accuracy. An insulated current sensor such as a GMR (Giant Magneto Resistance) sensor may be used instead of the Hall sensor.
　本開示は、下記の態様を含む。 This disclosure includes the following aspects.
　本開示の第一の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、前記２つの半導体素子のうち少なくとも一方に流れる電流に応じた電流検出信号を出力する電流検出手段と、前記電流検出信号に基づいて、前記半導体素子に対するオン指令信号が入力されている期間に前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、その後のオフ指令信号の入力時点を起点として、第１時間の経過時点から第２時間の経過時点まで、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する第１の制御手段とを備える。二つの半導体素子は、ハーフブリッジ回路を構成する。第１時間と第２時間は、二つの半導体素子の間でアーム短絡が生じないように予め設定されている。 In the first aspect of the present disclosure, each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate. The drive control device for two semiconductor elements, wherein the electrode and the current-carrying electrode of the diode structure are common, current detection means for outputting a current detection signal corresponding to a current flowing in at least one of the two semiconductor elements; On the basis of the current detection signal, when it is determined that a current flows in the forward direction of the diode structure in the semiconductor element during a period in which an ON command signal for the semiconductor element is input, a subsequent OFF command signal Starting from the input time point of the first to the second time point, the gate commanding the application of the gate drive voltage And a first control means for outputting a motion signal. The two semiconductor elements constitute a half bridge circuit. The first time and the second time are set in advance so as not to cause an arm short circuit between the two semiconductor elements.
　駆動対象の半導体素子は、トランジスタ構造とダイオード構造に対し共通のゲート構造を備えている。上下アーム間で通電が切り替わる時、例えば一方の半導体素子のダイオード構造に電流が流れている状態で、第１の制御手段が当該一方の半導体素子にゲート駆動電圧を印加すると、当該ダイオード構造に蓄積されるホールが減少し、逆回復電流を低減する作用が生じる。 The semiconductor element to be driven has a common gate structure for the transistor structure and the diode structure. When energization is switched between the upper and lower arms, for example, when the first control unit applies a gate drive voltage to the one semiconductor element in a state where a current flows through the diode structure of one semiconductor element, the current is accumulated in the diode structure. The number of holes to be reduced is reduced, and the effect of reducing the reverse recovery current occurs.
　しかし、オフ指令信号が入力された半導体素子について、ダイオード構造の順方向の向きに素子電流（例えばダイオード電流）が流れている場合と、逆方向の向きに素子電流（トランジスタ電流）が流れている場合とでは、ゲート駆動パルスを与えたときのゲート駆動電圧の波形が異なる。例えば、前者の場合には半導体素子間の電圧・電流の急峻な変化やミラー期間が生じないので、ゲート駆動電圧の立ち上がり時間および立ち下がり時間は短くなる（或いは短くできる）。これにより、ゲート駆動パルスの遅延やばらつきが小さくなる。一方、後者の場合には半導体素子間の電圧・電流の急峻な変化やミラー期間が生じるので、ゲート駆動パルスの遅延やばらつきが大きくなる。駆動制御装置は、半導体素子にダイオード構造の順方向の向きに電流が流れている場合に限りゲート駆動パルスを印加するので、前者の場合の小さい遅延やばらつきに基づいた制御が可能となり、印加タイミングの精度を高めることができる。 However, for a semiconductor element to which an off command signal is input, a device current (transistor current) flows in the reverse direction when a device current (for example, a diode current) flows in the forward direction of the diode structure. In some cases, the waveform of the gate drive voltage when a gate drive pulse is applied is different. For example, in the former case, there is no steep change in the voltage / current between the semiconductor elements or a mirror period, so that the rise time and fall time of the gate drive voltage are shortened (or can be shortened). This reduces the delay and variation of the gate drive pulse. On the other hand, in the latter case, a sharp change in the voltage and current between the semiconductor elements and a mirror period occur, so that the delay and variation of the gate drive pulse increase. The drive control device applies a gate drive pulse only when a current flows through the semiconductor element in the forward direction of the diode structure, so control based on small delays and variations in the former case is possible, and the application timing Can improve the accuracy.
　第１の制御手段は、相補的に変化する高電位側（ハイサイド）と低電位側（ローサイド）の指令信号（例えばＰＷＭ信号）のうち少なくとも一方の指令信号を入力し、少なくとも一方のサイドの半導体素子にゲート駆動電圧を印加する。この指令信号は、切り替え時にデッドタイム（アーム短絡防止のため両サイドがオフしている期間）を有している。デッドタイムは一定時間であるため、一方サイドのオフ指令信号の入力から他方サイドのオン指令信号の入力までの時間が正確に保証されている。 The first control means inputs at least one of the command signals (for example, PWM signals) on the high potential side (high side) and the low potential side (low side) that change in a complementary manner. A gate drive voltage is applied to the semiconductor element. This command signal has a dead time (period in which both sides are off to prevent arm short circuit) at the time of switching. Since the dead time is a fixed time, the time from the input of the off command signal on one side to the input of the on command signal on the other side is accurately guaranteed.
　本手段によれば、上述した遅延やばらつきを予め測定しデッドタイムを把握した上で、オフ指令信号の入力時点を起点として、ゲート駆動電圧を所望のタイミングで印加するために必要なゲート駆動信号のタイミング、すなわち第１時間と第２時間を正確に設定することが可能となる。 According to this means, after measuring the delay and variation described above in advance and grasping the dead time, the gate drive signal necessary for applying the gate drive voltage at a desired timing starting from the input time point of the off command signal. That is, the first time and the second time can be accurately set.
　これにより、一方の半導体素子に対するゲート駆動パルスの印加終了時点から逆回復電流が流れ始めるまでの時間、例えばゲート駆動パルスの印加終了後にダイオード構造に再びキャリア（ホール）が注入される時間（キャリアの再注入時間）を正確に制御可能となる。その結果、アーム短絡を防止しつつ再注入時間を短く制御することができるので、逆回復電流が減少し、スイッチング損失を低減できる。また、第１の制御手段は、オフ指令信号を基準タイミングとしてゲート駆動信号を印加できるので、別のタイミング信号が不要となり、従来から使用している駆動制御装置からの置き替えが容易になる。 Accordingly, the time from when the gate drive pulse is applied to one semiconductor element until the reverse recovery current starts to flow, for example, the time when carriers (holes) are injected again into the diode structure after the application of the gate drive pulse is completed. (Reinjection time) can be accurately controlled. As a result, since the reinjection time can be controlled to be short while preventing an arm short circuit, the reverse recovery current is reduced and the switching loss can be reduced. In addition, since the first control means can apply the gate drive signal using the off command signal as a reference timing, a separate timing signal is not required, and the replacement from the conventionally used drive control device is facilitated.
　代案として、駆動制御装置は、駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記電流検出信号に基づいて、前記ダイオード構造の順方向の向きに流れる前記半導体素子の電流が電流しきい値以上であると判定すると、前記ゲート駆動電圧の遮断を指令するゲート駆動信号を出力する第２の制御手段をさらに備えてもよい。第２の制御手段は、駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記電流検出信号に基づいて、前記ダイオード構造の順方向の向きに流れる前記半導体素子の電流が前記電流しきい値未満であると判定すると、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する。前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れる場合において、前記ゲート駆動電圧が遮断されている時における導通損失と前記ゲート駆動電圧が印加されている時における導通損失とが等しくなる電流値が予め測定されて、電流しきい値として設定されている。 As an alternative, the drive control device may be configured such that the current of the semiconductor element that flows in the forward direction of the diode structure is a current based on the current detection signal during a period in which an ON command signal is input to the semiconductor element to be driven and controlled. If it is determined that the threshold value is equal to or greater than the threshold value, a second control unit that outputs a gate drive signal that instructs to shut off the gate drive voltage may be further provided. The second control means is configured to cause the current of the semiconductor element that flows in the forward direction of the diode structure based on the current detection signal during a period in which an ON command signal is input to the semiconductor element to be driven and controlled, to the current direction. If it is determined that it is less than the threshold value, a gate drive signal for instructing application of the gate drive voltage is output. When a current flows through the semiconductor element in the forward direction of the diode structure, the conduction loss when the gate drive voltage is cut off is equal to the conduction loss when the gate drive voltage is applied. The current value is measured in advance and set as a current threshold value.
　半導体素子は、ゲート駆動電圧が遮断されている時と印加されている時における導通損失が相違する特性を有している。これは、チャネルの形成によりホールの注入が影響を受けるからである。ゲート駆動電圧が遮断されている時の導通損失と印加されている時の導通損失との大小関係は、半導体素子の種類、耐圧などにより異なる。そこで、本手段では、この関係を予め測定して大小関係が入れ替わる電流しきい値を設定する。 The semiconductor element has a characteristic that the conduction loss differs when the gate drive voltage is cut off and when it is applied. This is because hole injection is affected by channel formation. The magnitude relationship between the conduction loss when the gate drive voltage is cut off and the conduction loss when the gate drive voltage is applied varies depending on the type of semiconductor element, withstand voltage, and the like. Therefore, in this means, this relationship is measured in advance, and a current threshold value at which the magnitude relationship is switched is set.
　第２の制御手段は、半導体素子にダイオード構造の順方向の向きに流れる電流が電流しきい値以上のときにゲート駆動電圧の遮断指令を出力し、電流しきい値未満のときにゲート駆動電圧の印加指令を出力する。これにより、半導体素子の種類や耐圧にかかわらず、導通損失を適切に低減することができる。また、半導体素子にダイオード構造の逆方向の向きに電流が流れる期間に確実にゲート駆動電圧が印加されるので、トランジスタ構造にオン指令信号に従った電流を流すことができる。 The second control means outputs a gate drive voltage cutoff command when the current flowing in the forward direction of the diode structure in the semiconductor element is equal to or greater than the current threshold, and when the current is less than the current threshold, the gate drive voltage The application command is output. As a result, the conduction loss can be appropriately reduced regardless of the type and breakdown voltage of the semiconductor element. In addition, since the gate drive voltage is reliably applied to the semiconductor element during the period in which the current flows in the reverse direction of the diode structure, the current according to the ON command signal can be supplied to the transistor structure.
　代案として、前記第２の制御手段は、駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記半導体素子に前記ダイオード構造の順方向の向きに前記電流しきい値未満の電流が流れていると判定すると、前記ゲート駆動電圧の印加を指令するゲート駆動信号を、当該半導体素子に対するオフ指令信号の入力時点を越えて前記第２時間の経過時点まで延長して出力してもよい。 As an alternative, the second control means is configured such that a current less than the current threshold is applied to the semiconductor element in a forward direction of the diode structure during a period in which an ON command signal is input to the semiconductor element to be driven and controlled. If it is determined that the current is flowing, the gate drive signal for instructing the application of the gate drive voltage may be output after the input time of the off command signal to the semiconductor element is extended to the time point of the second time. .
　これにより、第２制御手段による制御と第１制御手段による制御とを一連のゲート駆動電圧により実行でき、導通損失を一層低減できる。 Thereby, the control by the second control means and the control by the first control means can be executed by a series of gate drive voltages, and the conduction loss can be further reduced.
　代案として、駆動制御装置は、駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力し、当該期間において前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定すると、前記ゲート駆動電圧の印加を指令するゲート駆動信号を、当該半導体素子に対するオフ指令信号の入力時点を越えて前記第２時間の経過時点まで延長して出力する第２の制御手段をさらに備えていてもよい。 As an alternative, the drive control device outputs a gate drive signal for instructing application of the gate drive voltage during a period in which an on-command signal for the semiconductor element to be driven is input, and the diode is supplied to the semiconductor element during the period When it is determined that a current is flowing in the forward direction of the structure, a gate drive signal for instructing application of the gate drive voltage is set to a time point at which the second time has passed after an input time point of the off command signal to the semiconductor element. There may be further provided a second control means for extending the output to the output.
　これにより、オン指令信号が入力されている期間のゲート駆動電圧と、その後の第一制御手段の制御に係るゲート駆動電圧とを、一連のゲート駆動電圧として実行でき、導通損失を一層低減できる。 Thereby, the gate drive voltage during the period when the ON command signal is inputted and the gate drive voltage related to the control of the first control means can be executed as a series of gate drive voltages, and the conduction loss can be further reduced.
　本開示の第二の態様において、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とが同一の半導体基板に形成され、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通とされた半導体素子の駆動制御装置は、前記半導体素子に流れる電流に応じた電流検出信号を出力する電流検出手段と、前記半導体素子に対するオン指令信号が入力されている期間、前記電流検出信号に基づいて、前記ダイオード構造の順方向の向きに流れる前記半導体素子の電流が前記電流しきい値以上であると判定すると、前記ゲート駆動電圧の遮断を指令するゲート駆動信号を出力する第２の制御手段とを備えている。第２の制御手段は、前記半導体素子に対するオン指令信号が入力されている期間、前記電流検出信号に基づいて、前記ダイオード構造の順方向の向きに流れる前記半導体素子の電流が前記電流しきい値未満であると判定すると、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する。前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れる場合において、前記ゲート駆動電圧が遮断されている時における導通損失と前記ゲート駆動電圧が印加されている時における導通損失とが等しくなる電流値が予め測定されて、電流しきい値として設定されている。 In a second aspect of the present disclosure, an insulated gate transistor structure to which a gate driving voltage is applied and a diode structure are formed on the same semiconductor substrate, and the current-carrying electrode of the transistor structure and the current-carrying electrode of the diode structure are A common drive control device for a semiconductor element includes: a current detection unit that outputs a current detection signal corresponding to a current flowing through the semiconductor element; and the current detection signal during a period when an ON command signal is input to the semiconductor element. If the current of the semiconductor element flowing in the forward direction of the diode structure is determined to be greater than or equal to the current threshold value based on the second, a gate drive signal for commanding the interruption of the gate drive voltage is output. Control means. The second control means is configured such that the current of the semiconductor element that flows in the forward direction of the diode structure is based on the current detection signal during the period when the ON command signal for the semiconductor element is input. If it is determined that the value is less than the value, a gate drive signal for instructing application of the gate drive voltage is output. When a current flows through the semiconductor element in the forward direction of the diode structure, the conduction loss when the gate drive voltage is cut off is equal to the conduction loss when the gate drive voltage is applied. The current value is measured in advance and set as a current threshold value.
　第２の制御手段は、半導体素子に対するオン指令信号が入力されている期間、電流検出信号に基づいて、半導体素子にダイオード構造の順方向の向きに流れる電流が電流しきい値以上であると判定すると、ゲート駆動電圧の遮断を指令するゲート駆動信号を出力する。電流しきい値未満であると判定すると、ゲート駆動電圧の印加を指令するゲート駆動信号を出力する。この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。さらに、半導体素子の種類や耐圧にかかわらず、導通損失を適切に低減することができる。また、半導体素子にダイオード構造の逆方向の向きに電流が流れる期間に確実にゲート駆動電圧が印加されるので、トランジスタ構造にオン指令信号に従った電流を流すことができる。 The second control means determines that the current flowing in the forward direction of the diode structure in the semiconductor element is greater than or equal to the current threshold based on the current detection signal during the period when the ON command signal for the semiconductor element is input. Then, a gate drive signal for instructing shutoff of the gate drive voltage is output. If it is determined that it is less than the current threshold value, a gate drive signal for instructing application of the gate drive voltage is output. According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above. Furthermore, the conduction loss can be appropriately reduced regardless of the type and breakdown voltage of the semiconductor element. In addition, since the gate drive voltage is reliably applied to the semiconductor element during the period in which the current flows in the reverse direction of the diode structure, the current according to the ON command signal can be supplied to the transistor structure.
　代案として、前記第２の制御手段は、外部から前記電流しきい値を特定するしきい値特定信号を入力可能に構成されていてもよい。前記第２の制御手段は、前記オン指令信号が入力されている期間において、入力した前記しきい値特定信号に応じた電流しきい値を前記半導体素子に流れる電流の判定に用いる。 As an alternative, the second control means may be configured to be able to input a threshold value specifying signal for specifying the current threshold value from the outside. The second control means uses a current threshold value corresponding to the input threshold value specifying signal for determination of a current flowing through the semiconductor element during a period in which the ON command signal is input.
　これにより、駆動制御装置は、種類、耐圧などが異なる種々の半導体素子を低い導通損失で駆動することができる。 Thereby, the drive control device can drive various semiconductor elements of different types, withstand voltages, etc. with low conduction loss.
　代案として、第１の制御手段または第２の制御手段の少なくとも一方は、通常制御を実行してもよい。通常制御において、第１の制御手段または第２の制御手段の少なくとも一方は、前記半導体素子を通して負荷に流れる電流が規定値よりも小さい場合、駆動制御する前記半導体素子に対するオン指令信号が入力されると前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する。通常制御において、第１の制御手段または第２の制御手段の少なくとも一方は、前記半導体素子を通して負荷に流れる電流が規定値よりも小さい場合、駆動制御する前記半導体素子に対するオフ指令信号が入力されると前記ゲート駆動電圧の遮断を指令するゲート駆動信号を出力する。 As an alternative, at least one of the first control means or the second control means may perform normal control. In normal control, at least one of the first control means and the second control means receives an ON command signal for the semiconductor element to be driven and controlled when the current flowing to the load through the semiconductor element is smaller than a specified value. And a gate drive signal for instructing application of the gate drive voltage. In normal control, at least one of the first control means and the second control means receives an off command signal for the semiconductor element to be driven and controlled when the current flowing through the semiconductor element to the load is smaller than a specified value. And a gate drive signal for instructing to cut off the gate drive voltage.
　これにより、電流検出精度の低下による誤制御を防止することができる。 This makes it possible to prevent erroneous control due to a decrease in current detection accuracy.
　代案として、駆動制御装置は、前記ゲート駆動信号を入力して前記ゲート駆動電圧を出力するドライブ回路をさらに備えてもよい。ドライブ回路は、前記ゲート駆動電圧に応じた耐圧を持つＩＣで構成されている。 As an alternative, the drive control device may further include a drive circuit that inputs the gate drive signal and outputs the gate drive voltage. The drive circuit is composed of an IC having a withstand voltage corresponding to the gate drive voltage.
　この構成によれば、ハーフブリッジ回路を構成する半導体素子ごとに駆動制御装置が設けられる。既に広く使用されている半導体素子の駆動システムに対し、駆動制御装置（駆動ＩＣ）を置き替えればよいので、駆動システムの変更が容易になる。 According to this configuration, a drive control device is provided for each semiconductor element constituting the half bridge circuit. Since it is only necessary to replace the drive control device (drive IC) with a drive system for semiconductor elements that has already been widely used, the drive system can be easily changed.
　代案として、駆動制御装置は、ハーフブリッジ回路を構成する２つの半導体素子を駆動制御してもよい。駆動制御装置は、前記ハーフブリッジ回路に加わる電源電圧に応じた耐圧を持つＩＣで構成されている。当該ＩＣは、前記ゲート駆動信号を入力して前記ゲート駆動電圧を出力するドライブ回路を備える。前記電流検出手段は、前記２つの半導体素子のうち少なくとも一方に流れる電流を検出可能に設けられる。第１の制御手段または第２の制御手段の少なくとも一方は、前記２つの半導体素子のうち一方の半導体素子に前記ゲート駆動電圧を印加している期間、他方の半導体素子への前記ゲート駆動電圧の印加を禁止する。 As an alternative, the drive control device may drive and control two semiconductor elements constituting the half bridge circuit. The drive control device is composed of an IC having a withstand voltage corresponding to the power supply voltage applied to the half bridge circuit. The IC includes a drive circuit that inputs the gate drive signal and outputs the gate drive voltage. The current detection means is provided so as to detect a current flowing in at least one of the two semiconductor elements. At least one of the first control means and the second control means is configured to apply the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements. Prohibit application.
　電流検出手段は、２つの半導体素子のうち少なくとも一方に流れる電流を検出する。一方の電流を検出できれば、他方の半導体素子の電流も間接的に検出可能となる。 The current detection means detects a current flowing through at least one of the two semiconductor elements. If one current can be detected, the current of the other semiconductor element can also be detected indirectly.
　本駆動制御装置は、ハーフブリッジ回路を構成する２つの半導体素子の駆動状態を把握できる。制御手段は、２つの半導体素子のうち一方の半導体素子にゲート駆動電圧を印加している期間、他方の半導体素子へのゲート駆動電圧の印加を禁止する。これにより、アーム短絡を確実に防止できる。 This drive control device can grasp the drive state of the two semiconductor elements constituting the half bridge circuit. The control unit prohibits application of the gate drive voltage to the other semiconductor element during the period in which the gate drive voltage is applied to one of the two semiconductor elements. Thereby, an arm short circuit can be prevented reliably.
　代案として、駆動制御装置は、ハーフブリッジ回路を構成する２つの前記半導体素子を駆動制御してもよい。駆動制御装置は、第１の制御手段または第２の制御手段の少なくとも一方を提供する制御ＩＣと、前記制御ＩＣから入力したゲート駆動信号に基づいて各半導体素子に前記ゲート駆動電圧を印加する駆動ＩＣと、前記制御ＩＣから出力されたゲート駆動信号を電気的に絶縁して前記駆動ＩＣに伝送する絶縁回路と、前記電流検出手段とから構成されている。前記制御ＩＣは、前記２つの半導体素子のうち一方の半導体素子に前記ゲート駆動電圧を印加している期間、他方の半導体素子への前記ゲート駆動電圧の印加を禁止するゲート駆動信号を出力する。 As an alternative, the drive control device may drive and control the two semiconductor elements constituting the half bridge circuit. The drive control device includes a control IC that provides at least one of the first control means and the second control means, and a drive that applies the gate drive voltage to each semiconductor element based on a gate drive signal input from the control IC. It comprises an IC, an insulating circuit that electrically insulates the gate drive signal output from the control IC and transmits the signal to the drive IC, and the current detection means. The control IC outputs a gate drive signal for prohibiting application of the gate drive voltage to the other semiconductor element during a period in which the gate drive voltage is applied to one of the two semiconductor elements.
　本駆動制御装置は、ハーフブリッジ回路を構成する２つの半導体素子の駆動状態を把握できる。制御ＩＣは、２つの半導体素子のうち一方の半導体素子にゲート駆動電圧を印加している期間、他方の半導体素子へのゲート駆動電圧の印加を禁止するゲート駆動信号を出力する。これにより、アーム短絡を確実に防止できる。また、電流検出手段は、２つの半導体素子のうち一方の電流のみを検出できれば、他方の半導体素子の電流も間接的に検出可能となる。 This drive control device can grasp the drive state of the two semiconductor elements constituting the half bridge circuit. The control IC outputs a gate drive signal for prohibiting application of the gate drive voltage to the other semiconductor element during a period in which the gate drive voltage is applied to one of the two semiconductor elements. Thereby, an arm short circuit can be prevented reliably. Moreover, if the current detection means can detect only one of the two semiconductor elements, the current of the other semiconductor element can also be indirectly detected.
　代案として、前記電流検出手段は、前記制御ＩＣにより提供されてもよい。 As an alternative, the current detection means may be provided by the control IC.
　例えば、制御ＩＣは、上述した各制御をソフトウェア処理する。 For example, the control IC performs software processing for each control described above.
　本開示の第三の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、前記２つの半導体素子のうち少なくとも一方に流れる電流に応じた電流検出信号を出力する電流検出手段と、前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電流検出信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、前記電流検出手段により電流検出信号の変動を検出した時点で、二つの半導体素子の間でアーム短絡が生じないようにパルスを出力させる制御手段とを備え、当該時点は、前記一方の半導体素子に対するオン指令信号の入力時点の前である、二つの半導体素子は、ハーフブリッジ回路を構成する。 In a third aspect of the present disclosure, each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate. The drive control device for two semiconductor elements, wherein the electrode and the current-carrying electrode of the diode structure are common, current detection means for outputting a current detection signal corresponding to a current flowing in at least one of the two semiconductor elements; When it is determined that a current flows in the forward direction of the diode structure to the one semiconductor element based on the current detection signal when an off command signal is input to the one semiconductor element, the current When the detection means detects a change in the current detection signal, a pulse is output so that an arm short circuit does not occur between the two semiconductor elements. And a that control means, the time is prior to the point of input of the ON command signal for the one of the semiconductor elements, two semiconductor elements constitute a half-bridge circuit.
　この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。 According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above.
　本開示の第四の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、一方の前記半導体素子の電極電位に基づく電圧検出信号を出力する電圧検出手段と、前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電圧検出信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、二つの半導体素子の間でアーム短絡が生じないように前記一方の半導体素子に対するオン指令信号の入力時点からパルスを出力させる制御手段と、を備える。二つの半導体素子は、ハーフブリッジ回路を構成する。 In the fourth aspect of the present disclosure, each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized. The drive control device for two semiconductor elements, in which the electrode and the current-carrying electrode of the diode structure are common, a voltage detection means for outputting a voltage detection signal based on the electrode potential of one of the semiconductor elements, and the one semiconductor element When it is determined that a current flows in the forward direction of the diode structure in the one semiconductor element based on the voltage detection signal when an off command signal is input to the two semiconductor elements, Control means for outputting a pulse from an input time point of an ON command signal to the one semiconductor element so as not to cause an arm short circuit. The two semiconductor elements constitute a half bridge circuit.
　この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。 According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above.
　代案として、駆動制御装置は、少なくとも一方の半導体素子に流れる電流に応じた電流検出信号を出力する電流検出手段と、前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電流検出信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、遅延時間分だけ、前記一方の半導体素子に対するオン指令信号の入力時点の前からパルスを出力させる他の制御手段をさらに備えてもよい。遅延時間は、前記一方の半導体素子に電流が流れなくなり始めるタイミングと前記ゲート駆動電圧が上昇するタイミングとの間で定義されている。 As an alternative, the drive control device includes: a current detection unit that outputs a current detection signal corresponding to a current flowing through at least one semiconductor element; and the current detection signal when an off command signal is input to the one semiconductor element. When it is determined that a current flows in the forward direction of the diode structure based on the one semiconductor element, a pulse is applied from the time before the ON command signal is input to the one semiconductor element by a delay time. You may further provide the other control means to output. The delay time is defined between the timing at which no current flows through the one semiconductor element and the timing at which the gate drive voltage rises.
　本開示の第五の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、一方の前記半導体素子に流れる電流に応じた電流検出信号を出力する電流検出手段と、他方の前記半導体素子に対する指令信号を入力する入力手段と、前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電流検出信号及び前記入力手段の入力信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、前記入力手段にオフ指令信号が入力されることに応じてパルスを出力させる手段であって、二つの半導体素子の間でアーム短絡が生じないように前記一方の半導体素子に対するオン指令信号の入力時点より所定時間前にパルスを出力させる制御手段を備える。二つの半導体素子は、ハーフブリッジ回路を構成する。 5th aspect of this indication WHEREIN: Each semiconductor element has the insulated gate type transistor structure and diode structure to which a gate drive voltage is applied formed in the same semiconductor substrate, and electricity supply of the said transistor structure The drive control device for two semiconductor elements, in which the electrode and the current-carrying electrode of the diode structure are common, current detection means for outputting a current detection signal corresponding to the current flowing through one of the semiconductor elements, and the other semiconductor An input means for inputting a command signal for the element, and the diode structure in the one semiconductor element based on the current detection signal and the input signal of the input means when an OFF command signal for the one semiconductor element is input. When it is determined that a current is flowing in the forward direction, a pulse is generated in response to an OFF command signal being input to the input means. And means for outputting comprises a control means for outputting a pulse a predetermined time before the input time of the ON command signal for the one of the semiconductor element so arm short circuit does not occur between the two semiconductor elements. The two semiconductor elements constitute a half bridge circuit.
　この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。 According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above.
　本開示の第六の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、一方の前記半導体素子の電極電位に基づく電圧検出信号を出力する電圧検出手段と、他方の前記半導体素子に対する指令信号を入力する入力手段と、前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電圧検出信号及び前記入力手段の入力信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、前記入力手段にオフ指令信号が入力されることに応じてパルスを出力させる手段であって、二つの半導体素子の間でアーム短絡が生じないように前記一方の半導体素子に対するオン指令信号の入力時点より所定時間前にパルスを出力させる制御手段を備える。二つの半導体素子は、ハーフブリッジ回路を構成する。 In a sixth aspect of the present disclosure, each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate drive voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized. A drive control device for two semiconductor elements, in which an electrode and a current-carrying electrode of the diode structure are common, a voltage detection means for outputting a voltage detection signal based on an electrode potential of one of the semiconductor elements, and the other semiconductor element Input means for inputting a command signal to the one semiconductor element, and when the off-command signal for the one semiconductor element is input, the one semiconductor element has the diode structure based on the voltage detection signal and the input signal of the input means. When it is determined that a current is flowing in the forward direction, a pulse is generated in response to an OFF command signal being input to the input means. A means for force, a control means for outputting a pulse a predetermined time before the input time of the ON command signal for the one of the semiconductor element so arm short circuit does not occur between the two semiconductor elements. The two semiconductor elements constitute a half bridge circuit.
　この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。 According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above.
　代案として、駆動制御装置は、他方の前記半導体素子の制御電圧に応じた制御電圧検出信号を出力する制御電圧検出手段をさらに備えてもよい。前記制御手段は、前記制御電圧検出手段の制御電圧検出信号の変動に基づいてパルスを出力させる。 As an alternative, the drive control device may further include control voltage detection means for outputting a control voltage detection signal corresponding to the control voltage of the other semiconductor element. The control means outputs a pulse based on the fluctuation of the control voltage detection signal of the control voltage detection means.
　本開示の第七の態様において、各々の半導体素子が、同一の半導体基板に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通である、二つの半導体素子の駆動制御装置は、少なくとも一方の半導体素子の電極電位に応じた電圧検出信号を出力する電圧検出手段と、前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電圧検出信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、その後にオン指令信号の入力を経てオフ指令信号が入力された時点を起点として、第１時間の経過時点から第２時点の経過時点まで、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する制御手段と、を備える。第1時間と第2時間は、二つの半導体素子の間でアーム短絡が生じないように予め設定されている。二つの半導体素子は、ハーフブリッジ回路を構成する。 In a seventh aspect of the present disclosure, each semiconductor element has an insulated gate transistor structure and a diode structure to which a gate driving voltage is applied, which are formed on the same semiconductor substrate, and the transistor structure is energized. The drive control device for two semiconductor elements, in which the electrode and the current-carrying electrode of the diode structure are common, a voltage detection means for outputting a voltage detection signal corresponding to the electrode potential of at least one of the semiconductor elements, and the one semiconductor When it is determined that a current flows in the forward direction of the diode structure to the one semiconductor element based on the voltage detection signal when an off command signal is input to the element, the ON command signal Starting from the time when the OFF command signal is input through the input, the gate drive power is supplied from the time when the first time has elapsed to the time when the second time has elapsed. And a control means for outputting a gate drive signal for commanding the application. The first time and the second time are set in advance so as not to cause an arm short circuit between the two semiconductor elements. The two semiconductor elements constitute a half bridge circuit.
　この構成によれば、上述した第一の態様と同様の作用および効果を得ることができる。 According to this configuration, it is possible to obtain the same operation and effect as the first aspect described above.
　代案として、前記制御手段は、前記電圧検出部により電圧が変動したか否かを判定することで負荷に流れる電流を判定してもよい。前記制御手段は、前記負荷の電流が０付近の所定範囲であると判定すると、前記ゲート駆動電圧の遮断を指令するゲート駆動信号を出力する。前記制御手段は、前記負荷の電流が０付近の所定範囲外であると判定すると前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する。 As an alternative, the control means may determine the current flowing through the load by determining whether or not the voltage has changed by the voltage detector. When the control means determines that the current of the load is within a predetermined range near 0, the control means outputs a gate drive signal for instructing cutoff of the gate drive voltage. When the control means determines that the load current is outside a predetermined range near 0, the control means outputs a gate drive signal for instructing application of the gate drive voltage.
　代案として、前記制御手段は、駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記電圧検出信号に基づいて前記ダイオード構造の順方向の向きに流れていると判定すると、前記ゲート駆動電圧の遮断を指定するゲート駆動信号を出力してもよい。前記制御手段は、駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記電圧検出信号に基づいて前記ダイオード構造の順方向の向きに流れていないと判定すると、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する。 Alternatively, when the control means determines that the current flows in the forward direction of the diode structure based on the voltage detection signal during a period in which an ON command signal is input to the semiconductor element to be driven and controlled, You may output the gate drive signal which designates interruption | blocking of a drive voltage. When the control means determines that the current does not flow in the forward direction of the diode structure based on the voltage detection signal during a period in which an ON command signal is input to the semiconductor element to be driven and controlled, A gate drive signal for commanding application is output.
　代案として、駆動制御装置は、前記ゲート駆動信号を入力して前記ゲート駆動電圧を出力するドライブ回路をさらに備えてもよい。ドライブ回路は、前記ゲート駆動電圧に応じた耐圧を持つＩＣで構成されている。 As an alternative, the drive control device may further include a drive circuit that inputs the gate drive signal and outputs the gate drive voltage. The drive circuit is composed of an IC having a withstand voltage corresponding to the gate drive voltage.
　代案として、駆動制御装置は、ハーフブリッジ回路を構成する２つの前記半導体素子を駆動制御してもよい。駆動制御装置は、は、前記ハーフブリッジ回路に加わる電源電圧に応じた耐圧を持つＩＣで構成されている。当該ＩＣは、前記ゲート駆動信号を入力して前記ゲート駆動電圧を出力するドライブ回路を提供する。前記電圧検出手段は、前記２つの半導体素子のうち少なくとも一方の電圧を検出可能に設けられる。前記制御手段は、前記２つの半導体素子のうち一方の半導体素子に前記ゲート駆動電圧を印加している期間、他方の半導体素子への前記ゲート駆動電圧の印加を禁止する。 As an alternative, the drive control device may drive and control the two semiconductor elements constituting the half bridge circuit. The drive control device is composed of an IC having a withstand voltage corresponding to the power supply voltage applied to the half bridge circuit. The IC provides a drive circuit that inputs the gate drive signal and outputs the gate drive voltage. The voltage detecting means is provided so as to detect at least one voltage of the two semiconductor elements. The control means prohibits application of the gate drive voltage to the other semiconductor element during a period in which the gate drive voltage is applied to one of the two semiconductor elements.
　代案として、駆動制御装置は、ハーフブリッジ回路を構成する２つの前記半導体素子を駆動制御してもよい。駆動制御装置は、前記制御手段を有する制御ＩＣと、前記制御ＩＣから入力したゲート駆動信号に基づいて前記半導体素子に前記ゲート駆動電圧を印加する駆動ＩＣと、前記制御ＩＣから出力されたゲート駆動信号を電気的に絶縁して前記駆動ＩＣに伝送する絶縁回路と、前記電圧検出手段とから構成されている。前記制御ＩＣは、前記２つの半導体素子のうち一方の半導体素子に前記ゲート駆動電圧を印加している期間、他方の半導体素子への前記ゲート駆動電圧の印加を禁止するゲート駆動信号を出力する。 As an alternative, the drive control device may drive and control the two semiconductor elements constituting the half bridge circuit. The drive control device includes a control IC having the control means, a drive IC for applying the gate drive voltage to the semiconductor element based on a gate drive signal input from the control IC, and a gate drive output from the control IC An insulating circuit that electrically insulates the signal and transmits the signal to the drive IC and the voltage detection means are configured. The control IC outputs a gate drive signal for prohibiting application of the gate drive voltage to the other semiconductor element during a period in which the gate drive voltage is applied to one of the two semiconductor elements.
　代案として、前記電圧検出手段は、前記制御ＩＣにより提供されてもよい。 As an alternative, the voltage detection means may be provided by the control IC.
　代案として、前記電圧検出手段は、前記半導体素子の素子形成領域の外周側に離間して半導体基板に形成されてもよい。前記電圧検出手段は、前記半導体基板の導電型とは逆導電型の電界制限リングを用いて中間電位を検出する。 As an alternative, the voltage detection means may be formed on the semiconductor substrate apart from the outer periphery of the element formation region of the semiconductor element. The voltage detecting means detects an intermediate potential using an electric field limiting ring having a conductivity type opposite to the conductivity type of the semiconductor substrate.
　本開示の第八の態様において、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造とダイオード構造とが同一の半導体基板に形成され、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通の電極とされた半導体素子の駆動制御装置は、前記半導体素子に流れる電流に応じた電流検出信号を出力する電流検出手段と、前記電流検出信号に基づいて、前記半導体素子に対するオン指令信号が入力されている期間に前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、その後のオフ指令信号の入力時点を起点として、予め設定された第１時間の経過時点から第２時間の経過時点まで前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する制御手段と、前記ゲート駆動信号を入力して前記ゲート駆動電圧を出力するドライブ回路とを備える。前記第１時間と前記第２時間との時間幅は、前記半導体素子に対するオン指令信号が入力されている期間に前記半導体素子に流れていた電流の大きさに応じた値に設定されている。 In an eighth aspect of the present disclosure, an insulated gate transistor structure to which a gate drive voltage is applied and a diode structure are formed on the same semiconductor substrate, and the conduction electrode of the transistor structure and the conduction electrode of the diode structure are The drive control device for a semiconductor element having a common electrode includes a current detection unit that outputs a current detection signal corresponding to a current flowing through the semiconductor element, and an on command signal for the semiconductor element based on the current detection signal. When it is determined that a current is flowing in the semiconductor element in the forward direction of the diode structure during the input period, a preset first time elapses from the input time point of the subsequent off command signal Control means for outputting a gate drive signal for instructing application of the gate drive voltage from a time point until a lapse of a second time; and If the input signal and a drive circuit for outputting the gate drive voltage. The time width between the first time and the second time is set to a value corresponding to the magnitude of the current flowing in the semiconductor element during the period when the ON command signal for the semiconductor element is input.
　駆動対象の半導体素子は、トランジスタ構造とダイオード構造に対し共通のゲート構造を備えている。上下アーム間で通電が切り替わる時、例えば一方の半導体素子のダイオード構造に電流が流れている状態で、制御手段が当該一方の半導体素子にゲート駆動電圧を印加すると、当該ダイオード構造に蓄積されるホールが減少し、逆回復電流を低減する作用が生じる。 The semiconductor element to be driven has a common gate structure for the transistor structure and the diode structure. When energization is switched between the upper and lower arms, for example, when a control means applies a gate drive voltage to the one semiconductor element in a state where current flows in the diode structure of one semiconductor element, holes accumulated in the diode structure Decreases, and the effect of reducing the reverse recovery current occurs.
　しかし、オフ指令信号が入力された半導体素子について、ダイオード構造の順方向の向きに素子電流（例えばダイオード電流）が流れている場合と、逆方向の向きに素子電流（トランジスタ電流）が流れている場合とでは、ゲート駆動パルスを与えたときのゲート駆動電圧の波形が異なる。例えば、前者の場合には急峻な電流変化、電圧変化やミラー期間が生じないので、ゲート駆動電圧の立ち上がり時間および立ち下がり時間は短くなる（或いは短くできる）。これにより、ゲート駆動パルスの遅延やばらつきが小さくなる。一方、後者の場合には急峻な電流変化、電圧変化やミラー期間が生じるので、ゲート駆動パルスの遅延やばらつきが大きくなる。駆動制御装置は、半導体素子にダイオード構造の順方向の向きに電流が流れている場合に限りゲート駆動パルスを印加するので、前者の場合の小さい遅延やばらつきに基づいた制御が可能となり、印加タイミングの精度を高めることができる。 However, for a semiconductor element to which an off command signal is input, a device current (transistor current) flows in the reverse direction when a device current (for example, a diode current) flows in the forward direction of the diode structure. In some cases, the waveform of the gate drive voltage when a gate drive pulse is applied is different. For example, in the former case, since a steep current change, voltage change and mirror period do not occur, the rise time and fall time of the gate drive voltage are shortened (or can be shortened). This reduces the delay and variation of the gate drive pulse. On the other hand, in the latter case, since a steep current change, voltage change, and mirror period occur, the delay and variation of the gate drive pulse increase. The drive control device applies a gate drive pulse only when a current flows through the semiconductor element in the forward direction of the diode structure, so control based on small delays and variations in the former case is possible, and the application timing Can improve the accuracy.
　上記半導体素子は、例えば、出力端子を挟んで高電位側（ハイサイド）と低電位側（ローサイド）に直列に配されてハーフブリッジ回路を構成する。駆動制御装置は、相補的に変化するハイサイドとローサイドの指令信号（例えばＰＷＭ信号）のうち少なくとも一方の指令信号を入力し、少なくとも一方のサイドの半導体素子にゲート駆動電圧を印加する。この指令信号は、切り替え時にデッドタイムを有している。デッドタイムは一定時間であるため、一方サイドのオフ指令信号の入力から他方サイドのオン指令信号の入力までの時間が正確に保証されている。 The semiconductor element is, for example, arranged in series on the high potential side (high side) and the low potential side (low side) across the output terminal to constitute a half bridge circuit. The drive control device inputs at least one command signal among high-side and low-side command signals (for example, PWM signals) that change complementarily, and applies a gate drive voltage to at least one side semiconductor element. This command signal has a dead time at the time of switching. Since the dead time is a fixed time, the time from the input of the off command signal on one side to the input of the on command signal on the other side is accurately guaranteed.
　制御手段は、上述した遅延やばらつきを予め測定し、デッドタイムを把握した上で、第１時間と第２時間との時間幅を、半導体素子に対するオン指令信号が入力されている期間に半導体素子に流れていた電流の大きさに応じた値に制御する。これにより、オフ指令信号の入力時点を起点として、ゲート駆動電圧を所望のタイミングで印加するために必要なゲート駆動信号のタイミング、すなわち第１時間と第２時間を正確に設定することが可能となる。 The control means measures the delay and variation described above in advance, grasps the dead time, and sets the time width between the first time and the second time during the period when the ON command signal for the semiconductor element is input. The value is controlled according to the magnitude of the current flowing in the current. As a result, it is possible to accurately set the timing of the gate drive signal necessary for applying the gate drive voltage at a desired timing, that is, the first time and the second time, starting from the input time point of the off command signal. Become.
　その結果、一方の半導体素子に対するゲート駆動パルスの印加終了時点から逆回復電流が流れ始めるまでの時間、例えばゲート駆動パルスの印加終了後に当該ダイオード構造に再びキャリア（ホール）が注入される時間（キャリアの再注入時間）を正確に制御可能となる。従って、本手段によれば、アーム短絡を防止しつつ再注入時間を短く制御することができるので、逆回復電流が減少し、スイッチング損失を低減できる。また、制御手段は、オフ指令信号を基準タイミングとしてゲート駆動信号を印加できるので、別のタイミング信号が不要となり、従来から使用している駆動制御装置からの置き替えが容易になる。 As a result, the time from when the gate drive pulse is applied to one semiconductor element until the reverse recovery current starts to flow, for example, the time when carriers (holes) are injected again into the diode structure after the application of the gate drive pulse (carrier) The reinjection time) can be accurately controlled. Therefore, according to this means, the reinjection time can be controlled to be short while preventing an arm short circuit, so that the reverse recovery current is reduced and the switching loss can be reduced. In addition, since the control means can apply the gate drive signal using the off command signal as a reference timing, a separate timing signal is not required, and replacement from a conventionally used drive control device is facilitated.
　代案として、当該半導体素子は、一方の半導体素子と他方の半導体素子を含んでもよい。一方の半導体素子と他方の半導体素子は、ハーフブリッジ回路を構成する。前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れている状態でオフ指令信号が入力された後、一定のデッドタイムを経て、他方の半導体素子に対してオン指令信号が入力されたときに、前記第２時間が経過して前記ゲート駆動電圧が遮断された時点と、前記他方の半導体素子のトランジスタ構造に当該一方の半導体素子に流れていた電流を超える電流が流れ始める時点との時間幅が、ゼロより大きく且つ所定の注入許容時間以下となるように、前記第１時間と前記第２時間が設定されている。 As an alternative, the semiconductor element may include one semiconductor element and the other semiconductor element. One semiconductor element and the other semiconductor element constitute a half-bridge circuit. After an off command signal is input to the semiconductor element in a state where a current flows in the forward direction of the diode structure, an on command signal is input to the other semiconductor element after a certain dead time. Sometimes, when the gate drive voltage is cut off after the second time has elapsed, and when a current exceeding the current flowing in the one semiconductor element starts flowing in the transistor structure of the other semiconductor element. The first time and the second time are set so that the time width is greater than zero and less than or equal to a predetermined allowable injection time.
　上記の時間幅は、上述したキャリア再注入時間である。この時間をゼロより大きく設定することにより、ハーフブリッジ回路に短絡電流が流れることを防止することができる。また、この時間を所定の注入許容時間以下に設定することにより、逆回復電流を注入許容時間に応じた大きさに制限することができ、スイッチング損失を低減できる。 The above time width is the above-described carrier reinjection time. By setting this time larger than zero, it is possible to prevent a short-circuit current from flowing through the half-bridge circuit. In addition, by setting this time to be equal to or less than the predetermined allowable injection time, the reverse recovery current can be limited to a magnitude corresponding to the allowable injection time, and switching loss can be reduced.
　代案として、前記第１時間と第２時間との時間幅は、前記半導体素子に対するオン指令信号が入力されている期間に当該半導体素子に流れていた電流が大きいほど長い時間となるように設定されてもよい。 As an alternative, the time width between the first time and the second time is set to be longer as the current flowing in the semiconductor element is larger during the period when the ON command signal to the semiconductor element is input. May be.
　上記によれば、第１時間と第２時間との時間幅は、半導体素子に対するオン指令信号が入力されている期間に当該半導体素子に流れていた電流が大きいほど長い時間となるように設定されている。電流が大きいほど、オフ指令信号が入力された時点から逆回復電流が流れ始めるまでの時間が長くなるからである。これにより、電流の大きさにかかわらず再注入時間の増大を抑えることができ、スイッチング損失を低減することができる。 According to the above, the time width between the first time and the second time is set to be longer as the current flowing through the semiconductor element is larger during the period when the ON command signal is input to the semiconductor element. ing. This is because the larger the current, the longer the time from when the OFF command signal is input until the reverse recovery current starts to flow. As a result, an increase in reinjection time can be suppressed regardless of the magnitude of current, and switching loss can be reduced.
　代案として、前記第１時間の経過時点から第２時間の経過時点まで出力されるゲート駆動信号に基づく前記ゲート駆動電圧が、前記ドライブ回路のゲート駆動能力に従って単調に増加または単調に減少するものとして、前記第１時間と前記第２時間が設定されてもよい。 As an alternative, it is assumed that the gate drive voltage based on the gate drive signal output from the time point of the first time to the time point of the second time monotonously increases or decreases monotonously according to the gate drive capability of the drive circuit. The first time and the second time may be set.
　オフ指令信号の入力後に印加する上記ゲート駆動パルスは、ダイオード構造に蓄積されるホールを減少させる作用を持ち、半導体素子を通電または断電させる作用を持たない。このため、トランジスタ素子の通電端子間（ＣＥ間、ＤＳ間）の電圧が変化せず、ミラー期間が生じない。また、ゲート駆動パルスの印加期間では、半導体素子にダイオード構造の順方向の向きに電流が流れ続けているので、アーム短絡に備えた保護作用を持つ特別なゲート駆動電圧も不要である。従って、ゲート駆動電圧が単調に増減するものとしてゲート駆動信号を設定することにより、キャリア再注入時間を所望の値に制御できる。 The gate drive pulse applied after the input of the off command signal has the effect of reducing the holes accumulated in the diode structure and does not have the effect of energizing or disconnecting the semiconductor element. For this reason, the voltage between the current-carrying terminals of the transistor elements (between CE and DS) does not change and the mirror period does not occur. Further, during the application period of the gate drive pulse, a current continues to flow in the semiconductor element in the forward direction of the diode structure, so that a special gate drive voltage having a protective action in preparation for an arm short circuit is not necessary. Therefore, the carrier reinjection time can be controlled to a desired value by setting the gate drive signal so that the gate drive voltage monotonously increases or decreases.
　代案として、前記第１時間の経過時点から第２時間の経過時点まで出力されるゲート駆動信号に基づく前記ゲート駆動電圧にミラー期間が生じないものとして、前記第１時間と前記第２時間が設定されていてもよい。 As an alternative, the first time and the second time are set on the assumption that a mirror period does not occur in the gate drive voltage based on the gate drive signal output from the elapse of the first time to the elapse of the second time. May be.
　上記によれば、第１時間の経過時点から第２時間の経過時点まで出力されるゲート駆動信号に基づくゲート駆動電圧にミラー期間が生じないものとして、第１時間と第２時間が設定されている。これにより、ミラー期間の発生を想定してゲート駆動信号の設定した場合に対し、キャリア再注入時間の増大を抑えることができる。 According to the above, the first time and the second time are set on the assumption that the mirror period does not occur in the gate drive voltage based on the gate drive signal output from the elapse of the first time to the elapse of the second time. Yes. As a result, an increase in the carrier reinjection time can be suppressed as compared with the case where the gate drive signal is set assuming the occurrence of the mirror period.
　代案として、ドライブ回路は、前記第１時間の経過時点で前記ゲート駆動信号が変化したときに、一定のゲート駆動能力を維持して前記ゲート駆動電圧を出力してもよい。 Alternatively, the drive circuit may output the gate drive voltage while maintaining a constant gate drive capability when the gate drive signal changes at the time when the first time has elapsed.
　上記によれば、ドライブ回路は、第１時間の経過時点でゲート駆動信号が変化したときに、一定のゲート駆動能力を維持してゲート駆動電圧を出力する。半導体素子を通電させる駆動では、ゲート駆動電圧の増加過程でゲート駆動電圧を一時的に中間電圧に留めることで、半導体素子が短絡故障している時の短絡電流を低減する方法が用いられている。しかし、適切なタイミングでゲート駆動パルスを印加すれば、短絡電流が流れることはない。本手段によれば、一定のゲート駆動能力を維持して無用な中間電圧を排除することにより、ゲート駆動電圧の立ち上がり時間のばらつきを低減し、再注入時間を正確に制御できる。 According to the above, the drive circuit outputs a gate drive voltage while maintaining a constant gate drive capability when the gate drive signal changes at the elapse of the first time. In driving to energize a semiconductor element, a method of reducing a short-circuit current when the semiconductor element has a short-circuit fault is used by temporarily holding the gate drive voltage at an intermediate voltage in the process of increasing the gate drive voltage. . However, if a gate drive pulse is applied at an appropriate timing, a short-circuit current will not flow. According to this means, by maintaining a constant gate drive capability and eliminating unnecessary intermediate voltages, variations in the rise time of the gate drive voltage can be reduced and the reinjection time can be accurately controlled.
　代案として、前記ドライブ回路は、前記第１時間の経過時点および前記第２時間の経過時点で前記ゲート駆動信号が変化したとき、前記半導体素子を通断電するときに比べ高い駆動能力で前記ゲート駆動電圧を出力してもよい。 As an alternative, the drive circuit has a high driving capability when the gate driving signal changes at the time when the first time elapses and at the time when the second time elapses. A drive voltage may be output.
　上記によれば、ドライブ回路は、第１時間の経過時点および第２時間の経過時点でゲート駆動信号が変化したときに、半導体素子を通断電するときに比べ高い駆動能力でゲート駆動電圧を出力する。これは、ゲート駆動パルスの印加期間では、半導体素子にダイオード構造の順方向の向きに電流が流れ続けているので、急峻な電流変化、電圧変化によるサージは発生しないからである。これにより、ゲート駆動電圧の立ち上がり時間および立ち下がり時間のばらつきを低減し、再注入時間を正確に制御できる。 According to the above, when the gate drive signal changes at the time when the first time elapses and at the time when the second time elapses, the drive circuit increases the gate drive voltage with a higher driving capability than when the semiconductor element is disconnected. Output. This is because, during the application period of the gate drive pulse, current continues to flow through the semiconductor element in the forward direction of the diode structure, so that a surge due to a steep current change or voltage change does not occur. Thereby, variations in the rise time and fall time of the gate drive voltage can be reduced, and the reinjection time can be accurately controlled.
　ここで、この出願に記載されるフローチャート、あるいは、フローチャートの処理は、複数のセクション（あるいはステップと言及される）から構成され、各セクションは、たとえば、Ｓ１００と表現される。さらに、各セクションは、複数のサブセクションに分割されることができる、一方、複数のセクションが合わさって一つのセクションにすることも可能である。さらに、このように構成される各セクションは、デバイス、モジュール、ミーンズとして言及されることができる。 Here, the flowchart or the process of the flowchart described in this application is configured by a plurality of sections (or referred to as steps), and each section is expressed as S100, for example. Further, each section can be divided into a plurality of subsections, while a plurality of sections can be combined into one section. Further, each section configured in this manner can be referred to as a device, module, or means.
　本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims (39)

  1. 　各々の半導体素子が、同一の半導体基板（８）に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造（５）とダイオード構造（６）とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通（１５，１８）である、二つの半導体素子（１Ａ，１Ｂ）の駆動制御装置（３２Ａ，３２Ｂ，５２，５４，５６，６１，６２，７１，７２）であって、
    　前記２つの半導体素子のうち少なくとも一方に流れる電流に応じた電流検出信号を出力する電流検出手段（７Ａ，７Ｂ，２５，５９，６０，６８）と、
    　前記電流検出信号に基づいて、前記半導体素子に対するオン指令信号が入力されている期間に前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、その後のオフ指令信号の入力時点を起点として、第１時間の経過時点から第２時間の経過時点まで、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する第１の制御手段（２７）とを備え、
    　二つの半導体素子は、ハーフブリッジ回路（４）を構成し、
    　第１時間と第２時間は、二つの半導体素子の間でアーム短絡が生じないように予め設定されている、
    　駆動制御装置。     Each semiconductor element has an insulated gate type transistor structure (5) and a diode structure (6) to which a gate drive voltage is applied, which are formed on the same semiconductor substrate (8). The drive control device (32A, 32B, 52, 54, 56, 61, 62, 71, 72) of the two semiconductor elements (1A, 1B), in which the electrode and the conducting electrode of the diode structure are common (15, 18). ) And
    Current detection means (7A, 7B, 25, 59, 60, 68) for outputting a current detection signal corresponding to a current flowing in at least one of the two semiconductor elements;
    On the basis of the current detection signal, when it is determined that a current flows in the forward direction of the diode structure in the semiconductor element during a period in which an ON command signal for the semiconductor element is input, a subsequent OFF command signal First control means (27) for outputting a gate drive signal for instructing application of the gate drive voltage from the time point of the first time to the time point of the second time from the input time point of
    The two semiconductor elements constitute a half-bridge circuit (4),
    The first time and the second time are set in advance so as not to cause an arm short circuit between the two semiconductor elements.
    Drive control device.
  2. 　駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記電流検出信号に基づいて、前記ダイオード構造の順方向の向きに流れる前記半導体素子の電流が電流しきい値以上であると判定すると、前記ゲート駆動電圧の遮断を指令するゲート駆動信号を出力する第２の制御手段（２６）をさらに備えており、
    　第２の制御手段は、駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記電流検出信号に基づいて、前記ダイオード構造の順方向の向きに流れる前記半導体素子の電流が前記電流しきい値未満であると判定すると、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力し、
    　前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れる場合において、前記ゲート駆動電圧が遮断されている時における導通損失と前記ゲート駆動電圧が印加されている時における導通損失とが等しくなる電流値が予め測定されて、電流しきい値として設定されている、
    　請求項１記載の駆動制御装置。     Based on the current detection signal, the current of the semiconductor element flowing in the forward direction of the diode structure is determined to be equal to or greater than a current threshold during a period in which an ON command signal is input to the semiconductor element to be driven and controlled. Then, it further comprises second control means (26) for outputting a gate drive signal for commanding the interruption of the gate drive voltage,
    The second control means is configured to cause the current of the semiconductor element that flows in the forward direction of the diode structure based on the current detection signal during a period in which an ON command signal is input to the semiconductor element to be driven and controlled, to the current direction. If it is determined that it is less than the threshold value, a gate drive signal for instructing application of the gate drive voltage is output,
    When a current flows through the semiconductor element in the forward direction of the diode structure, the conduction loss when the gate drive voltage is cut off is equal to the conduction loss when the gate drive voltage is applied. The current value is measured in advance and set as the current threshold,
    The drive control apparatus according to claim 1.
  3. 　前記第２の制御手段（２６）は、駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記半導体素子に前記ダイオード構造の順方向の向きに前記電流しきい値未満の電流が流れていると判定すると、前記ゲート駆動電圧の印加を指令するゲート駆動信号を、当該半導体素子に対するオフ指令信号の入力時点を越えて前記第２時間の経過時点まで延長して出力する請求項２記載の駆動制御装置。 The second control means (26) has a current less than the current threshold in the forward direction of the diode structure in the semiconductor element during a period in which an ON command signal for the semiconductor element to be driven is input. 3. When it is determined that the current is flowing, a gate drive signal for instructing application of the gate drive voltage is output after being extended from the input time point of the off command signal to the semiconductor element to the time point of the second time. The drive control apparatus described.
  4. 　駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力し、当該期間において前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定すると、前記ゲート駆動電圧の印加を指令するゲート駆動信号を、当該半導体素子に対するオフ指令信号の入力時点を越えて前記第２時間の経過時点まで延長して出力する第２の制御手段（２６）をさらに備えている請求項１記載の駆動制御装置。 A gate drive signal for commanding application of the gate drive voltage is output during a period in which an ON command signal is input to the semiconductor element to be driven and controlled, and current is supplied to the semiconductor element in the forward direction of the diode structure during the period. If it is determined that the current flows, the gate drive signal for instructing the application of the gate drive voltage is output after being extended to the time when the second time elapses after the input time of the off command signal to the semiconductor element. The drive control apparatus according to claim 1, further comprising a control means (26).
  5. 　ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造（５）とダイオード構造（６）とが同一の半導体基板（８）に形成され、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通（１５，１８）とされた半導体素子（１Ａ，１Ｂ）の駆動制御装置（３２Ａ，３２Ｂ，５２，５４，５６，６１，６２，７１，７２）であって、
    　前記半導体素子に流れる電流に応じた電流検出信号を出力する電流検出手段（７Ａ，７Ｂ，２５，５９，６０，６８）と、
    　前記半導体素子に対するオン指令信号が入力されている期間、前記電流検出信号に基づいて、前記ダイオード構造の順方向の向きに流れる前記半導体素子の電流が前記電流しきい値以上であると判定すると、前記ゲート駆動電圧の遮断を指令するゲート駆動信号を出力する第２の制御手段（２６）とを備えており、
    　第２の制御手段は、前記半導体素子に対するオン指令信号が入力されている期間、前記電流検出信号に基づいて、前記ダイオード構造の順方向の向きに流れる前記半導体素子の電流が前記電流しきい値未満であると判定すると、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力し、
    　前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れる場合において、前記ゲート駆動電圧が遮断されている時における導通損失と前記ゲート駆動電圧が印加されている時における導通損失とが等しくなる電流値が予め測定されて、電流しきい値として設定されている、
    　駆動制御装置。     An insulated gate transistor structure (5) to which a gate driving voltage is applied and a diode structure (6) are formed on the same semiconductor substrate (8), and the conducting electrode of the transistor structure and the conducting electrode of the diode structure are A drive control device (32A, 32B, 52, 54, 56, 61, 62, 71, 72) of the semiconductor elements (1A, 1B) that are made common (15, 18),
    Current detection means (7A, 7B, 25, 59, 60, 68) for outputting a current detection signal corresponding to the current flowing through the semiconductor element;
    When it is determined that the current of the semiconductor element that flows in the forward direction of the diode structure is greater than or equal to the current threshold value based on the current detection signal during a period in which an ON command signal is input to the semiconductor element, Second control means (26) for outputting a gate drive signal for commanding the interruption of the gate drive voltage,
    The second control means is configured such that the current of the semiconductor element that flows in the forward direction of the diode structure is based on the current detection signal during the period when the ON command signal for the semiconductor element is input. If determined to be less than, outputs a gate drive signal commanding the application of the gate drive voltage,
    When a current flows through the semiconductor element in the forward direction of the diode structure, the conduction loss when the gate drive voltage is cut off is equal to the conduction loss when the gate drive voltage is applied. The current value is measured in advance and set as the current threshold,
    Drive control device.
  6. 　前記第２の制御手段（２６）は、外部から前記電流しきい値を特定するしきい値特定信号を入力可能に構成されており、
    　前記第２の制御手段は、前記オン指令信号が入力されている期間において、入力した前記しきい値特定信号に応じた電流しきい値を前記半導体素子に流れる電流の判定に用いる請求項２、３および５の何れか一項に記載の駆動制御装置。     The second control means (26) is configured to be capable of inputting a threshold value specifying signal for specifying the current threshold value from the outside.
    The second control means uses a current threshold value corresponding to the input threshold value specifying signal for determination of a current flowing through the semiconductor element during a period in which the ON command signal is input. The drive control device according to any one of 3 and 5.
  7. 　第１の制御手段または第２の制御手段（２６，２７）の少なくとも一方は、通常制御を実行し、
    　通常制御において、第１の制御手段または第２の制御手段（２６，２７）の少なくとも一方は、前記半導体素子を通して負荷に流れる電流が規定値よりも小さい場合、駆動制御する前記半導体素子に対するオン指令信号が入力されると前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力し、
    　通常制御において、第１の制御手段または第２の制御手段（２６，２７）の少なくとも一方は、前記半導体素子を通して負荷に流れる電流が規定値よりも小さい場合、駆動制御する前記半導体素子に対するオフ指令信号が入力されると前記ゲート駆動電圧の遮断を指令するゲート駆動信号を出力する、
    　請求項１から６の何れか一項に記載の駆動制御装置。     At least one of the first control means or the second control means (26, 27) executes normal control,
    In normal control, at least one of the first control means and the second control means (26, 27) is configured to turn on an instruction to the semiconductor element to be driven and controlled when a current flowing through the semiconductor element to a load is smaller than a specified value. When a signal is input, a gate drive signal that instructs application of the gate drive voltage is output,
    In the normal control, at least one of the first control means and the second control means (26, 27) is configured to turn off the semiconductor element to be driven and controlled when the current flowing to the load through the semiconductor element is smaller than a specified value. When a signal is input, a gate drive signal for commanding the interruption of the gate drive voltage is output.
    The drive control apparatus as described in any one of Claim 1 to 6.
  8. 　前記ゲート駆動信号を入力して前記ゲート駆動電圧を出力するドライブ回路（２８）をさらに備え、
    　ドライブ回路は、前記ゲート駆動電圧に応じた耐圧を持つＩＣ（２４Ａ，２４Ｂ）で構成されている請求項１から７の何れか一項に記載の駆動制御装置。     A drive circuit (28) for inputting the gate drive signal and outputting the gate drive voltage;
    The drive control device according to any one of claims 1 to 7, wherein the drive circuit includes an IC (24A, 24B) having a withstand voltage corresponding to the gate drive voltage.
  9. 　駆動制御装置は、ハーフブリッジ回路を構成する２つの半導体素子を駆動制御し、
    　駆動制御装置は、前記ハーフブリッジ回路に加わる電源電圧に応じた耐圧を持つＩＣ（５１，５３，５５）で構成されており、
    　当該ＩＣは、前記ゲート駆動信号を入力して前記ゲート駆動電圧を出力するドライブ回路（２８）を備え、
    　前記電流検出手段（７Ａ，７Ｂ，２５，５９，６０）は、前記２つの半導体素子のうち少なくとも一方に流れる電流を検出可能に設けられ、
    　第１の制御手段または第２の制御手段（２６，２７）の少なくとも一方は、前記２つの半導体素子のうち一方の半導体素子に前記ゲート駆動電圧を印加している期間、他方の半導体素子への前記ゲート駆動電圧の印加を禁止する請求項１から７の何れか一項に記載の駆動制御装置。     The drive control device drives and controls two semiconductor elements constituting the half bridge circuit,
    The drive control device is composed of ICs (51, 53, 55) having a withstand voltage corresponding to the power supply voltage applied to the half bridge circuit,
    The IC includes a drive circuit (28) that inputs the gate drive signal and outputs the gate drive voltage,
    The current detection means (7A, 7B, 25, 59, 60) is provided to detect a current flowing in at least one of the two semiconductor elements,
    At least one of the first control means or the second control means (26, 27) applies the gate drive voltage to one of the two semiconductor elements during the period when the gate drive voltage is applied to the other semiconductor element. The drive control apparatus according to claim 1, wherein application of the gate drive voltage is prohibited.
  10. 　駆動制御装置は、ハーフブリッジ回路を構成する２つの前記半導体素子を駆動制御し、
    　駆動制御装置は、第１の制御手段または第２の制御手段（２６，２７）の少なくとも一方を提供する制御ＩＣ（２１，６３）と、前記制御ＩＣから入力したゲート駆動信号に基づいて各半導体素子に前記ゲート駆動電圧を印加する駆動ＩＣ（６５Ａ，６５Ｂ）と、前記制御ＩＣから出力されたゲート駆動信号を電気的に絶縁して前記駆動ＩＣに伝送する絶縁回路（６４Ａ，６４Ｂ）と、前記電流検出手段（７Ａ，７Ｂ，２５，５９，６０，６８）とから構成されており、
    　前記制御ＩＣは、前記２つの半導体素子のうち一方の半導体素子に前記ゲート駆動電圧を印加している期間、他方の半導体素子への前記ゲート駆動電圧の印加を禁止するゲート駆動信号を出力する請求項１から７の何れか一項に記載の駆動制御装置。     The drive control device drives and controls the two semiconductor elements constituting the half-bridge circuit,
    The drive control device includes a control IC (21, 63) that provides at least one of the first control means or the second control means (26, 27), and each semiconductor based on a gate drive signal input from the control IC. A driving IC (65A, 65B) for applying the gate driving voltage to the element; an insulating circuit (64A, 64B) for electrically insulating the gate driving signal output from the control IC and transmitting the signal to the driving IC; The current detection means (7A, 7B, 25, 59, 60, 68),
    The control IC outputs a gate drive signal for prohibiting application of the gate drive voltage to the other semiconductor element during a period in which the gate drive voltage is applied to one of the two semiconductor elements. Item 8. The drive control device according to any one of Items 1 to 7.
  11. 　前記電流検出手段（２５）は、前記制御ＩＣ（２１）により提供される請求項１０記載の駆動制御装置。 The drive control device according to claim 10, wherein the current detection means (25) is provided by the control IC (21).
  12. 　各々の半導体素子が、同一の半導体基板（８）に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造（５）とダイオード構造（６）とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通（１５，１８）である、二つの半導体素子（１０１Ａ，１０１Ｂ）の駆動制御装置（３２Ａ、３２Ｂ、５２、５４、５６、６１、６２、７１、７２）であって、
    　前記２つの半導体素子のうち少なくとも一方に流れる電流に応じた電流検出信号を出力する電流検出手段（７Ａ，７Ｂ，２５，５９，６０，６８）と、
    　前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電流検出信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、前記電流検出手段により電流検出信号の変動を検出した時点で、二つの半導体素子の間でアーム短絡が生じないようにパルスを出力させる制御手段（２６，２７）とを備え、当該時点は、前記一方の半導体素子に対するオン指令信号の入力時点（ｔ２）の前であり、
    　二つの半導体素子は、ハーフブリッジ回路（４）を構成する、
    　駆動制御装置。     Each semiconductor element has an insulated gate type transistor structure (5) and a diode structure (6) to which a gate drive voltage is applied, which are formed on the same semiconductor substrate (8). The drive control device (32A, 32B, 52, 54, 56, 61, 62, 71, 72) of the two semiconductor elements (101A, 101B), in which the electrode and the conducting electrode of the diode structure are common (15, 18). ) And
    Current detection means (7A, 7B, 25, 59, 60, 68) for outputting a current detection signal corresponding to a current flowing in at least one of the two semiconductor elements;
    When it is determined that a current flows in the forward direction of the diode structure to the one semiconductor element based on the current detection signal when an off command signal is input to the one semiconductor element, the current And a control means (26, 27) for outputting a pulse so as not to cause an arm short circuit between the two semiconductor elements when a change in the current detection signal is detected by the detection means. Before the input time point (t2) of the ON command signal to the semiconductor element,
    The two semiconductor elements constitute a half-bridge circuit (4).
    Drive control device.
  13. 　各々の半導体素子が、同一の半導体基板（８）に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造（１０５）とダイオード構造（１０６）とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通（１５，１８）である、二つの半導体素子（１０１Ａ，１０１Ｂ）の駆動制御装置（１３２Ａ，１３２Ｂ，１５２，１５４，１５６，１６２，１７２）であって、
    　一方の前記半導体素子の電極電位に基づく電圧検出信号を出力する電圧検出手段（１０７Ａ，１０７Ｂ，１２５，１６８，１８０）と、
    　前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電圧検出信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、二つの半導体素子の間でアーム短絡が生じないように前記一方の半導体素子に対するオン指令信号の入力時点（ｔ２）からパルスを出力させる制御手段（２６，２７）と、を備え、
    　二つの半導体素子は、ハーフブリッジ回路（４）を構成する、
    　駆動制御装置。     Each semiconductor element has an insulated gate type transistor structure (105) and a diode structure (106) to which a gate driving voltage is applied, which are formed on the same semiconductor substrate (8). The drive control device (132A, 132B, 152, 154, 156, 162, 172) of the two semiconductor elements (101A, 101B), in which the electrode and the conducting electrode of the diode structure are common (15, 18), ,
    Voltage detection means (107A, 107B, 125, 168, 180) for outputting a voltage detection signal based on the electrode potential of one of the semiconductor elements;
    When it is determined that a current flows in the forward direction of the diode structure in the one semiconductor element based on the voltage detection signal when an off command signal is input to the one semiconductor element, two Control means (26, 27) for outputting a pulse from an input time point (t2) of the ON command signal to the one semiconductor element so as not to cause an arm short circuit between the semiconductor elements;
    The two semiconductor elements constitute a half-bridge circuit (4).
    Drive control device.
  14. 　少なくとも一方の半導体素子に流れる電流に応じた電流検出信号を出力する電流検出手段（７Ａ，７Ｂ，２５，５９，６０，６８）と、
    　前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電流検出信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、遅延時間分だけ、前記一方の半導体素子に対するオン指令信号の入力時点（ｔ２）の前からパルスを出力させる他の制御手段（２６，２７）をさらに備え、
    　遅延時間は、前記一方の半導体素子（１０１Ａ）に電流が流れなくなり始めるタイミングと前記ゲート駆動電圧が上昇するタイミングとの間で定義されている、
    　請求項１３記載の駆動制御装置。     Current detection means (7A, 7B, 25, 59, 60, 68) for outputting a current detection signal corresponding to the current flowing through at least one semiconductor element;
    When it is determined that a current flows in the forward direction of the diode structure to the one semiconductor element based on the current detection signal when an off command signal is input to the one semiconductor element, the delay time And further includes other control means (26, 27) for outputting a pulse before the input time point (t2) of the ON command signal to the one semiconductor element,
    The delay time is defined between the timing when the current starts to flow through the one semiconductor element (101A) and the timing when the gate drive voltage rises.
    The drive control apparatus according to claim 13.
  15. 　各々の半導体素子が、同一の半導体基板（８）に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造（５）とダイオード構造（６）とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通（１５，１８）である、二つの半導体素子（１Ａ，１Ｂ）の駆動制御装置（３２Ａ，３２Ｂ，５２，５４，５６，６２，７２）であって、
    　一方の前記半導体素子に流れる電流に応じた電流検出信号を出力する電流検出手段（７Ａ，７Ｂ，２５，５９，６０，６８）と、
    　他方の前記半導体素子に対する指令信号を入力する入力手段（２６，２７）と、
    　前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電流検出信号及び前記入力手段の入力信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、前記入力手段にオフ指令信号が入力されることに応じてパルスを出力させる手段であって、二つの半導体素子の間でアーム短絡が生じないように前記一方の半導体素子に対するオン指令信号の入力時点（ｔ２）より所定時間前にパルスを出力させる制御手段（２６，２７）を備え、
    　二つの半導体素子は、ハーフブリッジ回路（４）を構成する、
    　駆動制御装置。     Each semiconductor element has an insulated gate type transistor structure (5) and a diode structure (6) to which a gate drive voltage is applied, which are formed on the same semiconductor substrate (8). The drive control device (32A, 32B, 52, 54, 56, 62, 72) of two semiconductor elements (1A, 1B), in which the electrode and the conducting electrode of the diode structure are common (15, 18), ,
    Current detection means (7A, 7B, 25, 59, 60, 68) for outputting a current detection signal corresponding to the current flowing through one of the semiconductor elements;
    Input means (26, 27) for inputting a command signal to the other semiconductor element;
    When an off command signal for the one semiconductor element is input, a current flows in the forward direction of the diode structure to the one semiconductor element based on the current detection signal and the input signal of the input means. Is determined to be a means for outputting a pulse in response to the input of an off command signal to the input means, and the on-state for the one semiconductor element is prevented so as not to cause an arm short circuit between the two semiconductor elements. Control means (26, 27) for outputting a pulse a predetermined time before the input time (t2) of the command signal;
    The two semiconductor elements constitute a half-bridge circuit (4).
    Drive control device.
  16. 　各々の半導体素子が、同一の半導体基板（８）に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造（１０５）とダイオード構造（１０６）とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通（１５，１８）である、二つの半導体素子（１０１Ａ，１０１Ｂ）の駆動制御装置（１３２Ａ，１３２Ｂ，１５２，１５４，１５６，１６２，１７２）であって、
    　一方の前記半導体素子の電極電位に基づく電圧検出信号を出力する電圧検出手段（１０７Ａ，１０７Ｂ，１２５，１６８，１８０）と、
    　他方の前記半導体素子に対する指令信号を入力する入力手段（２６，２７）と、
    　前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電圧検出信号及び前記入力手段の入力信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、前記入力手段にオフ指令信号が入力されることに応じてパルスを出力させる手段であって、二つの半導体素子の間でアーム短絡が生じないように前記一方の半導体素子に対するオン指令信号の入力時点（ｔ２）より所定時間前にパルスを出力させる制御手段（２６，２７）を備え、
    　二つの半導体素子は、ハーフブリッジ回路（４）を構成する、
    　駆動制御装置。     Each semiconductor element has an insulated gate type transistor structure (105) and a diode structure (106) to which a gate driving voltage is applied, which are formed on the same semiconductor substrate (8). The drive control device (132A, 132B, 152, 154, 156, 162, 172) of the two semiconductor elements (101A, 101B), in which the electrode and the conducting electrode of the diode structure are common (15, 18), ,
    Voltage detection means (107A, 107B, 125, 168, 180) for outputting a voltage detection signal based on the electrode potential of one of the semiconductor elements;
    Input means (26, 27) for inputting a command signal to the other semiconductor element;
    When an off command signal for the one semiconductor element is input, a current flows in the forward direction of the diode structure to the one semiconductor element based on the voltage detection signal and the input signal of the input means. Is determined to be a means for outputting a pulse in response to the input of an off command signal to the input means, and the on-state for the one semiconductor element is prevented so as not to cause an arm short circuit between the two semiconductor elements. Control means (26, 27) for outputting a pulse a predetermined time before the input time (t2) of the command signal;
    The two semiconductor elements constitute a half-bridge circuit (4).
    Drive control device.
  17. 　他方の前記半導体素子の制御電圧に応じた制御電圧検出信号を出力する制御電圧検出手段（２２５）をさらに備え、
    　前記制御手段は、前記制御電圧検出手段（２２５）の制御電圧検出信号の変動に基づいてパルスを出力させる請求項１２、１４、１５の何れか一項に記載の駆動制御装置。     Control voltage detection means (225) for outputting a control voltage detection signal corresponding to the control voltage of the other semiconductor element,
    The drive control apparatus according to any one of claims 12, 14, and 15, wherein the control means outputs a pulse based on a fluctuation of a control voltage detection signal of the control voltage detection means (225).
  18. 　各々の半導体素子が、同一の半導体基板（８）に形成された、ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造（５）とダイオード構造（６）とを有し、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通（１５，１８）である、二つの半導体素子（１０１Ａ，１０１Ｂ）の駆動制御装置（１３２Ａ，１３２Ｂ，１５２，１５４，１５６，１６２，１７２）であって、
    　少なくとも一方の半導体素子の電極電位に応じた電圧検出信号を出力する電圧検出手段（１０７Ａ，１０７Ｂ，１２５，１６８，１８０）と、
    　前記一方の半導体素子に対するオフ指令信号が入力されているときに前記電圧検出信号に基づいて前記一方の半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、その後にオン指令信号の入力を経てオフ指令信号が入力された時点を起点として、第１時間の経過時点から第２時点の経過時点まで、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する制御手段（２６，２７）と、を備え、
    　第1時間と第2時間は、二つの半導体素子の間でアーム短絡が生じないように予め設定されており、
    　二つの半導体素子は、ハーフブリッジ回路（４）を構成する、
    　駆動制御装置。     Each semiconductor element has an insulated gate type transistor structure (5) and a diode structure (6) to which a gate drive voltage is applied, which are formed on the same semiconductor substrate (8). The drive control device (132A, 132B, 152, 154, 156, 162, 172) of the two semiconductor elements (101A, 101B), in which the electrode and the conducting electrode of the diode structure are common (15, 18), ,
    Voltage detection means (107A, 107B, 125, 168, 180) for outputting a voltage detection signal corresponding to the electrode potential of at least one semiconductor element;
    When it is determined that a current flows in the forward direction of the diode structure to the one semiconductor element based on the voltage detection signal when the off command signal for the one semiconductor element is input, Control that outputs a gate drive signal for instructing application of the gate drive voltage from the time point at which the first time has elapsed to the time point at which the second time point has elapsed, starting from the time point when the off command signal is input through the input of the on command signal Means (26, 27),
    The first time and the second time are set in advance so as not to cause an arm short circuit between the two semiconductor elements,
    The two semiconductor elements constitute a half bridge circuit (4).
    Drive control device.
  19. 　前記制御手段（２６，２７）は、前記電圧検出部により電圧が変動したか否かを判定することで負荷に流れる電流を判定し、
    　前記制御手段（２６，２７）は、前記負荷の電流が０付近の所定範囲であると判定すると、前記ゲート駆動電圧の遮断を指令するゲート駆動信号を出力し、
    　前記制御手段（２６，２７）は、前記負荷の電流が０付近の所定範囲外であると判定すると前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する請求項１３、１６、１８の何れか１項に記載の駆動制御装置。     The control means (26, 27) determines the current flowing through the load by determining whether or not the voltage has been changed by the voltage detection unit,
    When the control means (26, 27) determines that the load current is within a predetermined range near 0, the control means (26, 27) outputs a gate drive signal for commanding the interruption of the gate drive voltage,
    The control means (26, 27) outputs a gate drive signal for instructing application of the gate drive voltage when the load current is determined to be outside a predetermined range near zero. The drive control apparatus according to claim 1.
  20. 　前記制御手段（２６，２７）は、駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記電圧検出信号に基づいて前記ダイオード構造の順方向の向きに流れていると判定すると、前記ゲート駆動電圧の遮断を指定するゲート駆動信号を出力し、
    　前記制御手段（２６，２７）は、駆動制御する前記半導体素子に対するオン指令信号が入力されている期間、前記電圧検出信号に基づいて前記ダイオード構造の順方向の向きに流れていないと判定すると、前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する請求項１８または１９記載の駆動制御装置。     When the control means (26, 27) determines that the current flows in the forward direction of the diode structure based on the voltage detection signal during a period in which an ON command signal is input to the semiconductor element to be driven and controlled, Outputting a gate drive signal designating the interruption of the gate drive voltage;
    When the control means (26, 27) determines that it does not flow in the forward direction of the diode structure based on the voltage detection signal during the period when the ON command signal for the semiconductor element to be driven is input. The drive control device according to claim 18 or 19, wherein a gate drive signal for commanding application of the gate drive voltage is output.
  21. 　前記ゲート駆動信号を入力して前記ゲート駆動電圧を出力するドライブ回路（２８）をさらに備え、
    　ドライブ回路（２８）は、前記ゲート駆動電圧に応じた耐圧を持つＩＣ（１２４Ａ，１２４Ｂ）で構成されている請求項１８から２０の何れか一項に記載の駆動制御装置。     A drive circuit (28) for inputting the gate drive signal and outputting the gate drive voltage;
    The drive control device according to any one of claims 18 to 20, wherein the drive circuit (28) includes an IC (124A, 124B) having a withstand voltage corresponding to the gate drive voltage.
  22. 　駆動制御装置は、ハーフブリッジ回路を構成する２つの前記半導体素子を駆動制御し、
    　駆動制御装置は、は、前記ハーフブリッジ回路に加わる電源電圧に応じた耐圧を持つＩＣ（１５１，１５３）で構成されており、
    　当該ＩＣは、前記ゲート駆動信号を入力して前記ゲート駆動電圧を出力するドライブ回路（２８）を提供し、
    　前記電圧検出手段（１０７Ａ，１０７Ｂ，１２５，１８０）は、前記２つの半導体素子のうち少なくとも一方の電圧を検出可能に設けられ、
    　前記制御手段（２６，２７）は、前記２つの半導体素子のうち一方の半導体素子に前記ゲート駆動電圧を印加している期間、他方の半導体素子への前記ゲート駆動電圧の印加を禁止する請求項１８から２１の何れか一項に記載の駆動制御装置。     The drive control device drives and controls the two semiconductor elements constituting the half-bridge circuit,
    The drive control device is composed of ICs (151, 153) having a withstand voltage corresponding to the power supply voltage applied to the half-bridge circuit,
    The IC provides a drive circuit (28) that inputs the gate drive signal and outputs the gate drive voltage;
    The voltage detection means (107A, 107B, 125, 180) is provided so as to detect at least one voltage of the two semiconductor elements,
    The control means (26, 27) prohibits application of the gate drive voltage to the other semiconductor element during a period in which the gate drive voltage is applied to one of the two semiconductor elements. The drive control device according to any one of 18 to 21.
  23. 　駆動制御装置は、ハーフブリッジ回路を構成する２つの前記半導体素子を駆動制御し、
    　駆動制御装置は、前記制御手段（２６，２７）を有する制御ＩＣ（２１，１２１，１６３）と、前記制御ＩＣから入力したゲート駆動信号に基づいて前記半導体素子に前記ゲート駆動電圧を印加する駆動ＩＣ（６５Ａ，６５Ｂ）と、前記制御ＩＣから出力されたゲート駆動信号を電気的に絶縁して前記駆動ＩＣに伝送する絶縁回路（６４Ａ，６４Ｂ）と、前記電圧検出手段（１０７Ａ，１０７Ｂ，１２５，１６８）とから構成されており、
    　前記制御ＩＣは、前記２つの半導体素子のうち一方の半導体素子に前記ゲート駆動電圧を印加している期間、他方の半導体素子への前記ゲート駆動電圧の印加を禁止するゲート駆動信号を出力する請求項１８から２１の何れか一項に記載の駆動制御装置。     The drive control device drives and controls the two semiconductor elements constituting the half-bridge circuit,
    The drive control device includes a control IC (21, 121, 163) having the control means (26, 27) and a drive for applying the gate drive voltage to the semiconductor element based on a gate drive signal input from the control IC. IC (65A, 65B), an insulating circuit (64A, 64B) for electrically insulating and transmitting the gate drive signal output from the control IC to the drive IC, and the voltage detection means (107A, 107B, 125) , 168), and
    The control IC outputs a gate drive signal for prohibiting application of the gate drive voltage to the other semiconductor element during a period in which the gate drive voltage is applied to one of the two semiconductor elements. Item 22. The drive control device according to any one of Items 18 to 21.
  24. 　前記電圧検出手段（１２５）は、前記制御ＩＣ（１２１）により提供されている請求項２３記載の駆動制御装置。 24. The drive control device according to claim 23, wherein the voltage detection means (125) is provided by the control IC (121).
  25. 　前記電圧検出手段（１８０）は、前記半導体素子の素子形成領域（１００）の外周側に離間して半導体基板（８）に形成され、
    　前記電圧検出手段（１８０）は、前記半導体基板（８）の導電型とは逆導電型の電界制限リング（８ａ）を用いて中間電位を検出する請求項１８から２４の何れか一項に記載の駆動制御装置。     The voltage detecting means (180) is formed on the semiconductor substrate (8) so as to be separated from the outer peripheral side of the element formation region (100) of the semiconductor element,
    25. The voltage detection means (180) detects an intermediate potential using an electric field limiting ring (8a) having a conductivity type opposite to the conductivity type of the semiconductor substrate (8). Drive control device.
  26. 　前記第１時間と前記第２時間との時間幅は、前記半導体素子に対するオン指令信号が入力されている期間に前記半導体素子に流れていた電流の大きさに応じた値に設定されている請求項１から３、６から１１、１８から２５の何れか一項に記載の駆動制御装置。 The time width between the first time and the second time is set to a value corresponding to the magnitude of current flowing in the semiconductor element during a period in which an ON command signal for the semiconductor element is input. Item 26. The drive control device according to any one of Items 1 to 3, 6 to 11, and 18 to 25.
  27. 　当該半導体素子は、一方の半導体素子と他方の半導体素子を含み、
    　一方の半導体素子と他方の半導体素子は、ハーフブリッジ回路を構成し、
    　前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れている状態でオフ指令信号が入力された後、一定のデッドタイムを経て、他方の半導体素子に対してオン指令信号が入力されたときに、前記第２時間が経過して前記ゲート駆動電圧が遮断された時点と、前記他方の半導体素子のトランジスタ構造に当該一方の半導体素子に流れていた電流を超える電流が流れ始める時点との時間幅が、ゼロより大きく且つ所定の注入許容時間以下となるように、前記第１時間と前記第２時間が設定されている請求項１から３、６から１１、１８から２５の何れか一項に記載の駆動制御装置。     The semiconductor element includes one semiconductor element and the other semiconductor element,
    One semiconductor element and the other semiconductor element constitute a half-bridge circuit,
    After an off command signal is input to the semiconductor element in a state where a current flows in the forward direction of the diode structure, an on command signal is input to the other semiconductor element after a certain dead time. Sometimes, when the gate drive voltage is cut off after the second time has elapsed, and when a current exceeding the current flowing in the one semiconductor element starts flowing in the transistor structure of the other semiconductor element. The first time and the second time are set such that the time width is greater than zero and less than or equal to a predetermined permissible injection time. The drive control device according to item.
  28. 　前記第１時間と第２時間との時間幅は、前記半導体素子に対するオン指令信号が入力されている期間に当該半導体素子に流れていた電流が大きいほど長い時間となるように設定されている請求項１から３、６から１１、１８から２５の何れか一項に記載の駆動制御装置。 The time width between the first time and the second time is set so as to become longer as the current flowing through the semiconductor element increases during a period in which the ON command signal for the semiconductor element is input. Item 26. The drive control device according to any one of Items 1 to 3, 6 to 11, and 18 to 25.
  29. 　前記ゲート駆動信号に基づく前記ゲート駆動電圧が、前記ドライブ回路のゲート駆動能力に従って単調に増加または単調に減少するものとして、前記第１時間と前記第２時間が設定されている請求項１から２８の何れか一項に記載の駆動制御装置。 29. The first time and the second time are set on the assumption that the gate drive voltage based on the gate drive signal monotonously increases or monotonously decreases according to the gate drive capability of the drive circuit. The drive control device according to any one of the above.
  30. 　前記ゲート駆動信号に基づく前記ゲート駆動電圧にミラー期間が生じないものとして、前記第１時間と前記第２時間が設定されている請求項１から２８の何れか一項に記載の駆動制御装置。 The drive control device according to any one of claims 1 to 28, wherein the first time and the second time are set so that a mirror period does not occur in the gate drive voltage based on the gate drive signal.
  31. 　前記ドライブ回路は、前記ゲート駆動信号が変化したときに、一定のゲート駆動能力を維持して前記ゲート駆動電圧を出力する請求項１から２８の何れか一項に記載の駆動制御装置。 The drive control device according to any one of claims 1 to 28, wherein the drive circuit outputs the gate drive voltage while maintaining a constant gate drive capability when the gate drive signal changes.
  32. 　前記ドライブ回路は、前記ゲート駆動信号が変化したとき、前記半導体素子を通断電するときに比べ高い駆動能力で前記ゲート駆動電圧を出力する請求項１から２８の何れか一項に記載の駆動制御装置。 The drive according to any one of claims 1 to 28, wherein when the gate drive signal changes, the drive circuit outputs the gate drive voltage with a higher drive capability than when the semiconductor element is cut off. Control device.
  33. 　ゲート駆動電圧が印加される絶縁ゲート型のトランジスタ構造（１００５）とダイオード構造（１００６）とが同一の半導体基板（１００８）に形成され、前記トランジスタ構造の通電電極と前記ダイオード構造の通電電極とが共通の電極（１０１５，１０１８）とされた半導体素子（１００１Ａ，１００１Ｂ）の駆動制御装置（１０３８Ａ，１０３８Ｂ）であって、
    　前記半導体素子に流れる電流に応じた電流検出信号を出力する電流検出手段（１００７Ａ，１００７Ｂ，１０２５）と、
    　前記電流検出信号に基づいて、前記半導体素子に対するオン指令信号が入力されている期間に前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れていると判定した場合、その後のオフ指令信号の入力時点を起点として、予め設定された第１時間の経過時点から第２時間の経過時点まで前記ゲート駆動電圧の印加を指令するゲート駆動信号を出力する制御手段（１０２７）と、
    　前記ゲート駆動信号を入力して前記ゲート駆動電圧を出力するドライブ回路（１０２８）とを備え、
    　前記第１時間と前記第２時間との時間幅は、前記半導体素子に対するオン指令信号が入力されている期間に前記半導体素子に流れていた電流の大きさに応じた値に設定されている駆動制御装置。     An insulated gate transistor structure (1005) to which a gate driving voltage is applied and a diode structure (1006) are formed on the same semiconductor substrate (1008), and the conduction electrode of the transistor structure and the conduction electrode of the diode structure are A drive control device (1038A, 1038B) for semiconductor elements (1001A, 1001B), which are common electrodes (1015, 1018),
    Current detection means (1007A, 1007B, 1025) for outputting a current detection signal corresponding to the current flowing through the semiconductor element;
    On the basis of the current detection signal, when it is determined that a current flows in the forward direction of the diode structure in the semiconductor element during a period in which an ON command signal for the semiconductor element is input, a subsequent OFF command signal A control means (1027) for outputting a gate drive signal for instructing application of the gate drive voltage from the preset time point of the first time to the time point of the second time, starting from the input time point of
    A drive circuit (1028) for inputting the gate drive signal and outputting the gate drive voltage;
    The time width between the first time and the second time is set to a value corresponding to the magnitude of the current flowing in the semiconductor element during the period when the ON command signal for the semiconductor element is input Control device.
  34. 　当該半導体素子は、一方の半導体素子と他方の半導体素子を含み、
    　一方の半導体素子と他方の半導体素子は、ハーフブリッジ回路を構成し、
    　前記半導体素子に前記ダイオード構造の順方向の向きに電流が流れている状態でオフ指令信号が入力された後、一定のデッドタイムを経て、他方の半導体素子に対してオン指令信号が入力されたときに、前記第２時間が経過して前記ゲート駆動電圧が遮断された時点と、前記他方の半導体素子のトランジスタ構造に当該一方の半導体素子に流れていた電流を超える電流が流れ始める時点との時間幅が、ゼロより大きく且つ所定の注入許容時間以下となるように、前記第１時間と前記第２時間が設定されている請求項３３記載の駆動制御装置。     The semiconductor element includes one semiconductor element and the other semiconductor element,
    One semiconductor element and the other semiconductor element constitute a half-bridge circuit,
    After an off command signal is input to the semiconductor element in a state where a current flows in the forward direction of the diode structure, an on command signal is input to the other semiconductor element after a certain dead time. Sometimes, when the gate drive voltage is cut off after the second time has elapsed, and when a current exceeding the current flowing in the one semiconductor element starts flowing in the transistor structure of the other semiconductor element. 34. The drive control device according to claim 33, wherein the first time and the second time are set so that a time width is greater than zero and equal to or less than a predetermined allowable injection time.
  35. 　前記第１時間と第２時間との時間幅は、前記半導体素子に対するオン指令信号が入力されている期間に当該半導体素子に流れていた電流が大きいほど長い時間となるように設定されている請求項３３または３４記載の駆動制御装置。 The time width between the first time and the second time is set so as to become longer as the current flowing through the semiconductor element increases during a period in which the ON command signal for the semiconductor element is input. Item 35. The drive control device according to Item 33 or 34.
  36. 　前記第１時間の経過時点から第２時間の経過時点まで出力されるゲート駆動信号に基づく前記ゲート駆動電圧が、前記ドライブ回路のゲート駆動能力に従って単調に増加または単調に減少するものとして、前記第１時間と前記第２時間が設定されている請求項３３から３５の何れか一項に記載の駆動制御装置。 The gate drive voltage based on the gate drive signal output from the elapse of the first time to the elapse of the second time is assumed to monotonously increase or monotonously decrease according to the gate drive capability of the drive circuit. 36. The drive control apparatus according to any one of claims 33 to 35, wherein one hour and the second time are set.
  37. 　前記第１時間の経過時点から第２時間の経過時点まで出力されるゲート駆動信号に基づく前記ゲート駆動電圧にミラー期間が生じないものとして、前記第１時間と前記第２時間が設定されている請求項３６記載の駆動制御装置。 The first time and the second time are set so that a mirror period does not occur in the gate drive voltage based on the gate drive signal output from the time point of the first time to the time point of the second time. 37. The drive control device according to claim 36.
  38. 　前記ドライブ回路は、前記第１時間の経過時点で前記ゲート駆動信号が変化したときに、一定のゲート駆動能力を維持して前記ゲート駆動電圧を出力する請求項３６または３７記載の駆動制御装置。 38. The drive control apparatus according to claim 36 or 37, wherein the drive circuit outputs the gate drive voltage while maintaining a constant gate drive capability when the gate drive signal changes at the time point of the first time.
  39. 　前記ドライブ回路は、前記第１時間の経過時点および前記第２時間の経過時点で前記ゲート駆動信号が変化したとき、前記半導体素子を通断電するときに比べ高い駆動能力で前記ゲート駆動電圧を出力する請求項３３から３８の何れか一項に記載の駆動制御装置。 The drive circuit generates the gate drive voltage with a higher drive capability when the gate drive signal changes at the elapse of the first time and the elapse of the second time than when the semiconductor element is disconnected. The drive control apparatus according to any one of claims 33 to 38, which outputs the drive control apparatus.
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Publication number Priority date Publication date Assignee Title
WO2023138161A1 (en) * 2022-01-24 2023-07-27 比亚迪股份有限公司 Low-side driving circuit, electronic device having same, and vehicle

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009268336A (en) * 2007-09-05 2009-11-12 Denso Corp Semiconductor device
JP2010154595A (en) * 2008-12-24 2010-07-08 Denso Corp Power conversion device
JP2014117044A (en) * 2012-12-07 2014-06-26 Toyota Motor Corp Over current detection device and semiconductor driving apparatus with the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009268336A (en) * 2007-09-05 2009-11-12 Denso Corp Semiconductor device
JP2010154595A (en) * 2008-12-24 2010-07-08 Denso Corp Power conversion device
JP2014117044A (en) * 2012-12-07 2014-06-26 Toyota Motor Corp Over current detection device and semiconductor driving apparatus with the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023138161A1 (en) * 2022-01-24 2023-07-27 比亚迪股份有限公司 Low-side driving circuit, electronic device having same, and vehicle

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