JP6122542B1 - Active clamp circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an element breakdown of a power MOSFET or an IGBT module by suppressing an increase in drain voltage or collector voltage at the time of turn-off and suppressing an excessive increase in gate voltage. An IGBT collector terminal is a cathode terminal of a first Zener diode Dz1, a gate terminal is a positive output terminal of a drive circuit, a cathode terminal of a first diode D1, an emitter terminal is a negative output terminal of the drive circuit, and a second output terminal. The cathode terminal of the diode D2 is connected, the drain terminal of the FET Q1 is connected to the anode terminal of the first Zener diode Dz1, the source terminal of the FET Q1 is connected to the anode terminal of the first diode D1, and the second Zener diode Dz2 is connected to the anode terminal of the second diode D2. An active clamp circuit in which an anode terminal is connected, a gate terminal and a drain terminal of FETQ1 are connected via a resistor R1, and a gate terminal of FETQ1 and a cathode terminal of a second Zener diode Dz2 are connected. [Selection] Figure 1

Description

  The present invention is a voltage drive type represented by a large current type insulated gate bipolar transistor (hereinafter referred to as “IGBT”), a MOS field effect transistor (hereinafter referred to as “MOSFET”), and the like used in a power conversion device and the like. The present invention relates to an active clamp circuit that suppresses a voltage rise at a collector terminal or a drain terminal when an element is turned off.

Conventionally, as shown in FIG. 6, a simple active clamp circuit in which a series circuit of a Zener diode DZ1 and a diode D1 is connected between the collector and gate of the IGBT is generally used.
In this active clamp circuit, when the IGBT is driven off and the current flowing in the load is cut off, a surge voltage is generated between the collector terminal and the emitter terminal of the IGBT due to the floating inductance of the power supply line.
When this surge voltage exceeds the sum of the forward voltages of the Zener diode DZ1 and the diode D1, a current flows from the collector of the IGBT to the gate to turn on the IGBT, thereby limiting the surge voltage to a predetermined voltage and stray inductance to the IGBT. Energy can be absorbed.
However, since the energy of the stray inductance is large and the response speed of the element itself tends to be slow for a high withstand voltage and high current type element with a withstand voltage of 1200 V or higher, the effect of limiting the surge voltage of the collector voltage is effective. By the time it appeared, the gate voltage of the device was increased too much, and there was a high possibility of destruction exceeding the maximum gate voltage rating.

Patent Document 1 (Japanese Patent No. 4343897) discloses an active clamp circuit shown in FIG. 7 (see in particular FIG. 2 and paragraphs 0017 to 0018).
In this active clamp circuit, the cathode terminal of the constant voltage diode (Z1) is connected to the drain terminal of the power MOSFET (51), the cathode terminal of the reverse blocking diode (D1) is connected to the gate terminal, and the anode terminal of the constant voltage diode (Z1). The semiconductor switch circuit (11) controlled by the gate-source voltage of the power MOSFET (51) is connected between the anode terminal of the reverse blocking diode (D1).
The semiconductor switch circuit (11) has a multi-stage configuration of a MOSFET (Q2) and a pnp type transistor (Q1), and the emitter terminal of the output stage transistor (Q1) is connected to the anode terminal of the constant voltage diode (Z1). The collector terminal is connected to the anode terminal of the reverse blocking diode (D1). In addition, a resistor (R1) and a resistor (R2) are connected to the base terminal of the transistor (Q1), the other end of the resistor (R1) is connected to the emitter terminal of the transistor (Q1), and the other end of the resistor (R2) is a MOSFET. The source terminal of the MOSFET (Q2) is connected to the source terminal of the power MOSFET (51), and the gate terminal is connected to the gate terminal of the power MOSFET (51).

FIG. 8 schematically shows an example of the waveform of each part until the power MOSFET (51) driven by the gate drive circuit (31) of FIG. 7 shifts from the on state to the off state.
Vgs (51), Vds (51), and Id (51) indicate the gate-source voltage, drain-source voltage, and drain current of the power MOSFET 51, respectively, and If (D1) is the reverse blocking diode ( The forward current Vgs (Q2) of D1) indicates the gate-source voltage (= Vgs (51)) of the MOSFET (Q2).

In paragraphs 0020 to 0024 of Patent Document 1, the states of sections A to G are described as follows.
Section A: Based on the ON command from the control circuit (41), the gate driver (21) turns on the power MOSFET (51), and the forward current (from the drain to the source) is shown from the DC power supply (not shown). In this state, the current flows via the parasitic inductance Ldc of the DC power supply line. At this time, the MOSFET (Q2) is in the ON state, but Vds (51) is sufficiently smaller than the breakdown voltage (ON threshold voltage) of the constant voltage diode (Z1). Turns off. The reverse blocking diode (D1) prevents current from flowing through the semiconductor switch circuit (11).
Section B: A turn-off command is output from the control circuit (41), and the gate driver 21 is turned off accordingly, so that Vgs (51) starts to decrease, but switching does not occur until the voltage near the on-threshold value is reached. Absent.
Section C: When Vgs (51) reaches a voltage in the vicinity of the ON threshold value, Vds (51) rises as the on-resistance of the power MOSFET 51 rises rapidly, and Vgs (51) at this time The rate of decrease suddenly decreases due to the mirror effect, and changes almost flat.
Section D: When Vds (51) exceeds the voltage of the DC power supply, Id (51) starts decreasing. A surge voltage determined by multiplying the decrease rate of Id (51) by the parasitic inductance Ldc of the DC power supply line is generated in Vds (51).

Section E: When the surge voltage of Vds (51) reaches the sum of the breakdown voltage of the constant voltage diode (Z1), the forward voltage of the reverse blocking diode (D1) and the current Vgs (51), MOSFET (Q2 ) Is still on. Therefore, the breakdown current of the constant voltage diode (Z1) flows to the base of the transistor (Q1) through the MOSFET (Q2), the transistor (Q1) is turned on, and Id (51) from the drain to the gate of the power MOSFET (51). If (D1) flows so as to adjust the decrease rate of Vgs (51) so that the decrease rate of Vgs becomes constant, an equilibrium state is reached. As a result, the surge voltage due to the parasitic inductance Ldc of the DC power supply line is limited to a predetermined value determined by the breakdown voltage of the constant voltage diode (Z1).
Section F: When the Id (51) becomes zero and all the parasitic inductance energy of the DC power supply line consumed by the turn-off of the power MOSFET (51) is absorbed by the power MOSFET (51), the power MOSFET (51) is completely Will be off. At this time, Vds (51) falls to the voltage of the DC power supply and falls below the breakdown voltage of the constant voltage diode (Z1). Therefore, both If (D1) and the base current of the transistor (Q1) become zero, and the transistor (Q1) has a resistance ( Turned off by R1). Thereafter, when Vgs (Q2) decreases and falls below the ON threshold, the MOSFET (Q2) is also turned off.
Section G: Based on the OFF signal from the control circuit (41), the gate driver 21 maintains the OFF state of the power MOSFET (51) via the gate resistor Rg. Further, since the MOSFET (Q2) is also kept off by the gate driver (21), the transistor (Q1) is also kept off. Therefore, in this interval, if (D1) does not flow even if Vds (51) exceeds the breakdown voltage of the constant voltage diode (Z1), the power MOSFET (51) is turned on to absorb the energy of the surge voltage. No action is taken.

Incidentally, in FIG. 8, Vgs (51) is drawn so as to gradually decrease in the section E, and the breakdown current of the constant voltage diode (Z1) flows to the base of the transistor (Q1) via the MOSFET (Q2) and flows into the transistor (Q1 ) Is turned on, and If (D1) for adjusting the decrease rate of Vgs (51) flows from the drain to the gate of the power MOSFET 51 so that the decrease rate of Id (51) becomes constant, the equilibrium state It is explained that it becomes.
However, when the power MOSFET (51) is a high current type with a high breakdown voltage, the power MOSFET (51) self-consumes the energy of the surge voltage after the surge voltage of Vds (51) is generated, and the drain voltage is reduced. Since there is a reaction delay until the effect of suppressing the increase appears, the gate voltage may increase excessively for a short time.
Such a phenomenon also occurs in the IGBT having the active clamp circuit shown in FIG.
In general power MOSFETs and IGBT modules, the maximum rating of the gate voltage is 20 to 30V, and most of the commercially available IGBT modules are guaranteed only up to 20V. The IGBT or the like provided with the active clamp circuit shown in FIG. 7 has a problem that there is a high possibility that element destruction will occur due to excessive rise of the gate voltage at the time of turn-off.

Japanese Patent No. 4343897

  The present invention relates to an active clamp circuit operation that suppresses a voltage rise of a drain terminal or a collector terminal at the time of turn-off of a voltage driven element represented by a power MOSFET, an IGBT module, etc., and when the active clamp circuit operates, The object is to prevent element destruction due to excessive rise of the gate voltage.

The invention according to claim 1 is an active clamp circuit that suppresses a voltage rise at the collector terminal or the drain terminal at the time of turn-off of the voltage-driven element,
The collector terminal or drain terminal of the voltage-driven element and the drain terminal of the N-channel MOSFET are connected via a unidirectional or bidirectional first Zener diode, and the gate terminal of the voltage-driven element is connected to the gate terminal of the voltage-driven element. A positive output terminal is connected, a cathode terminal of the first diode is connected, and a negative output terminal of the drive circuit is connected to an emitter terminal or a source terminal of the voltage driven element,
A gate terminal and a drain terminal of the N-channel MOSFET are connected via a first resistor, and a source terminal of the N-channel MOSFET is connected to an anode terminal of the first diode;
An emitter terminal or a source terminal of the voltage-driven element and a gate terminal of the N-channel MOSFET are connected via a one-way type second Zener diode and a second diode;
A gate resistor is connected between the gate terminal of the voltage-driven element and the positive output terminal, or an emitter resistor is connected between the emitter terminal or source terminal of the voltage-driven element and the negative output terminal. It is an active clamp circuit characterized by being connected.

  The invention according to claim 2 is the active clamp circuit according to claim 1, wherein a gate terminal and a source terminal of the N-channel MOSFET are connected via a capacitor, or a gate terminal of the N-channel MOSFET and the gate terminal of the N-channel MOSFET The second Zener diode or the second diode is connected via a second resistor, or the source terminal of the N-channel MOSFET and the second Zener diode or the second diode are connected via a third resistor. It is characterized by being.

  The invention according to claim 3 is the active clamp circuit according to claim 1 or 2, wherein the first Zener diode or the second Zener diode is formed by connecting a plurality of Zener diodes in series. .

  According to a fourth aspect of the present invention, in the active clamp circuit according to any one of the first to third aspects, a bidirectional type zener diode is used instead of the second zener diode and the second diode. To do.

  According to the first aspect of the present invention, the rise of the drain voltage or the collector voltage at the time of turn-off of the voltage driven element is suppressed by the operation of the active clamp circuit with a relatively simple configuration. It is possible to suppress an excessive increase in the gate voltage, and to prevent the element from being destroyed.

  According to the invention of claim 2, in addition to the effect of the active clamp circuit of the invention of claim 1, it is possible to prevent the oscillation of the N-channel MOSFET and to improve the stability of the active clamp circuit operation. .

  According to the invention of claim 3, in addition to the effect of the active clamp circuit of the invention of claim 1 or 2, even when only a Zener diode having a small Zener voltage can be procured, a desired active clamp circuit can be manufactured. .

  According to the invention of claim 4, in addition to the effect of the active clamp circuit of the invention of any one of claims 1 to 3, the number of elements can be reduced by using a bidirectional type zener diode.

FIG. 3 is a diagram illustrating a configuration of an active clamp circuit according to the first embodiment. The graph which shows an example of the waveform of each part in the circuit of Example 1 at the time of turn-off. The graph which shows an example of the waveform of each part in the circuit shown in FIG. 6 at the time of turn-off. An equivalent circuit of a device that controls a three-phase motor using six gate drive circuits. FIG. 6 is a diagram illustrating an example of a modification of the active clamp circuit according to the first embodiment. The figure which shows the active clamp circuit in a prior art. The figure which shows the active clamp circuit in patent document 1. FIG. The graph which shows an example of the waveform of each part in the circuit shown in FIG. 7 at the time of turn-off.

  Hereinafter, embodiments of the present invention will be described by way of examples.

FIG. 1 is a diagram illustrating a configuration of an active clamp circuit according to the first embodiment.
In the active clamp circuit of the first embodiment, the cathode terminal of the first Zener diode Dz1 is connected to the collector terminal of the IGBT, and the positive output terminal of the drive circuit and the cathode of the first diode D1 are connected to the gate terminal of the IGBT via the gate resistance. The terminal is connected, and the negative output terminal of the drive circuit and the cathode terminal of the second diode D2 are connected to the emitter terminal of the IGBT.
Furthermore, the drain terminal of the N-channel MOSFET (hereinafter referred to as “FET”) Q1 is connected to the anode terminal of the first Zener diode Dz1, the source terminal of the FET Q1 is connected to the anode terminal of the first diode D1, and the gate of the FET Q1. The terminal and the source terminal are connected via the capacitor C1, the anode terminal of the second Zener diode Dz2 is connected to the anode terminal of the second diode D2, and the gate terminal and the drain terminal of the FET Q1 are connected via the resistor R1. The gate terminal of the FET Q1 and the cathode terminal of the second Zener diode Dz2 are connected.

FIG. 2 is a graph showing an example of the waveform of each part in the circuit shown in FIG. 1 when the IGBT is turned off at a DC power supply voltage of 2400 V and a collector current of 3000 A. FIG. FIG. 7 is a graph showing an example of the waveform of each part in the circuit shown in FIG. 6 when the IGBT is turned off.
2 and 3, the IGBT collector-emitter voltage Vce, gate-emitter voltage Vge, and collector current Ic are respectively the drain-source voltage Vds (51) and the gate-source voltage Vgs (51) in FIG. ) And drain current Id (51).
2 and 3 are divided into sections A to G according to waveform states, as in FIG.

Next, the states of sections A to G in FIGS.
Section A: The drive circuit is driving the IGBT on, and the current in the forward direction (from the collector to the emitter) is flowing from the DC power supply (not shown) via the main circuit wiring (not shown).
Section B: The drive circuit is turned off and the gate voltage of the IGBT decreases, but switching does not occur until it falls below the gate threshold.
Section C: When Vge falls below the gate threshold value, Vce increases as the resistance of the IGBT increases rapidly.
Section D: When Vce exceeds the DC power supply voltage Vdc, Ic decreases rapidly, and an electromotive force Vs calculated by Ls × dIc / dt is generated by the floating inductance Ls in the main circuit wiring. And Vce further rises.
FIG. 4 is an equivalent circuit created for a device for controlling a three-phase motor using six gate drive circuits in consideration of the floating inductance Ls and the like existing in the main circuit wiring.

Section E: When the value obtained by adding the electromotive force Vs to the DC power supply voltage Vdc exceeds the Zener voltage Vz1 of the first Zener diode Dz1, the Zener current Iz1 starts to flow, and the gate of the FET Q1 is charged via the resistor R1. The gate voltage of FETQ1 rises.
Therefore, the Zener voltage Vz1 must be set so as to satisfy the formula (1).
Formula (1): Maximum rated value of collector-emitter voltage of Vdc <Vz1 <IGBT Also, when the gate voltage of FETQ1 exceeds the threshold value, most of Zener current Iz1 flows as the drain current of FETQ1, and the gate of IGBT As a result, the IGBT gate voltage rises.
As the gate voltage of the IGBT increases, the collector current decrease rate dIc / dt decreases, and as a result, the electromotive force Vs is suppressed, so that Vce starts to decrease and does not exceed the maximum rating of the IGBT.
When the section F: Ic becomes zero and all the energy of the floating inductance Ls in the main circuit wiring is absorbed by the IGBT, the IGBT is completely turned off.
Section G: A state in which the off state of the IGBT is maintained.

The most different point between the waveform of FIG. 2 and the waveform of FIG. 3 is the peak value of the gate voltage in the process of increasing the gate voltage of the IGBT in section E.
In FIG. 3, no special measures are taken for the active clamp circuit, and some degree (several number) is required until the IGBT self-consumes the electromotive force Vs generated by the floating inductance Ls and suppresses the rise in the collector voltage. Therefore, although it is a short time, the peak value of the gate voltage reaches 47 V, far exceeding the maximum gate voltage rating of 20 V in most IGBT modules.
On the other hand, in FIG. 2, due to the unique configuration of the active clamp circuit according to the first embodiment, the peak value of the gate voltage is 15.5V even when the collector current is 3000A, and it is 20V or less.

An operation in which the active clamp circuit according to the first embodiment suppresses the peak value of the gate voltage will be described.
In the process of increasing the gate voltage in the section E, the gate voltage of the FET Q1 is always higher than the source voltage, and the gate voltage of the IGBT is always lower than the source voltage of the FET Q1 by the forward voltage Vf1 of the first diode D1. When the gate voltage exceeds the value obtained by adding the Zener voltage Vz2 of the second Zener diode Dz2 and the forward voltage Vf2 of the second diode D2, the current flowing through the resistor R1 flows into the second Zener diode Dz2. The gate voltage of the FET Q1 can only rise to a voltage of Vz2 + Vf2 with reference to the emitter of the IGBT.
As a result, the increase in the gate-emitter voltage Vge of the IGBT is also suppressed to a constant voltage according to the equation (2) when the gate threshold value of the FET Q1 is Vth.
Formula (2): Vge = Vz2 + Vf2- (Vth + Vf1)
When the maximum rating of the gate voltage of the IGBT is Vgm, if Vz2 is set so as to satisfy the expression (3), the destruction of the IGBT due to the Vge exceeding Vgm can be prevented.
Formula (3): Vz2 <Vgm + Vth + Vf1-Vf2

The modification of Example 1 is listed.
(1) Although the IGBT is used in the first embodiment, a MOSFET module or the like may be used.
In short, the active clamp circuit of the first embodiment can be suitably applied to a voltage-driven element having a relatively high breakdown voltage (element breakdown voltage of 1200 V or more).
(2) In the active clamp circuit of the first embodiment, the gate terminal and the source terminal of the FET Q1 are connected via a capacitor, but the capacitor is not always necessary.

(3) In the first embodiment, the first Zener diode Dz1 at which the Zener current Iz1 starts flowing when the difference between the voltage on the collector side of the IGBT and the voltage on the drain side of the FET Q1 exceeds the Zener voltage Vz1 is used. A bidirectional type Zener diode may be used in which a Zener current starts to flow when the difference between the two exceeds a predetermined Zener voltage.
FIG. 5 shows an example of a modification of the active clamp circuit according to the first embodiment. In this modification, a bidirectional type third Zener diode Dz3 is used instead of the first Zener diode Dz1.
(4) In the first embodiment, the difference between the voltage on the gate side of the FET Q1 and the voltage on the emitter side of the IGBT between the gate terminal of the FET Q1, the emitter terminal of the IGBT, and the negative output terminal of the drive circuit is the zener voltage Vz2. When a value exceeding the forward voltage Vf2 of the second diode D2 is exceeded, the second Zener diode Dz2 and the second diode D2 are connected, and the arrangement of the second Zener diode Dz2 and the second diode D2 is switched. You can also.
Further, as shown in FIG. 5, a bidirectional type fourth Zener diode Dz4 may be used instead of the second Zener diode Dz2 and the second diode D2.
(5) In the first embodiment, only one first Zener diode Dz1 and second Zener diode Dz2 are used, but a plurality of Zener diodes connected in series may be used.

(6) Although the gate terminal of the FETQ1 and the cathode terminal of the second Zener diode Dz2 are directly connected in the first embodiment, they may be connected via a resistor.
In the modification shown in FIG. 5, a resistor R2 is connected between the gate terminal of the FET Q1 and the second Zener diode Dz2, and a resistor R3 is connected between the source terminal of the FET Q1 and the second Zener diode Dz2.
(7) In the first embodiment, the gate resistance is connected between the positive output terminal of the drive circuit and the gate terminal of the IGBT. However, as shown in FIG. 5, the negative output terminal of the drive circuit and the emitter terminal of the IGBT An emitter resistor may be connected between them, or only the emitter resistor may be connected and the gate resistor may be omitted.

IGBT Insulated gate bipolar transistor MOSFET MOS field effect transistor
Dz1 First Zener Diode Dz2 Second Zener Diode
Dz3 Third Zener Diode Dz4 Fourth Zener Diode
D1 1st diode D2 2nd diode
Q1 N-channel MOSFET (FET)
C1 Capacitor R1, R2, R3 Resistance Vce IGBT collector-emitter voltage Vge IGBT gate-emitter voltage Ic IGBT collector current Vdc DC power supply voltage Ls Floating inductance in main circuit wiring Vs Electromotive force Vz1 First Zener diode Dz1 Zener voltage Vz2 Zener voltage Iz1 of the second Zener diode Dz2 Zener current Vf1 of the first Zener diode Dz1 Forward voltage of the first diode D1 Vf2 Forward voltage Vth of the second diode D2 Gate threshold of the FET Q1 Vgm IGBT gate Maximum voltage rating Vds (51) Power MOSFET (51) drain-source voltage Vgs (51) Power MOSFET (51) gate-source voltage Id (51) Power MOSFET (51) drain current
If (D1) Reverse blocking diode (D1) forward current Vgs (Q2) MOSFET (Q2) gate-source voltage

Claims (4)

An active clamp circuit that suppresses voltage increase at the collector terminal or drain terminal at the time of turn-off of the voltage-driven element,
The collector terminal or drain terminal of the voltage-driven element and the drain terminal of the N-channel MOSFET are connected via a unidirectional or bidirectional first Zener diode,
A positive output terminal of the drive circuit is connected to the gate terminal of the voltage driven element, and a cathode terminal of the first diode is connected,
A negative output terminal of a drive circuit is connected to an emitter terminal or a source terminal of the voltage-driven element;
A gate terminal and a drain terminal of the N-channel MOSFET are connected via a first resistor;
A source terminal of the N-channel MOSFET is connected to an anode terminal of the first diode;
An emitter terminal or a source terminal of the voltage-driven element and a gate terminal of the N-channel MOSFET are connected via a one-way type second Zener diode and a second diode;
A gate resistor is connected between the gate terminal of the voltage-driven element and the positive output terminal,
An active clamp circuit, wherein an emitter resistor is connected between an emitter terminal or a source terminal of the voltage-driven element and the negative output terminal. Whether the gate terminal and the source terminal of the N-channel MOSFET are connected via a capacitor,
The gate terminal of the N-channel MOSFET and the second Zener diode or the second diode are connected via a second resistor,
2. The active clamp circuit according to claim 1, wherein a source terminal of the N-channel MOSFET and the second Zener diode or the second diode are connected via a third resistor. The active clamp circuit according to claim 1, wherein the first Zener diode or the second Zener diode is formed by connecting a plurality of Zener diodes in series. The active clamp circuit according to any one of claims 1 to 3, wherein a bidirectional Zener diode is used instead of the second Zener diode and the second diode.