JP2015012168A - Printed circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase inductance for decoupling without increasing an area of a printed wiring board.SOLUTION: A printed circuit board comprises: a conductor layer 201 on which a semiconductor package 300 is mounted; a conductor layer 203 on which a power source conductor pattern 211 which is connected to a supply terminal 301 of the semiconductor package 300 via a power source via conductor 231 is arranged; and a conductor layer 204 on which a ground conductor pattern 212 which is connected to a ground terminal 302 of the semiconductor package 300 via a ground via conductor 232 is arranged. In the power supply conductor pattern 211, a slit 251 is formed in a projection region formed when the semiconductor package 300 is projected on the conductor layer 203. In the ground conductor pattern 212, a slit 252 is formed so as to cross a projection image obtained by projecting the slit 251 on the conductor layer 202.

Description

  The present invention relates to a printed circuit board in which a semiconductor device is mounted on a printed wiring board.

  A semiconductor device such as a semiconductor integrated circuit (Large-Scale Integration: LSI) is mounted on a printed wiring board, and operates by being supplied with power through a power supply conductor and a ground conductor of the printed wiring board.

  Due to the switching operation of the transistors in the LSI, current is instantaneously generated in the power supply conductor and the ground conductor. Due to the product of the parasitic inductance components of the power supply conductor and ground conductor and the instantaneous current during LSI operation, potential fluctuation (power supply noise) occurs between the power supply terminal and the ground terminal of the LSI.

  Due to the power supply noise, the output characteristics of the transistors arranged in the input / output circuit of the LSI become unstable, the delay time of the digital signal propagating through the signal wiring fluctuates, and a timing error occurs.

  In order to eliminate the timing error, the power supply noise (inductance from the LSI to the bypass capacitor) between the power supply conductor and the ground conductor can be reduced to reduce power supply noise. However, if the power supply inductance of the power supply conductor and the ground conductor is reduced, the power supply noise generated by the operation of the LSI is easily propagated to the main power supply wiring. If power supply noise propagates to the main power supply wiring, it may cause malfunction of other LSIs or EMI (Electro Magnetic Interference).

  Therefore, conventionally, decoupling has been performed that increases the inductance of the noise propagation path (inductance from the bypass capacitor to the main power supply) while reducing the power supply inductance of the power supply conductor and the ground conductor connected to the LSI. For example, in Patent Document 1, an LSI and a bypass capacitor are connected so as to have a low inductance, while a connection between the bypass capacitor and a main power supply pattern is connected via another power supply via conductor. By adopting such a structure, the inductance between the bypass capacitor and the main power supply conductor pattern is increased, and both reduction of the feeding inductance and decoupling are achieved.

Japanese Patent No. 4273098

  However, the conventional example described in Patent Document 1 requires another power supply via conductor in addition to the connection between the LSI and the bypass capacitor. Therefore, because of the decoupling structure, the installation area of the bypass capacitor is larger than that of the bypass capacitor. There was a problem that a large area was required. As a result, it is necessary to increase the area of the printed wiring board.

  Therefore, an object of the present invention is to increase the inductance for decoupling without increasing the area of the printed wiring board.

  A printed circuit board according to the present invention includes a semiconductor device having a signal terminal, a power supply terminal, and a ground terminal, a first conductor layer on which the semiconductor device is mounted, and a power supply conductor pattern connected to the power supply terminal via a power via conductor. A printed wiring board in which a second conductor layer is disposed, and a third conductor layer in which a ground conductor pattern connected to the ground terminal via a ground via conductor is laminated via an insulator layer; The power supply conductor pattern has a first slit formed in a projection region when the semiconductor device is projected onto the second conductor layer, and the ground conductor pattern has the first slit formed in the third slit. A second slit is formed so as to intersect the projected image projected on the conductor layer.

  According to the present invention, it is possible to increase the inductance for decoupling without increasing the area of the printed wiring board and to suppress the propagation of power supply noise.

It is explanatory drawing which shows schematic structure of the printed circuit board which concerns on 1st Embodiment. It is a top view which shows a part of each conductor layer of a printed wiring board. It is a figure for demonstrating the direction through which a power supply current and a ground current flow. It is a schematic diagram which shows the whole simulation model. It is a top view which shows the structure in the projection area | region which projected the area | region surrounding a terminal group on each conductor layer. It is a graph which shows the result of having simulated the model of FIG.4 and FIG.5. It is a top view which shows a part of each conductor layer of the printed wiring board of the printed circuit board which concerns on 2nd Embodiment. It is a top view which shows a part of each conductor layer of the printed wiring board of the printed circuit board concerning 3rd Embodiment. It is explanatory drawing of the crossing angle of the extending direction of a 1st slit, and the extending direction of a 2nd slit. It is a top view which shows a part of each conductor layer of the printed wiring board of the printed circuit board which concerns on 4th Embodiment. It is a top view which shows a part of each conductor layer of the printed wiring board of the printed circuit board concerning 5th Embodiment.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is an explanatory diagram showing a schematic configuration of a printed circuit board according to the first embodiment of the present invention. FIG. 1A is a cross-sectional view of a printed circuit board, and FIG. 1B is a perspective view showing a semiconductor device of the printed circuit board, and second and third conductor layers of the printed wiring board.

  The printed circuit board 100 includes a printed wiring board 200 that is a motherboard and a semiconductor package 300 that is a semiconductor device mounted on the printed wiring board 200. The printed circuit board 100 includes a power circuit 400 and a bypass capacitor 500 that are power supplies mounted on the printed wiring board 200.

  The printed wiring board 200 is a multilayer substrate in which a plurality of conductor layers 201, 202, 203, and 204 are laminated via insulator layers 205, 206, and 207. In the first embodiment, a four-layer substrate is used. It is. The conductor layer (first conductor layer) 201 is one surface layer, the conductor layer 204 is the other surface layer opposite to the one surface layer, and the conductor layer (third conductor layer) 202 and the conductor layer (first layer). The (two conductor layers) 203 is an inner layer disposed between the pair of conductor layers 201 and 204.

  The semiconductor package 300 and the power supply circuit 400 are mounted on the conductor layer 201, and the bypass capacitor 500 is mounted on the conductor layer 204.

  The semiconductor package 300 includes one or more power terminals 301, one or more ground terminals 302, and a plurality of signal terminals 303. These terminals 301, 302, and 303 are formed of solder balls in the first embodiment. Note that the semiconductor package 300 of the first embodiment is a BGA type (Ball Grid Array) semiconductor package, and includes a plurality of power supply terminals 301, a plurality of ground terminals 302, and a plurality of signal terminals 303. These signal terminals 303 are a transmission terminal that transmits a digital signal or a reception terminal that receives a digital signal. These terminals 301, 302, and 303 are arranged in an array (more specifically, a square lattice).

  In the first embodiment, in the semiconductor package 300, a plurality of power supply terminals 301 and a plurality of ground terminals 302 are arranged in a square shape at intervals from each other to constitute a terminal group 305. A plurality of signal terminals 303 are arranged at intervals along the outer periphery of the terminal group 305 so as to surround the terminal group 305.

  The power supply circuit 400 is a DC power supply circuit, has a power supply terminal 401 and a ground terminal 402, and outputs a DC voltage necessary for the operation of the semiconductor package 300 from the power supply terminal 401 and the ground terminal 402 by external power supply. Is.

  The printed wiring board 200 has a power supply conductor pattern 211 disposed on the conductor layer 203 and a ground conductor pattern 212 disposed on the conductor layer 202. The power supply conductor pattern 211 is disposed so as to face the ground conductor pattern 212 with the insulator layer 206 interposed therebetween. In the present embodiment, the ground conductor pattern 212 has a larger area than the power supply conductor pattern 211, and the power supply conductor pattern 211 is formed to extend from the projection area of the semiconductor package 300 to the projection area of the power supply circuit 400.

  FIG. 2 is a plan view showing a part of each conductor layer of the printed wiring board. 2A is a plan view showing a part of the first conductor layer of the printed wiring board, FIG. 2B is a plan view showing a part of the third conductor layer of the printed wiring board, and FIG. ) Is a plan view showing a part of the second conductor layer of the printed wiring board.

  As shown in FIG. 2A, the printed wiring board 200 has a power pad 213 to which the power terminal 301 of the semiconductor package 300 is bonded and a ground pad 214 to which the ground terminal 302 of the semiconductor package 300 is bonded. Yes.

  In the present embodiment, a plurality of power supply terminals 301 arranged in a straight line and a plurality of ground terminals 302 arranged in a straight line are alternately arranged in a direction orthogonal to the arrangement direction of the power supply terminals 301 or the ground terminals 302. Has been.

  The power pads 213 are arranged in the same number as the power terminals 301 so as to face each power terminal 301, and the ground pads 214 are arranged in the same number as the ground terminals 302 so as to face each ground terminal 302. Therefore, the power supply pad 213 and the ground pad 214 are in the same arrangement as the power supply terminal 301 and the ground terminal 302.

  A plurality of through holes 221 that are first through holes (through vias) penetrating the printed wiring board 200 are formed in the vicinity of the power supply pads 213 (power supply terminals 301). A power supply via conductor 231 that electrically connects the power supply terminal 301 and the power supply conductor pattern 211 is disposed in each through hole 221.

  Similarly, a plurality of through holes 222 which are second through holes (through vias) penetrating the printed wiring board 200 are formed in the vicinity of the ground pads 214 (ground terminals 302). In each through hole 222, a ground via conductor 232 that electrically connects the ground terminal 302 and the ground conductor pattern 212 is disposed.

  That is, the printed wiring board 200 includes a plurality of power via conductors 231 disposed in the respective through holes 221 and a plurality of ground via conductors 232 disposed in the respective through holes 222. The via conductors 231 and 232 are formed so that the through holes 221 and 222 are hollow in FIG. 2, but may be formed so as to be solid in the through holes 221 and 222.

  Here, the number of power supply terminals 301 (power supply pads 213) and the number of power supply via conductors 231 do not have to correspond one-to-one, and a plurality of (for example, two) power supply terminals 301 (power supply pads 213). One power supply via conductor 231 may be connected to each other. Similarly, the number of ground terminals 302 and the number of ground via conductors 232 do not have to correspond one-to-one, and one ground via is provided for a plurality of (for example, two) ground terminals 302 (ground pads 214). The conductor 232 may be connected.

  In the present embodiment, the bypass capacitor 500 mounted on the conductor layer 204 has one end electrically connected to the power via conductor 231 and the other end electrically connected to the ground via conductor 232.

  In the present embodiment, in the power supply circuit 400, as shown in FIG. 1A, the power supply terminal 401 is electrically connected to the power supply conductor pattern 211 of the conductor layer 203 via the power supply via conductor 241. The ground terminal 402 is electrically connected to the ground conductor pattern 212 of the conductor layer 202 via the ground via conductor 242.

  With the above configuration, the power supply terminal 401 of the power supply circuit 400 is electrically connected to the power supply terminal 301 of the semiconductor package 300 via the power supply via conductor 241, the power supply conductor pattern 211, the power supply via conductor 231, the power supply pad 213, and the like. Yes. The ground terminal 402 of the power supply circuit 400 is electrically connected to the ground terminal 302 of the semiconductor package 300 through the ground via conductor 242, the ground conductor pattern 212, the ground via conductor 232, the ground pad 214, and the like. As a result, a DC voltage necessary for the operation of the semiconductor elements in the semiconductor package 300 is applied between the power supply terminal 301 and the ground terminal 302 of the semiconductor package 300.

  As shown in FIG. 1B, the printed wiring board 200 has a plurality of signal via conductors 233 that are electrically connected to the signal terminals 303 of the semiconductor package 300. A plurality of signal via conductors 233 are arranged at intervals on the outer periphery of a via conductor group including a plurality of power supply via conductors 231 and a plurality of ground via conductors 232.

  The power supply conductor pattern 211 is formed with a plurality of slits (defects) 251 that are first slits. The plurality of slits 251 are in the projection region when the semiconductor package 300, that is, the region surrounding the terminal group 305 of the semiconductor package 300 is projected onto the conductor layer 203 in the stacking direction of the conductor layers 201 to 204 (in FIG. 1B). , In the projection region R1). The plurality of slits 251 are formed so as not to cross each other, and are formed in parallel with each other in this embodiment.

  Further, in the ground conductor pattern 212, as shown in FIG. 2B, a slit (defect) 252 that is a second slit is formed so as to intersect a projected image R251 obtained by projecting the slit 251 on the conductor layer 202 in the stacking direction. A plurality of are formed. The plurality of slits 252 are in the projection region when the semiconductor package 300, that is, the region surrounding the terminal group 305 of the semiconductor package 300 is projected onto the conductor layer 202 in the stacking direction (in FIG. 1B, in the projection region R2). Is formed. The plurality of slits 252 are formed so as not to cross each other, and are formed in parallel with each other in this embodiment.

  The principle of increasing the decoupling inductance (power supply inductance) in the conductor patterns 211 and 212 by the slits 251 and 252 will be described with reference to FIG.

FIG. 3 is a diagram for explaining the flow direction of the power supply current I ₁ and the ground current I _2. FIG. 3A shows a comparative example when there are no slits 251 and 252, and FIG. The case where there exists the slits 251 and 252 of 1st Embodiment is shown.

Comparative Example Considering the loop inductance _{L loop} between the power supply conductor pattern 211 and ground conductor pattern 212 in (FIG. 3 (a)), flowing supply current _{I 1} and ground current _{I 2} to face the opposite direction. Therefore, L _loop can be considered by the following formula (1).
L _loop = L _D + L _G −2 × M Formula (1)

L _D and L _G are self-inductances of the power supply conductor pattern 211 and the ground conductor pattern 212, respectively, and M is a mutual inductance generated between the power supply conductor pattern 211 and the ground conductor pattern 212.

Next, consider the loop inductance L _loop ′ between the power supply conductor pattern 211 and the ground conductor pattern 212 in the first embodiment (FIG. 3B). L _D ′ and L _G ′ are self-inductances of the power supply conductor pattern 211 and the ground conductor pattern 212, respectively, and M ′ is a mutual inductance generated between the power supply conductor pattern 211 and the ground conductor pattern 212. The loop inductance L _loop ′ is expressed by the following equation (2).
_{L loop '= L D' +} L G '-2 × M' (2)

  Here, the magnitude relationship between the inductances expressed by the equations (1) and (2) is considered.

In FIG. 3 (b), since the slits 251 to power supply conductor pattern 211 in a direction that does not interfere with the supply current _{I 1} is formed, the relationship _{L D} 'and _{L D} is be considered the following equations (3) it can.
_{L D} '≒ L _D (3)

On the other hand, the slit 252 is formed in the ground conductor pattern 212 so as to be orthogonal to the projected image R251 of the slit 251. Therefore, the ground current _{I 2} bypasses the slit 252 of the ground conductor pattern 212, the current path becomes longer. Therefore, when L _G and L _G ′ are compared, the following equation (4) is established.
_{L G} '> L _G formula (4)

Further, mutual inductance does not occur in a region where the current bypassing the slit 252 of the ground conductor pattern 212 and the current of the power supply conductor pattern 211 are orthogonal to each other. Therefore, when M and M ′ are compared, the relationship of Expression (5) is obtained.
M> M ′ Formula (5)

From the above, the magnitude relationship between L _loop 'and L _loop is the relationship of the following equation (6) from the equations (3), (4), and (5).
L _loop '> L _loop expression (6)

  That is, according to the first embodiment, the inductance from the power ground connection portion of the semiconductor package 300 to the main power ground wiring portion, that is, the power supply inductance for decoupling can be increased as compared with the comparative example. In other words, the power supply inductance of the path from the power supply terminal 301 and the ground terminal 302 of the semiconductor package 300 to the power supply terminal 401 and the ground terminal 402 of the power supply circuit 400 can be increased as compared with the comparative example.

  In the first embodiment, as shown in FIG. 1B, the power supply inductance can be increased only by providing the slits 251 and 252 in the projection regions R1 and R2 immediately below the semiconductor package 300. Therefore, area consumption such as addition of a power supply via conductor does not occur unlike the conventional example.

  Further, since the arrangement position and the number of the power supply via conductor 231 and the ground via conductor 232 and the bypass capacitor 500 necessary for reducing the feeding resistance are not limited, the feeding resistance can be reduced by a conventional method.

  In the first embodiment, the slit 251 is formed in a straight line so as to connect the plurality of through holes 222 arranged in a straight line (second through holes). The direction in which the slit 251 extends is the longitudinal direction of the power supply conductor pattern 211 (that is, the direction toward the power supply of the power supply conductor pattern 211). In addition, the slit 252 is formed in a straight line so as to connect the plurality of through holes 221 arranged in a straight line (first through holes). The direction in which the slit 252 extends intersects with the direction in which the slit 251 extends (orthogonal in the present embodiment). Thereby, power supply inductance can be raised more effectively.

  Next, the effect of 1st Embodiment calculated | required by simulation is demonstrated using FIG.4, FIG.5 and FIG.6.

  FIG. 4 is a schematic diagram showing the entire simulation model. The power supply pads 213 in the conductor layer 201 are arranged in a 16 × 8 lattice pattern, and the ground pads 214 are arranged in a 16 × 9 lattice pattern. The power supply and ground are both connected to one via conductor from two or one pad.

  Table 1 shows the detailed parameters of the simulation model.

  FIG. 5 is a plan view showing the structure in the projection regions R1 and R2 in which the region surrounding the terminal group 305 is projected onto the conductor layers 202 and 203. FIG. 5A shows the case where the slits 251 and 252 are not provided, FIG. 5B shows the case where only the ground conductor pattern 212 has the slit 252, and FIG. 5C shows the case where the slits 251 and 252 are provided.

  In the simulation, in order to obtain the power supply inductance for decoupling, one Port is set in which the power supply pad 213 and the ground pad 214 of the conductor layer 201 are short-circuited. Furthermore, the power supply conductor pattern 211 and the ground conductor pattern 212 are short-circuited by a short-circuit line S1 at a position of 6.5 [mm] from the ends of the projection regions R1 and R2.

  As an electromagnetic field analysis tool, PowerSI (Ver11) manufactured by Sigrity was used. FIG. 6 is a graph showing the result of simulating the models of FIGS. 4 and 5.

  In FIG. 6, La is the frequency characteristic of the power supply impedance of the model shown in FIG. 5A, Lb is the frequency characteristic of the power supply impedance of the model shown in FIG. 5B, and Lc is FIG. 5C. It is the frequency characteristic of the power supply impedance of the model shown in FIG. When the inductance is obtained from the impedance at 100 [MHz], 636 [pH] in the form of FIG. 5A, 1209 [pH] in the form of FIG. 5B, and the first implementation shown in FIG. 5C. It was 1718 [pH] in form.

  From the above, by forming the slit 252 that intersects (orthogonally) the projected image R251 in the ground conductor pattern 212, the self-inductance of the ground conductor pattern 212 increases due to the ground current bypass. Further, the slits 251 and 252 are formed in the power supply conductor pattern 211 and the ground conductor pattern 212, respectively, and the inductance is increased by the effect of reducing the mutual inductance by intersecting (orthogonal) the slits 251 and 252.

  Therefore, it is possible to increase the inductance for decoupling without increasing the area of the printed wiring board 200 and to suppress the propagation of power supply noise.

  In addition, since the slit 251 is formed to extend along the direction of the power supply conductor pattern 211 toward the power supply circuit 400, the DC current density of the power supply conductor pattern 211 is suppressed from locally increasing while increasing the power supply inductance. be able to.

  In addition, since a plurality of slits 251 and 252 are formed, the power supply inductance can be increased more effectively, and the propagation of power supply noise can be more effectively suppressed.

  Further, by forming the slits 251 and 252 so as to connect the through holes, the power supply inductance can be increased more effectively in the narrow projection areas R1 and R2, and the power supply noise can be more effectively propagated. Can be suppressed.

  Note that only the same type of power supply terminals and ground terminals exist within the region surrounding the terminal group 305. As a result, it is possible to prevent other signals due to the slit and power supply wiring from being deteriorated.

[Second Embodiment]
Next, a printed circuit board according to a second embodiment of the present invention will be described. FIG. 7 is a plan view showing a part of each conductor layer of the printed wiring board of the printed circuit board according to the second embodiment of the present invention. FIG. 7A is a plan view showing a part of the third conductor layer of the printed wiring board, and FIG. 7B is a plan view showing a part of the second conductor layer of the printed wiring board. In the second embodiment, the number of slits formed in the conductor patterns 211 and 212 is different from that in the first embodiment, and other configurations are the same as those in the first embodiment.

  In the second embodiment, as compared with the first embodiment, the number of slits 251 and 252 formed in the power supply conductor pattern 211 of the conductor layer 203 and the ground conductor pattern 212 of the conductor layer 202 in the projection regions R1 and R2 is larger. Is decreasing.

  As described above, the number and position of the slits 251 and 252 are the required values when the required value of the power supply inductance for decoupling and another design required value such as reducing the direct current density of the power supply conductor pattern 211 are mixed. You can decide accordingly.

[Third Embodiment]
Next, a printed circuit board according to a third embodiment of the invention will be described. FIG. 8 is a plan view showing a part of each conductor layer of the printed wiring board of the printed circuit board according to the third embodiment of the present invention. FIG. 8A is a plan view showing a part of the third conductor layer of the printed wiring board, and FIG. 8B is a plan view showing a part of the second conductor layer of the printed wiring board.

  The third embodiment is different from the first and second embodiments in that the slit 251 formed in the power supply conductor pattern 211 of the conductor layer 203 and the slit 252 formed in the ground conductor pattern 212 of the conductor layer 202 are different. Is a point that is not orthogonal in plan view.

  The effect of reducing the mutual inductance due to the intersection angle between the projected image obtained by projecting the slit 251 of the power supply conductor pattern 211 on the conductor layer 202 in the stacking direction and the slit 252 of the ground conductor pattern 212 is most reduced when orthogonal. However, the present invention is not limited to the case of being orthogonal, and a reduction effect can be obtained even when the crossing angle is not 90 degrees. The reason for this will be described with reference to FIG.

  FIG. 9 is an explanatory diagram of an intersection angle between the direction in which the slit 251 extends and the direction in which the slit 252 extends. FIG. 9A is an explanatory diagram showing the direction in which the slits 251 and 252 extend in the projection regions R1 and R2, and FIG. 9B shows the mutual inductance with respect to the crossing angle at which the slits 251 and 252 intersect in plan view. It is a graph which shows the reduction effect.

As shown in FIG. 9A, the angle formed between the projected image when the slit 251 is projected onto the conductor layer 202 and the slit 252, that is, the angle formed between the direction in which the slit 251 extends and the direction in which the slit 252 extends, is an intersection angle. Let θ. The mutual inductance M between the power supply conductor pattern 211 and the ground conductor pattern 212 can be expressed by the following equation, where M (θ = 0) is the mutual inductance when the crossing angle θ = 0.
M = M (θ = 0) × cos θ

Here, since the reduction effect is maximized when θ = 90 degrees, assuming that the reduction effect when θ = 90 degrees is 100%, the reduction effect can be expressed by the following expression. FIG. 9B is a graph showing this reduction effect.
Reduction effect = (1-cos θ) × 100

  As can be seen from FIG. 9B, when the crossing angle θ is 60 degrees or more, the effect of reducing the mutual inductance can be secured by 50% or more. That is, it is preferable that the crossing angle θ is 60 degrees or more and 90 degrees or less.

  As described above, in the third embodiment, by setting the crossing angle θ to 60 degrees or more and 90 degrees or less, the reduction effect of the mutual inductance can be ensured by 50% or more, and the propagation of power supply noise is more effectively suppressed. be able to.

  In addition, since the degree of freedom can be given to the intersection angle θ within the range of 60 degrees or more and 90 degrees or less, the degree of freedom in designing the number, position, and direction of the slits can be increased. Therefore, it becomes easy to respond to other required design values such as a required value of power supply inductance for decoupling and a reduced direct current density of the power supply conductor pattern 211.

[Fourth Embodiment]
Next, a printed circuit board according to a fourth embodiment of the invention will be described. FIG. 10 is a plan view showing a part of each conductor layer of the printed wiring board of the printed circuit board according to the fourth embodiment of the present invention. FIG. 10A is a plan view showing a part of the third conductor layer of the printed wiring board, and FIG. 10B is a plan view showing a part of the second conductor layer of the printed wiring board.

  In the first, second, and third embodiments, it has been described that it is preferable that at least one slit, particularly both slits 251 and 252 are linearly formed. It is not limited to the shape, and may be bent. Thus, since each of the slits 251 and 252 may be bent depending on the situation, it is possible to further increase the degree of freedom in designing the printed circuit board.

[Fifth Embodiment]
Next, a printed circuit board according to a fifth embodiment of the invention will be described. FIG. 11 is a plan view showing a part of each conductor layer of the printed wiring board of the printed circuit board according to the fifth embodiment of the present invention. FIG. 11A is a plan view showing a part of the first conductor layer of the printed wiring board, FIG. 11B is a plan view showing a part of the third conductor layer of the printed wiring board, and FIG. ) Is a plan view showing a part of the second conductor layer of the printed wiring board.

  In the fifth embodiment, as shown in FIG. 11A, in the conductor layer 201, the power pad 213 is arranged along the four sides at the center, and the ground pad 214 is arranged at the corner. The power supply pad 213 is electrically connected to the power supply conductor pattern 211 of the conductor layer 203 by the power supply via conductor 231 in the through hole 221.

  In addition, the ground pad 214 is electrically connected to the ground conductor pattern 212 of the conductor layer 202 by the ground via conductor 232 in the through hole 222. In the conductor layer 201, pads other than the power supply pad 213 and the ground pad 214 are signal pads 1001.

  As shown in FIG. 11B, the slit 252 of the ground conductor pattern 212 is formed inside the projection region R2, and as shown in FIG. 11C, the power source conductor pattern 211 is formed inside the projection region R1. A slit 251 is formed. In order to simplify the drawing, signal vias connected to the signal pad 1001 are not shown in FIGS. 11B and 11C, but there are actually signal vias.

  As described above, the regions R1 and R2 do not need to be configured only by the power supply and ground structure. The regions where the slits 251 and 252 are provided are arbitrarily determined, and the slits of the power supply conductor pattern and the ground conductor pattern are formed in the region. It only has to cross.

  The present invention is not limited to the embodiments described above, and many modifications can be made by those having ordinary knowledge in the art within the technical idea of the present invention.

  Although the case where the power supply circuit 400 which is a power supply is mounted on the printed wiring board 200 has been described in the above embodiment, the present invention is not limited to this, and the present invention can be applied even when a DC voltage is applied from an external power supply. The invention is applicable. For example, a printed wiring board is provided with a power terminal and a ground terminal (not shown) connected to a power conductor pattern and a ground conductor pattern, respectively, and a DC voltage is applied from an external power source through the power terminal and the ground terminal. You may do it.

  Moreover, although the said embodiment demonstrated that the case where two or more slits 251 and 252 were formed was suitable, it is not limited to this, The case where one each is formed may be sufficient.

  In the above embodiment, the slits 251 and 252 are formed so as to connect the through holes. However, the present invention is not limited to this, and the slits 251 and 252 may not pass through the through holes.

  Moreover, although the case where the printed wiring board was a four-layer board | substrate was demonstrated in the said embodiment, it is not limited to this, If this is a multilayer board | substrate with at least three conductor layers, this invention is applicable. . Further, the stacking order of the first conductor layer, the second conductor layer, and the third conductor layer is not limited to the above embodiment. For example, the first conductor layer, the second conductor layer, and the third conductor layer may be laminated in this order, or another conductor layer may be interposed between these conductor layers.

DESCRIPTION OF SYMBOLS 100 ... Printed circuit board, 200 ... Printed wiring board, 201 ... Conductor layer (1st conductor layer), 202 ... Conductor layer (3rd conductor layer), 203 ... Conductor layer (2nd conductor layer), 211 ... Power supply conductor pattern 212, ground conductor pattern, 231 ... power via conductor, 232 ... ground via conductor, 251 ... slit (first slit), 252 ... slit (second slit), 300 ... semiconductor package (semiconductor device), 301 ... power terminal , 302 ... ground terminal, 303 ... signal terminal, 305 ... terminal group

Claims (8)

A semiconductor device having a signal terminal, a power supply terminal, and a ground terminal;
A first conductor layer on which the semiconductor device is mounted; a second conductor layer in which a power supply conductor pattern connected to the power supply terminal via a power via conductor; and a ground via conductor connected to the ground terminal. A third conductive layer in which a ground conductor pattern is disposed, and a printed wiring board laminated via an insulator layer,
In the power supply conductor pattern, a first slit is formed in a projection region when the semiconductor device is projected onto the second conductor layer,
The printed circuit board according to claim 1, wherein a second slit is formed in the ground conductor pattern so as to intersect a projected image obtained by projecting the first slit onto the third conductor layer.   The printed circuit board according to claim 1, wherein the first slit is formed to extend along a direction of the power supply conductor pattern toward the power supply.   3. The print according to claim 1, wherein an angle formed between a projection image obtained by projecting the first slit on the third conductor layer and the second slit is 60 degrees or more and 90 degrees or less. Circuit board. A plurality of the first slits are formed in the power supply conductor pattern,
4. The printed circuit board according to claim 1, wherein a plurality of the second slits are formed in the ground conductor pattern. 5. The printed wiring board has a plurality of power via conductors and ground via conductors, respectively.
Each of the power via conductors is formed in each first through hole that penetrates the printed wiring board,
Each ground via conductor is formed in each second through hole penetrating the printed wiring board,
The first slit is formed so as to connect the second through holes,
5. The printed circuit board according to claim 1, wherein the second slit is formed so as to connect the first through holes. 6.   6. The printed circuit board according to claim 1, wherein the semiconductor device is a BGA type semiconductor package including a plurality of the signal terminals, the power supply terminals, and the ground terminals. 7. In the semiconductor package, the plurality of signal terminals are arranged along an outer periphery of a terminal group including the plurality of power supply terminals and the plurality of ground terminals,
The first slit is formed in a projection region obtained by projecting a region surrounding the terminal group onto the second conductor layer,
The printed circuit board according to claim 6, wherein the second slit is formed in a projection region obtained by projecting a region surrounding the terminal group onto the third conductor layer.   The printed circuit board according to claim 1, wherein at least one of the first slit and the second slit is formed in a linear shape.

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