JP2014506773A5 - - Google Patents

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Publication number
JP2014506773A5
JP2014506773A5 JP2013555511A JP2013555511A JP2014506773A5 JP 2014506773 A5 JP2014506773 A5 JP 2014506773A5 JP 2013555511 A JP2013555511 A JP 2013555511A JP 2013555511 A JP2013555511 A JP 2013555511A JP 2014506773 A5 JP2014506773 A5 JP 2014506773A5
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JP
Japan
Prior art keywords
adc
stage
coupled
pipeline
sub
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JP2013555511A
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English (en)
Japanese (ja)
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JP6076268B2 (ja
JP2014506773A (ja
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Priority claimed from US13/032,457 external-priority patent/US8451152B2/en
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JP2013555511A 2011-02-22 2012-02-22 パイプラインａｄｃ内部ステージ誤差キャリブレーション Active JP6076268B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/032,457 US8451152B2 (en) 2011-02-22 2011-02-22 Pipelined ADC inter-stage error calibration
US13/032,457 2011-02-22
PCT/US2012/026022 WO2012116006A2 (en) 2011-02-22 2012-02-22 Pipelined adc inter-stage error calibration

Publications (3)

Publication Number Publication Date
JP2014506773A JP2014506773A (ja) 2014-03-17
JP2014506773A5 true JP2014506773A5 (cg-RX-API-DMAC10.html) 2015-03-26
JP6076268B2 JP6076268B2 (ja) 2017-02-08

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JP2013555511A Active JP6076268B2 (ja) 2011-02-22 2012-02-22 パイプラインａｄｃ内部ステージ誤差キャリブレーション

Country Status (4)

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US (1) US8451152B2 (cg-RX-API-DMAC10.html)
JP (1) JP6076268B2 (cg-RX-API-DMAC10.html)
CN (1) CN103392297B (cg-RX-API-DMAC10.html)
WO (1) WO2012116006A2 (cg-RX-API-DMAC10.html)

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US8836558B1 (en) * 2013-03-15 2014-09-16 Analog Devices, Inc. Method and device for improving convergence time in correlation-based algorithms
US9154146B1 (en) 2014-06-03 2015-10-06 The Board Of Regents, The University Of Texas System Dynamic offset injection for CMOS ADC front-end linearization
CN104300981B (zh) * 2014-09-30 2018-04-27 成都市晶林科技有限公司 高速、高精度图像信号模数转换电路
CN105897265B (zh) 2014-12-12 2020-08-21 恩智浦美国有限公司 具有受控误差校准的模数转换器
US9602121B2 (en) * 2015-07-07 2017-03-21 Analog Devices, Inc. Background estimation of comparator offset of an analog-to-digital converter
CN107453756B (zh) * 2017-08-17 2020-02-04 电子科技大学 一种用于流水线adc的前端校准方法
US10284188B1 (en) 2017-12-29 2019-05-07 Texas Instruments Incorporated Delay based comparator
US10673452B1 (en) 2018-12-12 2020-06-02 Texas Instruments Incorporated Analog-to-digital converter with interpolation
US10673456B1 (en) 2018-12-31 2020-06-02 Texas Instruments Incorporated Conversion and folding circuit for delay-based analog-to-digital converter system
US11316526B1 (en) 2020-12-18 2022-04-26 Texas Instruments Incorporated Piecewise calibration for highly non-linear multi-stage analog-to-digital converter
US11387840B1 (en) 2020-12-21 2022-07-12 Texas Instruments Incorporated Delay folding system and method
US11309903B1 (en) 2020-12-23 2022-04-19 Texas Instruments Incorporated Sampling network with dynamic voltage detector for delay output
US11438001B2 (en) 2020-12-24 2022-09-06 Texas Instruments Incorporated Gain mismatch correction for voltage-to-delay preamplifier array
US11962318B2 (en) 2021-01-12 2024-04-16 Texas Instruments Incorporated Calibration scheme for a non-linear ADC
CN112910462B (zh) * 2021-01-15 2023-02-21 迈科微电子(深圳)有限公司 一种基于亚稳态检测的pipeline-SAR ADC数字级间增益校准方法
US11316525B1 (en) 2021-01-26 2022-04-26 Texas Instruments Incorporated Lookup-table-based analog-to-digital converter
EP4285487A4 (en) 2021-02-01 2024-07-10 Texas Instruments Incorporated LOOKUP TABLE FOR NONLINEAR SYSTEMS
US11881867B2 (en) 2021-02-01 2024-01-23 Texas Instruments Incorporated Calibration scheme for filling lookup table in an ADC
US12101096B2 (en) 2021-02-23 2024-09-24 Texas Instruments Incorporated Differential voltage-to-delay converter with improved CMRR
CN113098511B (zh) * 2021-03-01 2023-03-21 深圳市纽瑞芯科技有限公司 一种流水线逐次逼近型模数转换器的前端自校准方法
US12206424B2 (en) * 2022-08-30 2025-01-21 Texas Instruments Incorporated Methods and apparatus to reduce inter-stage gain errors in analog-to-digital converters

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JP4547064B2 (ja) 1999-03-24 2010-09-22 株式会社アドバンテスト Ａ／ｄ変換装置およびキャリブレーション装置
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