DE60229689D1 - Korrektion der Verstärkungsfehler des Operationsverstärkers in Fliessband-Analog-Digital-Wandler - Google Patents

Korrektion der Verstärkungsfehler des Operationsverstärkers in Fliessband-Analog-Digital-Wandler

Info

Publication number
DE60229689D1
DE60229689D1 DE60229689T DE60229689T DE60229689D1 DE 60229689 D1 DE60229689 D1 DE 60229689D1 DE 60229689 T DE60229689 T DE 60229689T DE 60229689 T DE60229689 T DE 60229689T DE 60229689 D1 DE60229689 D1 DE 60229689D1
Authority
DE
Germany
Prior art keywords
analog
correction
line
operational amplifier
digital converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60229689T
Other languages
English (en)
Inventor
Ahmed Ali
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/847,612 external-priority patent/US6501400B2/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE60229689D1 publication Critical patent/DE60229689D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/0678Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/14Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
    • H03M1/167Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
    • H03M1/168Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters and delivering the same number of bits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/34Analogue value compared with reference values
    • H03M1/38Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/44Sequential comparisons in series-connected stages with change in value of analogue signal
    • H03M1/442Sequential comparisons in series-connected stages with change in value of analogue signal using switched capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
DE60229689T 2001-05-02 2002-04-30 Korrektion der Verstärkungsfehler des Operationsverstärkers in Fliessband-Analog-Digital-Wandler Expired - Lifetime DE60229689D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/847,612 US6501400B2 (en) 2000-09-18 2001-05-02 Correction of operational amplifier gain error in pipelined analog to digital converters

Publications (1)

Publication Number Publication Date
DE60229689D1 true DE60229689D1 (de) 2008-12-18

Family

ID=25301054

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60229689T Expired - Lifetime DE60229689D1 (de) 2001-05-02 2002-04-30 Korrektion der Verstärkungsfehler des Operationsverstärkers in Fliessband-Analog-Digital-Wandler

Country Status (3)

Country Link
EP (1) EP1255357B1 (de)
JP (1) JP3964739B2 (de)
DE (1) DE60229689D1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2043267B1 (de) * 2006-06-08 2012-11-21 National University Corporation Shizuoka University Analog-digital-wandler, a/d-wandlerstufe, verfahren zum erzeugen eines einem analogsignal entsprechenden digitalsignals und verfahren zum erzeugen eines den umwandlungsfehler in der a/d-wandlerstufe anzeigenden signals
JP4720842B2 (ja) 2008-03-27 2011-07-13 セイコーエプソン株式会社 パイプライン型a/d変換器
CN102571088B (zh) * 2010-12-31 2014-06-18 国民技术股份有限公司 一种用于流水线型模数转换器的溢出判断电路
US8451152B2 (en) * 2011-02-22 2013-05-28 Texas Instruments Incorporated Pipelined ADC inter-stage error calibration
CN102158229A (zh) * 2011-03-30 2011-08-17 上海北京大学微电子研究院 Adc失调电压和电荷注入消除技术

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6222471B1 (en) * 1998-01-15 2001-04-24 Texas Instruments Incorporated Digital self-calibration scheme for a pipelined A/D converter

Also Published As

Publication number Publication date
JP3964739B2 (ja) 2007-08-22
EP1255357B1 (de) 2008-11-05
EP1255357A2 (de) 2002-11-06
JP2002368618A (ja) 2002-12-20
EP1255357A3 (de) 2004-03-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition