JP2014501447A - 複合基板、複合基板を有する半導体チップ、並びに複合基板及び半導体チップの製造方法 - Google Patents
複合基板、複合基板を有する半導体チップ、並びに複合基板及び半導体チップの製造方法 Download PDFInfo
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Abstract
Description
Claims (15)
- キャリア(2)と、誘電体接着層(3)によって前記キャリア(2)に装着されたユーティリティ層(5)と、を有し、放射変換材料を含有する、複合基板(1)。
- 前記ユーティリティ層は、窒化物化合物半導体材料を含有する、請求項1に奇異債の複合基板。
- 前記ユーティリティ層は、最大で1μmの厚さを有する、請求項1又は2に記載の複合基板。
- 前記誘電体接着層は、酸化物、窒化物又は酸窒化物を含有する、請求項1から3のいずれかに記載の複合基板。
- 前記誘電体接着層の屈折率は、前記ユーティリティ層から前記キャリアに向かって低くなる、請求項1から4のいずれかに記載の複合基板。
- 前記誘電体接着層は少なくとも1つの側においてパターニング(25)を有する境界表面に隣接する、請求項1から5のいずれかに記載の複合基板。
- 放射を生成するための活性領域(70)を有する半導体ボディ(7)が前記ユーティリティ層上に配置され、動作中に生成された放射は前記放射変換材料によって少なくとも部分的に変換される、請求項1から6のいずれかに記載の複合基板を有する半導体チップ。
- 前記キャリアは、前記半導体ボディから離れた側にミラー層(96)を有する、請求項7に記載の半導体チップ。
- 前記半導体ボディから離れた側の前記キャリアの主面は放射出射面を形成する、請求項7に記載の半導体チップ。
- キャリア(2)とユーティリティ層(5)とを有する複合基板(1)の製造方法であって、
放射変換材料を含有する前記キャリア(2)を用意するステップと、
誘電体接着層(3)によって前記キャリア(2)に前記ユーティリティ層(5)を装着するステップと、
を有する方法。 - 前記ユーティリティ層は直接接着によって前記キャリアに装着される、請求項10に記載の方法。
- 前記ユーティリティ層は、補助キャリア(4)上に設けられ、前記キャリアへの装着後、前記ユーティリティ層は、残っている前記補助キャリアから取り外される、請求項10又は11に記載の方法。
- 前記ユーティリティ層の装着前、分離核(51)が形成され、前記分離核に沿って前記ユーティリティ層が前記キャリアへの装着後に取り外される、請求項12記載の方法。
- 複数の半導体チップ(10)の製造方法であって、
a)請求項1から6のいずれかに記載の複合基板を用意するステップと、
b)前記複合基板上に、放射を生成するための活性領域を有する半導体層積層体を形成するステップと、
c)前記半導体層積層体を有する前記複合基板を複数の半導体チップに単体化するステップと、
を有する方法。 - 前記キャリアの厚さは前記ステップb)の後に減らされる、請求項14に記載の方法。
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DE102011012298.2 | 2011-02-24 | ||
PCT/EP2011/073134 WO2012089540A1 (de) | 2010-12-28 | 2011-12-16 | Verbundsubstrat, halbleiterchip mit verbundsubstrat und verfahren zur herstellung von verbundsubstraten und halbleiterchips |
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DE102017114467A1 (de) | 2017-06-29 | 2019-01-03 | Osram Opto Semiconductors Gmbh | Halbleiterchip mit transparenter Stromaufweitungsschicht |
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US9123528B2 (en) | 2015-09-01 |
US20150287883A1 (en) | 2015-10-08 |
KR101526090B1 (ko) | 2015-06-04 |
WO2012089540A1 (de) | 2012-07-05 |
DE102011012298A1 (de) | 2012-06-28 |
US9997671B2 (en) | 2018-06-12 |
US20140203413A1 (en) | 2014-07-24 |
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KR20130102117A (ko) | 2013-09-16 |
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