JP2014225541A - Semiconductor light-emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting device with high quality.SOLUTION: A semiconductor light-emitting device comprises: a semiconductor light-emitting element having a first conductivity type first semiconductor layer, a light-emitting layer formed on the first semiconductor layer, a second semiconductor layer with a second conductivity type opposite to the first conductivity type and formed on the light-emitting layer, a first electrode electrically connected to the first semiconductor layer, and a second electrode electrically connected to the second semiconductor layer; a phosphor layer covering the semiconductor light-emitting element; and a feeding part arranged in a region covered with the phosphor layer and electrically connected to the first electrode or the second electrode. The feeding part comprises: a first material layer formed of a first material and electrically connected to the first electrode or the second electrode; and a second material layer formed of a second material which absorbs fluorescent light generated from the phosphor layer more than the first material, and is formed on a part of the first material layer.

Description

  The present invention relates to a semiconductor light emitting device.

  In the semiconductor light emitting device, an n-side electrode and a p-side electrode that are electrically connected to the stacked n-type semiconductor layer and p-type semiconductor layer are formed. For example, a p-side electrode is formed on the same surface side of the device by forming a p-side electrode on the p-type semiconductor layer and forming an n-side electrode in a recess that is perforated from the p-type semiconductor layer side and exposes the n-type semiconductor layer. And an n-side electrode can be formed (see, for example, Patent Documents 1 to 3).

  7A and 7B are photographs showing a continuous type semiconductor light emitting device in which a plurality of semiconductor light emitting elements are connected in series. This photo shows a quadruple device in which four semiconductor light emitting elements emitting blue light are arranged. Electric power is supplied from a power feeding unit arranged on both sides of the quadruple element (both ears type).

  A semiconductor light-emitting device includes a light-emitting element and a resin that seals the light-emitting element, and a phosphor may be added to the resin. For example, when a phosphor that emits yellow light is added to a resin that seals a semiconductor light emitting element that emits blue light, white light is emitted from the semiconductor light emitting device. 7A shows a semiconductor light emitting device sealed with a resin to which no phosphor is added, and FIG. 7B shows a semiconductor light emitting device sealed with a resin to which a yellow light emitting phosphor is added.

  In the semiconductor light emitting device shown in FIG. 7B, yellowish color unevenness occurs on the light emitting surface in the power feeding unit. This is due to the reflection of yellow light propagating to the power feeding unit. In semiconductor light-emitting devices sealed with a resin to which a phosphor emitting yellow light is added, bluish color unevenness may be observed due to reflection of blue light propagating to the power feeding unit. is there.

  For example, when a semiconductor light emitting device is used as a light source for a headlight of an automobile, the color unevenness reflected on the projection surface is a serious problem.

JP 2011-066644 A JP 2011-249501 A JP 2011-199221 A

  An object of the present invention is to provide a high-quality semiconductor light-emitting device.

  According to an aspect of the present invention, a first conductivity type first semiconductor layer, a light emitting layer formed on the first semiconductor layer, a light emitting layer formed on the light emitting layer, and opposite to the first conductivity type. A semiconductor light emitting device comprising: a second semiconductor layer having a second conductivity type; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the second semiconductor layer. And a phosphor layer that covers the semiconductor light emitting element, and a power feeding unit that is disposed in a region covered with the phosphor layer and is electrically connected to the first electrode or the second electrode, The power supply unit is formed of a first material, and absorbs the first material layer electrically connected to the first electrode or the second electrode and the fluorescence emitted from the phosphor layer from the first material. A semiconductor light emitting device comprising a second material and a second material layer formed on a part of the first material layer is provided. It is.

  According to the present invention, a high-quality semiconductor light emitting device can be provided.

1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to an embodiment. 1D to 1F are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to an embodiment. 1G and 1H are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to an embodiment. 1I and 1J are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to an embodiment. 1K and 1L are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to an embodiment. 2A is a schematic cross-sectional view in the vicinity of the n-side highly reflective layer 13, and FIGS. 2B and 2C are schematic plan views showing the arrangement of the n-side highly reflective layer 13 and the like. 3A and 3B are schematic cross-sectional views showing a bonding and mounting process. 3C and 3D are schematic cross-sectional views showing the bonding and mounting process. 3E and 3F are schematic cross-sectional views showing the bonding and mounting process. 3G and 3H are schematic cross-sectional views showing the bonding and mounting process. 3I and 3J are schematic cross-sectional views showing the bonding and mounting process. FIG. 4 is a schematic diagram illustrating a power feeding unit ES of the semiconductor light emitting device according to the embodiment. FIG. 5A and FIG. 5B are schematic views showing the power feeding part ES and the wire 43n. 6A and 6B are photographs of a quadruple semiconductor light emitting device manufactured in the same manner as the semiconductor light emitting device according to the example. 7A and 7B are photographs showing a continuous type semiconductor light emitting device in which a plurality of semiconductor light emitting elements are connected in series.

  With reference to FIGS. 1A to 3J, a method for manufacturing a semiconductor light emitting device according to an embodiment will be described. The semiconductor light emitting device according to the embodiment is manufactured through a manufacturing process of semiconductor light emitting elements (see FIGS. 1A to 1L) and a bonding / mounting process (see FIGS. 3A to 3J).

  1A to 1L are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to an embodiment. In the embodiment, a nitride semiconductor light emitting device is formed. As a method for growing the semiconductor layer, for example, metal organic chemical vapor deposition (MOCVD) is used, and a large number of light-emitting elements are simultaneously formed on one growth substrate. 1A to 1L typically show one element.

  Reference is made to FIG. 1A. For example, a growth substrate 1 which is a sapphire substrate is prepared. The growth substrate 1 is put into an MOCVD apparatus and thermal cleaning is performed. After growing the GaN buffer layer and the undoped GaN layer, an n-type GaN layer 2 having a thickness of about 5 μm doped with Si or the like is grown. For simplification of the drawing, the GaN buffer layer and the undoped GaN layer are included in the n-type GaN layer 2.

A light emitting layer (active layer) 3 is grown on the n-type GaN layer 2. The light emitting layer 3 is, for example, an Al _x In _y Ga _z N (0 ≦ x, y, z ≦ 1, x + y + z = 1) layer. A multiple quantum well structure in which the InGaN layer is a well layer and the GaN layer is a barrier layer may be formed. A p-type GaN layer 4 having a thickness of about 0.5 μm doped with Mg or the like is grown on the light emitting layer 3.

  The growth substrate 1 is a single crystal substrate having a lattice constant capable of epitaxial growth of GaN, and is transparent to light having a wavelength of 362 nm which is an absorption edge wavelength of GaN so that the substrate can be peeled off by laser lift-off in a later process. Selected from ones. In addition to sapphire, spinel, SiC, ZnO, or the like can be used.

  Refer to FIG. 1B. On the p-type GaN layer 4, an Ag layer having a thickness of 200 nm is deposited by electron beam evaporation, resistance heating evaporation, sputtering, etc., and patterned by lift-off to form a hole HL. Layer 5 is formed. In order to make the p-side semiconductor upper electrode layer 5 function as a reflective electrode, it is preferable to use Ag or an alloy containing Ag. Further, the initial layer may contain a metal such as Ni, Ti, or Pt that promotes contact, or ITO.

  A via electrode is disposed in the hole HL in a later process. The number of holes HL (via electrodes) per element is, for example, about 40, but one hole HL is typically shown in the drawing.

Reference is made to FIG. 1C. On the p-type GaN layer 4 so as to surround the p-side semiconductor upper electrode layer 5, the film thickness is equal to that of the p-side semiconductor upper electrode layer 5 by electron beam evaporation, sputtering, chemical vapor deposition (CVD), or the like. A SiO ₂ layer is deposited to form a fringe layer 6. The fringe layer 6 may be formed using SiN or the like in addition to SiO ₂ .

  Reference is made to FIG. 1D. An Ag layer having a film thickness of 100 nm serving as a highly reflective layer on the upper surfaces of the p-side semiconductor upper electrode layer 5 and the fringe layer 6 and on the p-type GaN layer 4 between the p-side semiconductor upper electrode layer 5 and the fringe layer 6. Further, a TiW / Ti / Pt / Au / Ti layer serving as a diffusion prevention layer is deposited to a film thickness of 250 nm / 50 nm / 100 nm / 1000 nm / 30 nm, and patterned by lift-off to form the p-side highly reflective layer 7 and p A p-side highly reflective cap layer 9 made of a laminated layer of the side diffusion preventing layer 8 is formed. The Ag layer is formed by electron beam evaporation, resistance heating evaporation, sputtering, or the like, and the TiW / Ti / Pt / Au / Ti layer is formed by electron beam evaporation or sputtering. The p-side highly reflective layer 7 may be formed of an alloy containing Ag. The Ti layer on the uppermost surface of the p-side diffusion prevention layer 8 has a function of improving adhesion with an insulating cap layer formed in the next step.

  The p-side diffusion preventing layer 8 prevents diffusion of materials used for the p-side semiconductor upper electrode layer 5 and the p-side highly reflective layer 7. For example, it can be formed using Ti, W, Pt, Pd, Mo, Ru, Ir, Au, and alloys thereof.

  The p-side highly reflective cap layer 9 is not formed near the edge of the hole HL. (The edge on the hole HL side of the p-side highly reflective cap layer 9 is disposed outside the edge of the hole HL.) The end of the p-side diffusion prevention layer 8 is the end of the p-side highly reflective layer 7. It is arranged so as to cover.

  On the element outer peripheral side, the p-side highly reflective layer 7 and the p-side diffusion prevention layer 8 are disposed on the upper surface of the fringe layer 6 so that the edges coincide. The edge of the p-side highly reflective cap layer 9 is disposed on the upper surface of the fringe layer 6 and is formed away from the semiconductor layers 2, 3, 4, so that the Ag semiconductor layer 2 in the p-side highly reflective layer 7 is formed. Prevent leakage to 3, 4

Reference is made to FIG. 1E. An insulating cap layer 10 that covers the p-side highly reflective cap layer 9 is formed. The insulating cap layer 10 is formed by depositing an insulating material such as SiO ₂ or SiN having a film thickness of 300 nm by, for example, electron beam evaporation, sputtering, CVD or the like, and patterning by lift-off.

  The insulating cap layer 10 prevents leakage of the Ag-based material used for the p-side semiconductor upper electrode layer 5 and the p-side highly reflective layer 7. In order to improve insulation, for example, an oxide layer may be formed in two stages. The insulating cap layer 10 is also disposed on the side surface of the p-side semiconductor upper electrode layer 5 that defines the hole HL.

  Reference is made to FIG. 1F. In order to secure a contact region for the n-side electrode, the p-type GaN layer 4 exposed on the bottom surface of the hole HL and the light emitting layer 3 therebelow are removed by, for example, dry etching using a chlorine-based gas to form a recess CV. To do. As an example, about 1 μm is etched beyond the junction region including the light emitting layer 3 to a depth at which the n-type semiconductor layer 2 is electrically exposed.

  Reference is made to FIG. 1G. On the n-type GaN layer 2 exposed at the bottom of the recess CV, a Ti / Ag / Ti / Pt / Au layer is deposited to a thickness of 1 nm / 200 nm / 100 nm / 200 nm / 200 nm, for example, by electron beam evaporation, sputtering, etc. The n-side via electrode 11 is formed by patterning by lift-off.

  Here, for example, the diameter of the hole HL at the position of the p-side semiconductor upper electrode layer 5 is about 40 μm, the diameter of the bottom surface of the recess CV is about 35 μm, and the diameter of the bottom surface of the via electrode 11 is about 30 μm.

Refer to FIG. 1H. Cover the p-side semiconductor upper electrode layer 5, the fringe layer 6, the p-side highly reflective cap layer 9, and the insulating cap layer 10, and deposit SiO ₂ having a thickness of 600 nm by, for example, electron beam evaporation, sputtering, CVD, etc., and lift off Then, the insulating float layer 12 is formed by patterning. The insulating float layer 12 may be formed of an insulating material such as SiN in addition to SiO ₂ . In order to improve insulation, for example, three layers of oxide layers can be formed.

  The insulating float layer 12 is also formed in the hole HL and the recess CV and covers the pn junction region exposed on the side surface of the recess CV. The insulating float layer 12 is opened on the upper surface of the n-side via electrode 11. A pn interelectrode insulating layer IS is formed by stacking the insulating cap layer 10 and the insulating float layer 12. The pn interelectrode insulating layer IS is interposed between the p-side electrode Ep and the n-side electrode En completed in a later step, and electrically separates the p-side electrode Ep and the n-side electrode En.

Reference is made to FIG. In the vicinity of the outer periphery of the element, a part of the pn inter-electrode insulating layer IS is removed by dry etching using, for example, CF ₄ gas to expose the p-side diffusion prevention layer 8 and ensure conduction for the p-side electrode. A contact hole CH for this purpose is formed.

  Reference is made to FIG. 1J. On the n-side via electrode 11, for example, a Ti / Ag / Ti / Pt / Au layer is deposited to a thickness of 1 nm / 200 nm / 100 nm / 200 nm / 200 nm by electron beam evaporation or sputtering, respectively, and patterned by lift-off. The side highly reflective layer 13 is formed. A Ti / Al / Ti / Pt / Au layer may be used. The initial Ti layer is a contact layer, and if the thickness is greater than 1 nm, the reflectance of the n-side highly reflective layer 13 may decrease. The n-side highly reflective layer 13 is formed so that its edge region overlaps with the edge region of the p-side semiconductor upper electrode layer 5 that defines the hole HL in plan view. Details of the arrangement structure of the n-side highly reflective layer 13 will be described later.

  Reference is made to FIG. 1K. A Ti / Pt / Au layer is deposited to a film thickness of 50 nm / 100 nm / 400 + 900 nm by electron beam evaporation or sputtering, and patterned by lift-off to form the conductive layer 14. By forming the film by electron beam evaporation or sputtering, the lift-off property can be improved with respect to the Au layer.

  A portion of the conductive layer 14 extending from the n-side highly reflective layer 13 to the pn interelectrode insulating layer IS covering the p-side highly reflective cap layer 9 is an n-side cap layer (element n-side connection electrode layer). 14n. The n-side via electrode 11, the n-side highly reflective layer 13, and the element n-side connection electrode layer 14n constitute an element n-side electrode En.

  A portion of the conductive layer 14 formed so as to enter the contact hole CH and electrically separated from the element n-side connection electrode layer 14n with a gap constitutes the element p-side connection electrode layer 14p. The p-side semiconductor upper electrode layer 5, the p-side highly reflective cap layer 9, and the element p-side connection electrode layer 14p constitute a p-side electrode Ep of the element.

  Reference is made to FIG. 1L. For example, dry etching using a chlorine-based gas is performed using a photoresist mask having an opening that exposes a region between adjacent elements, and the p-type semiconductor layer 4, the light-emitting layer 3, and the n-type semiconductor layer 2 are removed and grown. The substrate 1 is exposed to form streets ST that separate adjacent elements from each other. Thus, the semiconductor light emitting device according to the embodiment is formed. The semiconductor light emitting device according to the embodiment is, for example, a semiconductor light emitting device that emits blue light.

  A structure in the vicinity of the n-side highly reflective layer 13 of the semiconductor light emitting device according to the embodiment will be described with reference to FIGS. 2A is a schematic cross-sectional view in the vicinity of the n-side highly reflective layer 13, and FIGS. 2B and 2C are schematic plan views showing the arrangement of the n-side highly reflective layer 13 and the like.

  In the hole HL formed in the p-side semiconductor upper electrode layer 5 of the p-side electrode Ep, a recess CV exposing the n-type semiconductor layer 2 is formed on the bottom surface, and the n-side via electrode 11 is formed in the recess CV. Yes. In plan view, an edge E9 of the p-side highly reflective cap layer 9 surrounding the hole HL is disposed outside the edge E5 of the p-side semiconductor upper electrode layer 5 defining the hole HL in the radial direction. In plan view, the edge E5 of the hole HL surrounds the edge ECV of the recess CV formed in the semiconductor layers 2, 3, and 4.

  The p-side electrode Ep has a flat region RG formed on the upper surface of the p-side semiconductor upper electrode layer 5 inside the hole HL in the radial direction from the edge E9 of the p-side highly reflective cap layer 9, and is formed on the region RG. An edge region of the n-side highly reflective layer 13 is formed on the formed pn interelectrode insulating layer IS. In plan view, the n-side highly reflective layer 13 is formed so as to cover the hole HL, and the edge E13 of the n-side highly reflective layer 13 is outside the edge E5 of the p-side semiconductor upper electrode layer 5 and p-side highly reflective. The cap layer 9 is disposed inside the edge E9.

  That is, the n-side highly reflective layer 13 of the n-side electrode En has an edge region in plan view that is an edge region of the p-side electrode Ep that defines the hole HL (an edge region of the p-side semiconductor layer upper electrode layer 5). The p-side electrode Ep is not overlapped with the p-side highly reflective cap layer 9. In FIG. 2B, the n-side high reflection layer 13 is indicated by upper right hatching, and the p-side semiconductor upper electrode layer 5 and the p side high reflection cap layer 9 are indicated by left upward hatching. The overlapping portion of the n-side highly reflective layer 13 and the p-side semiconductor upper electrode layer 5 is indicated by cross hatching. The overlapping width WD of the edge region of the n-side highly reflective layer 13 and the edge region of the p-side electrode Ep is preferably 25 μm or less, for example.

  The n-side cap layer 14n of the n-side electrode En is formed to extend outward from the edge E13 of the n-side high reflection layer 13 with respect to the hole HL in plan view, and further, the p-side high reflection cap of the p-side electrode Ep. The layer 9 is formed to extend outward from the edge E9. That is, the n-side cap layer 14n overlaps the p-side highly reflective cap layer 9 in plan view. In FIG. 2C, the n-side cap layer 14n is indicated by upper right hatching.

  On the pn interelectrode insulating layer IS, an outer region of the edge E9 is formed so as to run over the upper surface of the p-side highly reflective cap layer 9. The upper surface S13 of the edge portion of the n-side highly reflective layer 13 formed so as to run over the region RG is at a position lower than the upper surface S12 of the pn interelectrode insulating layer IS in the outer region of the edge E9.

  The semiconductor light emitting device according to the example includes an n-side high reflection layer 13 which is a light reflection electrode portion formed as a part of the n-side electrode En, and a p-side electrode Ep formed as a light reflection electrode over the entire surface. The n-side highly reflective layer 13 and the hole forming part of the p-side electrode Ep are formed so as to overlap in the edge region in plan view. Thereby, the light incident from the light emitting layer 3 side is reflected by the n-side highly reflective layer 13 inside the hole and reflected by the p-side electrode Ep outside the hole, so that the light extraction efficiency can be improved.

  The bonding / mounting process will be described with reference to FIGS. 3A to 3J.

Refer to FIG. 3A. For example, a support substrate 21 which is a silicon substrate is prepared. A thermal oxidation process is performed to form an insulating layer 22 of SiO _{2 on the} surface. The support substrate 21 is preferably made of a material having a thermal expansion coefficient close to that of sapphire (7.5 × 10 ⁻⁶ / K) or GaN (5.6 × 10 ⁻⁶ / K) and having high thermal conductivity. . In addition to Si, AlN, Mo, W, CuW, or the like can be used. The film thickness of the insulating layer 22 should just be the thickness which can ensure insulation.

  On the insulating layer 22, a Ti / Pt / Au layer is deposited to a thickness of 600 nm / 50 nm / 1000 nm by, for example, electron beam evaporation, sputtering, etc., thereby forming a fusion layer 23 to be an electrode on the support substrate 21 side. In the post-process, the electrode layer 23 on the support substrate side, the n-side connection electrode layer 14n and the p-side connection electrode layer 14p on the element side are bonded. For this reason, the support substrate side electrode layer 23, the element n side connection electrode layer 14n, and the element p side connection electrode layer 14p, which are bonded adhesive layers, are Au-Sn, Au-In, It is formed using a metal containing Pd—In, Cu—In, Cu—Sn, Ag—Sn, Ag—In, Ni—Sn, or the like, or a metal containing Au capable of diffusion bonding.

  Refer to FIG. 3B. In the embodiment, a manufacturing process of a dual semiconductor light emitting device having a structure in which two semiconductor light emitting elements 31A and 31B are connected in series is shown. An electrode layer 23p connected to the p-side electrode EpA of the light emitting element 31A via the insulating layer 22 on the support substrate 21, an electrode connected to the n-side electrode EnA of the light emitting element 31A and the p-side electrode EpB of the light emitting element 31B. The layer 23np and the electrode layer 23n connected to the n-side electrode EnB of the light emitting element 31B are formed to be electrically separated.

  The electrode layers 23p, 23np, 23n on the support substrate 21 side and the n-side connection electrode layer 14n and the p-side connection electrode layer 14p of each element 31A, 31B are aligned and bonded, for example, in a 3MP pressure state, 300 Heat to 0 ° C. and hold for 10 minutes. Then, fusion bonding is performed by cooling to room temperature.

  Thus, the p-side electrode EpA of the light-emitting element 31A is drawn out by the electrode layer 23p, the n-side electrode EnA of the light-emitting element 31A and the p-side electrode EpB of the light-emitting element 31B are connected in series by the electrode layer 23np, and light is emitted by the electrode layer 23n. An electrical connection structure for drawing out the n-side electrode EnB of the element 31B is formed.

  Refer to FIG. 3C. For example, the growth substrate 1 is peeled off by laser lift-off by irradiating UV excimer laser light UVL from the back side of the sapphire substrate 1 and thermally decomposing the buffer layer. Note that another method such as etching may be used for peeling or removing the growth substrate 1.

  Ga generated by laser lift-off is removed with hot water or the like, and then the surface is treated with hydrochloric acid. As a result, the n-type GaN layer 2 is exposed. The surface treatment is not particularly limited as long as the nitride semiconductor can be etched, and an acid or alkali chemical such as phosphoric acid, sulfuric acid, KOH, or NaOH can be used. The surface treatment may be performed by dry etching using Ar plasma or chlorine plasma, polishing, or the like. Subsequently, the surface of the n-type GaN layer 2 is subjected to a Cl, Ar treatment using a dry etching device or a smoothing treatment using a CMP polishing device to remove the laser marks and the laser damage layer.

  Reference is made to FIG. 3D. In order to improve the light extraction efficiency, the surface of the exposed n-type GaN layer 2 is subjected to a concavo-convex process derived from a crystal structure to form a light extraction structure or a microcone structure, for example, by dipping in an alkaline solution such as a KOH solution. .

  Refer to FIG. 3E. A glare light absorbing layer 24 is formed by depositing Ti having a thickness of 20 nm, for example, by electron beam evaporation or sputtering in the outer end region of the support substrate upper electrodes 23p, 23n, thereby demarcating the power feeding portion. The power feeding unit includes the electrode layers 23p and 23n and the glare light absorption layer 24, and is a region used for wire bonding. The power feeding unit and the glare light absorption layer 24 will be described later.

Reference is made to FIG. 3F. The entire protective film 25 is formed by depositing SiO ₂ having a thickness of 350 nm, for example, by electron beam evaporation, sputtering, CVD, or the like on the entire upper surface of the elements 31A and 31B. You may form by SiN etc. The SiO ₂ film 25 is also formed on the glare light absorption layer 24.

  Reference is made to FIG. 3G. The back side of the support substrate 21 is ground and polished, for example, to a thickness of 300 μm, and the thermal resistance of the support substrate 21 is lowered. In addition, in order to secure the bonding adhesion to the package substrate described later, Ti / Pt / Au is formed on the ground / polished surface of the support substrate 21 by, for example, electron beam evaporation, sputtering, etc., to a thickness of 50 nm / 150 nm / 200 nm. A back metal layer 26 is formed. Since the back metal layer 26 does not require electrical contact properties, for example, other materials having good compatibility with the later-described bonding material can be used.

  Refer to FIG. 3H. The support substrate 21 is divided by laser scribing or dicing. In this figure, the division positions are indicated by arrows.

  Refer to FIG. 3I. The support substrate 21 to which the elements 31A and 31B are bonded is die-bonded on the package substrate 41 using a bonding material 42 such as Ag paste or AuSn. Thereafter, by wire bonding using Au wires 43p and 43n, the p-side electrode EpA of the element 31A and the n-side electrode EnB of the element 31B are connected to the power supply pads 44p and 44n of the package substrate 41, respectively, and package mounting is performed. Complete.

  Reference is made to FIG. 3J. For example, a phosphor that emits yellow light is added to the resin that seals the light emitting elements 31A and 31B and cured to form a phosphor layer 45 that covers the light emitting elements 31A and 31B. The blue light emitted from the semiconductor light emitting elements 31 </ b> A and 31 </ b> B is transmitted through the phosphor layer 45 and is emitted as white light from the semiconductor light emitting device. The semiconductor light emitting device according to the embodiment is completed through the above steps.

  FIG. 4 is a schematic diagram illustrating a power feeding unit ES of the semiconductor light emitting device according to the embodiment.

The power feeding part ES is, for example, 160 μm × 500 μm that is defined above both ends of the support substrate 21 along the arrangement direction of the semiconductor light emitting elements 31A and 31B and is disposed in a region covered with the phosphor layer 45 (see FIG. 3J). This is a rectangular region. The power feeding unit ES includes a part of the electrode layers 23p and 23n having a thickness of 1.65 μm and a glare light absorbing layer 24 having a thickness of 20 nm formed in a partial region thereon. In this figure, the SiO ₂ film 25 (see FIG. 3J) on the glare light absorption layer 24 is omitted.

  The glare light absorption layer 24 is opened at a position where wire bonding is performed to expose the electrode layers 23p and 23n (Au layer). In this drawing, the exposed regions are shown as bonding openings 23po and 23no. The opening diameters of the bonding openings 23po and 23no are, for example, about 100 μm to 120 μm. The glare light absorption layer 24 covers the electrode layers 23p and 23n at positions other than the openings 23po and 23no of the power feeding portion ES.

The bonding openings 23po and 23no are formed by, for example, lift-off using a negative photoresist or dry etching using a positive photoresist. The SiO ₂ film 25 formed on the bonding openings 23po and 23no is patterned by using, for example, a positive photoresist and then removed by reactive ion etching using a CF ₄ gas.

  The glare light absorbing layer 24 is formed of a material (Ti) that can more easily absorb the fluorescence (yellow light) emitted by the phosphor contained in the phosphor layer 45 than the material (Au) that forms the electrode layers 23p and 23n. That is, in the power feeding portion ES, the fluorescence emitted from the phosphor layer 45 is relatively easily absorbed (reflected) on the electrode layers 23p and 23n formed of a material that is relatively easily reflected (difficult to absorb). A glare light absorption layer 24 formed of a material which is difficult to be disposed. For this reason, reflection of yellow light propagating to the power supply unit ES is suppressed, and uneven color at the end of the semiconductor light emitting device (power supply unit ES) can be suppressed.

  Furthermore, the glare light absorption layer 24 is preferably formed of a material that absorbs light (blue light) emitted from the semiconductor light emitting elements 31A and 31B more easily than the material forming the electrode layers 23p and 23n. The reflection of the blue light propagating to the power supply unit ES is suppressed, and the color unevenness at the semiconductor light emitting device end (power supply unit ES) can be further suppressed.

  As described above, the semiconductor light emitting device according to the embodiment suppresses color unevenness due to light propagating to the regions other than the light emitting portions of the elements 31A and 31B (region where blue light is not generated), specifically, to the end portions of the semiconductor light emitting device. Can do.

  The step of forming the glare light absorbing layer 24 is a step of reducing the exposed areas of the electrode layers 23p and 23n at the end of the semiconductor light emitting device.

The glare light absorbing layer 24 may be formed of Cr, Ni, TiN or the like in addition to Ti. However, from the viewpoint of adhesion with the SiO ₂ film 25, Ti is preferably used.

  The power feeding part ES is defined so that the end regions on the elements 31A and 31B side where the glare light absorption layer 24 is formed overlap with the end areas on the power feeding part ES side of the elements 31A and 31B in plan view. . The overlapping width is, for example, about 5 μm to 20 μm. By disposing the power feeding part ES with respect to the elements 31A and 31B in this way, color unevenness in the vicinity of the end of the semiconductor light emitting device other than the power feeding part ES can be suppressed.

  FIG. 5A and FIG. 5B are schematic views showing the power feeding part ES and the wire 43n. FIG. 5B shows a cross section taken along line 5B-5B in FIG. 5A.

  The power feeding unit ES is electrically connected to power feeding pads 44p and 44n (see FIG. 3J) of the package substrate 41 by wire bonding using Au wires 43p and 43n. The Au wires 43p and 43n are bonded to the openings 23po and 23no by, for example, Au. The wire 1st ball diameter (bonding diameter) is, for example, about 140 μm. Electric power is supplied to the semiconductor light emitting elements 31A and 31B via the power feeding unit ES.

  6A and 6B are photographs of a quadruple semiconductor light emitting device manufactured in the same manner as the semiconductor light emitting device according to the example. 6A shows a semiconductor light emitting device sealed with a resin to which no phosphor is added, and FIG. 6B shows a semiconductor light emitting device sealed with a resin to which a yellow light emitting phosphor is added. For example, a glare light absorption layer (Ti layer) is formed in a region surrounded by a dotted line.

  In either light emitting device, it can be seen that there is no color unevenness at the end. As described above, the semiconductor light emitting device according to the embodiment is a high quality semiconductor light emitting device having no color unevenness.

  As mentioned above, although this invention was demonstrated along the Example, this invention is not restrict | limited to these.

  It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

  The present invention can be used for all semiconductor light-emitting devices including a phosphor layer. For example, it can be suitably used as a light source for automobile headlamps.

DESCRIPTION OF SYMBOLS 1 Growth substrate 2 n-type GaN layer 3 Light emitting layer 4 p-type GaN layer 5 p side semiconductor layer upper electrode layer 6 Fringe layer 7 p side high reflection layer 8 p side diffusion prevention layer 9 p side high reflection cap layer 10 insulating cap layer 11 n-side via electrode 12 insulating float layer 13 n-side highly reflective layer 14 conductive layer 14n element n-side connection electrode layer (n-side cap layer)
14p Element p-side connection electrode layer 21 Support substrate 22 Insulating layer 23 Fusion layer 23n, 23np, 23p Electrode layer 23no, 23po Bonding opening 24 Glare light absorption layer 25 Whole surface protective film 26 Back surface metal layers 31A, 31B Semiconductor light emitting element 41 Package substrate 42 Bonding material 43p, 43n Wire 44p, 44n Feeding pad 45 Phosphor layer CH Contact hole CV Recess En, EnA, EnB n-side electrode Ep, EpA, EpB p-side electrode ES Feeding part HL Hole IS pn inter-electrode insulation layer

Claims (6)

A first semiconductor layer of a first conductivity type, a light emitting layer formed on the first semiconductor layer, and a second semiconductor formed on the light emitting layer and having a second conductivity type opposite to the first conductivity type A semiconductor light emitting device comprising: a layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the second semiconductor layer;
A phosphor layer covering the semiconductor light emitting element;
A power feeding portion that is disposed in a region covered with the phosphor layer and electrically connected to the first electrode or the second electrode;
The power feeding unit is
A first material layer formed of a first material and electrically connected to the first electrode or the second electrode;
A semiconductor light emitting device comprising: a second material that is formed on a part of the first material layer by a second material that absorbs fluorescence emitted from the phosphor layer from the first material.   The semiconductor light-emitting device according to claim 1, wherein the second material absorbs light of a color emitted from the semiconductor light-emitting element from the first material.   The semiconductor light emitting device according to claim 1, wherein the second material is Ti, Cr, Ni, or TiN.   4. The semiconductor light-emitting device according to claim 1, wherein, in the power feeding unit, the second material layer covers the first material layer at a position other than a position where wire bonding is performed.   5. The semiconductor light emitting device according to claim 1, wherein an end region of the power feeding unit on the semiconductor light emitting element side overlaps with an end region of the semiconductor light emitting element in a plan view. The semiconductor light emitting element is
A recess formed so as to penetrate the light emitting layer and expose the first semiconductor layer from the second semiconductor layer side;
The first electrode electrically connected to the first semiconductor layer at the bottom surface of the recess and extending above the upper surface of the second semiconductor layer;
A hole that is electrically connected to the second semiconductor layer on an upper surface of the second semiconductor layer and surrounds the recess in plan view, and the first electrode is inserted into the second semiconductor from the recess through the hole. The second electrode formed with a hole extending above the layer;
An insulating layer disposed between the first electrode and the second electrode above the second semiconductor layer;
The second electrode is a light reflecting electrode that reflects light incident from the light emitting layer side,
The first electrode is formed so as to cover the hole in plan view, and includes a light reflecting electrode layer that reflects light incident from the light emitting layer side,
The edge area | region of the light reflection electrode layer of the said 1st electrode is formed so that it may overlap with the edge area | region which defines the hole of the said 2nd electrode in planar view. Semiconductor light emitting device.