JP5986904B2 - Semiconductor light emitting element array and vehicle lamp - Google Patents

Description

  The present invention relates to a semiconductor light emitting element array and a vehicular lamp using the same.

  A semiconductor light emitting device (LED) using a nitride semiconductor such as GaN (gallium / nitrogen) can emit ultraviolet light or blue light, and can also emit white light by using a phosphor. . Such a semiconductor light emitting element is used for illumination, for example. When a semiconductor light emitting device is used for lighting that requires high light output, such as a vehicular lamp, in general, a plurality of semiconductor light emitting devices are electrically connected in series from the viewpoint of suppressing heat generation or equalizing luminance unevenness. (Series connected semiconductor light emitting element array).

  The series connection type semiconductor light emitting element array has a configuration in which a plurality of semiconductor light emitting elements are arranged on a support substrate. The semiconductor light emitting element has a configuration in which at least a p-type semiconductor layer, an active layer (light emitting layer) for light emission, and an n-type semiconductor layer are stacked. Each of the plurality of semiconductor light emitting elements is formed such that, for example, the p-type semiconductor layer is on the support substrate side (lower surface) and the n-type semiconductor layer is on the opposite side (upper surface) of the support substrate. In the semiconductor light emitting devices adjacent to each other, a wiring layer that electrically connects the upper surface (n-type semiconductor layer) of one semiconductor light emitting device and the lower surface (p-type semiconductor layer) of the other semiconductor light emitting device. It is formed.

  The wiring layer that electrically connects the adjacent semiconductor light emitting elements is formed, for example, so as to look over the side of one of the semiconductor light emitting elements and above the support substrate viewed from between the adjacent semiconductor light emitting elements. . In general, a concavo-convex structure can exist in a region where a wiring layer is formed (for example, Patent Document 1). This concavo-convex structure induces disconnection of the wiring layer and reduces the reliability of the semiconductor light emitting element array.

US Pat. No. 7,985,970

  An object of the present invention is to provide a semiconductor light emitting element array having higher reliability than the conventional one and a uniform light emission distribution.

  According to a main aspect of the present invention, there is provided a semiconductor light-emitting element array including a support substrate and first and second semiconductor light-emitting elements arranged on the support substrate and adjacent to each other, the support substrate Are provided between the first conductive region, the second conductive region spaced apart from the first conductive region, and the first conductive region and the second conductive region. A first conductive region electrically connected to the first conductive region, and a third conductive region formed through an insulating region from the second conductive region, wherein the first semiconductor light emitting element comprises: A first lower electrode disposed on the first conductive region and electrically conducting with the first conductive region; a first optical semiconductor stack disposed on the first lower electrode; And a first upper electrode selectively disposed on the first optical semiconductor stack, the second semiconductor The optical element is disposed on the second conductive region, and is disposed on the second lower electrode that is electrically connected to the second conductive region, the second lower electrode, and the support substrate. A second optical semiconductor laminate having a projecting portion projecting above the third conductive region, a hole penetrating the projecting portion and looking into the third conductive region, and the second optical semiconductor laminate And a second upper electrode electrically connected to the third conductive region of the support substrate through the hole, and a semiconductor light emitting element array.

  It is possible to obtain a semiconductor light emitting element array having higher reliability than the conventional one and a uniform light emission distribution.

1A to 1C are a plan view and a cross-sectional view showing a semiconductor light emitting element array according to a first reference example. 2A and 2B are a plan view and a cross-sectional view showing a semiconductor light emitting element array according to a second reference example. and, 3A to 3D are a plan view and a cross-sectional view showing a semiconductor light emitting element array according to a third reference example. 4A to 4C are a plan view and a cross-sectional view showing a semiconductor light emitting element array according to an embodiment. , , and, 5A to 5N are cross-sectional views illustrating a state in which the semiconductor light emitting element array according to the embodiment is manufactured. 6A to 6C are a plan view and a cross-sectional view showing a modification of the semiconductor light emitting element array according to the embodiment. 7A and 7B are conceptual diagrams showing the configuration of a vehicular lamp (headlamp) incorporating a semiconductor light emitting element array according to an embodiment.

  FIG. 1A is a schematic plan view showing a semiconductor light emitting element array (LED array) 200 according to a first reference example. Note that the relative sizes of the components shown in the figure are different from the actual ones.

  The LED array 200 according to the first reference example includes a support substrate 210 and, for example, four semiconductor light emitting elements (LED elements) 201 arranged on the support substrate 210. The LED array 200 has, for example, a rectangular shape with a width of 6000 μm in the direction in which the LED elements are arranged and a width of 1000 μm in a direction perpendicular to the direction.

  Each LED element 201 includes an optical semiconductor stack 202 including n-type and p-type GaN-based semiconductors, and the n-type semiconductor of the optical semiconductor stack 202 is electrically connected to the first electrode 208. A p-type semiconductor is electrically connected to the second electrode 211. The first electrode 208 of the predetermined LED element 201 is electrically connected to the second electrode 211 of the adjacent LED element. Thereby, the some LED element 201 is electrically connected in series. Electric power is supplied to the plurality of LED elements 201 connected in series via power supply pads 215 and 216 arranged at both ends of the support substrate 210.

  1B and 1C are an enlarged plan view showing a part of the LED array 200 and a cross-sectional view showing an IB-IB cross section of the LED array 200 shown in FIG. 1B. Below, the structure of a predetermined | prescribed LED element (1st LED element 201a) and the LED element (2nd LED element 201b) adjacent to it among several LED elements arranged on the support substrate 210 is demonstrated. . However, it is assumed that the LED elements other than the first and second LED elements have the same configuration.

  As shown in FIG. 1B, the first and second LED elements 201a and 201b have, for example, a rectangular planar shape extending in a direction in which a plurality of LED elements are arranged. Regarding the dimensions of the LED elements, for example, the width in the direction in which the plurality of LED elements are arranged is 1400 μm, and the width in the direction orthogonal to the direction is 900 μm. For example, the first electrode 208 has a configuration in which a plurality of LED elements extend in a direction in which a plurality of LED elements are arranged and a plurality of first electrodes 208 are arranged in a direction orthogonal to the direction.

  As shown in FIG. 1C, each of the first and second LED elements 201a and 201b includes a GaN-based optical semiconductor stack 202 including a p-type GaN layer 224, an active layer 223, and an n-type GaN layer 222, and an optical semiconductor stack 202. P-side electrode 203 formed on the back surface (p-type GaN layer 224 side, support substrate 210 side or lower side of the drawing), etch stop layer 204 formed side by side on the same plane as p-side electrode 203, and light And an n-side electrode (first electrode) 208 selectively formed on the surface of the semiconductor stack 202 (on the n-type GaN layer 222 side, the opposite side of the support substrate 210 or the upper side in the drawing). In addition, in the figure, the code | symbol of each structure of the 2nd LED element 201b is abbreviate | omitted for convenience.

  The etch stop layer 204 is a layer that functions as an etch stopper in the manufacturing process of the LED element (or LED array). The etch stop layer 204 has electrical insulation.

  The first and second LED elements 201 a and 201 b (or the optical semiconductor stack 202) have a cross-sectional shape such that their side surfaces gradually approach the adjacent LED elements toward the support substrate 210. Such a shape is referred to as a forward tapered shape.

  Each of the first and second LED elements 201a and 201b is provided on a support substrate 210 having an insulating film 209 formed on the surface thereof, with a fusion layer 212 including a first adhesive layer 205 and a second adhesive layer 206 interposed therebetween. Supported. The fusion layer 212 has electrical conductivity and is electrically connected to the p-side electrode 203.

  Here, the region of the fusion layer 212 that fuses the first LED element 201a and the support substrate 210 and supports the first LED element 201a is referred to as a first conductive region 212a. In addition, a region of the fusion layer 212 that fuses the second LED element 201a and the support substrate 210 and supports the second LED element 201b is referred to as a second conductive region 212b. A groove region 213 is formed between the first conductive region 212a and the second conductive region 212b, and the first and second conductive regions 212a and 212b are directly electrically insulated. ing. The first conductive region 212a has an exposed region (second electrode) 211 that protrudes from the first LED element 201a on the second LED element 201b side in a plan view.

  Side surfaces of the first and second LED elements 201a and 201b (or side surfaces of the optical semiconductor stack 202 and the etch stop layer 204), side surfaces of the first and second conductive regions 212a and 212b, and the groove region 213 On the bottom surface (or the surface of the support substrate 210 exposed between the first and second conductive regions 212a and 212b), a protective film 207 having electrical insulation is formed except for the exposed region 211. Furthermore, a wiring electrode 214 is formed on the surface of the protective film 207. The wiring electrode 214 straddles the groove region 213, and the n-side electrode 208 of the second LED element 201b and the exposed region 211 of the first conductive region 212a (that is, the p-side electrode 203 of the first LED element 201a). And are electrically connected. Accordingly, the first and second LED elements 201a and 201b are electrically connected in series.

  The first and second LED elements 201a and 201b (the optical semiconductor stack 202 and the etch stop layer 204) and the side surface of the fusion layer 12 (the side surfaces of the first and second conductive regions 212a and 212b or the groove portion 213) On the side surface), a step may be formed at the boundary between the layers constituting them. The wiring electrodes 214 passing through the side surfaces of the first and second LED elements 201a and 201b and the fusion layer 212 through the protective film 207 are broken or disconnected due to a stress generated at a step which can be formed at the boundary between the layers. May cause. For this reason, it is desirable that the region where the wiring electrode 214 is formed is designed to have as few steps as possible. More specifically, the wiring electrode 214 electrically connects the n-side electrode 208 of the second LED element 201b and the p-side electrode of the first LED element 201a without straddling the groove region 213. It is preferable. Further, when the wiring distance of the wiring electrode 214 is long, the resistance component of the wiring electrode 214 becomes large, and a problem that the voltage drop due to the wiring electrode 214 becomes large may occur. For this reason, it is desirable to design the wiring distance of the wiring electrode 214 to be as short as possible.

  2A and 2B are a schematic plan view showing a part of the LED array 300 according to the second reference example, and a cross-sectional view showing a IIB-IIB cross section of the LED array 300 shown in FIG. 2A. Hereinafter, the difference between the LED array according to the first reference example and the configuration of the LED array according to the second reference example will be mainly described with reference to FIGS. 2A and 2B.

  As in the LED array according to the first reference example, the LED array 300 according to the second reference example includes a plurality of LED elements including the first and second LED elements 301a and 301b adjacent to each other, and an insulating film on the surface. 309 is arranged on a support substrate 310 on which 309 is formed. Each of the first and second LED elements 301a and 301b is supported on a support substrate 310 via a fusion layer 312 composed of first and second adhesive layers 305 and 306. In addition, each of the first and second LED elements 301a and 301b is an optical semiconductor multilayer 302 including a p-type GaN layer 324, an active layer 323, and an n-type GaN layer 322, as in the LED element according to the first reference example. A p-side electrode 303, an etch stop layer 304, and an n-side electrode 308.

  Here, a region of the fusion layer 312 that supports the first LED element 301a and is electrically connected to the p-side electrode 303 is defined as a first conductive region 312a, and the second LED element 301b. And a region of the fusion layer 312 that is electrically connected to the p-side electrode 303 is defined as a second conductive region 312b. Further, in the fusion layer 312, a region located between the first and second conductive regions 312a and 312b is defined as a third conductive region 312c. The first conductive region 312a and the third conductive region 312c are formed continuously, and the first and third conductive regions 312a and 312c are electrically conductive. Further, the groove region 313 is disposed between the second conductive region 312b and the third conductive region 312c so as to completely divide the two regions and do not directly connect the two regions. Therefore, the groove region 313 functions as an insulating region, and the second and third conductive regions 312b and 312c are directly electrically insulated. The first and second conductive regions 312a and 312b have portions that overlap with the first and second LED elements 301a and 301b, respectively, in plan view. The third conductive region 312c has a portion exposed from the first and second LED elements 301a and 301b in plan view.

  The p-side electrode 303 of the first LED element 301a is disposed on the first conductive region 312a and is electrically connected to the first conductive region 312a and the third conductive region 312c.

  The p-side electrode 303 of the second LED element 301b is disposed on the second conductive region 312b and is electrically connected to the second conductive region 312b. However, the third conductive region 312c (or the first conductive region 312a) is directly electrically insulated by the groove region 313 and the etch stop layer 304 having electrical insulation.

  In the second LED element 301 b, the optical semiconductor stack 302 is disposed on the p-side electrode 303. In addition, the optical semiconductor laminate 302 has an overhanging portion 302c that protrudes above the groove region 313 and the third conductive region 312c. The protruding portion 302c of the optical semiconductor stack 302 is supported by the third conductive region 312c of the fusion layer 312 via the etch stop layer 304 having electrical insulation. The optical semiconductor stack 302, particularly the p-type GaN layer 324, is not directly connected to the third conductive region 312c.

  The side surface of the projecting portion 302c of the second LED element 301b is formed to be inclined so as to gradually approach the first LED element 301a toward the support substrate 310. The wiring electrode 314 is in contact with the third conductive region 312c through the surface of the insulating protective film 307 formed on the side surface of the protruding portion 302c, and the n-side electrode 308 and the third conductive region of the second LED element 301b. 312c is electrically connected. That is, the second conductive region 312b, and the p-side electrode 303 and the optical semiconductor stack 302 of the second LED element 301b are electrically connected to the third conductive region 312 indirectly via the wiring electrode 314. It will be. Thereby, the first and second LED elements 301a and 301b are electrically connected in series.

  In the LED array 300 according to the second reference example, the groove region 313 is disposed below the projecting portion 302c of the optical semiconductor stack 302 in the second LED element 301b. The wiring electrode 314 is electrically connected to the third conductive region 312c continuous with the first conductive region 312a without straddling the groove region 313. That is, the step that can be formed in the region where the wiring electrode is formed can be reduced as compared with the LED array according to the first reference example. Thereby, the reliability is improved as compared with the LED array according to the first reference example. In addition, as compared with the LED array according to the first reference example, the wiring distance of the wiring electrode 314 can be shortened by the wiring distance necessary for straddling the groove region 313.

  FIG. 3A shows a schematic plan view of an LED array 350 according to a third reference example. FIG. 3B shows a planar shape of the fusion layer 312 of the LED array 350. In FIG. 3B, the optical semiconductor stack 302 disposed above the fusion layer 312 is indicated by a dotted line. Further, FIGS. 3C and 3D show a IIIC-IIIC cross section and a IIID-IIID cross section of the LED array 350 shown in FIG. 3A, respectively. The LED array 350 according to the third reference example is a modification of the LED array 300 (see FIG. 2) according to the second reference example.

  As shown in FIG. 3A, the n-side electrodes 308 of the LED elements 301a and 301b according to the third reference example extend in the direction in which the plurality of LED elements are arranged, and the surface of the optical semiconductor stack 302 (n-type GaN layer 322). A comb including a common portion 308a disposed on one end side, and a comb tooth portion 308b extending in a direction orthogonal to the direction in which the common portion 308a extends and electrically connected to the common portion 308a on one end side. It has a tooth-like planar shape.

  The third conductive region 312c is formed only on the extended line of the common portion 308a in plan view, and is exposed from between the first and second LED elements 301a and 301b. The wiring electrode 314 electrically connects the common part 308a of the n-side electrode 308 and the third conductive region 312c. Thereby, the 1st and 2nd LED element 301a, 301b is electrically connected in series.

  As shown in FIG. 3B, the planar shape of the fusion layer 312 in the LED array 350 is such that one corner of the rectangular shape protrudes directly below the protruding portion 302c of the LED element adjacent to the LED array 350 (third conductive region 312c). One corner has a concave shape so as to escape from the protruding portion of the adjacent fusion layer 312. Further, as shown in FIGS. 3B to 3D, the groove region 313 is formed in the second conductive region 312 b and the third conductive region in the region where the wiring electrode 314 and the third conductive region 312 c are connected (FIG. 3C). In the region other than the region where the wiring electrode 314 and the third conductive region 312c are connected (FIG. 3D), the first conductive region 312a and the second conductive region 312b are separated. To be arranged. Thereby, similarly to the LED array according to the second reference example, the second conductive region 312c, the p-side electrode 303 of the second LED element 3101b, and the optical semiconductor stack 302 are indirectly connected via the wiring electrode 314. Thus, it is electrically connected to the third conductive region 312c (or the first conductive region 312a).

  Also, in the LED array 350 according to the third reference example, as shown in FIG. 3A, the third conductive region 312c is exposed only on one end side where the common portion 308a of the n-side electrode 308 is formed, and the n-side electrode 308 is exposed. The common electrode 314 continuing to the common portion 308a is electrically connected to the third conductive region 312c. In a region other than the region where the wiring electrode 314 and the third conductive region 312c are connected (FIG. 3D), the third conductive region 312c is exposed from between the first and second LED elements 301a and 301b, and Since it is not necessary to form the wiring electrode 314 on the side surface of the second LED element 301b and the upper surface of the third conductive region 312c, the optical semiconductor stack 302 of the first LED element 301a can be formed to that extent. (Expansion part 302d). Thereby, the light emission amount is improved as compared with the LED array 300 (see FIG. 2) according to the second reference example.

  In the LED array 350 according to the third reference example, regions other than the region where the wiring electrode 314 and the third conductive region 312c are connected can be formed by expanding the optical semiconductor stack 2 (expansion portion 302d). As a result, the overall planar shape of the optical semiconductor stack 302 becomes a shape in which a rectangular corner is cut out. The corners (notches 302e) of the optical semiconductor stack 302 do not contribute to light emission.

  In addition, it is difficult to form the comb-tooth portion 308b extending from the common portion 308a of the n-side electrode 308 in the extended portion 302d of the optical semiconductor stack 302, and thus it is difficult to diffuse current in this region. It is. Therefore, there is a possibility that the light emission intensity of the extended portion 302d is reduced as compared with the light emission intensity of the region other than the extended portion 302d.

  As described above, although the LED array 350 according to the third reference example is expected to improve the light emission amount as compared with the LED array 300 according to the second reference example (see FIG. 2), the first and second LED elements 301a, There is a concern that light emission unevenness (light emission distribution) becomes remarkable in the region between 301b.

  4A and 4B are a schematic plan view showing a part of the LED array 100 according to an embodiment of the present invention, and a cross-sectional view showing a cross section taken along the line IVB-IVB of the LED array 100 shown in FIG. 4A. FIG. 4C shows a planar shape of the fusion layer 12 of the LED array 100. In FIG. 4B, the optical semiconductor stack 2 disposed above the fusion layer 12 is indicated by a dotted line. Hereinafter, with reference to FIG. 4A to FIG. 4C, differences in the configuration of the LED array according to the embodiment of the present invention from the LED array according to the third reference example will be mainly described.

  As shown in FIG. 4A, the LED array 100 according to the embodiment includes a plurality of LED elements including the first and second LED elements 101a and 101b adjacent to each other, as in the LED array according to the third reference example. The structure is arranged on a support substrate 10 having an insulating film 9 formed on the surface.

  Further, as shown in FIG. 4B, each of the first and second LED elements 101a and 101b is provided on the support substrate 10 via the fusion layer 12 including the first and second adhesive layers 5 and 6. Supported. Each of the first and second LED elements 101a and 101b is an optical semiconductor stack 2 composed of a p-type GaN layer 24, an active layer 23, and an n-type GaN layer 22, as in the LED element according to the third reference example. And a p-side electrode 3, an etch stop layer 4, and an n-side electrode 8.

  The region of the fusion layer 12 that supports the first LED element 101a and is electrically connected to the p-side electrode 3 is the first conductive region 12a. The region of the fusion layer 12 that supports the second LED element 101b and is electrically connected to the p-side electrode 3 is the second conductive region 12b. Further, in the fusion layer 12, a region located between the first and second conductive regions 12a and 12b is a third conductive region 12c. A groove region 13 as an insulating region is disposed between the second conductive region 12b and the third conductive region.

  In the second LED element 101b, the optical semiconductor laminate 2 has a protruding portion 2c that protrudes above the groove region 13 and the third conductive region 12c. The projecting portion 2 c of the optical semiconductor stack 2 is supported by the third conductive region 12 c of the fusion layer 12 through the etch stop layer 4 having electrical insulation.

  Further, the overhanging portion 2c of the optical semiconductor laminate 2 and the etch stop layer 4 that supports the overhanging portion 2c are provided with a hole portion 2h that looks into the third conductive region 12c. The hole 2 h is, for example, a quadrangular pyramid whose opening area gradually decreases toward the support substrate 10. The hole 2h may be conical, for example, whose opening area gradually decreases toward the support substrate 10. A wiring electrode 14 is formed on the inner side surface of the hole 2 h via the protective film 7.

  As shown in FIG. 4C, the planar shape of the fusion layer 12 is the same as that of the fusion layer according to the third reference example, and one corner of the rectangle protrudes immediately below the overhanging portion 2c of the adjacent LED element. It becomes a shape dented so that one corner may escape from the protruding part of the adjacent fusion bonding layer 2. Similarly to the fusion layer according to the third reference example, the groove region 13 is also continuously provided so as to divide the second conductive region 12b and the first and third conductive regions 12a and 12c. It has been. Thereby, there is no region where the second conductive region 12b is directly connected to the first and third conductive regions 12a and 12c.

  In the LED array 100 according to the embodiment, the wiring electrode 14 electrically connects the n-side electrode 8 and the third conductive region 12 c through the hole 2 h provided in the projecting portion 2 c of the optical semiconductor stack 2. For this reason, it is not necessary to provide a region for forming the wiring electrode between the first and second LED elements, and it is not necessary to provide a notch (see FIG. 3) of the optical semiconductor stack. That is, the planar shape of the optical semiconductor stack 2 can be made rectangular as shown in FIG. 4A. Moreover, the comb-tooth part 8b extended from the common part 8a of the n side electrode 8 can be formed to the edge of the surface of the optical semiconductor laminate 2. Therefore, uneven light emission in the region between the first and second LED elements 101a and 101b is suppressed.

  In the LED array 350 according to the third reference example, the wiring electrode 314 is formed on one side surface of the optical semiconductor stack 302 (the overhang portion 302c) (see FIG. 3). When the wiring electrode 314 is broken or disconnected on the side surface of the optical semiconductor stack 302, the n-side electrode 308 and the third conductive region 312c are not electrically connected.

  In contrast, in the LED array 100 according to the embodiment, the wiring electrode 14 is formed on the inner side surface (four side surfaces) of the quadrangular pyramid hole 2h. Even when a fracture or disconnection occurs on any one of the four side surfaces of the wiring electrode formed in the hole 2h, the n-side electrode 8 and the third conductive material are electrically connected to each other as long as the other side surfaces are electrically connected. The region 12c is electrically connected. Therefore, it is considered that the LED array 100 according to the embodiment is more reliable than the LED array 350 according to the third reference example. Similarly, when the hole 2h is conical, the wiring electrode 14 is formed on the entire inner surface of the hole 2h, so that even if a partial breakage or disconnection occurs, the other part is electrically If it is conductive, electrical conduction between the n-side electrode 8 and the third conductive region 12c can be ensured.

  Hereinafter, with reference to FIG. 5A to FIG. 5N, in the manufacturing method of the LED array 100 according to the embodiment, the region where the n-side electrode and the third conductive region are electrically connected, that is, the vicinity of the hole of the optical semiconductor stack The explanation will be focused on. Note that the relative sizes of the components shown in the figure are different from the actual ones.

  First, as shown in FIG. 5A, a growth substrate 1 made of sapphire is prepared, and an optical semiconductor stack 2 made of a nitride-based semiconductor is formed using a metal organic chemical vapor deposition (MOCVD) method. Specifically, for example, after putting the sapphire substrate 1 into the MOCVD apparatus, thermal cleaning is performed, and after growing the GaN buffer layer 20 and the undoped GaN layer 21, n-type GaN having a thickness of about 5 μm doped with Si or the like. A layer 22, a multiple quantum well light emitting layer (active layer) 23 including an InGaN quantum well layer, and a p-type GaN layer 24 having a thickness of about 0.5 μm doped with Mg or the like are sequentially grown. The growth substrate 1 is a single crystal substrate having a lattice constant capable of epitaxial growth of GaN, and is transparent to light having a wavelength of 362 nm which is an absorption edge wavelength of GaN so that the substrate can be peeled off by laser lift-off in a later process. Selected from ones. In addition to sapphire, spinel, SiC, ZnO, or the like may be used.

  Thereafter, an Ag layer having a film thickness of 200 nm is formed on the surface of the optical semiconductor stack 2 (the surface of the p-type GaN layer 24) by an electron beam evaporation method, and patterned by a lift-off method or the like to form a p-side electrode 3 having a predetermined shape. . In order for the p-side electrode 3 to function as a reflective electrode, it is preferable to use Ag, Pt, Ni, Al, Pd, and alloys or laminated structures thereof as the p-side electrode 3. Further, an ohmic junction layer such as ITO (indium tin oxide) may be sandwiched between the p-side electrode 3 and the optical semiconductor laminate 2. When sandwiching the ohmic junction layer, the side surface of the ohmic junction layer may be covered with a p-side electrode 3 as a reflective electrode.

Next, as shown in FIG. 5B, SiO ₂ having the same film thickness as that of the p-side electrode 3 is formed on the optical semiconductor stack 2 around the p-side electrode 3 (on the p-type GaN layer 24) by sputtering. An etch stop layer 4 is formed. The etch stop layer 4 functions as an etch stopper in an etching process described later with reference to FIG. 5L. Further, as described above, the etch stop layer 4 includes the p-side electrode 3 or the optical semiconductor stack 2 (particularly, the overhanging portion 2C, see FIG. 4B) and the third conductive region 12c in the finally manufactured LED array. And directly supporting the optical semiconductor stack 2 (particularly, the protruding portion).

  Next, as shown in FIG. 5C, a 200 nm-thick Au film is formed in the region including the p-side electrode 3 and the etch stop layer 4 using a sputtering method, and patterned by a lift-off method or the like. 1 adhesive layer 5 is formed. Here, the first adhesive layer 5 is patterned so that a gap 5z is provided in a part of the etch stop layer 4.

  The first adhesive layer 5 may be formed after forming a diffusion prevention layer or the like in a region including the p-side electrode 3 and the etch stop layer 4. The diffusion prevention layer is for preventing the diffusion of the material used for the p-side electrode 3, and when the p-side electrode 3 contains Ag, Ti, W, Pt, Pd, Mo, Ru, Ir, Au, and These alloys can be used.

  Next, as shown in FIG. 5D, the optical semiconductor laminate 2 is divided into a plurality of elements by using a dry etching method using a resist mask and chlorine gas. The side surface of the divided optical semiconductor stack 2 has a forward tapered shape with respect to the growth substrate 1.

  Next, as shown in FIG. 5E, a support substrate 10 made of Si is prepared, and a thermal oxidation process is performed to form an insulating film (thermally oxidized SiO 2 film) 9 on the surface. The support substrate 10 is preferably made of a material having a thermal expansion coefficient close to that of sapphire (7.5 × 10 −6 / K) or GaN (5.6 × 10 −6 / K) and having high thermal conductivity. For example, Si, AlN, Mo, W, CuW, or the like can be used. The film thickness of the insulating film 9 should just be the thickness which can achieve the objective of ensuring insulation.

  Next, a second adhesive layer 6 made of AuSn (Sn: 20 wt%) having a thickness of 1 μm is formed on the insulating film 9 by resistance heating vapor deposition. The material of the first adhesive layer 5 (see FIG. 5C) and the material of the second adhesive layer 6 are Au-Sn, Au-In, Pd-In, Cu-In, Cu-Sn that can be fusion bonded. , Ag-Sn, Ag-In, Ni-Sn, or the like, or a metal containing Au capable of diffusion bonding can be used.

  As shown in FIGS. 5F and 5G, the second adhesive layer 6 can be formed using, for example, a lift-off method. First, a photoresist (for example, Clariant Co. photoresist AZ5200) is applied to the entire surface of a support substrate 10 (support substrate 10 having an insulating film 9 formed on the surface) subjected to a thermal oxidation treatment, and a hot plate set at 90 ° C. or higher. And pre-bake for about 90 seconds in the atmosphere. Next, a pattern is exposed on the photoresist using ultraviolet light (UV light) with a first exposure amount of 17 mJ. The exposed photoresist is subjected to reversal baking for about 90 seconds in an atmosphere at 120 ° C. to thermally crosslink the exposed portion. Next, the entire surface of the support substrate 10 is irradiated with UV light at a reversal exposure amount of 600 mJ. Further, the photoresist pattern PR1 is formed (in addition to the portion to be the second adhesive layer 6) by dipping in a developing solution for 130 seconds and performing development processing. The photoresist pattern PR <b> 1 formed in this way has a reverse tapered shape with respect to the support substrate 10 at the periphery. Note that the resist and photolithography conditions to be used can be changed as appropriate.

  Next, a metal laminate 6 made of Ti (150 nm) / Ni (50 nm) / Au (100 nm) / Pt (200 nm) / AuSn (1000 nm, Sn: 20 wt%) is formed using a resistance heating vapor deposition method, Thereafter, by lift-off, the second adhesive layer 6 having an end tapered toward the support substrate 10 as shown in FIG. 3G is formed. The region where the photoresist pattern PR1 has been formed becomes a gap 6z. Note that the second adhesive layer 6 can be formed by using a dry etching method or a wet etching method in addition to the lift-off method.

  Next, as shown in FIG. 5H, the first adhesive layer 5 and the second adhesive layer 6 are contacted so that the gap 5z of the first adhesive layer 5 and the gap 6z of the second adhesive layer 6 overlap each other. And heated to 300 ° C. under a pressure of 3 MPa and held for 10 minutes. Then, fusion bonding is performed by cooling to room temperature. The fusion layer 12 is formed by this fusion bonding. Further, the gap 5z of the first customer service layer 5 and the gap 6z of the second adhesive layer 6 are integrated to form the groove region 13.

  Thereafter, as shown in FIG. 5I, UV excimer laser light is irradiated from the back side of the sapphire substrate 1, and the buffer layer 20 is thermally decomposed to peel off the sapphire substrate 1 by laser lift-off. Note that another method such as etching may be used for peeling or removing the substrate 1.

  Next, as shown in FIG. 5J, Ga generated by laser lift-off is removed with hot water or the like, and then surface-treated with hydrochloric acid. As a result, the n-type Gan layer 22 is exposed. Any surface treatment can be used as long as it can etch a nitride semiconductor, and acids such as phosphoric acid, sulfuric acid, KOH, and NaOH, and chemicals such as alkali can also be used. The surface treatment may be performed by dry etching using Ar plasma or chlorine plasma, polishing, or the like. Further, the surface of the n-type GaN layer 22 is smoothed using a Cl or Ar treatment using a dry etching apparatus such as RIE or a CMP polishing apparatus to remove a laser mark or a laser damage layer. In order to improve the light extraction efficiency, the surface of the n-type GaN layer 22 exposed may be subjected to uneven processing (light extraction structure or microcone structure is formed).

  Next, as shown in FIG. 5K, a photoresist PR2 having a predetermined pattern is formed on the optical semiconductor laminate 2. Thereafter, the end portion (a part of the overhanging portion) of the optical semiconductor laminate 2 exposed from the photoresist PR2 is etched by a dry etching method using chlorine gas until the etch stop layer 4 is exposed. As a result, as shown in FIG. 5L, the opening 2c of the optical semiconductor stack 2 is gradually reduced in area toward the support substrate 10 and a hole 2h surrounded by the optical semiconductor stack 2 is formed. . The shape of the hole 2h on the surface of the optical semiconductor laminate 2 is a square shape having a side of about 30 μm.

Next, the protective film 7 made of SiO ₂ is formed on the entire upper surface of the element formed in the above-described process by chemical vapor deposition (CVD) or the like. Thereafter, a part of the protective film 7 formed on the optical semiconductor stack 2, and the protective film 7 on the bottom surface of the hole 2 h of the optical semiconductor stack 2 and the etch stop are performed by dry etching using a CF ₄ / Ar mixed gas. A portion of layer 4 is etched. As a result, as shown in FIG. 5M, the hole 2h penetrates the protruding portion 2c of the optical semiconductor stack 2 and also the etch stop layer 4, and looks into the third conductive region 12c. Note that a wet etching method using BHF or the like may be used for etching the protective film 7 and the etch stop layer 4.

  Next, as shown in FIG. 5N, a 1 nm thick Ti layer, a 200 nm thick Al layer, a 100 nm thick Ti layer, and a 2 μm thick Au layer are stacked in this order by electron beam evaporation. By patterning by lift-off, the n-side electrode 8 that is in ohmic contact with the n-type GaN layer 22 and the wiring electrode 14 that connects the n-side electrode 8 and the third conductive region 12c are formed. The n-side electrode 8 and the wiring electrode 14 are formed on the inner surface of the hole 2c via the protective film 7 continuously from the surface of the optical semiconductor stack 2 (n-type GaN layer 22).

  Thereafter, the support substrate 10 is divided by laser scribing or dicing. As a result, an LED array including a plurality of LED elements including the first and second LED elements 101a and 101b is completed. When the blue GaN light emitting element is whitened, a phosphor (for example, yellow light emission) is put in a resin for sealing and filling the light emitting element.

  6A is a schematic plan view showing a modification of the LED array according to the embodiment, FIG. 6B is a plan view showing a fusion layer of the LED array, and FIG. 6C is a cross-sectional view taken along the line VIB-VIB of the LED array shown in FIG. 6A. FIG.

  The number of holes 2h provided in the optical semiconductor stack 2 is not limited to one, and two or more holes may be provided as shown in FIG. 6A. A configuration in which a plurality of regions that electrically connect the n-side electrode 8 and the third conductive region 12c are provided may be more preferable from the viewpoint of improving reliability.

  In FIG. 6A, in the second LED element 101b, holes 2h are provided at two corners on the edge side close to the first LED element 101a. In this case, as shown in FIG. 6B, the third conductive region 12c of the fusion layer 12 is provided so as to protrude directly below each of the projecting portions 2c in which the holes 2h are formed. 12b has a concave shape so as to escape from the third conductive region 12c. Further, the groove region 13 is continuously provided so as to divide the second conductive region 12b, the first conductive region 12a, and the two third conductive regions 12c. As a result, there is no region where the second conductive region 12b is directly connected to the first conductive region 12a and the two third conductive regions 12c.

  As shown in FIG. 6C, the groove region 13 may be filled with an insulating member 13a and used as an insulating region. That is, the second conductive region 312b and the third conductive region 312c may not be directly electrically connected. The p-side electrode 3 may be formed in contact with the etch stop layer 4.

  7A and 7B are conceptual diagrams showing the configuration of a vehicular lamp (headlamp) 50 incorporating the LED array 100 according to an embodiment of the present invention.

  FIG. 7A shows an example in which an irradiation lens 105 is used as the irradiation optical system 51. The irradiation lens 105 is set so that the light source image 106 of the LED array 100 is projected onto a virtual vertical screen (irradiation surface) 107 facing the front end of the vehicle.

  The irradiation optical system 51 may use a multi-reflector (reflection surface) 103 and an irradiation lens 105 as shown in FIG. 7B. The headlamp 50 shown in FIG. 7B is a multi-reflector partitioned into a light source 102 including a phosphor layer (wavelength conversion layer) 108 disposed so as to cover the light emitting surface of the LED array 100 and a plurality of small reflection regions. An illumination optical system 51 including a reflective surface 103, a shade 104, and an illumination lens 105 is configured.

  As shown in FIG. 7B, the light source 102 is arranged so that the irradiation direction (light emitting surface) is upward, and the reflecting surface 103 is set so that the first focal point is in the vicinity of the light source 102 and the second focal point is the upper end of the shade 104. It is a spheroid reflecting surface set in the vicinity of the edge, and is arranged so as to cover a range from the side of the light source 102 to the front so that the light from the light source 102 enters.

  As shown in FIG. 7B, the reflecting surface 103 irradiates the light source image 106 of the LED array 100 of the light source 102 in the predetermined light distribution shape to the front of the vehicle and faces the front end of the vehicle in a virtual vertical screen (irradiation surface) 107. A light source image 106 of the LED array 100 is projected on the top.

  The shade 104 is a light-shielding member for shielding a part of the reflected light from the reflective surface 103 to form a cut-off line suitable for a headlamp, with the upper edge positioned in the vicinity of the focal point of the irradiation lens 105. It is disposed between the irradiation lens 105 and the light source 102.

  The irradiation lens 105 is disposed on the front side of the vehicle and irradiates the irradiation surface 107 with the reflected light from the reflection surface 103.

  As mentioned above, although this invention was demonstrated along the Example and the modification, this invention is not limited to these. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

DESCRIPTION OF SYMBOLS 1 ... Growth substrate, 2 ... Optical semiconductor lamination | stacking (GaN-type light emission part), 3 ... P side electrode (reflection electrode), 4 ... Etch stop layer, 5 ... 1st adhesion layer, 6 ... 2nd adhesion layer, 7 ... Protective film, 8 ... n-side electrode, 9 ... insulating layer, 10 ... support substrate, 12 ... fused layer, 12a to 12c ... first to third conductive regions, 13 ... groove region, 14 ... wiring electrode, 20 ... buffer layer, 21 ... undoped GaN layer, 22 ... n-type GaN layer, 23 ... active layer (light emitting layer), 24 ... p-type GaN layer, 50 ... vehicular lamp (head lamp), 51 ... projection optical system, 100 DESCRIPTION OF SYMBOLS ... LED array (Example), 101 ... LED element, 108 ... Phosphor layer (wavelength conversion layer), 102 ... Light source, 103 ... Reflecting surface, 104 ... Shade, 105 ... Irradiation lens, 106 ... Light source image, 107 ... Irradiation Surface, 200 ... LED array (first reference example), 300 ... LED Ray (second Example), 350 ... LED array (Third Example).

Claims (5)

A semiconductor light-emitting element array comprising: a support substrate; and a plurality of semiconductor light-emitting elements including first and second semiconductor light-emitting elements arranged on the support substrate and adjacent to each other,
The surface of the support substrate is
A first conductive region;
A second conductive region provided spaced apart from the first conductive region;
Provided between the first conductive region and the second conductive region, electrically connected to the first conductive region, and formed through an insulating region with the second conductive region A third conductive region;
Including
The first semiconductor light emitting element is:
A first lower electrode disposed on the first conductive region and in electrical communication with the first conductive region;
A first optical semiconductor stack disposed on the first lower electrode;
A first upper electrode selectively disposed on the first optical semiconductor stack;
Including
The second semiconductor light emitting element is:
A second lower electrode disposed on the second conductive region and in electrical communication with the second conductive region;
A second protrusion disposed on the second lower electrode and extending over the third conductive region of the support substrate; and a hole penetrating the extended portion and looking into the third conductive region. Two optical semiconductor stacks;
A second upper electrode that is selectively disposed on the second optical semiconductor stack and electrically connected to the third conductive region of the support substrate through the hole;
including,
Semiconductor light emitting element array. The second semiconductor light emitting element further includes an electrical insulating layer disposed between the projecting portion and the third conductive region,
2. The semiconductor light emitting element array according to claim 1, wherein the hole portion of the second optical semiconductor laminate is formed so as to penetrate the protruding portion and the electric insulating layer.   The semiconductor light-emitting element array according to claim 2, wherein the hole portion is formed so that an opening area is gradually reduced toward the support substrate. The second semiconductor light emitting element further includes an insulating protective film covering an inner surface of the hole,
The semiconductor light-emitting element array according to claim 3, wherein the second upper electrode is formed so as to cover a surface of the insulating protective film and is electrically connected to the third conductive region. A semiconductor light emitting device array according to any one of claims 1 to 4,
An optical system for irradiating an irradiation image of the semiconductor light emitting element array in a predetermined light distribution shape;
A vehicular lamp comprising:

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