JP2014096455A - Semiconductor light emitting element array and lighting fixture for vehicle - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting element array having higher reliability than the conventional ones.SOLUTION: A semiconductor light emitting element array having higher reliability than the conventional ones includes: a support substrate including a first conductive region, a second conductive region, and a third conductive region that is provided between the first and second conductive regions, has electrical continuity with the first conductive region, and has electrical insulation with the second conductive region; a first LED element including a first lower side electrode on the first conductive region, a first optical semiconductor laminate that is arranged on the first lower side electrode, and a first upper side electrode that is arranged on the first optical semiconductor laminate; and a second LED element including a second lower side electrode that is arranged on the second conductive region, a second optical semiconductor laminate that is arranged on the second lower side electrode and has an overhanging part overhanging above the third conductive region, and a second upper side electrode that is arranged on the second optical semiconductor laminate, and electrically connected to the third conductive region along a side face of the overhanging part.

Description

  The present invention relates to a semiconductor light emitting element array and a vehicular lamp using the same.

  A semiconductor light emitting device (LED) using a nitride semiconductor such as GaN (gallium / nitrogen) can emit ultraviolet light or blue light, and can also emit white light by using a phosphor. . Such a semiconductor light emitting element is used for illumination, for example. When a semiconductor light emitting device is used for lighting that requires high light output, such as a vehicular lamp, in general, a plurality of semiconductor light emitting devices are electrically connected in series from the viewpoint of suppressing heat generation or equalizing luminance unevenness. (Series connected semiconductor light emitting element array).

  The series connection type semiconductor light emitting element array has a configuration in which a plurality of semiconductor light emitting elements are arranged on a support substrate. The semiconductor light emitting element has a configuration in which at least a p-type semiconductor layer, an active layer (light emitting layer) for light emission, and an n-type semiconductor layer are stacked. Each of the plurality of semiconductor light emitting elements is formed such that, for example, the p-type semiconductor layer is on the support substrate side (lower surface) and the n-type semiconductor layer is on the opposite side (upper surface) of the support substrate. In the semiconductor light emitting devices adjacent to each other, a wiring layer that electrically connects the upper surface (n-type semiconductor layer) of one semiconductor light emitting device and the lower surface (p-type semiconductor layer) of the other semiconductor light emitting device. It is formed.

  The wiring layer that electrically connects the adjacent semiconductor light emitting elements is formed, for example, so as to look over the side of one of the semiconductor light emitting elements and above the support substrate viewed from between the adjacent semiconductor light emitting elements. . In general, a concavo-convex structure can exist in a region where a wiring layer is formed (for example, Patent Document 1). This concavo-convex structure induces disconnection of the wiring layer and reduces the reliability of the semiconductor light emitting element array.

US Pat. No. 7,985,970

  An object of the present invention is to provide a semiconductor light emitting element array having higher reliability than conventional ones.

  According to a main aspect of the present invention, there is provided a semiconductor light-emitting element array including a support substrate and first and second semiconductor light-emitting elements arranged on the support substrate and adjacent to each other, the support substrate Are provided between the first conductive region, the second conductive region spaced apart from the first conductive region, and the first conductive region and the second conductive region. A third conductive region electrically conducting with the first conductive region and electrically insulating with the second conductive region, wherein the first semiconductor light emitting element includes the first conductive light emitting element. A first lower electrode disposed on the first conductive region and electrically connected to the first conductive region, a first optical semiconductor stack disposed on the first lower electrode, and the first A first upper electrode selectively disposed on one optical semiconductor stack, and the second semiconductor light emitting element includes: A second lower electrode disposed on the second conductive region and electrically connected to the second conductive region; a second lower electrode disposed on the second lower electrode; A second optical semiconductor stack having a projecting portion extending above the conductive region, and a third conductive layer of the support substrate, which is selectively disposed on the second optical semiconductor stack and passes along a side surface of the projecting portion. There is provided a semiconductor light emitting element array including a second upper electrode electrically connected to the region.

  A semiconductor light emitting element array with higher reliability than the conventional one can be obtained.

1A to 1C are a plan view and a cross-sectional view showing a semiconductor light emitting element array according to a reference example. 2A and 2B are a plan view and a cross-sectional view showing a semiconductor light emitting element array according to an embodiment. , , and, 3A to 3N are cross-sectional views illustrating how the semiconductor light-emitting element array according to the embodiment is manufactured. and, 4A to 4E are a plan view and a cross-sectional view showing a modification of the semiconductor light emitting element array according to the embodiment. 5A and 5B are conceptual diagrams showing the configuration of a vehicular lamp (headlamp) incorporating a semiconductor light emitting element array according to an embodiment.

  FIG. 1A is a schematic plan view showing a semiconductor light emitting element array (LED array) 200 according to a reference example. Note that the relative sizes of the components shown in the figure are different from the actual ones.

  The LED array 200 according to the reference example includes a support substrate 210 and, for example, four semiconductor light emitting elements (LED elements) 201 arranged on the support substrate 210. The LED array 200 has, for example, a rectangular shape with a width of 6000 μm in the direction in which the LED elements are arranged and a width of 1000 μm in a direction perpendicular to the direction.

  Each LED element 201 includes an optical semiconductor stack 202 including n-type and p-type GaN-based semiconductors, and the n-type semiconductor of the optical semiconductor stack 202 is electrically connected to the first electrode 208. A p-type semiconductor is electrically connected to the second electrode 211. The first electrode 208 of the predetermined LED element 201 is electrically connected to the second electrode 211 of the adjacent LED element. Thereby, the some LED element 201 is electrically connected in series. Electric power is supplied to the plurality of LED elements 201 connected in series via power supply pads 215 and 216 arranged at both ends of the support substrate 210.

  1B and 1C are an enlarged plan view showing a part of the LED array 200 and a cross-sectional view showing an IC-IC cross section of the LED array 200 shown in FIG. 1B. Below, the structure of a predetermined | prescribed LED element (1st LED element 201a) and the LED element (2nd LED element 201b) adjacent to it among several LED elements arranged on the support substrate 210 is demonstrated. . However, it is assumed that the LED elements other than the first and second LED elements have the same configuration.

  As shown in FIG. 1B, the first and second LED elements 201a and 201b have, for example, a rectangular planar shape extending in a direction in which a plurality of LED elements are arranged. Regarding the dimensions of the LED elements, for example, the width in the direction in which the plurality of LED elements are arranged is 1400 μm, and the width in the direction orthogonal to the direction is 900 μm. For example, the first electrode 208 has a configuration in which a plurality of LED elements extend in a direction in which a plurality of LED elements are arranged, and a plurality of first electrodes 208 are arranged in a direction orthogonal to the direction.

  As shown in FIG. 1C, each of the first and second LED elements 201a and 201b includes a GaN-based optical semiconductor stack 202 including a p-type GaN layer 224, an active layer 223, and an n-type GaN layer 222, and an optical semiconductor stack 202. The p-side electrode 203 formed on the back surface (substrate side or the lower side of the drawing), the etch stop layer 204 formed side by side on the same plane as the p-side electrode 203, and the surface of the optical semiconductor stack 202 (substrate And an n-side electrode (first electrode) 208 selectively formed on the opposite side or the upper side of the drawing. In addition, in the figure, the code | symbol of each structure of the 2nd LED element 201b is abbreviate | omitted for convenience.

  The etch stop layer 204 is a layer that functions as an etch stopper in the manufacturing process of the LED element (or LED array). The etch stop layer 204 has electrical insulation.

  The first and second LED elements 201 a and 201 b (or the optical semiconductor stack 202) have a cross-sectional shape such that their side surfaces gradually approach the adjacent LED elements toward the support substrate 210. Such a shape is referred to as a forward tapered shape.

  Each of the first and second LED elements 201a and 201b is provided on a support substrate 210 having an insulating film 209 formed on the surface thereof, with a fusion layer 212 including a first adhesive layer 205 and a second adhesive layer 206 interposed therebetween. Supported. The fusion layer 212 has electrical conductivity and is electrically connected to the p-side electrode 203.

  Here, the region of the fusion layer 212 that fuses the first LED element 201a and the support substrate 210 and supports the first LED element 201a is referred to as a first conductive region 212a. In addition, a region of the fusion layer 212 that fuses the second LED element 201a and the support substrate 210 and supports the second LED element 201b is referred to as a second conductive region 212b. A groove region 213 is formed between the first conductive region 212a and the second conductive region 212b, and the first and second conductive regions 212a and 212b are electrically insulated. The first conductive region 212a has an exposed region (second electrode) 211 that protrudes from the first LED element 201a on the second LED element 201b side in a plan view.

  Side surfaces of the first and second LED elements 201a and 201b (or side surfaces of the optical semiconductor stack 202 and the etch stop layer 204), side surfaces of the first and second conductive regions 212a and 212b, and the groove region 213 On the bottom surface (or the surface of the support substrate 210 exposed between the first and second conductive regions 212a and 212b), a protective film 207 having electrical insulation is formed except for the exposed region 211. Furthermore, a wiring electrode 214 is formed on the surface of the protective film 207. The wiring electrode 214 straddles the groove region 213, and the n-side electrode 208 of the second LED element 201b and the exposed region 211 of the first conductive region 212a (that is, the p-side electrode 203 of the first LED element 201a). And are electrically connected. Accordingly, the first and second LED elements 201a and 201b are electrically connected in series.

  The first and second LED elements 201a and 201b (the optical semiconductor stack 202 and the etch stop layer 204) and the side surface of the fusion layer 12 (the side surfaces of the first and second conductive regions 212a and 212b or the groove portion 213) On the side surface), a step may be formed at the boundary between the layers constituting them. The wiring electrode 214 that travels along the side surfaces of the first and second LED elements 201a, 201b and the fusion layer 212 via the protective film 207 causes breakage or disconnection due to stress generated at a step that can be formed at the boundary between the layers. there is a possibility. For this reason, it is desirable that the region where the wiring electrode 214 is formed is designed to have as few steps as possible. More specifically, the wiring electrode 214 electrically connects the n-side electrode 208 of the second LED element 201b and the p-side electrode of the first LED element 201a without straddling the groove region 213. It is preferable. Further, when the wiring distance of the wiring electrode 214 is long, the resistance component of the wiring electrode 214 becomes large, and a problem that the voltage drop due to the wiring electrode 214 becomes large may occur. For this reason, it is desirable to design the wiring distance of the wiring electrode 214 to be as short as possible.

  2A and 2B are a schematic plan view showing a part of the LED array 100 according to an embodiment of the present invention, and a cross-sectional view showing a IIB-IIB cross section of the LED array 100 shown in FIG. 2A. Hereinafter, with reference to FIG. 2A and FIG. 2B, the difference of the LED array according to the embodiment of the present invention from the LED array according to the reference example will be mainly described.

  The LED array 100 according to the embodiment is similar to the LED array according to the reference example, in that the plurality of LED elements including the first and second LED elements 101a and 101b adjacent to each other are supported by the insulating film 9 formed on the surface. The structure is arranged on the substrate 10. Each of the first and second LED elements 101a and 101b is supported on a support substrate 10 via a fusion layer 12 including first and second adhesive layers 5 and 6. Further, each of the first and second LED elements 101a and 101b is similar to the LED element according to the reference example, and the optical semiconductor stack 2 including the p-type GaN layer 24, the active layer 23, and the n-type GaN layer 22, and p The side electrode 3, the etch stop layer 4, and the n-side electrode 8 are included.

  Here, the region of the fusion layer 12 that supports the first LED element 101a and is electrically connected to the p-side electrode 3 is defined as a first conductive region 12a, and the second LED element 101b. And a region of the fusion layer 12 that is electrically connected to the p-side electrode 3 is defined as a second conductive region 12b. Furthermore, a region located between the first and second conductive regions 12a and 12b in the fusion layer 12 is defined as a third conductive region 12c. The first conductive region 12a and the third conductive region 12c are formed continuously, and the first and third conductive regions 12a and 12c are electrically connected. Further, between the second conductive region 12b and the third conductive region 12c, the groove region 13 is arranged so as to completely divide the two regions and have no direct connection portion. Therefore, the groove region 13 functions as an insulating region, and the second and third conductive regions 12b and 12c are directly electrically insulated. The first and second conductive regions 12a and 12b have portions that overlap the first and second LED elements 101a and 101b, respectively, in plan view. The third conductive region 12c has a portion exposed from the first and second LED elements 101a and 101b in plan view.

  The p-side electrode 3 of the first LED element 101a is disposed on the first conductive region 12a and is electrically connected to the first conductive region 12a and the third conductive region 12c.

  The p-side electrode 3 of the second LED element 101b is disposed on the second conductive region 12b and is electrically connected to the second conductive region 12b. However, the third conductive region 12c (or the first conductive region 12a) is directly electrically insulated by the groove region 13 and the etch stop layer 4 having electrical insulation.

  In the second LED element 101b, the optical semiconductor laminate 2 is disposed on the p-side electrode 3. In addition, the optical semiconductor laminate 2 has a protruding portion 2c that protrudes above the groove region 13 and the third conductive region 12c. The projecting portion 2 c of the optical semiconductor stack 2 is supported by the third conductive region 12 c of the fusion layer 12 through the etch stop layer 4 having electrical insulation. The optical semiconductor stack 2, particularly the p-type GaN layer 24, is not directly connected to the third conductive region 12 c.

  The side surface of the protruding portion 2c of the second LED element 101b is formed to be inclined so as to gradually approach the first LED element 101a toward the support substrate 10. The wiring electrode 14 is in contact with the third conductive region 12c through the surface of the insulating protective film 7 formed on the side surface of the protruding portion 2c, and the n-side electrode 8 and the third conductive region of the second LED element 101b. 12c is electrically connected. That is, the second conductive region 12b, and the p-side electrode 3 and the optical semiconductor stack 2 of the second LED element 101b are indirectly electrically connected to the third conductive region 12c through the wiring electrode 14. Will do. Thereby, the 1st and 2nd LED element 101a, 101b is electrically connected in series.

  In the LED array 100 according to the embodiment, the groove region 13 is disposed below the projecting portion 2c of the optical semiconductor stack 2 in the second LED element 101b. The wiring electrode 14 is electrically connected to the third conductive region 12c continuous with the first conductive region 12a without straddling the groove region 13. That is, the step that can be formed in the region where the wiring electrode is formed can be reduced as compared with the LED array according to the reference example. Thereby, reliability improves compared with the LED array by a reference example. In addition, compared with the LED array according to the reference example, the wiring distance of the wiring electrode 14 can be shortened by about the wiring distance necessary for straddling the groove region 13.

  Hereinafter, a method of manufacturing the LED array 100 according to the embodiment will be described with reference to FIGS. 3A to 3N.

  First, as shown in FIG. 3A, a growth substrate 1 made of sapphire is prepared, and an optical semiconductor stack 2 made of a nitride-based semiconductor is formed using a metal organic chemical vapor deposition (MOCVD) method. Specifically, for example, after putting the sapphire substrate 1 into the MOCVD apparatus, thermal cleaning is performed, and after growing the GaN buffer layer 20 and the undoped GaN layer 21, n-type GaN having a thickness of about 5 μm doped with Si or the like. A layer 22, a multiple quantum well light emitting layer (active layer) 23 including an InGaN quantum well layer, and a p-type GaN layer 24 having a thickness of about 0.5 μm doped with Mg or the like are sequentially grown. The growth substrate 1 is a single crystal substrate having a lattice constant capable of epitaxial growth of GaN, and is transparent to light having a wavelength of 362 nm which is an absorption edge wavelength of GaN so that the substrate can be peeled off by laser lift-off in a later process. Selected from ones. In addition to sapphire, spinel, SiC, ZnO, or the like may be used.

  Thereafter, as shown in FIG. 3B, an Ag layer having a thickness of 200 nm is formed on the surface of the optical semiconductor stack 2 (the surface of the p-type GaN layer 24) by an electron beam evaporation method, and patterned by a lift-off method or the like. The p-side electrode 3 is formed. In order for the p-side electrode 3 to function as a reflective electrode, it is preferable to use Ag, Pt, Ni, Al, Pd, and alloys thereof as the p-side electrode 3. Further, an ohmic junction layer such as ITO (indium tin oxide) may be sandwiched between the p-side electrode 3 and the surface of the optical semiconductor laminate 2. When sandwiching the ohmic junction layer, the side surface of the ohmic junction layer may be covered with a p-side electrode 3 as a reflective electrode.

Next, as shown in FIG. 3C, SiO ₂ having the same thickness as that of the p-side electrode 3 is formed on the optical semiconductor stack 2 (on the p-type GaN layer 24) around the p-side electrode 3 by using a sputtering method. An etch stop layer 4 is formed. The etch stop layer 4 functions as an etch stopper in an etching process described later with reference to FIG. 3K. Further, as described above, the etch stop layer 4 includes the p-side electrode 3 or the optical semiconductor stack 2 (particularly, the overhang portion 2C, see FIG. 2B) and the third conductive region 12c in the LED array finally manufactured. And directly supporting the optical semiconductor stack 2 (particularly, the protruding portion).

  Next, as shown in FIG. 3D, 200 nm-thickness Au is formed by sputtering in a region including the p-side electrode 3 and the etch stop layer 4, and patterned by a lift-off method or the like. 1 adhesive layer 5 is formed. Here, the first adhesive layer 5 is patterned so that a gap 5z is provided in a part of the etch stop layer 4.

  The first adhesive layer 5 may be formed after forming a diffusion prevention layer or the like in a region including the p-side electrode 3 and the etch stop layer 4. The diffusion prevention layer is for preventing the diffusion of the material used for the p-side electrode 3, and when the p-side electrode 3 contains Ag, Ti, W, Pt, Pd, Mo, Ru, Ir, Au, and These alloys can be used.

  Next, as shown in FIG. 3E, a support substrate 10 made of Si is prepared, and a thermal oxidation process is performed to form an insulating film (thermally oxidized SiO 2 film) 9 on the surface. The support substrate 10 is preferably made of a material having a thermal expansion coefficient close to that of sapphire (7.5 × 10 −6 / K) or GaN (5.6 × 10 −6 / K) and having high thermal conductivity. For example, Si, AlN, Mo, W, CuW, or the like can be used. The film thickness of the insulating film 9 should just be the thickness which can achieve the objective of ensuring insulation.

  Next, a second adhesive layer 6 made of AuSn (Sn: 20 wt%) having a thickness of 1 μm is formed on the insulating film 9 by resistance heating vapor deposition. The material of the first adhesive layer 5 and the material of the second adhesive layer 6 are Au-Sn, Au-In, Pd-In, Cu-In, Cu-Sn, Ag-Sn, which can be fusion bonded. A metal containing Ag—In, Ni—Sn, or the like, or a metal containing Au capable of diffusion bonding can be used.

  As shown in FIGS. 3F and 3G, the second adhesive layer 6 can be formed by using, for example, a lift-off method. First, a photoresist (for example, Clariant Co. photoresist AZ5200) is applied to the entire surface of a support substrate 10 (support substrate 10 having an insulating film 9 formed on the surface) that has been subjected to thermal oxidation, and a hot plate set at 90 ° C. or lower. And pre-bake for about 90 seconds in the atmosphere. Next, a pattern is exposed on the photoresist using ultraviolet light (UV light) with a first exposure amount of 17 mJ. The exposed photoresist is subjected to reversal baking for about 90 seconds in an atmosphere at 120 ° C. to thermally crosslink the exposed portion. Next, the entire surface of the support substrate 10 is irradiated with UV light at a reversal exposure amount of 600 mJ. Further, the photoresist pattern PR1 is formed (in addition to the portion to be the second adhesive layer 6) by dipping in a developing solution for 130 seconds and performing development processing. The photoresist pattern PR <b> 1 formed in this way has a reverse tapered shape with respect to the support substrate 10 at the periphery. Note that the resist and photolithography conditions to be used can be changed as appropriate.

  Next, a metal laminate 6 made of Ti (150 nm) / Ni (50 nm) / Au (100 nm) / Pt (200 nm) / AuSn (1000 nm, Sn: 20 wt%) is formed using a resistance heating vapor deposition method, Thereafter, by lift-off, the second adhesive layer 6 having an end tapered toward the support substrate 10 as shown in FIG. 3G is formed. The region where the photoresist pattern PR1 has been formed becomes a gap 6z. Note that the second adhesive layer 6 can be formed by using a dry etching method or a wet etching method in addition to the lift-off method.

  Next, as shown in FIG. 3H, the first adhesive layer 5 and the second adhesive layer 6 are contacted so that the gap 5z of the first adhesive layer 5 and the gap 6z of the second adhesive layer 6 overlap each other. And heated to 300 ° C. under a pressure of 3 MPa and held for 10 minutes. Then, fusion bonding is performed by cooling to room temperature. The fusion layer 12 is formed by this fusion bonding. Further, the gap 5z of the first customer service layer 5 and the gap 6z of the second adhesive layer 6 are integrated to form the groove region 13.

  Thereafter, as shown in FIG. 3I, the sapphire substrate 1 is peeled off by laser lift-off by irradiating UV excimer laser light from the back side of the sapphire substrate 1 and thermally decomposing the buffer layer 20. Note that another method such as etching may be used for peeling or removing the substrate 1.

  Next, as shown in FIG. 3J, Ga generated by laser lift-off is removed with hot water or the like, and then surface-treated with hydrochloric acid. As a result, the n-type Gan layer 22 is exposed. Any surface treatment can be used as long as it can etch a nitride semiconductor, and acids such as phosphoric acid, sulfuric acid, KOH, and NaOH, and chemicals such as alkali can also be used. The surface treatment may be performed by dry etching using Ar plasma or chlorine plasma, polishing, or the like. Further, the surface of the n-type GaN layer 22 is smoothed using a Cl or Ar treatment using a dry etching apparatus such as RIE or a CMP polishing apparatus to remove a laser mark or a laser damage layer. In order to improve the light extraction efficiency, the surface of the n-type GaN layer 22 exposed may be subjected to uneven processing (light extraction structure or microcone structure is formed).

  Next, as shown in FIG. 3K, a photoresist PR2 having a predetermined pattern is formed on the optical semiconductor laminate 2. Thereafter, the end portion of the optical semiconductor laminate 2 exposed from the photoresist PR2 is etched by dry etching using chlorine gas until the etch stop layer 4 is exposed. Thereby, the optical semiconductor stack 2 is divided into a plurality. The side surface of the divided optical semiconductor stack 2 has a forward tapered shape with respect to the support substrate 10.

Next, as shown in FIG. 3L, a mask pattern PR3 is formed from a photoresist, and the etch stop layer 4 is etched. The mask pattern PR3 is formed so as to cover the upper surface and side surfaces of the optical semiconductor stack 2 and to slightly cover the upper surface of the etch stop layer 4. The etching process can be performed by, for example, dry etching using CF ₄ gas. With this process, the uppermost surface of the optical semiconductor stack 2 to the third conductive region 12c of the fusion layer 12 is processed into a series of forward tapered shapes.

Next, as shown in FIG. 3M, a protective film 7 made of SiO ₂ is formed on the entire upper surface of the element formed in the above-described process by chemical vapor deposition (CVD) or the like, and then on the optical semiconductor stack 2. A part of the formed protective film 7 and a part of the protective film 7 formed on the third conductive region 12c are etched using buffered hydrofluoric acid to obtain a surface (n-type GaN layer) of the optical semiconductor stack 2. 22 surface) and the third conductive region 12c are exposed.

  Next, as shown in FIG. 3N, a 1 nm thick Ti layer, a 200 nm thick Al layer, a 100 nm thick Ti layer, and a 2 μm thick Au layer are stacked in this order by electron beam evaporation. By patterning by lift-off, the n-side electrode 8 that is in ohmic contact with the n-type GaN layer 22 and the wiring electrode 14 that connects the n-side electrode 8 and the third conductive region 12c are formed. The n-side electrode 8 and the wiring electrode 14 are continuously formed from the upper surface of the n-type GaN layer 22 on the forward tapered side surfaces of the optical semiconductor stack 2 and the etch stop layer 4 via the protective film 7. .

  Thereafter, the support substrate 10 is divided by laser scribing or dicing. As a result, an LED array including a plurality of LED elements including the first and second LED elements 101a and 101b is completed. When the blue GaN light emitting element is whitened, a phosphor (for example, yellow light emission) is put in a resin for sealing and filling the light emitting element.

  The LED array 100 according to the embodiment has a configuration in which the plurality of n-side electrodes 8 arranged orthogonal to the direction in which the plurality of LED elements are arranged are electrically connected to the third conductive region 12c. However, the present invention is not limited to this configuration. Hereinafter, a modification of the LED array according to the embodiment will be described with reference to FIGS. 4A to 4E.

  FIG. 4A shows a schematic plan view of an LED array 150 according to a modification. FIG. 4B shows a planar shape of the fusion layer 12 of the LED array 150. In FIG. 4B, the optical semiconductor stack 2 disposed above the fusion layer 12 is indicated by a dotted line. Further, FIGS. 4C and 4D show an IVC-IVC cross section and an IVD-IVD cross section of the LED array 150 shown in FIG. 4A, respectively.

  As shown in FIG. 4A, the n-side electrode 8 of the LED elements 101a and 101b according to the modification extends in the direction in which the plurality of LED elements are arranged, and is one end side of the surface of the optical semiconductor stack 2 (n-type GaN layer 22). A comb-shaped portion including a common portion 8a disposed on the first portion and a comb-tooth portion 8b extending in a direction orthogonal to a direction in which the common portion 8a extends and electrically connected to the common portion 8a on one end side. It has a planar shape.

  The third conductive region 12c is formed only on the extension line of the common portion 8a in plan view, and is exposed from between the first and second LED elements 101a and 101b. The wiring electrode 14 electrically connects the common part 8a of the n-side electrode 8 and the third conductive region 12c. Thereby, the first and second LED elements 101a and 101b are electrically connected in series.

  As shown in FIG. 4B, the overall planar shape of the fusion layer 12 in the LED array 150 is a fusion in which one corner of the rectangular shape projects directly below the projecting portion 2c of the adjacent LED element, and the other corner is adjacent. It becomes a shape which is dented so that it may escape from the protruding part of the layer 12. Further, as shown in FIGS. 4B to 4D, the groove region 13 is formed in the second conductive region 12b and the third conductive region in the region where the wiring electrode 14 and the third conductive region 12c are connected (FIG. 4C). The first conductive region 12a and the second conductive region 12b are separated in a region other than the region where the wiring electrode 14 and the third conductive region 12c are connected (FIG. 4D). Are arranged as follows. Thereby, similarly to the LED array according to the embodiment, the second conductive region 12c, and the p-side electrode 3 and the optical semiconductor stack 2 of the second LED element 101b are indirectly connected to the first via the wiring electrode 14. 3 conductive regions 12c (or first conductive regions 12a).

  Further, the optical semiconductor laminate 2 of the LED elements 101a and 101b according to the modification has a shape in which the overall planar shape is a rectangular corner cut out (notched portion 2e) as shown in FIG. 4A. Become. This is to secure a region for the wiring electrode 14 to connect to the third conductive region 12c. The interval between the first LED element 101a and the second LED element 101b is set so that the cutout portion 2e of the optical semiconductor stack 2 is not formed (so that the overall planar shape of the optical semiconductor stack 2 is rectangular). A region for connecting the wiring electrode 14 to the third conductive region 12c may be secured. However, in that case, the non-light emitting area between the first and second LED elements 101a and 101b becomes large, and there is a possibility that the light emission unevenness becomes remarkable as the LED array. Therefore, it is preferable that the overall planar shape of the optical semiconductor stack 2 is a shape in which only the region where the wiring electrode 14 is connected to the third conductive region 12c is cut out.

  As shown in FIG. 4A, the LED array 150 according to the modification has the third conductive region 12c exposed only at one end side where the common portion 8a of the n-side electrode 8 is formed, and the common portion 8a of the n-side electrode 8 and The continuous wiring electrode 14 is electrically connected to the third conductive region 12c. In a region other than the region where the wiring electrode 14 and the third conductive region 12c are connected, the third conductive region 12c is exposed from between the first and second LED elements 101a and 101b, and the second LED It is not necessary to form the wiring electrode 14 on the side surface of the element 101b and the upper surface of the third conductive region 12c. That is, the overhanging portion 2c disposed immediately above the third conductive region 12c can be only near the corner where the wiring electrode 14 is formed. Although the p-side electrode 3 cannot be disposed immediately below the overhanging portion 2c (FIG. 4C), the LED array 150 according to the modification can make the overhanging portion 2c smaller than the LED array according to the embodiment. 3 can be formed widely.

  The region contributing to light emission in the optical semiconductor stack 2 is a portion immediately above the region where the p-side electrode 3 is formed. Therefore, the light emitting area of the LED element (stacked optical semiconductor) can be formed larger than the LED element according to the embodiment. Thereby, the emitted light quantity improves rather than the LED array by an Example.

  The planar shapes of the third conductive region 12c (fusion layer 12), the optical semiconductor stack 2, the n-side electrode 8, and the like are used in the lift-off method or the etching method shown in FIGS. 3D, 3F, 3K, and 3N. It can be easily adjusted by changing the photoresist pattern.

  FIG. 4E is a cross-sectional view showing another modification of the LED array according to the embodiment. The groove region 13 may be filled with an insulating member 13a, and the second conductive region 12b and the third conductive region 12c may not be electrically connected. Further, the p-side electrode 3 may be formed in contact with the etch stop layer 4.

  5A and 5B are conceptual diagrams showing the configuration of a vehicular lamp (headlamp) 50 incorporating the LED array 100 according to an embodiment of the present invention.

  FIG. 5A shows an example in which an irradiation lens 105 is used as the irradiation optical system 51. The irradiation lens 105 is set so that the light source image 106 of the LED array 100 is projected onto a virtual vertical screen (irradiation surface) 107 facing the front end of the vehicle.

  The irradiation optical system 51 may use a multi-reflector (reflection surface) 103 and an irradiation lens 105 as shown in FIG. 5B. The headlamp 50 shown in FIG. 5B is a multi-reflector divided into a plurality of small reflection regions, and a light source 102 composed of a phosphor layer (wavelength conversion layer) 108 disposed so as to cover the light emitting surface of the LED array 100. An illumination optical system 51 including a reflective surface 103, a shade 104, and an illumination lens 105 is configured.

  As shown in FIG. 5B, the light source 102 is arranged so that the irradiation direction (light emitting surface) faces upward, and the reflecting surface 103 has the first focal point set near the light source 102 and the second focal point is the upper end of the shade 104. It is a spheroid reflecting surface set in the vicinity of the edge, and is arranged so as to cover a range from the side of the light source 102 to the front so that the light from the light source 102 enters.

  As shown in FIG. 5B, the reflecting surface 103 irradiates the light source image 106 of the LED array 100 of the light source 102 in the predetermined light distribution shape to the front of the vehicle, and faces a virtual vertical screen (irradiation surface) 107 facing the front end of the vehicle. A light source image 106 of the LED array 100 is projected on the top.

  The shade 104 is a light-shielding member for shielding a part of the reflected light from the reflective surface 103 to form a cut-off line suitable for a headlamp, with the upper edge positioned in the vicinity of the focal point of the irradiation lens 105. It is disposed between the irradiation lens 105 and the light source 102.

  The irradiation lens 105 is disposed on the front side of the vehicle and irradiates the irradiation surface 107 with the reflected light from the reflection surface 103.

  Instead of the LED array 100 according to the embodiment, an LED array 150 (see FIG. 4) according to a modification may be used.

  As mentioned above, although this invention was demonstrated along the Example and the modification, this invention is not limited to these. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

DESCRIPTION OF SYMBOLS 1 ... Growth substrate, 2 ... Optical semiconductor lamination | stacking (GaN-type light emission part), 3 ... P side electrode (reflection electrode), 4 ... Etch stop layer, 5 ... 1st adhesion layer, 6 ... 2nd adhesion layer, 7 ... Protective film, 8 ... n-side electrode, 9 ... insulating layer, 10 ... support substrate, 11 ... n-side electrode, 12 ... fused layer, 12a-12c ... first to third conductive regions, 13 ... groove region, DESCRIPTION OF SYMBOLS 14 ... Wiring electrode, 20 ... Buffer layer, 21 ... Undoped GaN layer, 22 ... N-type GaN layer, 23 ... Active layer (light emitting layer), 24 ... P-type GaN layer, 50 ... Vehicle lamp (headlamp), 51 DESCRIPTION OF SYMBOLS ... Projection optical system, 100 ... LED array (Example), 101 ... LED element, 108 ... Phosphor layer (wavelength conversion layer), 102 ... Light source, 103 ... Reflecting surface, 104 ... Shade, 105 ... Irradiation lens, 106 ... Light source image, 107... Irradiation surface, 150... LED array (modified example).

Claims (5)

A semiconductor light emitting element array including a support substrate and first and second semiconductor light emitting elements arranged on the support substrate and adjacent to each other,
The surface of the support substrate is
A first conductive region;
A second conductive region provided spaced apart from the first conductive region;
A third conductive region provided between the first conductive region and the second conductive region, electrically connected to the first conductive region, and electrically isolated from the second conductive region; A conductive region;
Including
The first semiconductor light emitting element is:
A first lower electrode disposed on the first conductive region and in electrical communication with the first conductive region;
A first optical semiconductor stack disposed on the first lower electrode;
A first upper electrode selectively disposed on the first optical semiconductor stack;
Including
The second semiconductor light emitting element is:
A second lower electrode disposed on the second conductive region and in electrical communication with the second conductive region;
A second optical semiconductor laminate having an overhanging portion disposed on the second lower electrode and extending above the third conductive region of the support substrate;
A second upper electrode that is selectively disposed on the second optical semiconductor stack and is electrically connected to a third conductive region of the support substrate through a side surface of the projecting portion;
including,
Semiconductor light emitting element array.   2. The semiconductor light emitting element array according to claim 1, wherein the second semiconductor light emitting element further includes an electrical insulating layer disposed between the projecting portion and the third conductive region.   3. The semiconductor light emitting device according to claim 2, wherein side surfaces of the projecting portion and the electrical insulating layer in the second semiconductor light emitting element are gradually inclined toward the support substrate so as to approach the first semiconductor light emitting element. Element array. The second semiconductor light emitting element further includes an insulating protective film formed on a side surface of the protruding portion and the electric insulating film,
The semiconductor light-emitting element array according to claim 3, wherein the second upper electrode is electrically connected to the third conductive region through the surface of the insulating protective film. A semiconductor light emitting device array according to any one of claims 1 to 4,
An optical system for irradiating an irradiation image of the semiconductor light emitting element array in a predetermined light distribution shape;
A vehicular lamp comprising:

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