JP2014116392A - Semiconductor light-emitting element array and lighting fixture for vehicle - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element array excellent in light-emitting quality and the amount of light emission.SOLUTION: A semiconductor light-emitting element array 100 excellent in light-emitting quality and the amount of light emission includes a plurality of semiconductor light-emitting elements arranged along a first direction on a supporting substrate 10. Each of the plurality of semiconductor light-emitting elements includes: a conductive layer including a first conductive region 12a and a second conductive region 12b electrically insulated with the first conductive region; a lower electrode disposed on the first conductive region; an optical semiconductor stacked layer 2 including a body portion 2a disposed on the lower electrode, a protruding portion 2b continuously formed with the body portion and protruding above the second conductive region, and a plurality of penetrating portions penetrating through the protruding portion and looking at the second conductive region; and a plurality of upper electrodes disposed on the optical semiconductor stacked layer and electrically connected to the second conductive region through each of the plurality of penetrating portions.

Description

  The present invention relates to a semiconductor light emitting element array and a vehicular lamp using the same.

  A semiconductor light emitting element using a nitride semiconductor such as GaN (gallium / nitrogen) can emit ultraviolet light or blue light, and can emit white light by using a phosphor. Such a semiconductor light-emitting element includes, for example, an optical semiconductor stack having a p-type GaN layer, a GaN-based active layer, and an n-type GaN layer, and an electrode for passing a current through the optical semiconductor stack. Used for.

  When a semiconductor light emitting device is used for lighting that requires high light output, such as a vehicular lamp, in general, a plurality of semiconductor light emitting devices are electrically connected in series from the viewpoint of suppressing heat generation or equalizing luminance unevenness. (Series connected semiconductor light emitting element array).

  A sapphire substrate is generally used as a substrate for growing a GaN-based optical semiconductor stack. However, since the sapphire substrate has a relatively low thermal conductivity and poor heat dissipation, it is not suitable as a support substrate for a device to which a large current is input. Therefore, in recent years, after growing a GaN-based optical semiconductor stack on a sapphire substrate, the optical semiconductor stack is bonded to a silicon substrate that is advantageous for heat dissipation, and the sapphire substrate is removed by laser lift-off or polishing. It has been developed (for example, Patent Document 1).

JP 2010-056458 A

  On the surface of the optical semiconductor stack from which the growth substrate has been removed, an electrode is formed for flowing current through the optical semiconductor stack. In order to make an electric current flow uniformly through the optical semiconductor stack and make the light emission distribution uniform, it is preferable to increase the electrode area per unit area on the surface of the optical semiconductor stack. However, when the electrode area per unit area is large, the ratio of the light that is blocked by the electrode out of the light emitted from the surface of the optical semiconductor stack increases, and the effective light emission amount decreases.

  An object of the present invention is to provide a semiconductor light emitting element array having better light emission quality and light emission amount than conventional ones.

  According to a main aspect of the present invention, there is provided a semiconductor light-emitting element array comprising a support substrate and a plurality of semiconductor light-emitting elements arranged along a first direction on the support substrate, the plurality of semiconductors Each of the light emitting elements is disposed on the support substrate, and is disposed at a distance from the first conductive region and the first conductive region in a direction orthogonal to the first direction. A conductive layer including a second conductive region electrically insulated from the conductive region, a lower electrode disposed on the first conductive region and electrically connected to the first conductive region, and the lower layer A main body portion disposed on the side electrode; a projecting portion formed continuously with the main body portion and projecting above the second conductive region; and looking through the projecting portion into the second conductive region A first having a plurality of through portions and having a first conductivity type in order from the conductive layer side An optical semiconductor stack in which a conductor layer, an active layer, and a second semiconductor layer having a second conductivity type different from the first conductivity type are stacked, and disposed on the optical semiconductor stack, and each of the plurality of through portions is disposed There is provided a semiconductor light emitting element array including a plurality of upper electrodes electrically connected to the second conductive region.

  A semiconductor light emitting element array with better light emission quality and light emission than conventional ones can be obtained.

1A to 1C are a plan view and a cross-sectional view showing a semiconductor light emitting element array according to a reference example. 2A to 2C are a plan view, a cross-sectional view, and a perspective plan view showing a semiconductor light emitting element array according to an embodiment. , , and, 3A to 3N are cross-sectional views illustrating how the semiconductor light-emitting element array according to the embodiment is manufactured. 4A to 4C are a perspective plan view and a cross-sectional view showing a modification of the semiconductor light emitting element array according to the embodiment. 5A and 5B are conceptual diagrams showing the configuration of a vehicular lamp (headlamp) incorporating a semiconductor light emitting element array according to an embodiment.

  FIG. 1A is a schematic plan view showing a semiconductor light emitting element array (LED array) 200 according to a reference example. Note that the relative sizes of the components shown in the figure are different from the actual ones.

  The LED array 200 according to the reference example includes a support substrate 210 and, for example, four semiconductor light emitting elements (LED elements) 201 arranged on the support substrate 210. The LED array 200 has, for example, a rectangular shape having a width of 6000 μm along the direction in which the LED elements are arranged and a width of 1000 μm along the direction orthogonal to the direction.

  Each LED element 201 has an optical semiconductor stack 202 including n-type and p-type GaN-based semiconductors. The n-type semiconductor of the optical semiconductor stack 202 is electrically connected to the first electrode 208, and the optical semiconductor stack 202 The p-type semiconductor is electrically connected to the second electrode 211. The first electrode 208 of the predetermined LED element 201 is electrically connected to the second electrode 211 of the adjacent LED element. Thereby, the some LED element 201 is electrically connected in series. The plurality of LED elements 201 connected in series are supplied with power from power supply pads 215 and 216 provided at both ends of the support substrate 210.

  1B and 1C are an enlarged plan view showing a part of the LED array 200 and a cross-sectional view showing an IC-IC cross section of the LED array 200 shown in FIG. 1B. Below, the structure of a predetermined | prescribed LED element (1st LED element 201a) and the LED element (2nd LED element 201b) adjacent to it among several LED elements arranged on the support substrate 210 is demonstrated. . However, it is assumed that the LED elements other than the first and second LED elements have the same configuration.

  As shown in FIG. 1B, the first and second LED elements 201a and 201b have, for example, a rectangular planar shape extending in a direction in which a plurality of LED elements are arranged (x-axis direction). Regarding the dimensions of the LED elements, for example, the width along the direction in which the plurality of LED elements are arranged is 1400 μm, and the width along the direction orthogonal to the direction is 900 μm.

  As shown in FIG. 1C, each of the first and second LED elements 201a and 201b includes a GaN-based optical semiconductor stack 202 including a p-type GaN layer 224, an active layer 223, and an n-type GaN layer 222, and an optical semiconductor stack 202. The p-side electrode 203 formed on the back surface (substrate side or the lower side of the drawing), the etch stop layer 204 formed side by side on the same plane as the p-side electrode 203, and the surface of the optical semiconductor stack 202 (substrate And an n-side electrode (first electrode) 208 selectively formed on the opposite side or the upper side of the drawing. In addition, in the drawing, a part of each configuration of the second LED element 201b is omitted for convenience.

  The etch stop layer 204 is a layer that functions as an etch stopper in the manufacturing process of the LED element (or LED array). The etch stop layer 204 has electrical insulation.

  The first and second LED elements 201 a and 201 b (or the optical semiconductor stack 202) have a cross-sectional shape such that their side surfaces gradually approach the adjacent LED elements toward the support substrate 210. Such a shape is referred to as a forward tapered shape.

  Each of the first and second LED elements 201a and 201b is provided on a support substrate 210 having an insulating film 209 formed on the surface thereof, with a fusion layer 212 including a first adhesive layer 205 and a second adhesive layer 206 interposed therebetween. Arranged. The fusion layer 212 has electrical conductivity and is electrically connected to the p-side electrode 203.

  Here, the first LED element 201a and the support substrate 210 are fused, and the fusion layer 212 that supports the first LED element 201a is referred to as a first fusion layer 212a. In addition, the fusion layer 212 that fuses the second LED element 201a and the support substrate 210 and supports the second LED element 201b is referred to as a second fusion layer 212b. A groove region 213 is formed between the first fusion layer 212a and the second fusion layer 212b, and the first and second fusion layers 212a and 212b are electrically insulated. Yes. The first fusion layer 212a has an exposed region (second electrode) 211 that protrudes from the first LED element 201a on the second LED element 201b side in a plan view.

  Side surfaces of the first and second LED elements 201a and 201b (or side surfaces of the optical semiconductor stack 202 and the etch stop layer 204), side surfaces of the first and second fusion layers 212a and 212b, and a groove region 213 On the bottom surface (or the surface of the support substrate 210 exposed between the first and second fusion layers 212a and 212b), a protective film 207 having electrical insulation is formed except for the exposed region 211. . Further, a wiring electrode 214 continuous with the n-side electrode 208 is formed on the surface of the protective film 207. The wiring electrode 214 electrically connects the n-side electrode 208 of the second LED element 201b and the exposed region 211 of the first conductive region 212a (that is, the p-side electrode 203 of the first LED element 201a). To do. Accordingly, the first and second LED elements 201a and 201b are electrically connected in series.

  As shown in FIG. 1B, the n-side electrode 208 extends in the direction in which the plurality of LED elements are arranged (x-axis direction), and is disposed on one end side of the surface of the optical semiconductor stack 202. Comb-shaped planar shape including a comb-tooth portion 208b that extends in a direction (y-axis direction) orthogonal to the direction in which 208a extends and is electrically connected to the common portion 208a on one end side. Yes. In the first LED element 201a, the common portion 208a is arranged at the end on the y-axis negative direction side of the surface of the optical semiconductor stack 202, and the comb-tooth portion 208b extends from the common portion 208a in the y-axis positive direction. doing. In the second LED element 201b, the common portion 208a is disposed at the end on the y-axis positive direction side of the surface of the optical semiconductor laminate 202, and the comb-tooth portion 208b extends from the common portion 208a in the y-axis negative direction. ing. The wiring electrode 214 electrically connects the exposed region 211 of the first LED element 201a and the common portion 208a of the second LED element 201b.

  In each of the first and second LED elements 201a and 201b, electrons injected from the n-side electrode 208 into the optical semiconductor stack 202 recombine with holes injected from the p-side electrode 203 in the active layer 223 (that is, The current in the optical semiconductor stack 202 flows from the p-side electrode to the n-side electrode). The energy for this recombination is emitted as light from the surface of the optical semiconductor stack 202 (n-type GaN layer 222).

  The current distribution in the optical semiconductor laminate 202 is relatively large in the region near the root of the comb tooth portion 208b (near the common portion 208a) due to the influence of the wiring resistance of the comb tooth portion 208b, and near the tip of the comb tooth portion 208b. Relatively small in area. For this reason, the amount of light emitted from the surface of the optical semiconductor stack 202 is relatively large in the region near the root of the comb tooth portion 208b and relatively small in the region near the tip of the comb tooth portion 208b. In an adjacent LED element, the position where the common portion 208a is arranged is reversed between the end on the positive side of the y-axis and the end on the negative side of the y-axis on the surface of the optical semiconductor stack 202, thereby macroscopically viewing the LED array. Thus, the difference in the amount of light emission (light emission distribution) between the y-axis positive direction side end and the y-axis negative direction side end can be reduced.

  Currents flowing from the optical semiconductor stack 202 to the comb-tooth portion 208 b merge at the common portion 208 a and flow to the exposed region 211 of the adjacent LED element via the wiring electrode 214. In order to suppress a voltage drop due to wiring resistance, at least the width Ws along the y-axis direction of the common portion 208a is preferably larger than the width Wc along the x-axis direction of the comb tooth portion 208b. However, when the width Ws of the common portion 208a is increased, the proportion of light that is blocked by the common portion 208a in the light emitted from the surface of the optical semiconductor stack 202 (n-type GaN layer 222) increases. Therefore, the effective light emission amount emitted from the surface of the optical semiconductor stack 202 is reduced. In addition, on the surface of the optical semiconductor stack 202, a difference in light emission amount (light emission distribution) becomes remarkable between a region where the common portion 208a is disposed and a region where the common portion 208a is not disposed.

  2A and 2B are a schematic plan view showing a part of the LED array 100 according to an embodiment of the present invention, and a cross-sectional view showing a IIB-IIB cross section of the LED array 100 shown in FIG. 2A. 2B shows the cross-sectional configuration of the second LED element 101b in the LED array 100, the first LED element 101a also has the same cross-sectional configuration.

  FIG. 2C shows a planar shape of the fusion layer 12 (particularly, the second adhesive layer 6) in the LED array 100. In FIG. 2C, the optical semiconductor stack 2 and the n-side electrode 8 disposed above the fusion layer 12 are indicated by dotted lines.

  Hereinafter, with reference to FIG. 2A to FIG. 2C, the difference of the configuration of the LED array according to the embodiment of the present invention from the LED array according to the reference example will be mainly described.

  As shown in FIGS. 2A and 2B, the LED array 100 according to the embodiment includes a plurality of LED elements including the first and second LED elements 101a and 101b adjacent to each other, as in the LED array according to the reference example. The structure is arranged on a support substrate 10 having an insulating film 9 formed on the surface. Each of the first and second LED elements 101 a and 101 b is disposed on the support substrate 10 via the fusion layer 12 including the first and second adhesive layers 5 and 6. Further, each of the first and second LED elements 101a and 101b is similar to the LED element according to the reference example, and the optical semiconductor stack 2 including the p-type GaN layer 24, the active layer 23, and the n-type GaN layer 22, and p The side electrode 3, the etch stop layer 4, and the n-side electrode 8 are included.

  As shown in FIGS. 2B and 2C, the fusion layer 12 for fusing each of the first and second LED elements 101a and 101b and the support substrate 10 has the first conductive region 12a and the gap region 18 interposed therebetween. And a second conductive region 12b that is electrically insulated from the first conductive region 12a. The first and second conductive regions 12a and 12b are arranged along a direction (y-axis direction) orthogonal to a direction (x-axis direction) in which the first and second LED elements 101a and 101b are arranged. The first and second conductive regions 12a and 12b have a comb-like planar shape, and are arranged so that the comb teeth mesh with each other. The p-side electrode 3 is disposed on the first conductive region 12a and is electrically connected to the first conductive region 12a.

  In addition, the optical semiconductor stack 2 is formed continuously with the main body 2a and the main body 2a disposed above the first conductive region 12a (and the p-side electrode 3), and extends above the second conductive region 12b. A projecting portion 2b to be projected. The overhang portion 2b is supported by the second conductive region 12b via the etch stop layer 4 having electrical insulation. The overhang portion 2b, particularly the p-type GaN layer 24, is not directly connected to the second conductive region 12b.

  Further, the overhanging portion 2c of the optical semiconductor stack 2 and the etch stop layer 4 that supports the overhanging portion 2c are provided with a plurality of holes 2h that look into each comb-tooth portion of the second conductive region 12b. Each of the hole portions 2h is provided independently, and has, for example, a quadrangular pyramid shape whose opening area gradually decreases toward the support substrate 10. Each hole 2h may have a conical shape in which the opening area gradually decreases toward the support substrate 10, for example.

  In the optical semiconductor stack 2, a region that mainly contributes to light emission is a region that corresponds to the region immediately above the first conductive region 12 a. The planar shape of the first and second conductive regions 12a and 12b is a comb-like shape, and the first conductive region 12a is disposed in a region other than the region immediately below the hole 2h. It is possible to increase the region that contributes to light emission.

  A wiring electrode 14 is formed on the inner side surface of the hole 2 h via an insulating protective film 7. The n-side electrode 8 is formed on the optical semiconductor stack 2 (n-type GaN layer 22) so as to extend from the hole 2h along the y-axis direction. The wiring electrode 14 electrically connects the n-side electrode 8 disposed on the optical semiconductor stack 2 and the second conductive region 12b. The wiring electrode 14 extending from each hole 2h is formed independently on the optical semiconductor stack 2 (n-type GaN layer 22). The n-side electrode 8 and the wiring electrode 14 formed continuously therewith are electrically connected to the second conductive region 12b from the surface of the optical semiconductor laminate 2 (n-type GaN layer 22) through the hole 2h.

  As shown in FIGS. 2A and 2C, in the first LED element 101a, the first conductive region 12a is disposed on the positive y-axis side of the surface of the support substrate 10, and the second conductive region 12b is the support substrate. It is arrange | positioned at the y-axis negative direction side of 10 surfaces. In the second LED element 101b, the first conductive region 12a is disposed on the negative y-axis side of the surface of the support substrate 10, and the second conductive region 12b is the positive y-axis side of the surface of the support substrate 10. Placed in. The first conductive region 12 a in the first LED element 101 a and the second conductive region 12 b in the second LED element 101 b are electrically connected by the power transmission electrode 17. Thereby, the first and second LED elements 101a and 101b are electrically connected in series.

  The second conductive region 12b in the first LED element 101a is electrically connected to the first conductive region of the LED element adjacent to the opposite side to the second LED element 101b through the power transmission electrode 17. To do. Further, the first conductive region 12a in the second LED element 101b is electrically connected to the second conductive region of the LED element adjacent to the opposite side to the first LED element 101a through the power transmission electrode 17. To do.

  The current flowing from the optical semiconductor laminate 2 to the n-side electrode 8 merges in the second conductive region 12b through the wiring electrode 14 formed so as to cover the inner surface of the hole 2h, and passes through the power transmission electrode 17 to be adjacent. The LED element flows to the first conductive region 12a. Since the second conductive region 12b and the power transmission electrode 12a are not formed on the optical semiconductor stack 2, even if the second conductive region 12b and the power transmission electrode 12a are formed thicker to suppress a voltage drop due to wiring resistance, the amount of light emitted from the surface of the optical semiconductor stack 2 Will not decrease.

  The region contributing to light emission in the optical semiconductor stack 2 is mainly a region where the p-side electrode 3 is formed immediately below the optical semiconductor stack 2, that is, the main body 2a. The region where the p-side electrode is not formed immediately below the optical semiconductor stack 2, that is, the overhang portion 2b does not contribute to light emission. However, part of the light emitted in the active layer 23 of the main body 2a propagates through the main body 2a and the overhang 2b and is also emitted from the surface of the overhang 2b (n-type GaN layer 22). Therefore, an electrode array according to a reference example in which an electrode having a relatively large area (a common part of the n-side electrode) is formed in a part of the optical semiconductor stack 2 and light from the optical semiconductor stack is blocked by the electrode (see FIG. The LED array 100 according to the embodiment in which the electrode having a relatively large area is not formed on the optical semiconductor laminate 2 has a more uniform light emission distribution than the optical semiconductor stack 2 (see 1).

  Hereinafter, with reference to FIG. 3A to FIG. 3N, in the method of manufacturing the LED array 100 according to the embodiment, the region where the n-side electrode and the second conductive region are electrically connected, that is, the vicinity of the hole of the optical semiconductor stack The description will focus on the region. Note that the relative sizes of the components shown in the figure are different from the actual ones.

  First, as shown in FIG. 3A, a growth substrate 1 made of sapphire is prepared, and an optical semiconductor stack 2 made of a nitride-based semiconductor is formed using a metal organic chemical vapor deposition (MOCVD) method. Specifically, for example, after putting the sapphire substrate 1 into the MOCVD apparatus, thermal cleaning is performed, and after growing the GaN buffer layer 20 and the undoped GaN layer 21, n-type GaN having a thickness of about 5 μm doped with Si or the like. A layer 22, a multiple quantum well light emitting layer (active layer) 23 including an InGaN quantum well layer, and a p-type GaN layer 24 having a thickness of about 0.5 μm doped with Mg or the like are sequentially grown. The growth substrate 1 is a single crystal substrate having a lattice constant capable of epitaxial growth of GaN, and is transparent to light having a wavelength of 362 nm which is an absorption edge wavelength of GaN so that the substrate can be peeled off by laser lift-off in a later process. Selected from ones. In addition to sapphire, spinel, SiC, ZnO, or the like may be used.

  Thereafter, an Ag layer having a film thickness of 200 nm is formed on the surface of the optical semiconductor stack 2 (the surface of the p-type GaN layer 24) by an electron beam evaporation method, and patterned by a lift-off method or the like to form a p-side electrode 3 having a predetermined shape. . In order for the p-side electrode 3 to function as a reflective electrode, it is preferable to use Ag, Pt, Ni, Al, Pd, and alloys thereof as the p-side electrode 3. Further, an ohmic junction layer such as ITO (indium tin oxide) may be sandwiched between the p-side electrode 3 and the surface of the optical semiconductor laminate 2. When sandwiching the ohmic junction layer, the side surface of the ohmic junction layer may be covered with a p-side electrode 3 as a reflective electrode.

Next, as shown in FIG. 3B, on the optical semiconductor stack 2 (on the p-type GaN layer 24) around the p-side electrode 3, it is made of SiO ₂ having the same thickness as that of the p-side electrode 3 by sputtering. An etch stop layer 4 is formed. The etch stop layer 4 functions as an etch stopper in an etching process described later with reference to FIG. 3K. Further, as described above, the etch stop layer 4 includes the p-side electrode 3 or the optical semiconductor stack 2 (particularly, the protruding portion 2b, see FIG. 2B) and the second conductive region 12b in the LED array finally manufactured. And directly supporting the optical semiconductor stack 2 (particularly, the protruding portion).

  Next, as shown in FIG. 3C, Au having a film thickness of 200 nm is formed in the region including the p-side electrode 3 and the etch stop layer 4 by sputtering, and patterned by a lift-off method or the like. 1 adhesive layer 5 is formed. Here, the first adhesive layer 5 is patterned so that a gap 5z is provided in a part of the etch stop layer 4. The gap 5z is provided so that a part of the first adhesive layer 5 is independent at a position corresponding to each hole 2h provided in a later step.

  The first adhesive layer 5 may be formed after forming a diffusion prevention layer or the like in a region including the p-side electrode 3 and the etch stop layer 4. The diffusion prevention layer is for preventing the diffusion of the material used for the p-side electrode 3, and when the p-side electrode 3 contains Ag, Ti, W, Pt, Pd, Mo, Ru, Ir, Au, and These alloys can be used.

  Next, as shown in FIG. 3D, the optical semiconductor stack 2 is divided into a plurality of elements by using a dry etching method using a resist mask and chlorine gas. The side surface of the divided optical semiconductor stack 2 has a forward tapered shape with respect to the growth substrate 1.

  Next, as shown in FIG. 3E, a support substrate 10 made of Si is prepared, and a thermal oxidation process is performed to form an insulating film (thermally oxidized SiO 2 film) 9 on the surface. The support substrate 10 is preferably made of a material having a thermal expansion coefficient close to that of sapphire (7.5 × 10 −6 / K) or GaN (5.6 × 10 −6 / K) and having high thermal conductivity. For example, Si, AlN, Mo, W, CuW, or the like can be used. The film thickness of the insulating film 9 should just be the thickness which can achieve the objective of ensuring insulation.

  Next, a second adhesive layer 6 made of AuSn (Sn: 20 wt%) having a thickness of 1 μm is formed on the insulating film 9 by resistance heating vapor deposition. The material of the first adhesive layer 5 and the material of the second adhesive layer 6 are Au-Sn, Au-In, Pd-In, Cu-In, Cu-Sn, Ag-Sn, which can be fusion bonded. A metal containing Ag—In, Ni—Sn, or the like, or a metal containing Au capable of diffusion bonding can be used.

  As shown in FIGS. 3F and 3G, the second adhesive layer 6 can be formed by using, for example, a lift-off method. First, a photoresist (for example, Clariant Co. photoresist AZ5200) is applied to the entire surface of a support substrate 10 (support substrate 10 having an insulating film 9 formed on the surface) that has been subjected to thermal oxidation, and a hot plate set at 90 ° C. or lower. And pre-bake for about 90 seconds in the atmosphere. Next, a pattern is exposed on the photoresist using ultraviolet light (UV light) with a first exposure amount of 17 mJ. The exposed photoresist is subjected to reversal baking for about 90 seconds in an atmosphere at 120 ° C. to thermally crosslink the exposed portion. Next, the entire surface of the support substrate 10 is irradiated with UV light at a reversal exposure amount of 600 mJ. Further, the photoresist pattern PR1 is formed (in addition to the portion to be the second adhesive layer 6) by dipping in a developing solution for 130 seconds and performing development processing. The photoresist pattern PR <b> 1 formed in this way has a reverse tapered shape with respect to the support substrate 10 at the periphery. Note that the resist and photolithography conditions to be used can be changed as appropriate.

  Next, a metal laminate 6 made of Ti (150 nm) / Ni (50 nm) / Au (100 nm) / Pt (200 nm) / AuSn (1000 nm, Sn: 20 wt%) is formed using a resistance heating vapor deposition method, Thereafter, by lift-off, the second adhesive layer 6 having an end tapered toward the support substrate 10 as shown in FIG. 3G is formed. The region where the photoresist pattern PR1 has been formed becomes a gap 6z. The second adhesive layer 6 separated by the gap 6z has such a shape that the comb-like shapes mesh with each other in plan view. Note that the second adhesive layer 6 can be formed by using a dry etching method or a wet etching method in addition to the lift-off method.

  Next, as shown in FIG. 3H, the first adhesive layer 5 and the second adhesive layer 6 are contacted so that the gap 5z of the first adhesive layer 5 and the gap 6z of the second adhesive layer 6 overlap each other. And heated to 300 ° C. under a pressure of 3 MPa and held for 10 minutes. Then, fusion bonding is performed by cooling to room temperature. The fusion layer 12 is formed by this fusion bonding. Further, the gap 5z of the first customer service layer 5 and the gap 6z of the second adhesive layer 6 are integrated to form a gap region 18.

  In the fusion layer 12, one region sandwiching the gap region 18, that is, the first conductive region 12a, and the other region sandwiching the gap region 18, that is, the second conductive region 12b are defined. Further, the optical semiconductor laminate 2 includes a main body 2a disposed above the first conductive region 12a, and an overhanging portion 2b that is formed continuously with the main body 2a and protrudes above the second conductive region 12b. Defined.

  Thereafter, as shown in FIG. 3I, the sapphire substrate 1 is peeled off by laser lift-off by irradiating UV excimer laser light from the back side of the sapphire substrate 1 and thermally decomposing the buffer layer 20. Note that another method such as etching may be used for peeling or removing the substrate 1.

  Next, as shown in FIG. 3J, Ga generated by laser lift-off is removed with hot water or the like, and then surface-treated with hydrochloric acid. As a result, the n-type Gan layer 22 is exposed. Any surface treatment can be used as long as it can etch a nitride semiconductor, and acids such as phosphoric acid, sulfuric acid, KOH, and NaOH, and chemicals such as alkali can also be used. The surface treatment may be performed by dry etching using Ar plasma or chlorine plasma, polishing, or the like. Further, the surface of the n-type GaN layer 22 is smoothed using a Cl or Ar treatment using a dry etching apparatus such as RIE or a CMP polishing apparatus to remove a laser mark or a laser damage layer. In order to improve the light extraction efficiency, the surface of the n-type GaN layer 22 exposed may be subjected to uneven processing (light extraction structure or microcone structure is formed).

  Next, as shown in FIG. 3K, a photoresist PR2 having a predetermined pattern is formed on the optical semiconductor laminate 2. Thereafter, the optical semiconductor stack 2 exposed from the photoresist PR2 (a part of the overhang portion) is etched by dry etching using chlorine gas until the etch stop layer 4 is exposed. As a result, a hole 2 h whose opening area gradually decreases toward the support substrate 10 is formed in the projecting portion 2 c of the optical semiconductor stack 2. Note that the size of the hole 2 h is about 30 μm on one side on the surface of the optical semiconductor laminate 2. After the hole 2h is formed, the photoresist PR2 is removed.

Next, the protective film 7 made of SiO ₂ is formed on the entire upper surface of the element formed in the above-described process by chemical vapor deposition (CVD) or the like. Thereafter, a part of the protective film 7 formed on the surface of the optical semiconductor multilayer 2 and the protective film 7 on the bottom surface of the hole 2h of the optical semiconductor multilayer 2 and the etch stop are performed by a dry etching method using a CF ₄ / Ar mixed gas. A portion of layer 4 is etched. As a result, as shown in FIG. 3L, the protective film 7 remains on the entire inner surface of the hole 2h, and the hole 2h penetrates the overhanging portion 2b and further the etch stop layer 4 to form the second conductive layer. It comes to look into the area 12b. Note that a wet etching method using BHF or the like may be used for etching the protective film 7 and the etch stop layer 4.

  Next, as shown in FIG. 3M, a 1 nm thick Ti layer, a 200 nm thick Al layer, a 100 nm thick Ti layer, and a 2 μm thick Au layer are stacked in this order by electron beam evaporation. By patterning by lift-off, the n-side electrode 8 that is in ohmic connection with the n-type GaN layer 22 and the wiring electrode 14 that connects the n-side electrode 8 and the second conductive region 12b are formed. The width of the n-side electrode 8 is about 10 μm. The wiring electrode 14 is formed on the entire inner side surface of the hole 2 c via the protective film 7. The n-side electrode 8 and the wiring electrode 14 are formed continuously from the surface of the optical semiconductor stack 2 (n-type GaN layer 22), and are electrically connected to the second conductive region 12b through the hole 2h.

  Next, as shown in FIG. 3N, the power transmission electrode 17 that electrically connects the fusion layers of the LED elements adjacent to each other is formed by an electron beam evaporation method or the like. The width of the power transmission electrode 17 is about 15 μm to 25 μm. Thereafter, the support substrate 10 is divided by laser scribing or dicing.

  As a result, an LED array including a plurality of LED elements including the first and second LED elements 101a and 101b is completed. When the blue GaN light emitting element is whitened, a phosphor (for example, yellow light emission) is put in a resin for sealing and filling the light emitting element.

  Hereinafter, modifications of the LED array according to the embodiment will be described.

  4A to 4C are a plan view and a cross-sectional view showing a modification of the LED array 100 according to the embodiment. As shown in FIG. 4A, the first conductive region 12a in the first LED element 101a and the second conductive region 12b in the second LED element 101b are in direct contact with each other without passing through the power transmission electrode 17. That is, it may be formed continuously. The planar shape of the fusion layer 12 (particularly the second adhesive layer 6) including the first and second conductive regions 12a and 12b can be easily changed by changing the photoresist pattern (see FIG. 3F) used in the lift-off method. It is possible to adjust to.

  Further, as shown in FIG. 4B, the gap region 18 disposed between the first conductive region 12a and the second conductive region 12b may be filled with an insulating member 18a. The conductive region 12a and the second conductive region 12b may not be electrically connected.

  Further, as shown in FIG. 4C, a cut portion 2c penetrating the p-type GaN layer 24 and the active layer 23 is formed in the region of the optical semiconductor stack 2 corresponding to the gap region 18, and the p-type GaN layer in the main body portion 2a is formed. 24. The active layer 23 may be separated from the p-type GaN layer 24 and the active layer 23 in the overhang portion 2b so that they are not directly electrically connected. Note that the cut portion 2c can be formed, for example, by etching the surface of the optical semiconductor laminate 2 in the step shown in FIG. 3A.

  In such a configuration, an etch stop layer that electrically insulates the overhanging portion 2b (particularly the p-type GaN layer 24) and the second conductive region 12b (particularly the first adhesive layer 5), and There is no need to form a protective film for preventing electrical conduction of each layer of the optical semiconductor laminate 2 via the wiring electrode 14. That is, the protruding portion 2b may be in direct contact with the second conductive region 12b, and the wiring electrode 14 formed continuously with the n-side electrode 8 may be in direct contact with the inner surface of the hole 2h. Since it is not necessary to form the etch stop layer 4, the p-side electrode 3 can be formed larger and a region contributing to light emission in the main body 2a can be formed larger.

  When a voltage is applied from the p-side electrode 3 and the n-side electrode 8 in the configuration shown in FIG. 4C, each layer in the projecting portion 2b is connected via the wiring electrode 14 (or the n-side electrode 8 and the second conductive region 12b). It becomes the same potential. Therefore, no current flows between the p-type GaN layer 24 and the n-type GaN layer 22 in the overhang portion 2b. The p-type GaN layer 24 and the active layer 23 in the main body portion 2a are not directly electrically connected to the p-type GaN layer 24 and the active layer 23 in the projecting portion 2b by the cut portion 2c. Therefore, the layers in the main body 2 a are not at the same potential, and a current flows between the p-type GaN layer 24 and the n-type GaN layer 22. For this reason, light emission occurs in the active layer 23 in the main body 2a.

  The planar shape of the first and second conductive regions 12a and 12b is not limited to a comb shape, and may be a rectangular shape as shown in FIG. 4A. At this time, the second conductive region 12b may be arranged so as to include the hole 2h in plan view. That is, the planar shape of the first and second conductive regions 12a and 12b may be a shape in which the second conductive region 12b is disposed immediately below the hole 2h.

  Moreover, the hole 2h provided in the optical semiconductor laminate 2 may be a through-hole that looks into the second conductive region 12b, and may be a notch, for example. When the hole is a notch, the overall planar shape of the optical semiconductor stack 2 is comb-like. At this time, the wiring electrode 14 may be formed so as to cover the (inner) side surface of the notch.

  Hereinafter, an application example using the LED array according to the embodiment or a modification thereof will be described.

  5A and 5B are conceptual diagrams showing the configuration of a vehicular lamp (headlamp) 50 incorporating the LED array 100 according to an embodiment of the present invention.

  FIG. 5A shows an example in which an irradiation lens 105 is used as the irradiation optical system 51. The irradiation lens 105 is set so that the light source image 106 of the LED array 100 is projected onto a virtual vertical screen (irradiation surface) 107 facing the front end of the vehicle.

  The irradiation optical system 51 may use a multi-reflector (reflection surface) 103 and an irradiation lens 105 as shown in FIG. 5B. The headlamp 50 shown in FIG. 5B is a multi-reflector divided into a plurality of small reflection regions, and a light source 102 composed of a phosphor layer (wavelength conversion layer) 108 disposed so as to cover the light emitting surface of the LED array 100. An illumination optical system 51 including a reflective surface 103, a shade 104, and an illumination lens 105 is configured.

  As shown in FIG. 5B, the light source 102 is arranged so that the irradiation direction (light emitting surface) faces upward, and the reflecting surface 103 has the first focal point set near the light source 102 and the second focal point is the upper end of the shade 104. It is a spheroid reflecting surface set in the vicinity of the edge, and is arranged so as to cover a range from the side of the light source 102 to the front so that the light from the light source 102 enters.

  As shown in FIG. 5B, the reflecting surface 103 irradiates the light source image 106 of the LED array 100 of the light source 102 in the predetermined light distribution shape to the front of the vehicle, and faces a virtual vertical screen (irradiation surface) 107 facing the front end of the vehicle. A light source image 106 of the LED array 100 is projected on the top.

  The shade 104 is a light-shielding member for shielding a part of the reflected light from the reflective surface 103 to form a cut-off line suitable for a headlamp. It is disposed between the irradiation lens 105 and the light source 102.

  The irradiation lens 105 is disposed on the front side of the vehicle and irradiates the irradiation surface 107 with the reflected light from the reflection surface 103.

  As mentioned above, although this invention was demonstrated along the Example, the modification, and the application example, this invention is not limited to these. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

DESCRIPTION OF SYMBOLS 1 ... Growth substrate, 2 ... Optical semiconductor lamination | stacking (GaN-type light emission part), 2a ... Main body part, 2b ... Overhang | projection part, 2c ... Notch part, 2h ... Hole part, 3 ... P side electrode (reflection electrode), 4 ... Etch Stop layer, 5 ... first adhesive layer, 6 ... second adhesive layer, 7 ... protective film, 8 ... n-side electrode, 9 ... insulating layer, 10 ... support substrate, 12 ... fusion layer, 12a, 12b ... First and second conductive regions, 14 ... wiring electrode, 17 ... power transmission electrode, 18 ... gap region, 20 ... buffer layer, 21 ... undoped GaN layer, 22 ... n-type GaN layer, 23 ... active layer (light emitting layer) 24 ... p-type GaN layer, 50 ... vehicle lamp (headlamp), 51 ... projection optical system, 100 ... LED array (example), 101 ... LED element, 108 ... phosphor layer (wavelength conversion layer), 102 ... light source, 103 ... reflecting surface, 104 ... shade, 105 ... irradiation lens, 10 ... light source image, 107 ... irradiation surface.

Claims (6)

A semiconductor light-emitting element array comprising a support substrate and a plurality of semiconductor light-emitting elements arranged along the first direction on the support substrate,
Each of the plurality of semiconductor light emitting elements includes:
The first conductive region, the first conductive region, and the first conductive region disposed on the support substrate, spaced apart from each other in a direction perpendicular to the first direction, and electrically connected to the first conductive region. A conductive layer including a second conductive region that is insulated from the conductive layer;
A lower electrode disposed on the first conductive region and in electrical communication with the first conductive region;
A main body portion disposed on the lower electrode, an overhang portion formed continuously with the main body portion and extending above the second conductive region; and the second conductive region penetrating through the overhang portion A first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type different from the first conductivity type, in order from the conductive layer side An optical semiconductor stack,
A plurality of upper electrodes disposed on the optical semiconductor stack and electrically connected to the second conductive region through each of the plurality of through portions;
A semiconductor light emitting device array including: Each of the plurality of semiconductor light emitting elements further includes an electrical insulating layer disposed between the projecting portion of the optical semiconductor stack and the second conductive region and supporting the projecting portion,
The semiconductor light emitting element array according to claim 1, wherein each of the plurality of through portions of the optical semiconductor stack is formed so as to penetrate the overhanging portion and the electrical insulating layer. Each of the plurality of semiconductor light emitting elements further includes an insulating protective film covering an inner surface of each of the plurality of through portions of the optical semiconductor stack,
3. The semiconductor light emitting element array according to claim 2, wherein each of the plurality of upper electrodes is formed so as to cover a surface of the insulating protective film and is electrically connected to the second conductive region. In each of the plurality of semiconductor light emitting elements,
The optical semiconductor stack further includes a first semiconductor layer and an active layer in the main body portion, and a cut portion that divides the first semiconductor layer and the active layer in the projecting portion,
The semiconductor light emitting element array according to claim 1, wherein the projecting portion is supported in contact with the second conductive region. The plurality of semiconductor light emitting elements include a first semiconductor light emitting element and a second semiconductor light emitting element adjacent to the first semiconductor light emitting element,
In the first semiconductor light emitting device, the first conductive region is disposed on a second direction side orthogonal to the first direction, and the second conductive region is opposite to the second direction. Placed on the side
In the second semiconductor light emitting device, the first conductive region is disposed on a side opposite to the second direction, and the second conductive region is disposed on the second direction side,
The first conductive region in the first semiconductor light emitting element and the second conductive region in the second semiconductor light emitting element, which are arranged on the second direction side, are electrically connected. Item 5. The semiconductor light-emitting element array according to any one of Items 1 to 4. A semiconductor light emitting element array according to any one of claims 1 to 5,
An optical system for irradiating an irradiation image of the semiconductor light emitting element array in a predetermined light distribution shape;
A vehicular lamp comprising:

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