JP2014187443A - Drive circuit - Google Patents
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Abstract
Description
本発明は、ＩＣの出力に基づいて負荷を駆動するドライブ回路に関する。 The present invention relates to a drive circuit that drives a load based on an output of an IC.
フォトカプラ搭載のＩＣ等からの出力に基づいて負荷を駆動するドライブ回路としては、多段のトランジスタにて構成したものが様々提案されている（例えば特許文献１の第６図等参照）。 Various drive circuits configured with multistage transistors have been proposed as drive circuits for driving a load based on an output from an IC or the like equipped with a photocoupler (see, for example, FIG. 6 of Patent Document 1).
上記のようなドライブ回路は、ＩＣの出力に対して個々のトランジスタの応答性が高くなるような回路構成とし、負荷駆動に対する応答性をより向上させるが検討課題の一つとなっている。 The drive circuit as described above has a circuit configuration in which the responsiveness of each transistor is high with respect to the output of the IC and further improves the responsiveness to load driving, which is one of the problems to be studied.
本発明は、上記課題を解決するためになされたものであって、その目的は、応答性の向上を図ることができるドライブ回路を提供することにある。 The present invention has been made to solve the above problems, and an object of the present invention is to provide a drive circuit capable of improving responsiveness.
上記課題を解決するドライブ回路は、ＩＣの出力に基づいて負荷を駆動するドライブ回路であって、入力バッファを構成する一対の入力段トランジスタと、該トランジスタ間の出力ノードからの出力に基づいて動作する出力段スイッチとを備え、前記ＩＣの出力を受けて前記入力段トランジスタが動作し次いで前記出力段スイッチが動作して前記負荷を駆動するものであり、前記入力段トランジスタの動作速度を第１コンデンサの充放電態様に基づいて変更可能とするその第１コンデンサが前段の抵抗を介して前記入力段トランジスタの制御端子に接続され、その制御端子と前記ＩＣの出力端子とが直接接続されると共に、前記出力段スイッチの出力端子と逆方向にダイオードを接続し、負荷電流の検出に用いる前記出力段スイッチの出力端子間電圧を含む所定電圧まで第２コンデンサを充電させる充電電流を前記入力段トランジスタ間の出力ノードから得るべく該出力ノードと前記第２コンデンサとが接続されてなる。 A drive circuit that solves the above problem is a drive circuit that drives a load based on an output of an IC, and operates based on a pair of input stage transistors that constitute an input buffer and an output from an output node between the transistors. An output stage switch that receives the output of the IC, operates the input stage transistor, and then operates the output stage switch to drive the load. The first capacitor, which can be changed based on the charge / discharge mode of the capacitor, is connected to the control terminal of the input stage transistor via the resistor in the previous stage, and the control terminal and the output terminal of the IC are directly connected. A diode connected in the opposite direction to the output terminal of the output stage switch, and the output terminal of the output stage switch used for detection of load current The charging current for charging the second capacitor to a predetermined voltage so as to obtain from the output node between said input-stage transistor and the output node and the second capacitor is connected comprised between voltage.
この構成によれば、ＩＣの出力端子からの出力電流が第１コンデンサの充電以外で分岐経路や抵抗も無く入力段トランジスタの制御端子に直接的に作用することから、入力段トランジスタの制御端子に供給する制御電流が速やかに変化する。また、入力段トランジスタ間の出力ノードからの出力電流の一部は第２コンデンサの充電電流として分岐するが、その出力電流が十分に大きいために分岐の影響は小さく、出力段スイッチの制御端子に供給する制御電流の変化も速やかである。これらにより、入力段トランジスタ及び出力段スイッチの動作速度が敏速となり、負荷駆動に対する応答性が向上する。 According to this configuration, since the output current from the output terminal of the IC directly acts on the control terminal of the input stage transistor without any branch path or resistance other than charging the first capacitor, The supplied control current changes quickly. Also, a part of the output current from the output node between the input stage transistors branches as the charging current of the second capacitor, but the influence of the branch is small because the output current is sufficiently large, and it is connected to the control terminal of the output stage switch. Changes in the supplied control current are also rapid. As a result, the operation speeds of the input stage transistor and the output stage switch become quick, and the response to load driving is improved.
本発明のドライブ回路によれば、応答性の向上を図ることができる。 According to the drive circuit of the present invention, the responsiveness can be improved.
以下、ドライブ回路の一実施形態について説明する。
図１に示すように、ドライブ回路１０は、フォトカプラ２１や保護回路２２等を搭載するハイブリッドＩＣ２０に対して用いるドライバ回路であり、該ＩＣ２０からの出力（出力信号Ｓａ）に基づいて負荷を駆動する。
Hereinafter, an embodiment of the drive circuit will be described.
As shown in FIG. 1, the drive circuit 10 is a driver circuit used for a hybrid IC 20 equipped with a photocoupler 21, a protection circuit 22, and the like, and drives a load based on an output (output signal Sa) from the IC 20. To do.
ドライブ回路１０は、入力バッファとして電源線間に直列接続された一対の入力段トランジスタＱ１，Ｑ２を備え、プルアップ側の入力段トランジスタＱ１にはＮＰＮバイポーラトランジスタが、プルダウン側の入力段トランジスタＱ２にはＰＮＰバイポーラトランジスタがそれぞれ用いられている。入力段トランジスタＱ１のコレクタ端子はプラス側電源線ＶＣＣに、入力段トランジスタＱ２のコレクタ端子はマイナス側電源線ＶＥＥにそれぞれ接続され、トランジスタＱ１，Ｑ２の各エミッタ端子は互いに接続されている。入力段トランジスタＱ１，Ｑ２のベース端子（制御端子）は、フォトカプラ搭載のＩＣ２０の出力端子Ｔ１と接続、本実施形態では抵抗等の他の素子を介さず直接接続されている。また、入力段トランジスタＱ１，Ｑ２のベース端子（ＩＣ２０の出力端子Ｔ１）とトランジスタＱ２のコレクタ端子（マイナス側電源線ＶＥＥ）との間には、ベース端子側から順に抵抗Ｒ１とコンデンサＣ１とが直列接続されている。 The drive circuit 10 includes a pair of input stage transistors Q1 and Q2 connected in series between power lines as an input buffer. An NPN bipolar transistor is connected to the pull-up side input stage transistor Q1, and an input stage transistor Q2 is connected to the pull-down side. PNP bipolar transistors are used. The collector terminal of the input stage transistor Q1 to the positive side power supply line V CC, a collector terminal of the input stage transistor Q2 is connected to the negative side power line V EE, the emitter terminals of the transistors Q1, Q2 are connected to each other. The base terminals (control terminals) of the input stage transistors Q1 and Q2 are connected to the output terminal T1 of the IC 20 equipped with a photocoupler, and in this embodiment are directly connected without passing through other elements such as resistors. In addition, a resistor R1 and a capacitor C1 are arranged in order from the base terminal side between the base terminal of the input stage transistors Q1 and Q2 (output terminal T1 of the IC 20) and the collector terminal of the transistor Q2 (minus side power supply line VEE ). They are connected in series.
入力段トランジスタＱ１，Ｑ２のエミッタ端子間のノードＮ１は、抵抗Ｒ２を介して出力段スイッチＱ３のゲート端子（制御端子）と接続されている。出力段スイッチＱ３は、本実施形態ではＭＯＳＦＥＴが用いられるが、ＩＧＢＴ等であってもよい。出力段スイッチＱ３のゲート端子とソース端子との間には、抵抗Ｒ３が接続されている。 A node N1 between the emitter terminals of the input stage transistors Q1 and Q2 is connected to the gate terminal (control terminal) of the output stage switch Q3 via the resistor R2. The output stage switch Q3 is a MOSFET in this embodiment, but may be an IGBT or the like. A resistor R3 is connected between the gate terminal and the source terminal of the output stage switch Q3.
また、出力段スイッチＱ３のドレイン端子と、入力段トランジスタＱ１，Ｑ２のエミッタ端子間のノードＮ１との間には、出力段スイッチＱ３が駆動する負荷電流Ｉｏが過電流か否かを検出するための過電流検出回路１１が備えられている。 Further, between the drain terminal of the output stage switch Q3 and a node N1 between the emitter terminals of the input stage transistors Q1 and Q2, it is detected whether or not the load current Io driven by the output stage switch Q3 is an overcurrent. The overcurrent detection circuit 11 is provided.
過電流検出回路１１は、抵抗Ｒ４，Ｒ５及び複数のダイオード列Ｄａがこの順で直列接続され、抵抗Ｒ４の一端が入力段トランジスタＱ１，Ｑ２のエミッタ端子間のノードＮ１に、最終のダイオード列Ｄａのカソード端子が出力段スイッチＱ３のドレイン端子にそれぞれ接続されている。また、抵抗Ｒ４，Ｒ５間のノードＮ２とグランド線ＧＮＤとの間には、コンデンサＣ２が接続されている。 In the overcurrent detection circuit 11, resistors R4 and R5 and a plurality of diode arrays Da are connected in series in this order, and one end of the resistor R4 is connected to the node N1 between the emitter terminals of the input stage transistors Q1 and Q2, and the final diode array Da. Are respectively connected to the drain terminal of the output stage switch Q3. A capacitor C2 is connected between the node N2 between the resistors R4 and R5 and the ground line GND.
また、ノードＮ２は、ＩＣ２０の検出端子Ｔ２と接続されている。ＩＣ２０内には保護回路２２が備えられ、該保護回路２２を構成するコンパレータ２３の非反転入力端子はその検出端子Ｔ２と接続されている。コンパレータ２３の反転入力端子には、基準電圧Ｖｒｅｆが入力されている。コンパレータ２３は、コンデンサＣ２の充電電圧（ノードＮ２の電圧）を検出電圧Ｖａとして入力し、該検出電圧Ｖａと基準電圧Ｖｒｅｆとの比較に基づいて負荷電流Ｉｏが過電流かを判定する。そして、コンパレータ２３による過電流判定に基づいて、ＩＣ２０内の保護回路２２の動作が通常動作と保護動作のいずれかに切り替えられる。 The node N2 is connected to the detection terminal T2 of the IC 20. The protection circuit 22 is provided in the IC 20, and the non-inverting input terminal of the comparator 23 constituting the protection circuit 22 is connected to the detection terminal T2. A reference voltage Vref is input to the inverting input terminal of the comparator 23. The comparator 23 receives the charging voltage of the capacitor C2 (the voltage at the node N2) as the detection voltage Va, and determines whether the load current Io is an overcurrent based on a comparison between the detection voltage Va and the reference voltage Vref. Based on the overcurrent determination by the comparator 23, the operation of the protection circuit 22 in the IC 20 is switched between the normal operation and the protection operation.
次に、本実施形態のドライブ回路１０の動作（作用）を説明する。
ＩＣ２０は、外部からＨ・Ｌレベルの制御信号を受けると、ＩＣ２０内のフォトカプラ２１を介して出力端子Ｔ１から出力信号Ｓａを入力段トランジスタＱ１，Ｑ２のベース端子に出力する。
Next, the operation (action) of the drive circuit 10 of this embodiment will be described.
When receiving an H / L level control signal from the outside, the IC 20 outputs the output signal Sa from the output terminal T1 to the base terminals of the input stage transistors Q1, Q2 via the photocoupler 21 in the IC 20.
ＩＣ２０の出力端子Ｔ１からの出力信号ＳａがＨレベルになると、入力段トランジスタＱ１がオン、入力段トランジスタＱ２がオフし、ノードＮ１の電圧はＨレベルとなる。すると、ノードＮ１の電圧をゲート端子に受ける出力段スイッチＱ３はオンし、これにより負荷電流Ｉｏが流れ出す。一方、ＩＣ２０の出力端子Ｔ１からの出力信号ＳａがＬレベルになると、入力段トランジスタＱ１がオフ、入力段トランジスタＱ２がオンし、ノードＮ１の電圧はＬレベルとなる。すると、ノードＮ１の電圧をゲート端子に受ける出力段スイッチＱ３はオフし、これにより負荷電流Ｉｏは流れない。 When the output signal Sa from the output terminal T1 of the IC 20 becomes H level, the input stage transistor Q1 is turned on, the input stage transistor Q2 is turned off, and the voltage of the node N1 becomes H level. Then, the output stage switch Q3 that receives the voltage of the node N1 at the gate terminal is turned on, whereby the load current Io flows out. On the other hand, when the output signal Sa from the output terminal T1 of the IC 20 becomes L level, the input stage transistor Q1 is turned off, the input stage transistor Q2 is turned on, and the voltage at the node N1 becomes L level. Then, the output stage switch Q3 that receives the voltage of the node N1 at the gate terminal is turned off, so that the load current Io does not flow.
ここで、図３は、比較例におけるドライブ回路１０ｘを示す。このドライブ回路１０ｘでは、コンデンサＣ１の前段に挿入する抵抗Ｒ１がＩＣ２０の出力端子Ｔ１と入力段トランジスタＱ１，Ｑ２のベース端子との間に配置されている。また、過電流検出回路１１を構成する抵抗Ｒ４の一端の接続先がＩＣ２０の出力端子Ｔ１に変更されている。つまり、ＩＣ２０の出力端子Ｔ１からの出力信号ＳａがＨレベルで、入力段トランジスタＱ１をオン（入力段トランジスタＱ２はオフ）、次いで出力段スイッチＱ３をオンさせる場合、ＩＣ２０の出力端子Ｔ１から出力される出力電流Ｉａに着目すると、該出力電流Ｉａの一部は分岐して検出回路１１のコンデンサＣ２の充電電流Ｉｘとして消失し、残りの電流が抵抗Ｒ１を介し更にコンデンサＣ１の充電後に初めて入力段トランジスタＱ１のベース電流Ｉｂとなる構成となっている。 Here, FIG. 3 shows the drive circuit 10x in the comparative example. In this drive circuit 10x, a resistor R1 inserted before the capacitor C1 is disposed between the output terminal T1 of the IC 20 and the base terminals of the input stage transistors Q1 and Q2. Further, the connection destination of one end of the resistor R4 constituting the overcurrent detection circuit 11 is changed to the output terminal T1 of the IC 20. That is, when the output signal Sa from the output terminal T1 of the IC 20 is at the H level, the input stage transistor Q1 is turned on (the input stage transistor Q2 is turned off), and then the output stage switch Q3 is turned on, the signal is output from the output terminal T1 of the IC20. Focusing on the output current Ia, a part of the output current Ia branches and disappears as the charging current Ix of the capacitor C2 of the detection circuit 11, and the remaining current is input to the input stage only after the capacitor C1 is further charged through the resistor R1. The base current Ib of the transistor Q1 is configured.
そのため、図３及び図２の一点鎖線で示すように、論理ゲート等を搭載するＩＣ２０は出力電流Ｉａの駆動能力が低いこともあり、入力段トランジスタＱ１のベース電流Ｉｂの立ち上がりが緩やかとなり、該トランジスタＱ１の出力電流Ｉｃ、即ち出力段スイッチＱ３のゲート端子に向かうゲート電流Ｉｇの立ち上がりも緩やかとなる。結果、出力段スイッチＱ３のゲート・ソース間電圧Ｖｇｓの立ち上がりも緩やかとなって、該スイッチＱ３のオンへの切り替わりが緩慢な動作となる。 Therefore, as shown by the one-dot chain line in FIG. 3 and FIG. 2, the IC 20 mounted with a logic gate or the like may have a low driving capability of the output current Ia, and the rise of the base current Ib of the input stage transistor Q1 becomes gradual. The rise of the output current Ic of the transistor Q1, that is, the gate current Ig directed to the gate terminal of the output stage switch Q3 also becomes gentle. As a result, the rise of the gate-source voltage Vgs of the output stage switch Q3 also becomes gentle, and the switch Q3 is turned on slowly.
これに対して本実施形態では、同じくＩＣ２０の出力端子Ｔ１からの出力信号ＳａがＨレベルで、入力段トランジスタＱ１をオン（入力段トランジスタＱ２はオフ）、次いで出力段スイッチＱ３をオンさせる場合、ＩＣ２０の出力端子Ｔ１から出力される出力電流Ｉａが分岐経路や抵抗も無く入力段トランジスタＱ１のベース端子に直接的に作用する構成となっている。 On the other hand, in the present embodiment, similarly, when the output signal Sa from the output terminal T1 of the IC 20 is at the H level, the input stage transistor Q1 is turned on (the input stage transistor Q2 is turned off), and then the output stage switch Q3 is turned on. The output current Ia output from the output terminal T1 of the IC 20 directly acts on the base terminal of the input stage transistor Q1 without any branch path or resistance.
そのため、図１及び図２の実線で示すように、入力段トランジスタＱ１のベース電流Ｉｂの立ち上がりが速やかとなり、該トランジスタＱ１の出力電流Ｉｃ、即ち出力段スイッチＱ３のゲート端子に向かうゲート電流Ｉｇの立ち上がりも速やかとなる。ここで、入力段トランジスタＱ１（ノードＮ１）の出力電流Ｉｃの一部は分岐して検出回路１１のコンデンサＣ２の充電電流Ｉｘとして消失するのが懸念されるが、出力電流ＩｃはＩＣ２０の出力電流Ｉａと比べて十分に大きく分岐の充電電流Ｉｘが十分に小さくなることから、出力段スイッチＱ３のゲート電流Ｉｇへの影響は小さい。結果、出力段スイッチＱ３のゲート・ソース間電圧Ｖｇｓの立ち上がりも速やかであり、該スイッチＱ３のオンへの切り替わりが敏速な動作となる。 Therefore, as indicated by the solid line in FIG. 1 and FIG. 2, the rise of the base current Ib of the input stage transistor Q1 becomes rapid, and the output current Ic of the transistor Q1, that is, the gate current Ig directed to the gate terminal of the output stage switch Q3. The rise is also quick. Here, there is a concern that part of the output current Ic of the input stage transistor Q1 (node N1) branches and disappears as the charging current Ix of the capacitor C2 of the detection circuit 11, but the output current Ic is the output current of the IC 20. Since the branch charging current Ix is sufficiently larger than Ia and sufficiently small, the influence on the gate current Ig of the output stage switch Q3 is small. As a result, the rise of the gate-source voltage Vgs of the output stage switch Q3 is rapid, and the switch Q3 is turned on quickly.
因みに、本実施形態で用いるＩＣ２０は、ドライブ回路１０との組み合わせにおいて、入力段トランジスタＱ１がオフ、入力段トランジスタＱ２がオンし、出力段スイッチＱ３がオフする場合、負荷電流Ｉｏが許容範囲である場合には出力段スイッチＱ３は速やかにオフするが、過電流が生じた場合には緩やかにオフする所謂ソフトターンオフ機能を備えている。 Incidentally, in the IC 20 used in the present embodiment, when the input stage transistor Q1 is turned off, the input stage transistor Q2 is turned on, and the output stage switch Q3 is turned off in the combination with the drive circuit 10, the load current Io is in an allowable range. In this case, the output stage switch Q3 is quickly turned off, but has a so-called soft turn-off function that turns off slowly when an overcurrent occurs.
過電流検出回路１１のコンデンサＣ２の充電電圧（ノードＮ１の電圧）は、ダイオード列Ｄａの順方向電圧Ｖ１と出力段スイッチＱ３のソース・ドレイン間電圧Ｖ２との加算電圧値であり、出力段スイッチＱ３が駆動する負荷電流Ｉｏの大きさに応じてコンデンサＣ２の充電電圧、即ち検出電圧Ｖａが変化する。ＩＣ２０内の保護回路２２を構成するコンパレータ２３はその検出電圧Ｖａと基準電圧Ｖｒｅｆとを比較し、負荷電流Ｉｏの電流値が許容範囲内では検出電圧Ｖａが基準電圧Ｖｒｅｆを下回り、コンパレータ２３の出力はＬレベルとなっている。一方、負荷電流Ｉｏが過電流になると、コンデンサＣ２の充電電圧が上昇して検出電圧Ｖａが高くなり、コンパレータ２３の基準電圧Ｖｒｅｆを上回る。そして、コンパレータ２３の出力は、過電流異常を示すＨレベルに切り替わる。コンパレータ２３の出力がＨレベルになると、ＩＣ２０内の保護回路２２は通常動作から保護動作に切り替わる。 The charging voltage (the voltage at the node N1) of the capacitor C2 of the overcurrent detection circuit 11 is a sum voltage value of the forward voltage V1 of the diode array Da and the source-drain voltage V2 of the output stage switch Q3. The charging voltage of the capacitor C2, that is, the detection voltage Va changes according to the magnitude of the load current Io driven by Q3. The comparator 23 constituting the protection circuit 22 in the IC 20 compares the detected voltage Va with the reference voltage Vref. When the current value of the load current Io is within an allowable range, the detected voltage Va falls below the reference voltage Vref, and the output of the comparator 23 Is at L level. On the other hand, when the load current Io becomes an overcurrent, the charging voltage of the capacitor C2 rises and the detection voltage Va becomes high and exceeds the reference voltage Vref of the comparator 23. Then, the output of the comparator 23 is switched to the H level indicating an overcurrent abnormality. When the output of the comparator 23 becomes H level, the protection circuit 22 in the IC 20 switches from normal operation to protection operation.
ここで、入力段トランジスタＱ１をオフ、入力段トランジスタＱ２をオンさせる際には、入力段トランジスタＱ１側のオン時に充電されたコンデンサＣ１の充電電荷のＩＣ２０の出力端子Ｔ１に向けての放電が行われる。ＩＣ２０内においては、そのコンデンサＣ１の放電を行うために出力端子Ｔ１に接続され互いに並列をなす第１放電経路２４と第２放電経路２５が用意されている。第２放電経路２５の放電能力は、第１放電経路２４の放電能力に比べて例えば５０倍小さく構成されている。 Here, when the input stage transistor Q1 is turned off and the input stage transistor Q2 is turned on, the charge of the capacitor C1 charged when the input stage transistor Q1 is turned on is discharged toward the output terminal T1 of the IC 20. Is called. In the IC 20, a first discharge path 24 and a second discharge path 25 connected to the output terminal T1 and parallel to each other are prepared in order to discharge the capacitor C1. The discharge capacity of the second discharge path 25 is configured to be, for example, 50 times smaller than the discharge capacity of the first discharge path 24.
そして、負荷電流Ｉｏの電流値が許容範囲内でコンパレータ２３の出力がＬレベルの時には、通常動作として第１放電経路２４が選択され、コンデンサＣ１の放電が速やかに行われる。つまり、速やかに入力段トランジスタＱ１がオフ、入力段トランジスタＱ２がオンし、次いで出力段スイッチＱ３が速やかにオフする。 When the current value of the load current Io is within an allowable range and the output of the comparator 23 is at the L level, the first discharge path 24 is selected as a normal operation, and the capacitor C1 is discharged quickly. That is, the input stage transistor Q1 is quickly turned off, the input stage transistor Q2 is turned on, and then the output stage switch Q3 is quickly turned off.
これに対し、負荷電流Ｉｏの電流値が過電流となってコンパレータ２３の出力がＨレベルになると、保護動作に切り替わるべく第２放電経路２５が選択され、コンデンサＣ１の放電が緩やかに行われる。従って、入力段トランジスタＱ１のオフ、入力段トランジスタＱ２のオンも緩やかとなり、出力段スイッチＱ３も緩やかにオフするソフトターンオフ動作となり、負荷回路の過電流保護が図られるようになっている。 On the other hand, when the current value of the load current Io becomes an overcurrent and the output of the comparator 23 becomes the H level, the second discharge path 25 is selected to switch to the protection operation, and the capacitor C1 is discharged slowly. Accordingly, the input stage transistor Q1 is turned off and the input stage transistor Q2 is turned on gradually, and the output stage switch Q3 is also turned off gently. Thus, the overcurrent protection of the load circuit is achieved.
次に、本実施形態の特徴的な効果を記載する。
（１）ＩＣ２０の出力がＨレベルで出力段スイッチＱ３をオンさせる場合、ＩＣ２０の出力端子Ｔ１からの出力電流ＩａがコンデンサＣ１の充電以外で分岐経路や抵抗も無く入力段トランジスタＱ１のベース端子に直接的に作用することから、入力段トランジスタＱ１のベース電流Ｉｂが速やかに変化する。また、入力段トランジスタＱ１，Ｑ２間のノードＮ１からの出力電流Ｉｃの一部はコンデンサＣ２の充電電流Ｉｘとして分岐するが、その出力電流Ｉｃが十分に大きいために分岐の影響は小さく、出力段スイッチＱ３のゲート端子に供給するゲート電流Ｉｇの変化も速やかである。これらにより、入力段トランジスタＱ１及び出力段スイッチＱ３の動作速度が敏速となり、負荷駆動に対する応答性を向上させることができる。
Next, characteristic effects of the present embodiment will be described.
(1) When the output of the IC 20 is H level and the output stage switch Q3 is turned on, the output current Ia from the output terminal T1 of the IC 20 is not charged to the capacitor C1 and has no branch path or resistance, and is input to the base terminal of the input stage transistor Q1. Since it acts directly, the base current Ib of the input stage transistor Q1 changes rapidly. Further, a part of the output current Ic from the node N1 between the input stage transistors Q1 and Q2 branches as the charging current Ix of the capacitor C2. However, since the output current Ic is sufficiently large, the influence of branching is small, and the output stage The change in the gate current Ig supplied to the gate terminal of the switch Q3 is also quick. As a result, the operation speeds of the input stage transistor Q1 and the output stage switch Q3 become quick, and the response to load driving can be improved.
尚、上記実施形態は、以下のように変更してもよい。
・ドライブ回路１０の回路構成は一例であり、素子の種類や数、接続態様等はこの限りではなく、適宜変更してもよい。
In addition, you may change the said embodiment as follows.
The circuit configuration of the drive circuit 10 is an example, and the type and number of elements, the connection mode, etc. are not limited to this, and may be changed as appropriate.
・フォトカプラ２１を搭載したＩＣ２０のドライブ回路１０に適用したが、その他の構成のＩＣのドライブ回路に適用してもよい。 -Although it applied to the drive circuit 10 of IC20 carrying the photocoupler 21, you may apply to the drive circuit of IC of another structure.
１０…ドライブ回路、２０…ＩＣ、Ｑ１，Ｑ２…入力段トランジスタ、Ｑ３…出力段スイッチ、Ｃ１…コンデンサ（第１コンデンサ）、Ｃ２…コンデンサ（第２コンデンサ）、Ｄａ…ダイオード列（ダイオード）、Ｒ１…抵抗、Ｔ１…出力端子、Ｎ１…ノード（出力ノード）、Ｉｏ…負荷電流、Ｉｘ…充電電流、Ｉｂ…ベース電流（制御電流）、Ｉｇ…ゲート電流（制御電流）、Ｖ２…ソース・ドレイン間電圧（出力端子間電圧）、Ｖａ…検出電圧（所定電圧）。 DESCRIPTION OF SYMBOLS 10 ... Drive circuit, 20 ... IC, Q1, Q2 ... Input stage transistor, Q3 ... Output stage switch, C1 ... Capacitor (first capacitor), C2 ... Capacitor (second capacitor), Da ... Diode array (diode), R1 ... resistor, T1 ... output terminal, N1 ... node (output node), Io ... load current, Ix ... charging current, Ib ... base current (control current), Ig ... gate current (control current), V2 ... between source and drain Voltage (voltage between output terminals), Va ... detection voltage (predetermined voltage).
Claims (1)
前記入力段トランジスタの動作速度を第１コンデンサの充放電態様に基づいて変更可能とするその第１コンデンサが前段の抵抗を介して前記入力段トランジスタの制御端子に接続され、その制御端子と前記ＩＣの出力端子とが直接接続されると共に、
前記出力段スイッチの出力端子と逆方向にダイオードを接続し、負荷電流の検出に用いる前記出力段スイッチの出力端子間電圧を含む所定電圧まで第２コンデンサを充電させる充電電流を前記入力段トランジスタ間の出力ノードから得るべく該出力ノードと前記第２コンデンサとが接続されたことを特徴とするドライブ回路。 A drive circuit that drives a load based on an output of an IC, comprising: a pair of input stage transistors that constitute an input buffer; and an output stage switch that operates based on an output from an output node between the transistors, In response to the output of the IC, the input stage transistor operates, and then the output stage switch operates to drive the load.
The first capacitor, which enables the operating speed of the input stage transistor to be changed based on the charge / discharge mode of the first capacitor, is connected to the control terminal of the input stage transistor via a previous stage resistor, and the control terminal and the IC Is connected directly to the output terminal of
A diode is connected in the opposite direction to the output terminal of the output stage switch, and a charging current for charging the second capacitor to a predetermined voltage including a voltage between the output terminals of the output stage switch used for detecting a load current is supplied between the input stage transistors. A drive circuit, wherein the output node and the second capacitor are connected to obtain from the output node.
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| CN104617751A (en) * | 2015-02-03 | 2015-05-13 | 辉芒微电子（深圳）有限公司 | Audion drive circuit and drive method |
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