JP2014168367A - Three-phase rectifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a three-phase rectifier capable of synchronizing a cycle of a carrier and each cycle of six sections with each other.SOLUTION: A three-phase rectifier converting a three-phase AC power inputted from a three-phase AC power supply into a DC power, comprises: a bi-directional switch circuit turning on/off an input of each phase from the three-phase AC power supply; and a controller which performs switching control of the bi-directional switch circuit depending on six sections obtained by dividing a cycle of a phase voltage depending on a magnitude relation among voltages of the respective phases in the three-phase AC power. The controller comprises: a PLL circuit generating a carrier clock having a frequency obtained by multiplying a frequency of the phase voltage by integer number times of six, depending on a reference signal corresponding to the three-phase AC power; a carrier generator generating a carrier in synchronization with the generated carrier clock; and a switching pattern generator generating a switching pattern of the bi-directional switch circuit by using the generated carrier.

Description

  The present invention relates to a three-phase rectifier.

  In Patent Document 1, in a three-phase rectifier, a bidirectional switch for turning ON / OFF each phase input from a three-phase AC power source to a full-wave rectifier circuit is controlled based on a switching pattern of a predetermined switching cycle. Have been described. Thereby, according to patent document 1, it is supposed that the alternating current input can be made into the sine wave from which the harmonic was reduced, and the output DC voltage can be made constant.

JP 2011-30409 A

  In the technique described in Patent Document 1, the phase of the phase voltage is divided into six sections, and the content of the switching control is switched for each section. Therefore, if the carrier period used for switching control and each period of the six sections become asynchronous, the waveform of the phase voltage on the input side may be distorted.

  However, Patent Document 1 does not describe at all how to control the carrier period, and does not describe at all how to synchronize the carrier period and the respective periods of the six sections.

  This invention is made | formed in view of the above, Comprising: It aims at obtaining the three-phase rectifier which can synchronize the period of a carrier and each period of six areas.

  In order to solve the above-described problems and achieve the object, the three-phase rectifier according to the first aspect of the present invention is a three-phase rectifier that converts three-phase AC power input from a three-phase AC power source into DC power. The cycle of the phase voltage is divided according to the magnitude relationship between the bidirectional switch circuit for turning on / off the input of each phase from the three-phase AC power source and the voltage of each phase in the three-phase AC power. A control unit that performs switching control of the bidirectional switch circuit according to one section, and the control unit sets an integer multiple of 6 to the frequency of the phase voltage according to a reference signal corresponding to the three-phase AC power. A PLL circuit that generates a carrier clock having an applied frequency, a carrier generation unit that generates a carrier in synchronization with the generated carrier clock, and the bidirectional switch that uses the generated carrier. And having a switching pattern generator for generating a switching pattern of the switch circuit.

  Further, the three-phase rectifier according to the second aspect of the present invention is the three-phase rectifier according to the first aspect of the present invention, wherein the PLL circuit oscillates at a frequency corresponding to the reference signal and is used for the carrier. An oscillation unit that generates a clock; a first frequency division unit that divides the carrier clock by M when M is an integer, and generates a section cycle clock corresponding to the six sections; and the section period A second frequency divider that divides the clock by six to generate a tracking signal, and compares the phase of the reference signal with the phase of the tracking signal and outputs a phase error signal according to the comparison result And a generation unit that generates an oscillation control signal according to the phase error signal, and the oscillation unit oscillates at a frequency according to the reference signal based on the oscillation control signal. And

  Further, the three-phase rectifier according to the third aspect of the present invention is the three-phase rectifier according to the second aspect of the present invention, wherein the PLL circuit is a first divided clock obtained by dividing the interval cycle clock by two. In accordance with the combination of the second divided clock obtained by dividing the first divided clock by 2 and the third divided clock obtained by dividing the second divided clock by 2, A second generation unit configured to generate a section control signal indicating which of the sections, the carrier generation unit generates a carrier corresponding to a current section based on the section control signal; Features.

  Further, the three-phase rectifier according to the fourth aspect of the present invention is the three-phase rectifier according to the second aspect or the third aspect of the present invention, in which the generation unit has the follow-up signal compared to the reference signal. When the phase error signal indicates that the phase is a leading phase, the oscillation control signal is generated so that the frequency of the carrier clock is high, and the follow-up signal has a delayed phase compared to the reference signal. When indicated by the phase error signal, the oscillation control signal is generated so that the frequency of the carrier clock is lowered.

  Further, the three-phase rectifier according to the fifth aspect of the present invention is the three-phase rectifier according to any one of the first aspect to the fourth aspect of the present invention, wherein the control unit is the three-phase AC power. A zero-cross detection unit that detects a zero-crossing timing of at least one of the phase voltage or the line voltage in the signal and generates a zero-crossing signal indicating the detected zero-crossing timing of the phase voltage, and the PLL circuit includes: A signal corresponding to the generated zero cross signal is received as the reference signal.

  Further, the three-phase rectifier according to the sixth aspect of the present invention is the three-phase rectifier according to any one of the first to fifth aspects of the present invention, wherein the carrier generation unit has a counter. The carrier is generated by performing a counting operation in synchronization with the generated carrier clock.

  According to the present invention, for example, each period of the six sections is obtained by dividing one period of the phase voltage into six equal parts, so that the frequency of the carrier clock is multiplied by an integer multiple of 6 to the frequency of the phase voltage. By doing so, each period of the six sections can be an integral multiple of the period of the carrier generated in synchronization with the carrier clock. Thereby, an integer number of carrier waveforms can be accommodated in each of the six sections. That is, the carrier period and the respective periods of the six sections I to VI can be synchronized.

FIG. 1 is a diagram illustrating a configuration of a three-phase rectifier according to the embodiment. FIG. 2 is a diagram illustrating a configuration of the control unit in the embodiment. FIG. 3 is a diagram illustrating a configuration of the phase voltage discriminator in the embodiment. FIG. 4 is a diagram showing a configuration of the pattern signal generator in the embodiment. FIG. 5 is a diagram illustrating six sections I to VI in the embodiment. FIG. 6 is a diagram illustrating the operation of the three-phase rectifier in the sections II and V in the embodiment. FIG. 7 is a diagram illustrating the operation of the three-phase rectifier in the sections I and IV in the embodiment. FIG. 8 is a diagram illustrating the operation of the three-phase rectifier in the sections III and VI in the embodiment. FIG. 9 is a diagram illustrating a configuration of a PLL circuit according to the embodiment. FIG. 10 is a diagram illustrating a configuration of the carrier generation unit in the embodiment. FIG. 11 is a diagram illustrating the operation of the carrier generation unit in the embodiment. FIG. 12 is a diagram illustrating an operation of the second generation unit in the embodiment. FIG. 13 is a diagram illustrating the operation of the generation unit in the embodiment. FIG. 14 is a diagram illustrating the operation of the generation unit according to the embodiment. FIG. 15 is a diagram illustrating a configuration of the oscillation unit according to the embodiment. FIG. 16 is a diagram illustrating a configuration of the oscillation unit in the embodiment. FIG. 17 is a diagram illustrating a configuration of the oscillation unit in the embodiment. FIG. 18 is a diagram illustrating a configuration of the oscillation unit according to the embodiment. FIG. 19 is a diagram illustrating a configuration of a PLL circuit in the embodiment. FIG. 20 is a diagram illustrating a configuration of a control unit in a modification of the embodiment. FIG. 21 is a diagram illustrating a configuration of a PLL circuit according to another modification of the embodiment. FIG. 22 is a diagram illustrating a configuration of a carrier generation unit in another modification of the embodiment. FIG. 23 is a diagram showing a configuration of a PLL circuit in a basic form. FIG. 24 is a diagram showing a configuration of a PLL circuit in a modification of the basic mode.

  Embodiments of a three-phase rectifier according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment.
A three-phase rectifier 1 according to an embodiment will be described with reference to FIG. FIG. 1 is a diagram illustrating a configuration of the three-phase rectifier 1.

  The three-phase rectifier 1 converts the three-phase AC power input from the three-phase AC power source PS via the input terminals IT-r to IT-t into DC power, and outputs the load LD from the output terminals OT-p and OT-n. Output to. The three-phase AC power includes, for example, R-phase AC power, S-phase AC power, and T-phase AC power.

  Specifically, the three-phase rectifier 1 includes a three-phase reactor 8, an input capacitor 9, a full-wave rectifier circuit 4, a bidirectional switch circuit 3, a DC reactor 2, a capacitor 10, and a control unit 11.

  The three-phase reactor 8 is connected between the input terminals IT-r to IT-t and the bidirectional switch circuit 3. The input capacitor 9 is connected between the input terminals IT-r to IT-t and the bidirectional switch circuit 3.

  The full-wave rectifier circuit 4 is connected between the bidirectional switch circuit 3 and the output terminals OT-p and OT-n. The full-wave rectifier circuit 4 has, for example, six diodes connected in a bridge, and full-wave rectifies the three-phase AC power supplied via the bidirectional switch circuit 3 using the six diodes to generate DC power. Is generated.

  The bidirectional switch circuit 3 turns ON / OFF the connection between the input terminals IT-r to IT-t and the input node of each phase of the full-wave rectifier circuit 4. That is, the bidirectional switch circuit 3 includes a plurality of switching elements SW-r, SW-s, and SW-t that turn on / off the supply of AC power of each phase from the three-phase AC power source PS to the full-wave rectifier circuit 4. Have.

  The DC reactor 2 is connected between the full-wave rectifier circuit 4 and the output terminal OT-p. The DC reactor 2 is inserted in series in a P line between the full-wave rectifier circuit 4 and the output terminal OT-p, for example.

  The capacitor 10 is connected between the full-wave rectifier circuit 4 and the output terminals OT-p and OT-n. For example, the capacitor 10 has one end electrode 10p connected to the P line between the full-wave rectifier circuit 4 and the output terminal OT-p, and the other end electrode 10n connected to the full-wave rectifier circuit 4 and the output terminal OT-n. Are connected to the N line.

  The control unit 11 performs switching control of the bidirectional switch circuit 3 based on the voltage of each phase corresponding to the three-phase AC power input from the three-phase AC power source PS.

  Specifically, the control unit 11 includes a switching pattern generator 5 and a drive circuit 6. The switching pattern generator 5 generates a switching pattern of the bidirectional switch circuit 3 based on the voltage of each phase (for example, R phase, S phase, T phase). The drive circuit 6 performs switching control of the switching elements SW-r, SW-s, and SW-t of the bidirectional switch circuit 3 based on the switching pattern generated by the switching pattern generator 5. At this time, the switching pattern generator 5 has the bidirectional switch circuit 3 in accordance with six sections I to VI in which one cycle of the phase voltage is divided according to the magnitude relationship of the voltages of the phases in the three-phase AC power. A switching pattern is generated (see FIGS. 6 to 8).

  Next, the six sections I to VI will be described with reference to FIG. FIG. 5 is a diagram illustrating six sections I to VI.

  The control unit 11 recognizes, for example, six sections I to VI as shown in FIG. 5 according to the magnitude relationship of the AC voltage of each phase (R phase, S phase, T phase).

  In section I, the R phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the T phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the R phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the T phase is the intermediate voltage phase, it recognizes that the current mode is the section I. .

  In section II, the R phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the S phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the R phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the S phase is the intermediate voltage phase, it recognizes that the current mode is the section II. .

  In section III, the S phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the R phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the S phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the R phase is the intermediate voltage phase, the control unit 11 recognizes that the current mode is the section III. .

  In section IV, the S phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the T phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the S phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the T phase is the intermediate voltage phase, it recognizes that the current mode is the section IV. .

  In section V, the T phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the S phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the T phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the S phase is the intermediate voltage phase, it recognizes that the current mode is the section V. .

  In the section VI, the T phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the R phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the T phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the R phase is the intermediate voltage phase, the control unit 11 recognizes that the current mode is the section VI. .

  Next, a configuration example of the switching pattern generator 5 will be described with reference to FIGS. FIG. 2 is a block diagram showing an example of the switching pattern generator 5 of FIG. FIG. 3 is a diagram illustrating a configuration example of the phase voltage discriminator 52 of the switching pattern generator 5. FIG. 4 is a circuit diagram showing a configuration example of the pattern signal generator 51 of the switching pattern generator 5.

  The switching pattern generator 5 generates switching patterns (R, S, T phase pulses) as shown in FIGS. 6 to 8, for example, depending on which of the six sections I to VI is present. . The switching pattern generator 5 detects which phase of the three-phase AC power from the three-phase AC power source PS is an intermediate potential phase at a predetermined timing such as the rise of the switching cycle, and generates a modulation waveform according to the detection result. The switching pattern is generated by obtaining the ON / OFF timing of the switching pattern by the sawtooth wave.

  For example, the switching pattern generator 5 includes a carrier generator 5b and a switching pattern generator 5a as shown in FIG. The carrier generator 5b generates a carrier in synchronization with the carrier clock. The switching pattern generator 5a generates the switching pattern of the bidirectional switch circuit 3 using the generated carrier.

  The carrier generator 5 b includes a DC voltage setter 53 and a sawtooth generator 54. The switching pattern generator 5a includes a pattern signal generator 51, a phase voltage discriminator 52, comparators 55-1 to 55-3, NOT circuits 56-1 and 56-2, OR circuits 57-1 and 57-2, and a NOT circuit. 58-1, 58-2, AND circuits 59-1, 59-2, AND circuits 60R, 60T, OR circuit 60S, NAND circuits 61R-61T, AND circuits 62R-62T, OR circuits 63R-63T, and AND circuit 64 Have

  The pattern signal generator 51 uses the R-phase voltage normalized signals a and S-phase in which the peak value of the input phase voltage is normalized to “1” in order to make the pulse order of the interval voltages in all the intervals I to VI regular. The voltage standardized signal b and the T-phase voltage standardized signal c are calculated, and a modulation waveform 1, a modulation waveform 2A, a modulation waveform 2B, and a modulation waveform 3 are output.

  The DC voltage setting unit 53 sets a DC voltage setting gain k (where k ≦ 1) in the sawtooth wave generator 54. The sawtooth wave generator 54 outputs the sawtooth wave 1 and the sawtooth wave 2. The phase voltage discriminator 52 compares the potentials of the input R-phase voltage normalized signal a, S-phase voltage normalized signal b, and T-phase voltage normalized signal c, and R-phase middle, S-phase middle, T-phase An intermediate determination signal (“1” for intermediate, “0” for non-intermediate) is output, respectively. Specifically, in the middle of the S phase, modulation waveforms 1 and 3 are output, and sawtooth waves 1 and 2 are output (see FIG. 6). In the middle of the T phase, the modulation waveforms 1 and 2A are output, and the sawtooth wave 1 is output (see FIG. 7). In the middle of the R phase, the modulation waveforms 3 and 2B are output, and the sawtooth wave 2 is output (see FIG. 8). Thus, in the switching pattern generator 5, the switching pattern generation method is changed according to which phase the intermediate phase is. Thereby, the same regularity is given to the switching pattern of the same phase in all modes.

  The comparison signal obtained by comparing the modulation waveform 1 and the sawtooth wave 1 by the comparator 55-1 and the output obtained by performing the NOT operation on the R-phase intermediate signal by the NOT circuit 58-1 are ANDed by the AND circuit 60R. Output as a non-intermediate phase pulse.

  The comparison signal obtained by comparing the modulation waveform 3 and the sawtooth wave 2 by the comparator 55-3 and the output obtained by performing NOT operation on the T-phase intermediate signal by the NOT circuit 58-2 are ANDed by the AND circuit 60T. Output as a non-intermediate phase pulse.

  The comparison signal obtained by comparing the modulation waveform 2A and the sawtooth wave 1 by the comparator 55-2A and the output obtained by performing NOT operation on the comparison signal of the comparator 55-1 by the NOT circuit 56-1 are ORed by the OR circuit 57-1. Calculated. The comparison signal obtained by comparing the modulation waveform 2B and the sawtooth wave 2 by the comparator 55-2B and the output obtained by performing the NOT operation on the comparison output of the comparator 55-3 by the NOT circuit 56-2 are ORed by the OR circuit 57-2. The

  An AND circuit 59-1 performs an AND operation on the OR circuit 57-1 and an T-phase intermediate signal, and an OR circuit 57-2 performs an OR operation on the R-phase intermediate signal. The output of the AND operation in 2 is ORed by the OR circuit 60S, and an S-phase non-intermediate pulse is output.

  The NAND circuit 61R performs an NAND operation on the S-phase non-intermediate time pulse and the T-phase non-intermediate time pulse and the R-phase intermediate signal, and the AND circuit 62R performs an AND operation to output an R-phase intermediate time pulse.

  The NAND circuit 61S performs an NAND operation on the R-phase non-intermediate pulse and the T-phase non-intermediate pulse, and the S-phase intermediate signal is AND-operated by the AND circuit 62S, and is output as an S-phase intermediate pulse.

  The NAND circuit 61T performs an NAND operation on the R-phase non-intermediate time pulse and the S-phase non-intermediate time pulse and the T-phase intermediate signal, and the AND circuit 62T performs an AND operation to output it as a T-phase intermediate time pulse.

  The comparator 65 compares the sawtooth wave 1 with the “0” input, and outputs a comparison signal as a zero voltage insertion lock signal.

  The OR circuit 63R performs an OR operation on the R-phase non-intermediate time pulse and the R-phase intermediate time pulse, and the 0 voltage insertion signal is ANDed by the AND circuit 64 and is output as an R-phase pulse. Thereby, a switching pattern (section 4 in each section I to VI) for turning off the bidirectional switch is introduced into the R-phase pulse.

  In the OR circuit 63T, the T-phase non-intermediate time pulse and the T-phase intermediate time pulse are ORed and output as a T-phase pulse. Since the output of the OR circuit 63T is “0” during the zero voltage insertion signal period, the T phase pulse is not calculated with the zero voltage insertion signal.

  In the OR circuit 63S, the S-phase non-intermediate time pulse and the S-phase intermediate time pulse are ORed to output an S-phase pulse. The R-phase pulse and the T-phase pulse are “0” during the zero voltage insertion signal period, and no DC voltage is generated even when the S-phase pulse is ON. For the purpose of not increasing the number of times of T-phase switching, the calculation with the zero voltage insertion signal is not performed.

  The sawtooth wave generator 54 is a straight line connecting (time axis kT, gain axis 0) and (time axis 0, gain axis 1) when the period T is set based on the DC voltage setting gain k of the DC voltage generator 53. To output a sawtooth wave 1. The sawtooth wave generator 54 outputs the sawtooth wave 2 as a straight line connecting (time axis 0, gain axis 0) and (time axis kT, gain axis 1) based on the DC voltage setting gain k.

  As shown in FIG. 3, the phase voltage discriminator 52 includes comparators 70R, 70S, and 70T, AND circuits 71R, 71S, and 71T, AND circuits 72R, 72S, and 72T, and NOR circuits 73R, 73S, and 73T. ing.

  The comparator 70R compares the R-phase voltage normalized signal a and the S-phase voltage normalized signal b, and compares the comparison signal (“1” when R-phase voltage normalized signal a> S-phase voltage normalized signal b, When the R-phase voltage standardized signal a ≦ the S-phase voltage standardized signal b, “0”) is output to the AND circuits 71R, 72S, 71T, and 72T. The comparator 70S compares the S-phase voltage normalized signal b and the T-phase voltage normalized signal c, and compares the comparison signal (“1” when S-phase voltage normalized signal b> T-phase voltage normalized signal c; When the S-phase voltage normalized signal b ≦ T-phase voltage normalized signal c, “0”) is output to the AND circuits 71R, 72R, 71S, and 72T. The comparator 70T compares the T-phase voltage normalized signal c and the R-phase voltage normalized signal a, and compares the comparison signal (“1” when T-phase voltage normalized signal c> R-phase voltage normalized signal a; When the T-phase voltage normalized signal c ≦ the R-phase voltage normalized signal a, “0”) is output to the AND circuits 72R, 71S, 72S, 71T.

  The AND circuit 71R outputs an AND operation result of the comparison signal of the comparator 70R and the comparison signal of the comparator 70S. The AND circuit 72R outputs an AND operation result of the comparison signal of the comparator 70S and the comparison signal of the comparator 70T. The AND circuit 71S outputs an AND operation result of the comparison signal of the comparator 70S and the comparison signal of the comparator 70T. The AND circuit 72S outputs an AND operation result of the comparison signal of the comparator 70T and the comparison signal of the comparator 70R. The AND circuit 71T outputs an AND operation result of the comparison signal of the comparator 70T and the comparison signal of the comparator 70R. The AND circuit 72T outputs an AND operation result of the comparison signal of the comparator 70R and the comparison signal of the comparator 70S.

  The NOR circuit 73R outputs a NOR operation result (“1” in the case of the intermediate and “0” in the case of not the intermediate) between the output of the AND circuit 71R and the output of the AND circuit 72R as the R-phase intermediate signal. The NOR circuit 73S outputs a NOR operation result (“1” when intermediate, “0” when not intermediate) between the output of the AND circuit 71S and the output of the AND circuit 72S as an S-phase intermediate signal. The NOR circuit 73T outputs a NOR operation result (“1” when intermediate, “0” when not intermediate) between the output of the AND circuit 71T and the output of the AND circuit 72T as a T-phase intermediate signal.

  As shown in FIG. 4, the pattern signal generator 51 that forms each modulation waveform includes absolute value circuits 80R, 80S, and 80T, and 3-input adders 81-1 and 81-2. The absolute value circuit 80R calculates the absolute value | a | of the R-phase voltage normalized signal a and outputs a modulation waveform 1. The absolute value circuit 80S calculates and outputs the absolute value | b | of the S-phase voltage normalized signal b. The absolute value circuit 80T calculates the absolute value | c | of the T-phase voltage normalized signal c and outputs the modulation waveform 3.

  The 3-input adder 81-1 adds the modulation waveform 1, the output of the absolute value circuit 80S, and the constant −1, and outputs the modulation waveform 2A. The 3-input adder 81-2 adds the modulation wavelength 3, the output of the absolute value circuit 80S, and the constant −1, and outputs a modulation waveform 2B.

  Next, the operation in each section I to VI of the switching pattern generator 5 will be described with reference to FIGS.

  With reference to FIGS. 6-8, the direct-current voltage and the electric current of each phase by switching operation in each area I-VI are demonstrated. In sections I and IV, the T phase is an intermediate phase, in sections II and V, the S phase is an intermediate phase, and in sections III and VI, the R phase is an intermediate phase. , III will be described. FIG. 6 is a diagram illustrating an example of a modulation waveform, a sawtooth wave, and R, S, and T phase pulses in sections II and V. FIG. 7 is a diagram illustrating an example of a modulation waveform, a sawtooth wave, and R, S, and T phase pulses in sections I and IV. FIG. 8 is a diagram illustrating an example of a modulation waveform, a sawtooth wave, and R, S, and T phase pulses in sections III and VI.

  As shown in FIGS. 6 to 8, in all the sections I to VI, the R-phase pulse is OFF → ON → OFF, the S-phase pulse is ON → OFF → ON, and the T-phase pulse is ON → OFF. In addition, the same phase in all the sections I to VI has the same regular pattern in which the ON and OFF changes are regular. In all the sections I to VI, the R phase pulse has a period (section 4) in which the zero voltage insertion signal is inserted. The period in which this zero voltage insertion signal is inserted is A switching pattern for turning off the direction switch circuit is inserted. Accordingly, in section 4, two of the three phases (R phase and T phase) are turned off, so that no current flows in all phases.

(1) Section II
First, the DC voltage will be described. In FIG. 6, the DC voltages in sections 1, 2, 3, and 4 are ST voltage = b−c, RT voltage = ac, RS voltage = ab, and rectifier output short-circuit voltage = 0, respectively. . Next, each phase pulse will be described. In section II, the R phase is the maximum phase, the T phase is the minimum phase, and the S phase is the intermediate phase. In the maximum phase and the minimum phase, the pulse is turned on for a time proportional to each potential. Therefore, the R-phase pulse width x = kT | a | and the T-phase pulse width z = kT | c |. Here, the timing (section 2 + section 3) at which the R-phase pulse is turned on is obtained from the intersection of the R-phase voltage | a | and the sawtooth wave 1. Further, the timing (section 1 + section 4) when the R-phase pulse is turned off is obtained from the intersection of the sawtooth wave 1 and the gain axis 0. Thereby, an R-phase pulse is obtained. On the other hand, the timing (section 3 + section 4) at which the T-phase pulse is turned off is obtained from the intersection of the T-phase voltage | c | and the sawtooth wave 2. Thereby, a T-phase pulse is obtained. The intermediate phase pulse is turned ON when either the maximum phase pulse or the minimum phase pulse is OFF. Therefore, the S-phase pulse is obtained from the intersection between the R-phase voltage | a | and the sawtooth wave 1 and the intersection between the T-phase voltage | c | and the sawtooth wave 2. The widths of the sections 1, 2, 3, and 4 are kT × (1− | a |), kT × (| a | + | c | −1), kT × (1− | c |), T, respectively. X (1-k). The average of the DC voltage in the switching period T can be expressed as follows by integrating the DC voltage for each section, adding each, and dividing by the switching period T. Average of DC voltage in switching period T = {(b−c) × kT × (1−a) + (ac) × kT × (ac−1) + (ab) × kT × (1 + c ) + 0 × T × (1-k)} / T
= K {a ² + c ² −b (a + c)}
Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )

Furthermore, from AC theory, from a ² + b ² + c ² = 3/2,
= K x 3/2
Thus, it becomes a constant voltage proportional to k.

  Next, the input current will be described. As the R-phase input current, a positive current proportional to the time of the R-phase voltage a flows. As the T-phase input current, a negative current proportional to the magnitude of the T-phase voltage | c | flows. As for the S-phase input current, a positive current flows in section 1 and a negative current flows in section 3. Therefore, the flowing current is kT × (1−a) −kT × (1 + c) −kT (−a−c) = kTb, and the interval 4 in which the 0 voltage insertion signal is inserted is excluded from the switching period T. When divided by the period kT, the S-phase voltage b is obtained. Therefore, a current proportional to the R-phase voltage a, the S-phase voltage b, and the T-phase voltage c flows through the R phase, S phase, and T phase, resulting in a sine wave current.

(2) Section I
In FIG. 7, DC voltages in sections 1, 2, 3, and 4 are ST voltage = c−b, RT voltage = ac, RS voltage = ab, and rectifier output short-circuit voltage = 0, respectively. . Next, each phase pulse will be described. In section I, the R phase is the maximum phase, the S phase is the minimum phase, and the T phase is the intermediate phase. In order to make the time ON proportional to the respective potentials in the maximum phase and the minimum phase without changing the ON / OFF sequence of the R, S, T phase pulses, in the section I, the modulation waveforms 1, 2A and the sawtooth wave 1 Is used to obtain the ON / OFF timing of each pulse shown in FIG. The widths of the sections 1, 2, 3, and 4 are kT × (1− | a |), kT (1− | b |), kT × (| a | − | b | −1), and T ×, respectively. (1-k). The average of the DC voltage in the switching period T can be expressed as follows.

Average of DC voltage of switching period T = {(c−b) × kT × (1−a) + (ac) × kT × (b + 1) + (ab) × kT × (ab−1) ) + 0 * kT * (1-k)} / T
= K {a ² + b ² −c (a + b)}

Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )

Furthermore, from AC theory, from a ² + b ² + c ² = 3/2,
= K x 3/2
Thus, it becomes a constant voltage proportional to k.

  Next, the input current will be described. As in the case of the section II, a positive current proportional to the time of the R phase voltage a flows in the R phase of the maximum phase. A negative current proportional to the time of the S phase voltage b flows in the S phase of the minimum phase. In the T phase, a negative current flows in section 1 and a positive current flows in section 2. For this reason, the flowing current is kT × (1−a) −kT × (1 + b) = kTc, and c when divided by kT. Therefore, a current proportional to the voltage flows in each phase and becomes a sine wave current.

(3) Section III
In FIG. 8, the DC voltages in sections 1, 2, 3, and 4 are ST voltage = b−c, RT voltage = ac, RS voltage = b−a, and rectifier output short-circuit voltage = 0, respectively. . Next, each phase pulse will be described. In section III, the S phase is the maximum phase, the T phase is the minimum phase, and the R phase is the intermediate phase. As in the section I, in order to turn on the time proportional to the respective potentials in the maximum phase and the minimum phase without changing the ON / OFF order of the R, S, and T phase pulses, in the section III, the modulation waveform 3, 2B and the sawtooth wave 2 are used to obtain the ON / OFF timing of each phase pulse shown in FIG. The widths of the sections 1, 2, 3, and 4 are kT × (| b | + | c | −1), kT × (1− | b |), kT × (1− | c |), T × (1−k). The average of the DC voltage in the switching period T can be expressed as follows.

Average of DC voltage of switching period T = {(b−c) × kT × (−c + b−1) + (ac) × kT × (−b + 1) + (b−a) × kT × (1 + c) +0 * KT * (1-k)} / T
^{= K {b 2 + c 2} -a (b + c)}

Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )

Furthermore, from AC theory, from a ² + b ² + c ² = 3/2,
= K x 3/2
Thus, it becomes a constant voltage proportional to k.

  Next, the input current will be described. In section III, since the S phase is the maximum phase and the T phase is the minimum phase, a positive current that is proportional to the time of the S phase voltage b flows in the S phase, and the T phase is a negative that is proportional to the time of the T phase voltage c. Current flows. In the R phase, a negative current flows in section 2 and a positive current flows in section 3. Therefore, the flowing current is kT × (1−b) −kT × (1 + c) = kTa, which is a when divided by RT. Therefore, a current proportional to the voltage flows in each phase and becomes a sine wave current.

  Thus, in the switching pattern generator 5, one cycle of the phase voltage is divided into six sections I to VI, and the contents of the switching control are switched for each section I to VI. For this reason, if the carrier period used for switching control and the periods of the six sections I to VI become asynchronous, the waveform of the phase voltage on the input side may be distorted.

  That is, the switching pattern generator 5 normalizes the phase voltages of the R, S, and T phases to 1, compares them with the carrier signal, and generates a pulse signal. The pulse is calculated according to the determination of the magnitude relationship between the R, S, and T phases, the drive circuit 6 generates a drive signal, and the switching elements SW-r, SW-s, and SW-t of the bidirectional switch circuit 3 are driven. To do. Thereby, the DC voltage can be made constant and the input current can be made a sine wave.

  At this time, the phase voltages of the R, S, and T phases are generally distorted due to system noise, and if the three-phase AC power from the three-phase AC power source PS is used as it is, a theoretical result is obtained. Is difficult. Therefore, the phase voltage of each phase used for switching control is preferably an ideal sine wave.

  In addition, in the modulation, it is necessary that the beginning and end of each section I to VI in FIG. 5 coincide with the beginning and end of the carrier waveform. If this is not the case, that is, if the next carrier starts at the middle of the carrier cycle, it becomes difficult to obtain an ideal pulse signal, and it becomes difficult to obtain a theoretical waveform.

  That is, when an asynchronous carrier is used for each period of the six sections I to VI, the input current waveform and the DC voltage waveform tend to be distorted.

  Therefore, in the present embodiment, the control unit 11 performs control so as to synchronize the cycle of the carrier used for the switching control and each cycle of the six sections I to VI.

  Specifically, the control unit 11 further includes a zero-cross detection unit 12, a PLL circuit 13, and an estimation unit 14, as shown in FIG.

  The zero cross detector 12 detects the zero cross timing of the phase voltage in the three-phase AC power. For example, in the case illustrated in FIG. 1, the zero-cross detector 12 detects the timing at which the R-phase voltage zero-crosses. For example, the zero-cross detection unit 12 includes a comparator, and detects the zero-cross timing of the phase voltage by detecting inversion of the polarity of the phase voltage using the comparator or the like. The zero cross detection unit 12 outputs the detection result to the PLL circuit 13. Hereinafter, this detection result is referred to as a phase voltage zero-cross signal. That is, the phase voltage zero-cross signal is, for example, a signal indicating the timing at which the phase voltage zero-crosses in the rising direction, and is, for example, a pulse-like signal having the frequency of the phase voltage.

  The zero cross detection unit 12 may detect the zero cross timing of the line voltage instead of detecting the zero cross timing of the phase voltage. For example, although not shown, the zero cross detector 12 may detect the timing at which the R-phase and S-phase line voltages zero-cross. In this case, the zero cross detection unit 12 generates a zero cross signal of the line voltage as a detection result. The zero-cross signal of the line voltage is, for example, a signal indicating the timing at which the line voltage zero-crosses in the rising direction, and is, for example, a pulse signal having a phase voltage frequency. At this time, the zero-cross detection unit 12 considers that the zero-cross signal of the line voltage is approximately 30 degrees ahead of the zero-cross signal of the phase voltage, and the generated zero-cross signal of the line voltage is approximately 30 degrees. The phase-delayed signal is output to the PLL circuit 13 as a signal corresponding to the zero-cross signal of the line voltage. That is, the zero-cross detection unit 12 generates a signal corresponding to the zero-cross signal of the phase voltage according to the generated zero-cross signal of the line voltage, and outputs the signal to the PLL circuit 13.

  The PLL circuit 13 receives the zero cross signal as a reference signal corresponding to the three-phase AC power from the three-phase AC power source PS. The PLL circuit 13 grasps the frequency of the phase voltage according to a reference signal (for example, a zero cross signal) corresponding to the three-phase AC power. For example, since the zero cross signal has the frequency of the phase voltage, the PLL circuit 13 can grasp the frequency of the phase voltage from the frequency of the zero cross signal. The PLL circuit 13 generates a carrier clock having a frequency obtained by multiplying the grasped frequency of the phase voltage by an integer multiple of 6. The PLL circuit 13 outputs the generated carrier clock to the carrier generation unit 5b (see FIG. 2). Thereby, the carrier generation unit 5b generates a carrier in synchronization with a carrier clock having a frequency obtained by multiplying the frequency of the phase voltage by an integer multiple of 6.

  For example, since each period of the six sections I to VI is obtained by dividing one period of the phase voltage into six equal parts, the frequency of the carrier clock is obtained by multiplying the frequency of the phase voltage by an integer multiple of 6. Each period of the six sections I to VI can be an integral multiple of the period of the carrier (switching period T) generated in synchronization with the carrier clock. As a result, an integer number of carrier waveforms can be accommodated in each of the six sections I to VI (see FIG. 11). That is, the carrier period (switching period T) can be synchronized with the periods of the six sections I to VI.

  In addition, the PLL circuit 13 generates a section period clock having an equal period in each of the six sections I to VI according to a reference signal (for example, a zero cross signal) corresponding to the three-phase AC power. That is, the PLL circuit 13 divides a plurality of carrier clocks to generate a carrier cycle clock, and divides a plurality of carrier cycle clocks to generate an interval cycle clock. The PLL circuit 13 outputs the generated carrier cycle clock, the interval cycle clock, and a divided clock (hereinafter referred to as an intermediate divided clock) at an intermediate stage from the carrier cycle clock to the interval cycle clock to the estimation unit 14. The halfway divided clock may include divided clocks at a plurality of stages when the carrier cycle clock is repeatedly divided by two to generate the interval cycle clock.

  Further, the PLL circuit 13 divides the interval cycle clock by two to generate a first divided clock (see FIG. 12). The PLL circuit 13 divides the first frequency-divided clock by two to generate a second frequency-divided clock (see FIG. 12). The PLL circuit 13 generates a third divided clock (also called a follow-up signal, see FIG. 12) obtained by dividing the second divided clock by two.

  The estimation unit 14 receives from the PLL circuit 13 a carrier cycle clock, an intermediate divided clock, a section cycle clock, a first divided clock, a second divided clock, and a third divided clock. The estimation unit 14 estimates which of the six sections I to VI is the current section according to the combination of the first divided clock, the second divided clock, and the third divided clock. (See FIG. 12). Furthermore, the estimation unit 14 has the current timing at which time position in the current section (that is, the position on the horizontal axis in FIG. 5) according to the combination of the carrier cycle clock, the halfway divided clock, and the section cycle clock. Estimate. And the estimation part 14 estimates the voltage of each phase as shown in FIG. 5 according to an estimation result, and estimates the voltage of each phase (for example, R phase voltage a, S phase voltage b, T phase) The voltage c) is output to the switching pattern generator 5.

  Specifically, the estimation unit 14 includes a ROM 14a and a control signal generator 14b (see FIG. 9). The ROM 14a stores sine wave data (for example, table data) in which time position data in a sine wave whose peak value is normalized to “1” and the normalized amplitude are associated with each other. As described above, the control signal generator 14b estimates time positions in the current sections I to VI and the current sections I to VI.

  For example, the control signal generator 14b generates first data indicating the current section by collecting the bit values of the first divided clock, the second divided clock, and the third divided clock. The control signal generator 14b generates second data indicating the current timing by combining the bit values of the carrier clock, the halfway divided clock, and the interval cycle clock. The control signal generator 14b combines the first data and the second data to generate time position data. Then, the control signal generator 14b refers to the sine wave data stored in the ROM 14a, identifies the normalized amplitude of each phase corresponding to the generated time position data, and determines the normalized amplitude of each identified phase. It is assumed that the voltage of each phase is estimated. Thereby, compared with the case where the phase voltage of each phase in the three-phase AC power from the three-phase AC power source PS is used as it is, the phase of each phase (R phase, S phase, T phase) close to an ideal sine wave. A voltage can be obtained.

  In this way, the phase voltage of each phase used for switching control is zero cross signal of any of the phase voltages of R, S, T phase, instead of using the detected phase voltage of R, S, T phase, And by obtaining an ideal sine wave from the data stored in the ROM 14a from the phase, it can be obtained as being close to the ideal sine wave.

  In addition, a function for synchronizing the beginning and end of the carrier with the zero cross signal is required. In order not to leave a DC component, the number of carriers on the positive side of the sine wave waveform and the number of carriers on the negative side are made the same. Therefore, the frequency of the carrier clock is multiplied by a multiple of 2 to the frequency of the phase voltage. It is necessary to make it. Next, in order to make it symmetrical with the other two phases delayed by 120 °, it is necessary to multiply the frequency of the phase voltage by a multiple of 3. Thus, it is necessary to make the number of carriers that fit in the period of each section I to VI constant.

  If the carrier clock is a clock having a constant frequency, the carrier generated in synchronization with the carrier clock also has a constant frequency. In this case, when the frequency of the three-phase AC power from the three-phase AC power source PS changes, it is difficult to follow the change. As a result, the carrier period used for the switching control and the six sections I to VI It is easy for each period to become asynchronous.

  On the other hand, in the present embodiment, the PLL circuit 13 internally corresponds to the phase of the reference signal (for example, zero cross signal) corresponding to the three-phase AC power from the three-phase AC power source PS and the carrier clock. Is synchronized with the generated tracking signal. For example, the PLL circuit 13 is configured such that the frequency dividing stage is a multiple of 6 and is synchronized with the zero cross signal. As a result, when the frequency of the three-phase AC power from the three-phase AC power source PS changes, the change can be followed. That is, it can cope with fluctuations in the input waveform and can follow up according to the period of the input waveform.

  Next, the configuration in the PLL circuit 13 will be described with reference to FIG. FIG. 9 is a diagram illustrating a configuration of the PLL circuit 13.

  The PLL circuit 13 includes an oscillator 13a, a first frequency divider 13b, a second frequency divider 13c, a phase comparator 13d, and a generator 13e.

  The oscillating unit 13a oscillates at a frequency corresponding to a reference signal (for example, a zero cross signal) to generate a carrier clock. The oscillating unit 13a outputs the generated carrier clock to the first frequency dividing unit 13b and to the sawtooth wave generator 54 of the carrier generating unit 5b.

  As a result, as shown in FIG. 10, in the sawtooth generator 54 of the carrier generator 5b, the down counter 54a decrements the count value from the initial value in synchronization with the carrier clock, and carries over. When this occurs, a count operation is performed to return the count value to the initial value. The down counter 54a generates the sawtooth wave 1 as shown in FIG. 11 by repeating such a counting operation in synchronization with the carrier clock. That is, the period of the sawtooth wave 1 can be set to a constant value (that is, the switching period T shown in FIG. 11) corresponding to the upper limit of the count value of the down counter 54a.

  Similarly, in the sawtooth wave generator 54 of the carrier generator 5b, the up counter 54b increments the count value from the initial value in synchronization with the carrier clock, and when the carryover occurs, the count value is increased. A count operation is performed to return to the initial value. The up counter 54b generates such a sawtooth wave 2 as shown in FIG. 11 by repeating such a counting operation in synchronization with the carrier clock. That is, the period of the sawtooth wave 2 can be set to a constant value (that is, the switching period T shown in FIG. 11) corresponding to the upper limit of the count value of the up counter 54b.

The first frequency dividing unit 13b shown in FIG. 9 divides the carrier clock by M (for example, M = 2 ^N , N is a positive integer) and sets the six sections I, where M is a positive integer. A period cycle clock corresponding to .about.VI (for example, having a period equal to the period of each of the six sections I to VI) is generated. For example, the first frequency divider 13b includes a frequency divider 13b1 and a frequency divider 13b2.

For example, P, and Q is a positive integer, when the N = P + Q, the frequency divider 13b1 is the carrier clock by ^{2 P} division, the period of the carrier (i.e., the switching period T shown in FIG. 11) A corresponding carrier cycle clock (for example, having a cycle equal to the carrier cycle) is generated. Divider 13b2 is a carrier cycle clock by 2 ^Q divider, corresponding to the six sections I through Vl (e.g., six sections with each period and equal cycle of I through Vl) interval period clock Generate.

  That is, the integer P corresponds to the decrement count in the down counter 54a (see FIG. 10) and the increment count in the up counter 54b (see FIG. 10). The integer Q corresponds to the number of carriers that fit in each of the six sections I to VI (see FIG. 11).

The frequency divider 13b2 of the first frequency divider 13b outputs the generated interval clock to the second frequency divider 13c. At the same time, the frequency divider 13b2 of the first frequency divider 13b outputs the carrier cycle clock, the intermediate frequency divided clock, and the interval cycle clock to the control signal generator 14b of the estimation unit 14. The halfway divided clock may include frequency-divided clocks in a plurality of stages when the carrier cycle clock is repeatedly divided by two to generate the interval cycle clock. For example, R, when the the Q positive integer less than S, the middle division clock, a dividing clock that the carrier period clock to 2 ^{Q over R} divider, and the carrier cycle clocks 2 ^{Q over S-divider} min And a peripheral clock.

  The second frequency divider 13c divides the interval cycle clock by 6 and corresponds to the cycle of the three-phase AC power from the three-phase AC power source PS (for example, has a cycle equal to the cycle of the three-phase AC power). ) Generate a tracking signal. For example, the second frequency divider 13c includes a 6-frequency divider 13c1. The 6-frequency divider 13c1 divides the interval cycle clock by 6 to generate a follow-up signal. For example, each period of the six sections I to VI is obtained by dividing one period of the phase voltage into six equal parts. Therefore, by dividing the section period clock by six, the period of the tracking signal can be changed from the phase AC power supply PS. It can correspond to the cycle of the phase voltage in the three-phase AC power.

  For example, as shown in FIG. 12, the 6-frequency divider 13c1 includes a first frequency-divided clock obtained by dividing the interval cycle clock by 2, and a second frequency-divided clock obtained by dividing the first frequency-divided clock by 2. Then, a third divided clock (following signal) obtained by dividing the second divided clock by two is generated.

  For example, the 6-frequency divider 13c1 shown in FIG. 9 receives the interval cycle clock from the frequency divider 13b2. The 6-frequency divider 13c1 divides the interval cycle clock by 2 to generate a first divided clock. The 6-frequency divider 13c1 further divides the generated first frequency-divided clock by 2 to generate a second frequency-divided clock. The 6-frequency divider 13c1 further divides the generated second divided clock by two to generate a third divided clock. At this time, the 6-frequency divider 13c1 can recognize the timing tc for returning from the section VI to the section I based on the rising timing of the second frequency-divided clock. That is, the 6-frequency divider 13c1 resets the levels of the first frequency-divided clock, the second frequency-divided clock, and the third frequency-divided clock at the timing tc shown in FIG. For example, at the timing tc, the broken line level shown in FIG. 12 is reset to the solid line level. Thereby, since the period of the third frequency-divided clock is 6 clocks of the section cycle clock, the third frequency-divided clock can be a follow-up signal obtained by dividing the section-cycle clock by 6.

  The sixth frequency divider 13c1 of the second frequency divider 13c outputs the generated third frequency-divided clock (following signal) to the phase comparator 13d. At the same time, the 6-frequency divider 13c1 of the second frequency divider 13c receives the first frequency-divided clock, the second frequency-divided clock, and the third frequency-divided clock (follow-up signal) as a control signal for the estimation unit 14. Output to the generator 14b.

  The control signal generator 14b of the estimation unit 14 receives the carrier cycle clock, the midway division clock, and the interval cycle clock from the divider 13b2 of the first divider 13b, and receives the first divided clock and the second divided clock. The frequency-divided clock and the third frequency-divided clock (follow-up signal) are received from the 6-frequency divider 13c1 of the second frequency divider 13c. The control signal generator 14b determines which of the six sections I to VI is the current section according to the combination of the first divided clock, the second divided clock, and the third divided clock. presume. Further, the control signal generator 14b determines which time position the current timing is in the current section (that is, the position on the horizontal axis in FIG. 5) according to the combination of the carrier period clock, the halfway divided clock, and the section period clock. It is estimated whether it is in. Then, the control signal generator 14b estimates the voltage of each phase as shown in FIG. 5 according to the estimation result.

  For example, the control signal generator 14b generates first data indicating the current section by collecting the bit values of the first divided clock, the second divided clock, and the third divided clock. The control signal generator 14b generates second data indicating the current timing by combining the bit values of the carrier clock, the halfway divided clock, and the interval cycle clock. The control signal generator 14b combines the first data and the second data to generate time position data. Then, the control signal generator 14b refers to the sine wave data stored in the ROM 14a, identifies the normalized amplitude of each phase corresponding to the generated time position data, and determines the normalized amplitude of each identified phase. It is assumed that the voltage of each phase is estimated.

  The phase comparison unit 13d receives a reference signal (for example, a zero cross signal) from the zero cross detection unit 12, and receives a follow-up signal from the second frequency division unit 13c. The phase comparison unit 13d compares the phase of the reference signal and the phase of the tracking signal, and generates a phase error signal corresponding to the comparison result. The phase comparison unit 13d includes, for example, a phase difference detector 13d1. The phase difference detector 13d1 detects a phase difference between the phase of the reference signal and the phase of the tracking signal, and generates a phase error signal according to the detected phase difference. The phase comparison unit 13d outputs the generated phase error signal to the generation unit 13e.

  The generation unit 13e receives the phase error signal from the phase comparison unit 13d. The generation unit 13e generates an oscillation control signal according to the phase error signal. For example, when the phase error signal indicates that the follow-up signal has a leading phase compared to the reference signal, the generation unit 13e generates the oscillation control signal so that the frequency of the carrier clock is increased. For example, when the phase error signal indicates that the follow-up signal has a delayed phase compared to the reference signal, the generation unit 13e generates the oscillation control signal so that the frequency of the carrier clock is lowered. For example, the generation unit 13e includes a filter 13e1. For example, the filter 13e1 generates an oscillation control signal by performing a low-pass filter process on the phase error signal. The generation unit 13e outputs the generated oscillation control signal to the oscillation unit 13a.

  Thereby, the oscillation unit 13a oscillates at a frequency corresponding to the reference signal based on the oscillation control signal. For example, the oscillator 13a includes an oscillator 13a1 and a frequency divider 13a2. The oscillator 13a1 oscillates at a frequency corresponding to the oscillation control signal and generates an internal clock. The oscillator 13a1 outputs the generated internal clock to the frequency divider 13a2. The frequency divider 13a2 divides the internal clock (for example, divides it by 2) to generate a carrier clock.

  In the PLL circuit 13, a phase locked loop including a phase difference detector 13d1, a filter 13e1, an oscillator 13a1, a frequency divider 13a2, a frequency divider 13b1, a frequency divider 13b, and a 6 frequency divider 13c1 is formed. When the phase of the signal coincides with the phase of the tracking signal, the phase relationship between the two is locked. That is, the phase of the reference signal (zero cross signal) corresponding to the three-phase AC power from the three-phase AC power supply PS and the tracking signal generated internally corresponding to the carrier clock are synchronized. As a result, when the frequency of the three-phase AC power from the three-phase AC power source PS changes, the change can be followed. That is, it can cope with fluctuations in the input waveform and can follow up according to the period of the input waveform.

In response to this, the PLL circuit 13 generates a carrier clock having a frequency obtained by multiplying the frequency of the phase voltage by an integer multiple of 6. That is, by configuring the PLL circuit 13, it is possible to synchronize the cycle of the carrier used for switching control and each cycle of the six sections I to VI while using a sine wave phase voltage without distortion (FIG. 11). reference).
Next, the mounting form of the PLL circuit 13 will be examined.

  In the present embodiment, the introduction of the PLL circuit 13 to the control unit 11 is proposed as a solution to the above problem. As a candidate for the PLL circuit 13, for example, an analog PLL circuit as shown in FIG. In the analog PLL circuit shown in FIG. 23, a phase difference between a reference signal and a follow-up signal generated by the PLL circuit is detected by a phase difference detector, low-pass filter processing is performed by an analog filter, and then a VCO (voltage control) is performed. This is a circuit that divides the clock output and feeds back as a tracking signal. The tracking signal always operates to synchronize with the reference signal. Since the analog PLL circuit is configured by combining discrete parts, the cost is likely to increase and integration is also difficult.

  On the other hand, as another candidate of the PLL circuit 13, for example, an ADPLL (fully digital PLL) as shown in FIG. In the ADPLL circuit shown in FIG. 24, compared to the analog PLL circuit shown in FIG. 23, the analog filter and the VCO are replaced with a digital filter and a DCO (digitally controlled oscillator), respectively, and the phase difference detector is also configured with a digital circuit. . An ADPLL (fully digital PLL) circuit can be integrated and improved in accuracy at high frequencies.

  However, although the ADPLL circuit uses a DCO as an oscillator, coils, capacitors, and resistors, which are components of oscillation, are generated by LSI microfabrication technology. Therefore, the ADPLL circuit as shown in FIG. 24 has a problem that the ADPLL circuit is limited to an application that is developed for a circuit with a predetermined purpose (such as a radio oscillation circuit) at a large cost.

  Therefore, in the present embodiment, a three-phase rectifier method is proposed, and an ADPLL circuit as an implementation technology thereof can be created at a very low cost, and a PLL circuit 13 that can be configured by a general-purpose LSI (FPGA, gate array, etc.) is provided. To do.

  Next, a mounting form when the PLL circuit 13 is mounted as a complete digital PLL will be described.

  As the oscillator 13a1 shown in FIG. 9, an oscillator capable of generating a clock having an arbitrary frequency is required. That is, in order to configure a PLL circuit, an oscillator whose frequency can be controlled is required. In ordinary devices, there are many digital devices that can obtain a single high-frequency clock, but there are no digital devices that can use an oscillator whose frequency can be controlled. The original oscillator 30 is assumed to be a digital type device which can obtain a single frequency clock obtained by a normal device.

The clock reasoner 37 described the clock later (refer to FIG. 15), ¹ / 2,1 / ^{2 2} of the original frequency, 1/2 3, · · · · 1/2 ^k, fractionated on a clock group (Fig. 13). In addition, this classification clock group is characterized in that the timing does not overlap (see FIG. 14). Thus, clocks having different frequencies can be obtained by addition in the OR circuit (for example, in the clock synthesizer 26 shown in FIG. 18). Therefore, for example, it is possible to obtain a clock having a frequency proportional to the amount of process such as input current and output voltage, or to generate a clock having a frequency based on predetermined data.

  The phase difference detector 13d1 shown in FIG. 9 is configured to generate the next signal with a simple gate circuit. For example, the phase difference detector 13d1 is a signal for detecting the occurrence of phase mismatch between the reference signal and the tracking signal, a signal for determining the phase lag and phase advance between the reference signal and the tracking signal, and the phase mismatch between the reference signal and the tracking signal. It is configured to generate a signal or the like.

The filter 13e1 shown in FIG. 9 requires the characteristics of a low-pass filter and is configured to have the characteristics represented by the following equation (1), for example.
K (1 + ST) / ST = K / ST + K (1)

  In equation (1), T is an integral constant, and K is a proportionality constant. The first term in equation (1) means an integral operation, and the second term means a proportional operation. The integration operation can be realized by an up / down counter without reset, and the proportional operation can be realized by an up / down counter that resets every sample. The phase delay and advance correspond to the counter up and down operations. A clock is input to the counter during the phase mismatch period. The frequency of the input clock to the counter determines the integration time and the proportionality constant. This method will be described later. Equation (1) is obtained by adding both outputs.

  The output of the filter 13e1 configured in this way becomes frequency adjustment data. When this is input to the clock synthesizer in the oscillator 13a1, a clock having an adjusted frequency is obtained.

  The frequency dividers 13a2, 13b1, and 13b2 can be configured with counters, for example. Further, the 6-frequency divider 13c1 can be configured with a counter, for example.

  As described above, the complete digital PLL can be constituted by a general-purpose digital LSI (FPGA, gate array, etc.), and an inexpensive PLL circuit can be obtained.

  Next, a mounting form when the PLL circuit 13 is mounted as a complete digital PLL will be described more specifically.

The clock classifier 37 shown in FIG. 15 receives the original oscillation clock 31 from the original oscillator 30. Clock fractionator 37, the oscillation clock 31, ¹ / 2,1 / ^{2 2} of the original frequency, 1/2 3, fractionating the · · · · 1/2 ^k, the clock group.

For example, in the clock discriminator 37, when the counter 32 uses the counter output as the data input of the DFF 33 and is latched in each DFF 33 by the clock that is in reverse phase to the original oscillation clock 31 by the NOT circuit 35, the output of each DFF 33 is The clock is shifted by half a cycle with respect to the input of the counter 32. When an AND operation is performed on the output of the counter 32 and the inverted output of the DFF 33 by the AND circuit 34, a predetermined clock can be extracted from the original oscillation clock 31 in synchronization with the rising of the output of the counter 32 (see FIG. 13). Since the output of the counter 32 is an output in which the frequency is 1/2 ⁿ (n = 1, 2,..., K) times the frequency f0 of the original oscillation clock 31, the pulse is f0 / 2 ⁿ ( A plurality of pulses 36-1 to 36-k (clock group) having a frequency of n = 1, 2,..., k) can be obtained (see FIG. 14). As an example, FIG. 14 shows the case of a 4-bit counter. The simplified diagram is shown in FIG.

  The clock synthesizer 26 shown in FIG. 17 selects and selects a pulse corresponding to the oscillation control signals 22-1 to 22-k from among the plurality of pulses 36-1 to 36-k separated by the clock separator 37. The internal pulse 25 is generated by synthesizing the generated pulses.

  For example, in the clock synthesizer 26, a plurality of pulses 36-1 to 36-k (clock group) output from the clock discriminator 37 and oscillation control signals (frequency designation data) 22-1 to 22 for designating a pulse to be selected. -K is ANDed by AND circuits 23-1 to 23-k, and then ORed by OR circuit 24, whereby an output of a specified frequency, that is, internal clock 25 can be obtained (see FIG. 14). . FIG. 14 shows an example in which the plurality of pulses 36-1 to 36-k are 4 bits and the designated data is 10 (binary 1010). A simplified diagram is shown in FIG.

  Next, an example of a circuit configuration when the PLL circuit 13 is mounted as a complete digital PLL will be described with reference to FIG. FIG. 19 is a diagram showing a circuit configuration example when the PLL circuit 13 is mounted as a complete digital PLL.

  A clock group 193 is generated by the clock separator 192 for the original oscillation clock 191. The clock separator 192 corresponds to the clock separator 37 (see FIG. 15).

  In the phase difference detector 153, the OR operation is performed on the reference signal 141 and the follow-up signal 142 by the OR circuit 143, and the rising edge is set as a pulse for occurrence of phase mismatch (phase difference calculation start) at the monoste 144. On the other hand, if the follow-up signal 142 is input to the data input of the DFF 146 and the reference signal 141 is the clock input as the determination of delay or advance, the follow-up signal advances when the output of the DFF 146 is H, and the output of the DFF 146 is L It can be determined that the tracking signal is delayed.

  When the follow-up signal is advanced as the signal of the phase mismatch period, the AND circuit 149 calculates the AND of the reference signal 141, the follow-up signal 142 inverted by the NOT circuit 147, and the positive output signal of the DFF 146. . When the follow-up signal is delayed, the AND circuit 150 calculates an AND of the reference signal 141 inverted by the NOT circuit 148, the follow-up signal 142, and the negative output signal of the DFF 146. The OR circuit 151 performs an OR operation on the output of the AND circuit 149 and the output of the AND circuit 150, and outputs the signal 152 during the phase mismatch period from the OR circuit 151.

  In the filter 173, the up / down counter 161 is an up / down counter with a reset function for the second term calculation of the above equation (1). In the up / down counter 161, the output pulse of the monoste 144 of the phase difference detector 153 is input to the CL terminal and reset. In the up / down counter 161, the advance / delay output signal of the DFF 146 is input to the U / D terminal to determine the polarity of the count operation (whether to increment or decrement). In the up / down counter 161, the phase mismatch period signal 152 is input to the CE terminal.

  The resolution and gain of K in equation (1) vary depending on the number of stages of the up / down counter 161 with reset and the frequency of the input clock. The synthesized frequency signal 172 is obtained by the P clock synthesizer 171 from the output of the original oscillation classification clock group 169 (193) and the frequency designation data 170 set in advance from the calculation, and used as the clock input of the up / down counter 161. The P clock synthesizer 171 corresponds to the clock synthesizer 26 (see FIG. 17). The output of the up / down converter 161 with reset is calculated for the calculation result proportional to the phase difference for each cycle of the input signal. The gain can be adjusted by the frequency designation data 170.

  The up / down counter 162 is an up / down counter for the first term calculation of the above equation (1). In the up / down counter 162, the advance / delay output signal 146 of the phase difference detector 153 is input to the U / D terminal to determine the polarity of the count operation (whether to perform increment or decrement). In the up / down counter 162, the phase mismatch signal 152 is input to the CE terminal.

  The resolution and gain of K / T in the first term of equation (1) vary depending on the number of stages of the up / down counter 162 and the frequency of the input clock. The synthesized frequency signal 168 is obtained by the I clock synthesizer 167 from the output of the original oscillation classification clock group 165 (193) and the frequency designation data 166 set in advance, and used as the clock input of the up / down counter 162. The I clock synthesizer 167 corresponds to the clock synthesizer 26 (see FIG. 17). Since the addition is performed without resetting every cycle of the input signal, the up / down counter 162 calculates the calculation result of the integration. The gain can be adjusted by the frequency designation data 166. The calculation result of the adder 163 becomes frequency control data 164.

  In the oscillator 184, the original oscillation classification clock group 181 (193) and the frequency control data 164 from the filter 173 are input to the clock synthesizer 182, and a frequency output (internal clock) 183 proportional to the frequency control data 164 is obtained. The clock synthesizer 182 corresponds to the clock synthesizer 26 (see FIG. 17).

  The frequency output 183 is divided by the frequency divider 195 to generate the tracking signal 142.

  In the PLL circuit 13 shown in FIG. 19, the phase difference detector 153 calculates a phase mismatch generation pulse, advance / delay determination, and phase mismatch continuation signal from the reference signal 141 and the follow-up signal 142.

  The filter 173 is an up / down counter 161 that resets the counter internal data by the phase coincidence generation pulse, advances only during the phase mismatch period, and performs an up operation and a down operation in response to the delay signal. Calculate the two terms. The gain is adjusted by changing the speed of counting by counting with the output clock of the P clock synthesizer 171 according to the frequency designation data.

  The up / down counter 162 performs the up operation and the down operation corresponding to the advance / delay signal only during the phase mismatch period, and calculates the first term of the equation (1). Since this operation does not include an intermediate reset operation, it functions as an integration operation. The integral constant gain is adjusted by changing the speed of counting by counting with the output clock of the I clock synthesizer 167 according to the frequency designation data.

  The output of the up / down counter 161 and the output of the up / down counter 162 are added by the adder 163, and the calculation of the expression (1) can be performed.

  The oscillator 184 calculates the frequency adjustment data 164 that is the calculation output of the expression (1) and the data 181 of the classification clock group by the clock synthesizer 182 to obtain the frequency output 183.

  A frequency divider 195 divides the frequency output 183 to generate a follow-up signal 142.

  In this system, as in a normal PLL circuit, the frequency is increased or decreased according to the delay or advance of the tracking signal, so that the tracking signal and the reference signal are synchronized.

  In this way, by introducing the PLL circuit 13 to the three-phase rectifier 1, a sine wave without distortion can be used as the control of the three-phase rectifier 1 without using phase voltages of R, S, and T phases. The period and each period of the six sections can be synchronized. As a result, it is possible to perform modulation exactly as theoretically, and to obtain a precise and stable waveform.

  Further, by configuring the PLL circuit 13 as a complete digital PLL as described above, it is possible to obtain a variable frequency without using a microfabrication technique as a DCO. Accordingly, a general-purpose FPGA or gate array can be used without developing a dedicated LSI, so that the function can be achieved at a low cost. Further, since there are no analog parts, integration is easy. Furthermore, it is easy to set the gain. Further, since there is no multiplier, the logic circuit scale can be easily reduced. Thus, an inexpensive and small PLL circuit can be obtained.

  In the description of the text, the configuration of the oscillator is a configuration of a clock discriminator and a clock synthesizer so that the frequency can be generated for general purposes, but a general rate multiplier is integrated. Since the same effect can be obtained even if the number of required multi-rate mulch integrated is used, this method is also within the scope of the invention.

  As described above, in the embodiment, in the control unit 11 of the three-phase rectifier 1, the PLL circuit 13 sets the frequency of the phase voltage to 6 according to the reference signal corresponding to the three-phase AC power from the three-phase AC power supply. A carrier clock having a frequency multiplied by an integer multiple is generated. The carrier generator 5b generates a carrier in synchronization with the generated carrier clock. The switching pattern generator 5a generates the switching pattern of the bidirectional switch circuit 3 using the generated carrier. For example, since each period of the six sections I to VI is obtained by dividing one period of the phase voltage into six equal parts, the frequency of the carrier clock is obtained by multiplying the frequency of the phase voltage by an integer multiple of 6. Each period of the six sections I to VI can be an integral multiple of the period of the carrier (switching period T) generated in synchronization with the carrier clock. As a result, an integer number of carrier waveforms can be accommodated in each of the six sections I to VI (see FIG. 11). That is, the carrier period (switching period T) can be synchronized with the periods of the six sections I to VI. Therefore, since the period of each section I to VI of the phase voltage can be synchronized with the period of the carrier, distortion of the input current waveform and the DC voltage waveform can be reduced.

In the embodiment, in the PLL circuit 13, the oscillating unit 13a oscillates at a frequency according to a reference signal (for example, a zero cross signal) to generate a carrier clock. When M is an integer, the first frequency divider 13b divides the carrier clock by M (for example, 2 ^N ), and generates section period clocks corresponding to the six sections I to VI. The second frequency divider 13c divides the interval cycle clock by 6 to generate a follow-up signal. The phase comparison unit 13d compares the phase of the reference signal and the phase of the tracking signal, and outputs a phase error signal corresponding to the comparison result. The generation unit 13e generates an oscillation control signal according to the phase error signal. The oscillation unit 13a oscillates at a frequency corresponding to the reference signal based on the oscillation control signal. Thus, the PLL circuit 13 can generate a carrier clock having a frequency obtained by multiplying the frequency of the phase voltage by an integer multiple of 6 in accordance with the reference signal.

  In the embodiment, in the control unit 11, the estimation unit 14 uses the first divided clock obtained by dividing the section period clock by two and the second divided clock obtained by dividing the first divided clock by two. Then, it is estimated which of the six sections I to VI is the current section according to the combination with the third divided clock obtained by dividing the second divided clock by two. Thereby, since the voltage of each phase can be estimated in the control unit 11, the voltage of each phase in the three-phase AC power from the three-phase AC power source PS is not used as it is, and each phase close to an ideal sine wave is used. Switching control can be performed using voltage. Thereby, distortion of an input current waveform or a DC voltage waveform can be reduced.

  In the embodiment, in the PLL circuit 13, the generation unit 13 e oscillates so that the frequency of the carrier clock is increased when the phase error signal indicates that the follow-up signal is an advanced phase compared to the reference signal. When the control signal is generated and the phase error signal indicates that the follow-up signal has a delayed phase compared to the reference signal, the oscillation control signal is generated so that the frequency of the carrier clock is lowered. Thereby, the phase of a reference signal and the phase of a tracking signal can be made to correspond, and the period of each area I-VI of a phase voltage and the period of a carrier can be synchronized.

  In the embodiment, in the control unit 11, the zero cross detection unit 12 detects the zero cross timing of at least one phase voltage in the three-phase AC power, and indicates the zero cross timing of the detected phase voltage. Generate a signal. The PLL circuit 13 receives the generated zero cross signal as a reference signal. Thereby, since the PLL circuit 13 can grasp the frequency of the phase voltage based on the reference signal, a carrier clock having a frequency obtained by multiplying the frequency of the phase voltage by an integer multiple of 6 can be generated.

  In the embodiment, in the control unit 11, the carrier generation unit 5 b has counters (for example, the down counter 54 a and the up counter 54 b), and performs a count operation in synchronization with the generated carrier clock. Generate a career. Thereby, since it is easy to fit an integer number of carriers in the period of each section I to VI of the phase voltage, distortion of the input current waveform and the DC voltage waveform can be easily reduced.

In the control unit 11, the zero cross detection unit 12 may detect the timing of zero crossing of two or more phase voltages in the three-phase AC power.
Alternatively, in the control unit 11, the zero-cross detection unit 12 detects the zero-cross timing of the line voltage in the three-phase AC power, generates a zero-cross signal indicating the detected zero-cross timing of the line voltage, and delays the phase. May be. In this case, the PLL circuit 13 receives a signal corresponding to the generated zero cross signal (for example, a signal obtained by delaying the phase of the zero cross signal) as a reference signal. Also by this, the PLL circuit 13 can grasp the frequency of the phase voltage based on the reference signal, so that a carrier clock having a frequency obtained by multiplying the frequency of the phase voltage by an integer multiple of 6 can be generated.

  Alternatively, as shown in FIG. 20, in the control unit 11, the phase voltage discriminator 52 i compares the estimated voltage of each phase to discriminate between the R phase intermediate, the S phase intermediate, and the T phase intermediate, An estimation result as to which section is the current section may be received from the estimation unit 14, and the R-phase middle, S-phase middle, and T-phase middle may be determined according to the estimation result. In this case, for example, the phase voltage discriminator 52i is a table in which the section identification information for identifying the sections I to VI and the intermediate phase information indicating the intermediate phase are associated with each other as shown in FIG. Set to. When the phase voltage discriminator 52i receives the estimation result, the phase voltage discriminator 52i can discriminate between the R phase intermediate, the S phase intermediate, and the T phase intermediate by identifying the intermediate phase corresponding to the section indicated in the estimation result by referring to the table. .

  Or as shown in FIG.21 and FIG.22, the counter in the sawtooth wave generator 54j of the carrier generation part 5b may have a reset function. In this case, for example, as shown in FIG. 21, the carrier generator 5b further includes a reset signal generator 55j. The reset signal generator 55j, for example, counts the number of carrier clocks, and generates an active level reset signal when the number of clocks reaches a threshold number of clocks corresponding to the switching period T shown in FIG. In the sawtooth generator 54j, as shown in FIG. 22, the down counter 54ja and the up counter 54jb reset their count values in response to the input of the active level reset signal. Thereby, the period of the sawtooth wave 1 can be set to a constant value corresponding to the threshold clock number (that is, the switching period T shown in FIG. 11), and the period of the sawtooth wave 2 is constant corresponding to the threshold clock number. (That is, the switching period T shown in FIG. 11).

  As described above, the three-phase rectifier according to the present invention is useful for generating a DC voltage from three-phase AC power.

DESCRIPTION OF SYMBOLS 1 3 phase rectifier 3 Bidirectional switch circuit 4 Full wave rectifier circuit 5 Switching pattern generator 5a Switching pattern generation part 5b Carrier generation part 6 Drive circuit 8 Three phase reactor 9 Input capacitor 10 Capacitor 11 Control part 12 Zero cross detection part 13 PLL circuit 13a Oscillator 13b First frequency divider 13c Second frequency divider 13d Phase comparator 13e Generator 14 Estimator 14a ROM
14b Control signal generator

Claims (6)

A three-phase rectifier that converts three-phase AC power input from a three-phase AC power source into DC power,
A bidirectional switch circuit for turning ON / OFF the input of each phase from the three-phase AC power source;
A control unit that performs switching control of the bidirectional switch circuit according to six sections in which the period of the phase voltage is divided according to the magnitude relationship between the voltages of the phases in the three-phase AC power;
With
The controller is
A PLL circuit for generating a carrier clock having a frequency obtained by multiplying the frequency of the phase voltage by an integer multiple of 6 according to a reference signal corresponding to the three-phase AC power;
A carrier generating section for generating a carrier in synchronization with the generated carrier clock;
A switching pattern generator for generating a switching pattern of the bidirectional switch circuit using the generated carrier;
A three-phase rectifier characterized by comprising: The PLL circuit includes:
An oscillation unit that oscillates at a frequency according to the reference signal and generates the carrier clock;
When M is an integer, the carrier clock is divided by M, and a first frequency division unit that generates section period clocks corresponding to the six sections;
A second divider for dividing the interval period clock by 6 to generate a follow-up signal;
A phase comparator that compares the phase of the reference signal with the phase of the tracking signal and outputs a phase error signal according to the comparison result;
A generator for generating an oscillation control signal in response to the phase error signal;
Have
The three-phase rectifier according to claim 1, wherein the oscillating unit oscillates at a frequency corresponding to the reference signal based on the oscillation control signal. A first frequency-divided clock obtained by dividing the section period clock by 2, a second frequency-divided clock obtained by dividing the first frequency-divided clock by 2, and a second frequency-divided clock obtained by frequency-dividing the second frequency-divided clock by two. 3. The three-phase rectifier according to claim 2, further comprising an estimation unit configured to estimate which of the six sections is the current section in accordance with a combination of the three divided clocks. The generation unit generates the oscillation control signal so that the frequency of the carrier clock is increased when the phase error signal indicates that the follow-up signal has a leading phase compared to the reference signal, The oscillation control signal is generated so that the frequency of the carrier clock is lowered when the phase error signal indicates that the follow-up signal has a delayed phase compared to the reference signal. Or the three-phase rectifier of 3. The controller detects a zero-cross timing of a phase voltage in the three-phase AC power, and generates a zero-cross signal indicating a detected zero-cross timing of at least any one phase voltage or line voltage. In addition,
5. The three-phase rectifier according to claim 1, wherein the PLL circuit receives a signal corresponding to the generated zero-cross signal as the reference signal. 6. 6. The carrier generation unit according to claim 1, wherein the carrier generation unit includes a counter and generates the carrier by performing a counting operation in synchronization with the generated carrier clock. 3 phase rectifier.

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