JP4713525B2 - Frequency synthesizer - Google Patents

Description

  The present invention relates to a frequency synthesizer that can obtain an oscillation output of a desired frequency.

  As one of standard signal generators, there is a frequency synthesizer applying a PLL (Phase Locked Loop). As shown in FIG. 12, the frequency synthesizer divides the voltage controlled oscillator 201 into 1 / N by the frequency divider 202 and inputs the divided output to one input terminal of the phase comparator 203 and generates a reference signal. For example, the oscillation output of a crystal oscillator 204, which is a frequency divider, is frequency-divided to 1 / M by the frequency divider 200, and the frequency-divided output is input to the other input terminal of the phase comparator 203, and the comparison signal is input to the loop filter 205. Is fed back to the voltage controlled oscillator 201, thus configuring a PLL (for example, Patent Document 1). When the PLL is locked, the frequency fvco of the oscillation output of the voltage controlled oscillator 201 and the frequency f0 of the oscillation output of the crystal oscillator 204 are in a relationship of fvco / N = f0 / M, so that fvco = (N / M) f0. . Since the frequency divider 202 is constituted by a programmable counter and can set the frequency dividing ratio N by digital data from the outside, the frequency of fvco can be set freely.

  As an application of the frequency synthesizer, for example, it is used as a local oscillation unit in a mobile station. In other words, since the base station assigns a predetermined frequency band to the mobile station, the mobile station needs to generate an oscillation output of the assigned frequency band, so that the station oscillator has a function of adjusting the frequency. Is required. It is also used as a test signal source for radio communication equipment and broadcast equipment.

  In this way, for example, when applying a frequency synthesizer in the communication field, it is required to have low noise in order to avoid interference with other channels, and because radio waves are overcrowded, the frequency can be set as fine as possible Is desirable. In order to finely set the frequency, the above-described frequency division ratio N may be increased. However, if the frequency division ratio is increased too much, the delay occurring in the loop becomes longer and the noise becomes larger. .

  For this reason, if it is intended to design a frequency synthesizer that can adjust, for example, a frequency of about 1000 MHz in units of 1 Hz, the apparatus shown in FIG. 12 needs to be multistaged. That is, if the upper limit of N is 1000, a frequency synthesizer of 1 MHz to 1000 MHz that can be set in 1 MHz increments can be produced by setting the frequency (M / f0) of the reference signal entering the phase comparator to 1 MHz. Similarly, by setting the frequency of the reference signal to 1 kHz, a frequency synthesizer of 1 kHz to 1 MHz that can be set in steps of 1 kHz is produced. Similarly, by setting the frequency of the reference signal to 1 Hz, it can be set in steps of 1 Hz to 1 Hz. Produces a 1kHz frequency synthesizer. Then, by synthesizing each frequency synthesizer stepwise, a frequency synthesizer that can be set up to 1000 MHz in 1 Hz increments is obtained.

  However, if this is done, a PLL must be assembled for each synthesis circuit that synthesizes the frequency, and there is a problem that the circuit configuration is complicated, the number of parts increases, and noise increases.

  Therefore, the present inventor has developed a new type of frequency synthesizer that can set the frequency finely over a wide band by adopting a new configuration that is completely different in principle from the conventional frequency synthesizer. However, there is a problem that the pull-in range of the frequency is narrow and the pull-in cannot be performed reliably considering the variation of the voltage controlled oscillator product and the temperature characteristics, etc., and it is necessary to overcome this point for practical use. is there. This frequency synthesizer is composed of an analog circuit and a digital circuit, but there is also a problem that noise based on simultaneous switching of a large number of switching elements in the digital / analog conversion section must be suppressed.

Japanese Patent Laid-Open No. 2004-274673

  The present invention is a frequency synthesizer capable of finely setting frequencies over a wide band and obtaining a low-noise frequency signal by adopting a novel configuration that is completely different in principle from a conventional frequency synthesizer. Thus, it is an object of the present invention to provide a technique capable of widening the frequency pull-in range and a technique capable of suppressing noise based on simultaneous switching of a large number of switching elements in a digital / analog conversion unit.

The frequency synthesizer of the present invention includes a voltage controlled oscillation unit that oscillates a frequency signal having a frequency according to a supplied voltage,
Frequency dividing means for dividing the frequency signal into 1 / N (N is an integer) according to the set frequency of the voltage controlled oscillation unit;
An analog / digital converter that samples a sine wave signal having a frequency corresponding to 1 / N of the output frequency of the voltage-controlled oscillator based on a reference clock signal and outputs the sampled value as a digital signal;
The frequency signal corresponding to the output signal from the analog / digital converter is subjected to quadrature detection using a digital signal of a sine wave signal having a frequency of ω0 / 2π, and the frequency difference between the frequency signal and ω0 / 2π is detected. Vector extracting means for extracting a real part and an imaginary part when a vector rotating at a frequency corresponding to
A parameter output unit for calculating the frequency of the vector when the output frequency of the voltage controlled oscillation unit reaches a set value;
A frequency difference extracting means for extracting a difference between the frequency of the vector and the frequency calculated by the parameter output unit;
Means for integrating a voltage signal corresponding to the frequency difference extracted by the frequency difference extracting means and feeding it back to the voltage controlled oscillator as a control voltage via a digital / analog converter;
A) At the start of the operation of the apparatus, while the voltage signal cannot be obtained from the frequency difference extracting means due to the output frequency from the voltage controlled oscillation unit being too small, the first constant is integrated by the integrating circuit unit. The voltage for raising is output as the control voltage of the voltage controlled oscillator,
B) After the PLL is locked, when the control voltage from the means for returning deviates from a preset range, a second constant set smaller than the first constant is set so as to fall within the range. Output the frequency pull-in voltage integrated by the integration circuit ,
C) Frequency pulling means for stopping the integration operation after the control voltage from the feedback means falls within a preset range, and
The control voltage of the voltage controlled oscillating unit is an added value of the control voltage from the feedback means and the control voltage from the frequency pulling means,
A PLL is formed by the voltage controlled oscillation unit, the vector extracting unit, and the feedback unit that feeds back the voltage signal to the voltage controlled oscillation unit. When the PLL is locked, the output frequency of the voltage controlled oscillation unit is adjusted to the set frequency. It is characterized by that.

A frequency synthesizer according to another invention includes a voltage-controlled oscillator that oscillates a frequency signal having a frequency corresponding to a supplied voltage,
Frequency dividing means for dividing the frequency signal into 1 / N (N is an integer) according to the set frequency of the voltage controlled oscillation unit;
An analog / digital converter that samples a sine wave signal having a frequency corresponding to 1 / N of the output frequency of the voltage-controlled oscillator based on a reference clock signal and outputs the sampled value as a digital signal;
The frequency signal corresponding to the output signal from the analog / digital converter is subjected to quadrature detection using a digital signal of a sine wave signal having a frequency of ω0 / 2π, and the frequency difference between the frequency signal and ω0 / 2π is detected. Vector extracting means for extracting a real part and an imaginary part when a vector rotating at a frequency corresponding to
A parameter output unit for calculating the frequency of the vector when the output frequency of the voltage controlled oscillation unit reaches a set value;
A frequency difference extracting means for extracting a difference between the frequency of the vector and the frequency calculated by the parameter output unit;
Means for integrating a voltage signal corresponding to the frequency difference extracted by the frequency difference extracting means and feeding it back to the voltage controlled oscillator as a control voltage via a digital / analog converter;
A frequency pulling means,
The frequency pulling means is
A) At the start of operation of the apparatus, while the voltage signal cannot be obtained from the frequency difference extracting means due to the output frequency from the voltage controlled oscillator being too small , the voltage for starting up is controlled by the voltage controlled oscillator. Output as voltage,
B) After the voltage signal is output from the frequency difference extracting means, the voltage signal is integrated by the integrating circuit section and converted into an analog signal at a frequency step larger than that of the feedback means, and this analog signal is converted into the voltage controlled oscillator section. Output as control voltage,
C) After the frequency difference between the set frequency and the output frequency from the voltage controlled oscillation unit falls within a preset range, the integration operation of the integration circuit unit is stopped, and the control voltage from the frequency pulling means is A fixed value,
D) In order to reduce glitch noise by reducing simultaneous switching of the digital / analog converter in the feedback means, the fixed value is output within a control voltage that can be set by the digital / analog converter in the frequency pull-in means. The frequency is set to a value that deviates from the control voltage closest to the set frequency by an amount corresponding to an integral multiple of the adjustable frequency increment.
A PLL is formed by the voltage controlled oscillation unit, the vector extracting unit, and a feedback unit that feeds back the voltage signal to the voltage controlled oscillation unit. When the PLL is locked, the output frequency of the voltage controlled oscillation unit is adjusted to a set frequency. ,
The control voltage of the voltage controlled oscillator is an added value of the control voltage from the feedback means and the control voltage from the frequency pulling means.

The frequency dividing means includes a case where N = 1. In this case, the frequency divider is not used in an actual device, and the conduction between the output terminal of the voltage controlled oscillation unit and the input terminal of the analog / digital conversion unit. The road corresponds to the frequency dividing means in the present invention. Thus, in the present invention, in order to make the description of the scope of claims easy to understand, a configuration of frequency dividing means is described even when N = 1.
In order to set the control voltage of the voltage controlled oscillating unit as the sum of the control voltage from the feedback means and the control voltage from the frequency pulling means, the control voltage from the feedback means and the frequency pulling means from It can be configured to include a coupler for adding the control voltage and supplying the sum to the voltage controlled oscillator.

  Alternatively, the voltage-controlled oscillation unit may include a port to which a control voltage from the feedback unit and a control voltage from the frequency pulling unit are input.

  As a preferred aspect of the present invention, for example, the parameter output unit is configured to use a frequency of the reference clock signal used in the analog / digital conversion unit and a vector extraction unit when the set value of the output frequency of the voltage controlled oscillation unit is divided by N. An example can be given in which the value of N that is the frequency closest to the difference from ω0 / 2π used is calculated, and the frequency dividing means uses this value to divide the frequency signal from the voltage controlled oscillator.

Further, according to a preferred aspect of the present invention, the parameter output unit outputs the vector when the output frequency of the voltage controlled oscillation unit reaches a set value out of the frequency that is an integral multiple of the frequency increment fa for coarse adjustment. When the output frequency of the voltage controlled oscillation unit becomes a set value among the frequency n · fa (n is an integer) closest to the frequency and an integer multiple of the frequency step fb for fine adjustment smaller than the frequency step fa A frequency m · fb (m is an integer) closest to the difference between the frequency of the vector and the frequency n · fa;
The frequency difference extraction means multiplies the vector obtained by the vector extraction means by an inverse vector that rotates in reverse at a frequency n · fa, and subtracts the frequency of the inverse vector from the frequency of the vector. Means for taking out the frequency of the slow vector, a slow speed detecting means for the slow vector obtained from the values of the real part and imaginary part at the time of each sampling of the slow vector, and the frequency of the slow vector detected by the slow speed detecting means, And a means for outputting a signal corresponding to the difference between the frequency m · fb.

In this case, the frequency of the slow vector is preferably low enough that the phase θ on the complex plane representing the vector can be regarded as sin θ and the frequency can be obtained by approximate calculation.
In addition, the slow speed detection means for the slow vector is a position on the complex plane determined by the real part and the imaginary part of the slow vector at a certain sampling, and a position on the complex plane determined by the real part and the imaginary part of the slow vector at the next sampling. And a means for considering the calculated value as the phase difference of the slow vector at the time of both samplings.

The means for feeding back the voltage signal corresponding to the frequency difference to the voltage-controlled oscillator includes, for example, means for accumulating a signal corresponding to the difference between the frequency of the slow vector and the frequency m · fb.
The inverse vector includes a data table in which a set of a real part and an imaginary part defining the position of the inverse vector on the complex surface is arranged in order along the rotation direction, and an increment number corresponding to the rotation direction and frequency of the inverse vector, or It can be generated by means for generating the address of the data table according to the decrement number.

The frequency synthesizer of the present invention is a completely different method from the conventional method in which the frequency adjustment unit (how many frequencies can be adjusted) is left to the frequency divider ratio. That is,
I. A quadrature detection is performed on the sine wave signal of the output frequency of the voltage controlled oscillator, and a vector that rotates at the frequency (speed) of the difference from the frequency of the frequency signal used for detection is created.
B. Calculate in advance the frequency of the vector when the output frequency of the voltage-controlled oscillator reaches the set value,
C. When the voltage-controlled oscillator is driven, a voltage signal corresponding to the difference between the vector frequency and the calculated frequency is fed back to the voltage-controlled oscillator, and the PLL is formed so that the difference becomes zero. .
Therefore, when the PLL is locked, the output frequency of the voltage controlled oscillator is adjusted to the set frequency, but the vector frequency when the output frequency of the voltage controlled oscillator reaches the set value is calculated in advance. It is possible to set the output frequency just by setting the output frequency in a so-called PLL, so that the frequency can be set finely over a wide band with less noise. For example, a voltage controlled oscillator of several hundred MHz can be set in units of, for example, 1 Hz or less, and a very innovative frequency synthesizer can be obtained.

In the present invention, while the output frequency from the voltage controlled oscillator is small and there is a large difference with respect to the set frequency, the first constant is integrated by the integrating circuit and output as the control voltage of the voltage controlled oscillator. This increases the output frequency. In addition, after the PLL is locked, the control voltage from the feedback means is monitored, and when the control voltage deviates from a preset range, a frequency pull-in voltage is output so that the control voltage falls within the range. Yes. Thus a wide capture range of frequencies, or there are variations in the frequency of the voltage controlled oscillator, it is possible to perform the pull-in frequency even when the frequency is changed due to temperature characteristics, stable operation can be obtained.

  In the second invention, since the probability of switching near the center value in the digital / analog converter of the feedback means for fine adjustment is reduced, the number of switches that are simultaneously switched is reduced, and glitch noise is reduced. Can do.

  Since the frequency synthesizer of the present invention operates based on a novel principle, first, an outline of the operation principle of the present invention will be briefly described with reference to FIG. In FIG. 1, reference numeral 1 denotes a voltage controlled oscillator which is a voltage controlled oscillator, and outputs a frequency signal which is a rectangular wave having a frequency corresponding to the supply voltage from the voltage output unit 11 via the first addition unit 12. The frequency signal from the voltage controlled oscillator 1 is frequency-divided to 1 / N (N is an integer) by the frequency dividing means 2, further converted into a sine wave, and converted into a digital signal. 20, the explanation is that the vector rotating at the frequency (speed) corresponding to the frequency of the frequency signal is extracted.

  The frequency difference extracting means 30 following the vector extracting means 20 extracts the difference between the vector frequency and the vector frequency fr when the output frequency of the voltage controlled oscillator 1 reaches the set frequency. As a technique for extracting the frequency difference, for example, an inverse vector that rotates at a frequency fr in the direction opposite to the rotation direction of the vector extracted by the vector extracting means 20 when the output frequency of the voltage controlled oscillator 1 reaches the set frequency is created. In addition, there is a method of extracting the frequency difference by multiplying the vector and the inverse vector.

  Alternatively, the vector frequency may be reduced to some extent by using an inverse vector, and the remaining frequency difference may be detected by an approximate expression, for example, the vector speed. As a more specific example, such an adjustment that adjusts the frequency of the vector to fr (adjustment step for extracting the frequency difference by the frequency difference extracting means 30) is divided into rough adjustment and fine adjustment. A frequency n · fa (n is an integer) that is closest to the frequency of the vector when the output frequency of the voltage controlled oscillator 1 reaches a set value among the frequencies that are integral multiples of the frequency increment fa for coarse adjustment. The vector is multiplied by an inverse vector that reversely rotates at the frequency n · fa, and a slow vector having a frequency obtained by subtracting the frequency of the inverse vector from the frequency of the vector is extracted. Of the integer multiples of the frequency step fb for fine adjustment smaller than the frequency step fa, the frequency m · fb (m is an integer) closest to the difference between fr and the frequency n · fa is calculated. The difference between the frequency of the slow vector and the frequency m · fb is extracted, and the difference between the frequency of the vector obtained by the vector extracting means and fr is obtained.

  The above series of calculations is performed by a parameter output unit (not shown). When the adjustment process for extracting the frequency difference is divided into rough adjustment and fine adjustment in this way, there is an advantage that an accurate frequency difference can be obtained when the vector frequency approaches fr, There is an advantage that the calculation becomes simple. This point will be clarified by a specific example of FIG. 2 described later.

  Then, the voltage corresponding to the frequency difference extracted by the frequency difference extracting means 30 is integrated by the integrating means 40 forming a part of the feedback means and supplied to the input side of the voltage controlled oscillator 1. Accordingly, the loop of FIG. 1 forms a PLL. When the frequency difference becomes zero, the PLL is locked, and the output frequency of the voltage controlled oscillator 1 is locked to the set frequency.

By the way, when the frequency difference is large, generally, a voltage sufficient to operate the vector extraction means 20 or the frequency difference extraction means 30 for performing digital processing cannot be obtained. In other words, the output of the voltage controlled oscillator 1 Since the frequency is small, the control voltage to the voltage controlled oscillator 1 cannot be obtained. For this reason, at the beginning of operation, a control voltage is generated from the integration circuit section in the frequency pulling means 100 to raise the output frequency of the voltage controlled oscillator 1. Then, after entering the PLL control range, the integration operation of the integration circuit section in the frequency pull-in means 100 is stopped.
More specifically, first, when the voltage controlled oscillator 1 is started, a control voltage is supplied from the frequency pull-in means 100 to the voltage controlled oscillator 1 through the coupler 11, for example, and the control voltage is gradually increased. Along with this, when the output frequency of the voltage controlled oscillator 1 rises and the vector extraction means 20 and the frequency difference extraction means 30 start to function, the frequency of the vector extracted by the vector extraction means 20 increases. When this frequency enters the PLL control range, the vector frequency fr calculated when the output frequency of the voltage controlled oscillator 1 reaches the set frequency and the vector extracted by the vector extracting means 20 are calculated. The difference (frequency difference) with the frequency of becomes smaller.
Therefore, the control voltage from the frequency pulling means 100 is stopped from increasing to a fixed value, and a voltage corresponding to the frequency difference is integrated and applied to the voltage controlled oscillator 1 as a control voltage. As a result, the rate of increase of the output frequency of the voltage controlled oscillator 1 is also reduced, and the rate of increase of the integrated value of the frequency difference is gradually reduced. For this reason, the way of increasing the output frequency of the voltage controlled oscillator 1 becomes more gradual, and accordingly, the way of raising the integrated value of the voltage corresponding to the frequency difference becomes more gradual. Eventually, the output frequency settles at the set frequency, and the PLL loop is locked.

    However, this frequency synthesizer does not necessarily require the frequency pull-in means 100 in principle, and if the corresponding voltage is output even when the frequency difference is large in the digital processing portion, To work. That is, at the start of operation, the voltage corresponding to the frequency difference extracted by the frequency difference extracting means 30 is large, and this voltage is integrated and given as the control voltage of the voltage controlled oscillator 1, so that the output frequency increases. Thereafter, the PLL loop is locked as described above.

  In practice, it is only necessary to select a frequency division ratio according to the size of the set frequency. Therefore, by adopting the idea of a vector, a single-stage PLL is used in this way, but it is fine over a wide frequency band. The frequency can be set.

An example in which the frequency synthesizer of the present invention is embodied will be described below with reference to FIG. The means provided in the subsequent stage of the voltage-controlled oscillator 1 will be described in order. Reference numeral 2 denotes a frequency divider composed of, for example, a programmable counter, and the frequency division ratio N (N is an integer) of the frequency divider 2 is a parameter output described later. Determined by the department. A low-pass filter 21 is provided at a subsequent stage of the frequency divider 2 as means for converting a rectangular wave signal that is a frequency signal from the frequency divider 2 into a sine wave signal.
Reference numeral 3 denotes an A / D (analog / digital) converter, which samples a sine wave signal whose frequency is a few signals from the low-pass filter 21 with a clock signal from the reference clock generator 31 and uses the sampled value as a digital signal. Output. The reference clock generator 31 outputs a clock signal that is a frequency signal with extremely high frequency stability in order to sample the frequency signal.

  The high frequency signal specified by the digital signal obtained by the A / D converter 3 includes harmonics in addition to the fundamental wave. That is, when sampling a sine wave with harmonic distortion, the harmonic component is affected by aliasing, and in some cases, the fundamental frequency and the harmonic frequency may overlap on the frequency axis in the frequency spectrum. The Therefore, it is necessary to avoid the overlap and to later extract a vector that accurately corresponds to the output frequency of the voltage controlled oscillator 1.

  In general, when a sine wave signal having a frequency f1 is sampled with a clock signal having a frequency fs, the frequency f2 obtained as a result of the capture is expressed by equation (1). However, mod (,) represents a modulo function.

f2 = | mod (f1 + fs / 2, fs) −fs / 2 | (1)
In this acquisition result, the frequency of the nth-order harmonic with respect to the fundamental frequency is expressed as n × (fundamental frequency). If this is set as f2 and substituted into the above equation (1), the harmonic It can be calculated as to what frequency the wave is captured. By using this calculation, the frequency fc of the high frequency signal from the frequency divider 2 and the sampling frequency (frequency of the clock signal) fs can be set so that the frequency of the fundamental wave and the frequency of the harmonic do not overlap. For example, the frequency division ratio N is set so that fc when the vector stops is 36 MHz, and fs is set to 40 MHz. In this case, the fundamental wave of the frequency signal specified by the output signal which is a digital signal from the A / D converter 3 is a 4 MHz sine wave. If fc / fs is 9/10, the fundamental frequency and the harmonic frequency do not overlap, but fc / fs is not limited to this value.

  A carrier remove 4 is provided at the subsequent stage of the A / D converter 3. This carrier remove 4 performs quadrature detection on the sine wave signal specified by the digital signal from the A / D converter 3 by a sine wave signal having a frequency of ω0t / 2π (angular velocity is ω0t), and performs A / D conversion. Means for extracting a vector that rotates at the frequency of the difference between the frequency of the frequency signal specified by the digital signal of the device 3 and the frequency of the sine wave signal used for detection; more specifically, a real part and an imaginary number when this vector is complex-displayed It corresponds to the means for taking out the part.

  The carrier remove 4 will be described in detail. The carrier remove 4 has a multiplier 41a for multiplying the sine wave signal by cos (ω0t) and −sin (ω0t) for the sine wave signal as shown in FIG. A multiplication unit 41b that performs multiplication and low-pass filters 42a and 42b that are provided in the subsequent stages of the multiplication units 41a and 41b are provided. Accordingly, when the sine wave signal obtained by the A / D converter 3 is Acos (ω0t + θ), the output of the multiplier 41a and the output of the multiplier 41b are expressed by the equations (2) and (3), respectively.

Acos (ω0t + θ) ・ cos (ω0t)
= 1/2 · Acosθ + 1/2 {cos (2ω0t) · cosθ + sin (2ω0t) · sinθ} (2)
Acos (ω0t + θ) ・ -sin (ω0t)
= 1/2 · Asinθ-1/2 {sin (2ω0t) · cosθ + cos (2ω0t) · sinθ} (3)
Therefore, by passing the output of the multiplication unit 41a and the output of the multiplication unit 41b through the low-pass filters 42a and 42b, respectively, the frequency signal of 2ω0t is removed. Therefore, from the low-pass filters 42a and 42b, 1/2 · Acos θ and 1 / 2 · Asinθ is taken out. In the actual digital processing in the low-pass filters 42a and 42b, a moving average of a plurality of continuous data, for example, six data, is calculated for the time-series data output from the multiplication units 41a and 41b.

  As described above, when the frequency of the sine wave signal obtained by the A / D converter 3 is equal to the frequency of the sine wave signal used for quadrature detection, the output does not include a time function. The resulting vector will be stopped. On the other hand, when the frequency of the sine wave signal represented by Acos (ω0t + θ) changes, Acos (ω0t + θ) becomes Acos (ω0t + θ + ω1t). Accordingly, 1/2 · Acosθ is 1/2 · Acos (θ + ω1t), and 1/2 · Asinθ is 1/2 · Asin (θ + ω1t). That is, the output obtained from the low-pass filters 42a and 42b is a signal corresponding to the frequency change (ω1t) of the sine wave signal [Acos (ω0t + θ)], that is, the sine wave signal obtained by the A / D converter 3. These are the real part (I) and imaginary part (Q) when the vector rotating at the speed of the difference (ω1t / 2π) between the frequency of and the frequency of the sine wave signal used for quadrature detection is displayed in a complex manner. In this specification, since there is no significance in using the frequency and the angular velocity separately, both may be used together.

  FIG. 4 is a diagram showing the vector V. The vector V has a length A and a rotational speed ω1t (= φ) (frequency is ω1t / 2π). In this example, the frequency used for quadrature detection is 4 MHz. If the frequency of the sine wave signal obtained by the A / D converter 3 is 4 MHz, the vector rotation speed is zero, but if the frequency deviates from 4 MHz. , The motor rotates at a frequency (rotational speed) corresponding to the shifted frequency difference.

  An inverse vector multiplication unit 5 is provided in the subsequent stage of the carrier remove 4. The inverse vector multiplication unit 5 multiplies the vector V obtained by the carrier remove 4 by the inverse vector V ｀ created by the parameter output unit 6. If this expression is used intuitively, the speed of the vector V is reduced by the speed of the inverse vector V ｀. In other words, the multiplication is performed by the difference between the frequency of the vector V and the frequency of the inverse vector V ｀. You will get a vector.

The computation in the inverse vector multiplication unit 5 will be described. The carrier remove 4 and the inverse vector multiplication unit 5 are executed by computer computation, sampling at a certain timing in sampling of the computation, for example, sampling of the nth vector V If the value is I (n) + jQ (n), the sampling value of the nth inverse vector V ｀ is I` (n) + jQ` (n). A vector I + jQ obtained by multiplying both vectors is {I (n) + jQ (n)} × {I` (n) + jQ` (n)}. When this formula is arranged, the formula (4) is obtained.
I + jQ = {I (n) .I` (n) -Q (n) .Q` (n)} + j {I (n) .Q` (n) + I` (n) .Q (n)} (4)
FIG. 5 shows the configuration of the inverse vector multiplication unit 5, which performs the calculation of equation (4).
The generation of the inverse vector V ｀ means that the values of the real part and the imaginary part of the vector, that is, the phase of the inverse vector V ｀, are φ ｀ so that the vector on the complex plane is actually rotated in reverse. It is to generate a value with ｀. FIG. 6 shows an I / Q table 60 in which pairs of vector cosφ ｀ and sinφ ｀ are arranged in order along the rotation direction of the vector, and the parameter output unit 6 in this example uses the I / Q table 60 shown in FIG. A Q table 60 is provided, and the address of the I / Q table 60 is read with the increment number or the decrement number determined according to the set frequency of the instructed voltage controlled oscillator 1, and is output to the inverse vector multiplication unit 5. . For example, by reading one address at a time from clock address 0 to address k, the vector V rotates at a certain speed, and when every other address is read with the increment number set to 2, the vector speed is doubled. become. Whether the data is incremented or decremented can be determined by the rotation direction of the vector V extracted by the carrier remove 4. In this way, an inverse vector V ｀ that rotates in reverse with respect to the vector V can be generated.

  With respect to the blocks so far in FIG. 2, a specific series of operations will be described. If the output frequency of the voltage controlled oscillator 1 is fvco, the frequency divided by the frequency divider 2 is fvco / N. Since the A / D converter 3 is sampled by the clock signal having the frequency fs, the frequency of the frequency signal specified by the digital signal obtained by the A / D converter 3 is fs− (fvco / N). It becomes. In this example, since fs is 40 MHz, 40 MHz- (fvco / N). Since the frequency (ω0t / 2π) of the sine wave signal used for detection in the carrier remove 4 is 4 MHz, the frequency of the vector V extracted from the carrier remove 4 is 40 MHz− (fvco / N) −4 MHz.

  By the way, this invention is controlled so that the frequency difference between the frequency of the vector V and the frequency fr becomes zero when the output frequency fvco of the voltage controlled oscillator 1 reaches the set frequency. If (fvco / N) is 36 MHz, the vector V is stopped (since the frequency is zero). In this case, the PLL is locked by setting the frequency of the inverse vector VＰＬ to zero, The output frequency fvco of the voltage controlled oscillator 1 becomes the set frequency. However, since there is only one such case, the vector V extracted from the carrier remove 4 is actually rotating at a certain speed. For this reason, it is necessary to generate an inverse vector V ｀ for stopping the vector V, but since a series of calculations are performed by software, data for generating the inverse vector V ｀ is stored. The design requirement is to make the memory capacity as small as possible.

  From this point of view, assuming that the set frequency of the voltage controlled oscillator 1 is fset, fset / N is preferably as close to 36 MHz as possible. In this example, the parameter output unit 6 sets a desired set frequency fset set by the user. On the other hand, an integer whose fset / N is closest to 36 MHz is calculated, and the integer is used as the frequency division ratio N of the frequency divider 2. By doing so, the frequency of the inverse vector V ｀ for stopping the vector V taken out from the carrier remove 4 becomes a value smaller than 4 MHz, and the amount of data for generating the inverse vector V ｀ can be small.

As a specific example of the frequency, if the set frequency fset of the voltage controlled oscillator 1 is 520.0001 MHz, for example, if the division ratio N is an integer closest to, for example, fset / 36 MHz, N = 14. Become. In this case, the frequency after frequency division when the output frequency of the voltage controlled oscillator is the set frequency fset is fset / 14 = 37.1428428857143 MHz. As described above, when the frequency after frequency division is 36 MHz, the frequency of the frequency signal specified by the digital value obtained by the A / D converter 3 is 40 MHz−36 MHz = 4 MHz, and a 4 MHz sine wave. The frequency of the vector V obtained through the carrier remove 4 that performs quadrature detection with the signal is 4 MHz-4 MHz = 0, that is, the vector V stops. Therefore, the frequency signal of fset / 14 = 37.1428428257143 MHz is digitized by the A / D converter 3 and the frequency of the vector V obtained by inputting the frequency signal to the carrier remove 4 is 37.1426428857143 MHz−36 MHz = 1. 14284428857143 MHz.
Such calculation is performed by the parameter output unit 6 before the voltage controlled oscillator 1 is operated by inputting a set frequency to the frequency synthesizer. The parameter output unit 6 refers to a memory (not shown) and selects a voltage value that can obtain a frequency close to the set frequency, whereby the output voltage of the voltage output unit 11 increases toward the voltage value. . Then, if the frequency division ratio N is set to 14 and the frequency of the inverse vector V is set to 1.14284428257143 MHz, the voltage control is performed until the frequency of the frequency signal obtained by the A / D conversion unit 3 becomes 1.142864287143 MHz. When the output frequency fvco of the oscillator 1 rises and the frequency of the vector V and the frequency of the inverse vector V ｀ coincide with each other, the PLL is locked and fvco converges to fset.
FIG. 7 is a diagram conceptually showing a state in which the vector V is stopped by performing the reverse rotation process using the reverse vector V ｀.

  By the way, the above-described operation is an operation in the case of a method of stopping the vector V by relying only on the inverse vector V ｀. In this case, a signal corresponding to the frequency of the vector obtained by the inverse vector multiplication unit 5 is loop-filtered. 8 may be entered. However, with such a configuration, the amount of data for generating the inverse vector V ｀ becomes considerably large. For this reason, in the embodiment shown in FIG. 2, the frequency of the vector V is decelerated to some extent by the inverse vector V を, and the remaining deceleration is performed by the subsequent phase time difference detection unit 71, the addition unit 72, and the phase difference accumulation addition unit 73. It is up to the operation. In other words, the inverse vector multiplication unit 5 performs the coarse adjustment of the frequency of the vector V, and finely adjusts the vector V at the subsequent stage, thereby stopping the vector V.

The frequency of the inverse vector V ｀ for coarse adjustment of the frequency of the vector V can be set in increments of 152.5878890625 Hz, for example. The reason is that, when sampling data at 40 MHz, if the number of points of the phase of the inverse vector V 設定 is set to 2 to the 18th power, the 18th power of 40 MHz / 2 = 152.5878890625 Hz. That is, in the parameter output unit 6, the minimum adjustment frequency (frequency step fa) is 152.5878890625 Hz, and the frequency step fa is the most when the frequency step fa is multiplied with respect to the above-mentioned vector V frequency of 1142866.428557143 Hz (1.14282842871433 MHz). Calculate how close you are.
The integer closest to 1142862.2857143 Hz / 152.5878890625 Hz is 7490, and the parameter output unit 6 obtains this integer to obtain the frequency of the vector V when the output frequency of the voltage controlled oscillation unit 1 reaches the set value. The nearest frequency n · fa (n is an integer) = 7490 · 152.5878890625 Hz = 1142883.30078125 Hz is obtained.

Then, the parameter output unit 6 performs the following calculation. First, the frequency adjusted by the inverse vector V ｀ is subtracted from the frequency of the vector V to obtain 142864.2857143 Hz-1142883.30078125 Hz = 19.01506669664145 Hz.
Further, the frequency step fb for fine adjustment smaller than the frequency step fa for coarse adjustment. In this example, the vector when the output frequency of the voltage controlled oscillator 1 becomes a set value out of an integer multiple of the frequency step 1 Hz. A frequency m · fb (m is an integer) closest to 19.01506669664145 Hz, which is the difference between the frequency V and the frequency n · fa, is calculated. In this case, since fb is 1 Hz, m is 19, and the adjustment for 19 Hz is performed by the latter part of the inverse vector multiplication unit 5. The terms coarse adjustment and fine adjustment here are different from the coarse adjustment and fine adjustment in the feedback means, which is an improved part of the new frequency synthesizer.

Returning to FIG. 2, 7 is a reduction processing unit, 71 is a low-pass filter, 71 is a phase time difference detection unit, 72 is a second addition unit, 73 is a cumulative addition unit for phase difference, 8 is a loop filter, and 80 is a D / D A (digital / analog) conversion unit.
Since the rotation of the vector V is decelerated by the inverse vector V ｀, the frequency (speed) of the vector V can be obtained by a simple approximate expression. As shown in FIG. 8, on the complex plane, the vector V (n−1) obtained by the (n−1) th sampling and the vector V (n) = V (n−1) + ΔV obtained by the nth sampling. Can be regarded as the length of ΔV if the frequency of the vector V is sufficiently smaller than the sampling frequency and θ = sin θ. .

  The approximate expression for obtaining ΔV will be described. First, the phase difference Δφ is expressed by the equation (5). Here, imag is an imaginary part, conj {V (n)} is a conjugate vector of V (n), and K is a constant.

Δφ = K · imag [ΔV · conj {V (n)}] (5)
Here, if the values corresponding to the nth sampling are I (n) and Q (n) for the I value (the real part of the vector V) and the Q value (the imaginary part of the vector V), ΔV and conj {V (N)} is represented by the expressions (6) and (7), respectively, in a complex display.

ΔV = ΔI + jΔQ (6)
conj {V (n)} = I (n) -jQ (n) (7)
However, ΔI is I (n) −I (n−1), and ΔQ is Q (n) −Q (n−1). If the expressions (6) and (7) are substituted into the expression (5) and rearranged, Δφ is expressed by the expression (8).

Δφ = ΔQ · I (n) −ΔI · Q (n) (8)
The phase time difference detection unit 71 has a function of obtaining Δφ using the approximate expression in this way. Since Δφ is a value corresponding to the frequency of the vector V decelerated by the inverse vector multiplying unit 5, the phase time difference detecting unit 71 outputs a frequency of the decelerated vector V (slow-speed vector detecting unit). )You can say that.

  If the vectors V (n−1) and V (n) are obtained, various mathematical methods can be used as a method for obtaining the angle Δφ between them. As an example, the approximate expression (5) is given. Only. As the mathematical formula, {V (n) + V (n-1)} / 2 which is a vector VO connecting the midpoint of the line connecting the end points of V (n) and V (n-1) and the origin is used. In the equation (5), this vector VO may be substituted for V (n). The reason why the equation (5) can be approximated can be considered that VO and ΔV are orthogonal to each other. Therefore, the length of ΔV is the imaginary value of ΔV when VO is regarded as a real axis. This is because it can be handled if it corresponds to a numerical value.

  On the other hand, since the parameter output unit 6 obtains the value of 19 Hz, which is the fine frequency adjustment of the vector V, by calculation, the frequency of the vector V detected by the phase time difference detection unit 71 and the fine adjustment of 19 Hz are obtained. The difference between the frequency of the vector V and the fine adjustment of 19 Hz is taken out by the adder 72 and input to the phase difference accumulator 73. The output value from the phase difference accumulating unit 73 is input to the loop filter 8.

  The present invention performs the process of stopping the vector V as shown in FIG. 1, but in this example of FIG. 2, this process is a rough stop process by reverse rotation and the process of accurately stopping the vector V that has become slow. The latter half of the processing is assigned to the phase time difference detection unit 71 and the addition unit 72. The inverse vector multiplication unit 5, the phase time difference detection unit 71, and the second addition unit 72 correspond to frequency difference extraction means. In this example, when the output frequency of the voltage controlled oscillator 1 is lower than the set frequency, that is, when the frequency of the rotation vector is lower than the set frequency, the output of the phase time difference detector 71 is output as a negative value. A multiplication unit 711 for multiplying the output by -1 is provided.

As shown in FIG. 9, the phase difference accumulating unit 73 holds an input value at a certain sampling time in a register 73a, outputs the value held so far at the next sampling time, and returns it to the adding unit 73b for input. The value is added to the value, and the added value is input to the register 73a.
The loop filter 8 corresponds to the integrating means of FIG. 1, and as shown in FIG. 10, the input value is cumulatively added by the cumulative adder 8a, and the input value is added to the cumulative added value by the adder 8b. It is configured as follows. The output voltage of the loop filter 8 is converted to an analog voltage by the D / A conversion unit 80 and added to the output voltage from the D / A conversion unit of the frequency pull-in means described later to add to the voltage controlled oscillator 1. Input as control voltage. The loop filter has a role of suppressing signal fluctuation and stabilizing the loop.
In this example, the phase difference cumulative addition unit 73, the loop filter 8, and the D / A conversion unit 80 correspond to feedback means.
A loop returning from the voltage controlled oscillator 1 to the voltage controlled oscillator 1 through the frequency difference extracting means and the loop filter 8 forms a PLL. Each part from the A / D converter 3 to the loop filter 8 is constituted by a digital processing device such as an FPGA.

  Here, the inventor examined the relationship between the detection value of the phase time difference detection unit 71 and the output level of the low-pass filter 21 and found that the predetermined frequency centered on the point at which the output frequency of the voltage controlled oscillator 1 becomes the set frequency. It is understood that the gain of the low-pass filter 21 falls when the frequency domain is deviated. In this case, when the frequency of the voltage controlled oscillator 1 changes beyond this range due to temperature characteristics or the like, the control system does not follow, and therefore the frequency cannot be drawn to the set frequency. Further, since no control voltage is input to the voltage controlled oscillator 1 at the start of operation of the apparatus, it is necessary to raise the control voltage to the frequency pull-in range.

Therefore, as the frequency pull-in means 100, a switch unit 101, an integration circuit unit 102, an adder unit 103, and a D / A converter 104 are provided. The switch unit 101 is switched to one of the contacts a, b, and c. When the switch unit 101 is switched to a, the output of the phase time difference detection unit 71 is switched to b, and when the switch unit 101 is switched to b, the second constant is set to c. When switched, the first constant is taken into the integrating circuit unit 102, respectively. The first constant and the second constant are output from the parameter output unit 6. For example, the second constant (the set value of the contact b) is set smaller than the first constant (the set value of the contact c). Has been.

  The integrating circuit unit 102 is configured to latch the value obtained by the previous sampling by the latch unit 102a and sequentially add this value and the value obtained by the current sampling. Further, the D / A converter 104 has a smaller number of bits on the digital side than the D / A converter 80, and is configured to output the input signal at a large frequency step.

  Switching operation of the switch unit 101 and integration / stop of the integration circuit unit 102 are performed by the operation control unit 105. The operation control unit 105 determines a frequency serving as a threshold value for operation control according to the set frequency, and detects the output frequency of the voltage controlled oscillator 1 and the carrier level input to the phase time difference detection unit 71. Thus, it has a function of controlling the operation of the switch unit 101 and the integrating circuit unit 102 in accordance with the detection result and the threshold value.

The operation of the operation control unit 105 will be clarified as shown in FIGS. 11 and 12 in the description of the operation described later. The functions are summarized here as follows.
A) While the output frequency from the voltage controlled oscillator 1 is too small and the frequency difference between the set frequency and the output frequency is too large, a voltage signal cannot be obtained from the adder 72. And the integration circuit unit 102 is turned on so that the first constant is integrated by the integration circuit unit 102,
B) After the first constant is integrated by the integrating circuit unit 102 and the control voltage of the voltage controlled oscillator 1 is output, the frequency difference between the set frequency and the output frequency from the voltage controlled oscillator 1 is reduced, so that the phase After the voltage signal (this voltage signal is not yet valid) is output from the time difference detection unit 71, the integration circuit unit 102 is set to set the switch unit 101 to a and integrate the voltage signal from the addition unit 72. Turn on
C) The frequency difference between the set frequency and the output frequency from the voltage controlled oscillator 1 is further reduced, and an effective voltage signal can be obtained from the phase time difference detection unit 71 with respect to the frequency difference, and the loop filter After the output of 8 falls within a preset range, the integration operation of the integration circuit unit 102 is stopped,
D) After the integration operation of the integration circuit unit 102 is stopped, after the effective voltage signal is obtained from the phase time difference detection unit 71 and the output of the loop filter 8 is out of the preset range, The second constant is integrated by the integration circuit unit 102, and after the output of the loop filter 8 falls within a preset range, the integration operation of the integration circuit unit 102 is stopped.

  Next, the overall operation of the embodiment shown in FIG. 2 will be described with reference to FIGS. Now, as described in the above specific example, it is assumed that the set frequency fset of the voltage controlled oscillator 1 is, for example, 520.0001 MHz and input from an input unit (not shown) (step S1 in FIG. 11). The parameter output unit 6 includes a table in which the relationship between the set frequency of the voltage controlled oscillator 1 and the supply voltage is written, and selects the set frequency closest to 520.0001 MHz in this table.

  Further, as described above, the frequency division ratio N = 14, which is the integer closest to fset / 36 MHz, and the frequency of the vector V when the set frequency is obtained are divided into the adjustment amount and the fine adjustment amount, respectively. And calculate the amount. In this case, the frequency adjustment amount, that is, 1142883.30078125 Hz, which is the frequency of the inverse vector, and the vector frequency 19 Hz after the reverse rotation processing, which is the fine adjustment amount input to the second adder 72, are calculated.

Then, the initial voltage added to the adding unit 103 serving as a frequency pulling unit is calculated as a value corresponding to the set frequency, and the integrated value of the integrating circuit unit 102 is cleared (steps S2 and S3). When a start instruction is input from the input unit, the initial voltage is added to the adding unit 103 and the voltage controlled oscillator 1 is started up. At this time, since the output frequency is low and the frequency difference from the set frequency is large, the PLL loop Does not operate, that is, the voltage signal is not output from the adder 72, the process proceeds to step S5 through the determination step S4, the switch unit 101 is set to the contact c, and the first constant is integrated by the integration circuit unit 102. Is done.
The calculation from the carrier remove 4 to the adder 72 is as already described in detail, but a summary description will be given later.

As a result of the integration described above, the output frequency of the voltage controlled oscillator 1 increases as shown in FIG. 12, and the voltage signal starts to be output from the adder 72 at time t1. For this reason, the process proceeds to step S6 through the determination step S4. At this stage, although a voltage signal is output from the phase time difference detection unit 71, it is not an effective value corresponding to the output frequency. When the input carrier of the phase time difference detection unit 71 can be detected, the switch unit 101 switches to a in step S7. For this reason, the voltage signal from the phase time difference detection unit 71 is integrated into the integration circuit unit 102, and this integration value is given to the coupler 11 via the D / A converter 104, and from the D / A converter 80. The voltage is added to the voltage to be supplied to the voltage controlled oscillator 1 as a control voltage.
When the output frequency of the voltage controlled oscillator 1 rises and the output value of the loop filter 8 falls within the set threshold value range (first setting range) (time t2), the PLL is almost locked. In step S8, the switch unit 101 switches to b, and the integration operation of the integration circuit unit 102 is stopped.

After the PLL is locked, there is a possibility that the output frequency of the voltage controlled oscillator 1 may change due to temperature characteristics or the like. Therefore, in step S9, the operation control unit 105, for example, the digital value of the D / A converter 80 has a certain threshold value. It is monitored whether or not it is within a range (for example, a second setting range that is 1/6 to 5/6 of the full range), and if it is out of the range, the integration operation of the integration circuit unit 102 is started in step S10. . Thus, the second constant is integrated by the integration circuit unit 102 , and the second constant is supplied as a positive value or a negative value. This integral value is given to the coupler 11 via the D / A converter 104, added to the voltage from the D / A converter 80, and given to the voltage controlled oscillator 1 as a control voltage. When the digital value of the D / A converter 80 falls within the threshold value range, the integration operation of the integration circuit unit 102 is stopped (step S9).

  Next, the operation including the calculation from the carrier remove 4 to the adder 72 will be described. When a voltage is supplied to the voltage controlled oscillator 1 at the start of the apparatus, a frequency signal is output and the frequency increases. Since the output frequency of the voltage controlled oscillator 1 is low at the beginning, the frequency [40 MHz− (output frequency / N)] extracted by the A / D converter 3 is large. Therefore, the vector V extracted by the carrier remove 4 Is a large negative value, and the carrier is attenuated by the low-pass filter 71, so that no voltage signal is output from the phase time difference detector 71. When the output frequency of the voltage controlled oscillator 1 rises to a certain value, the extraction operation of the vector V from the carrier remove 4 becomes effective, and the frequency (speed) of the vector V starts to drop.

  In this description, when the value of 40 MHz− (output frequency / N) is smaller than 4 MHz, that is, when the rotation direction of the vector V when the output frequency / N is larger than 36 MHz is called a positive direction, a negative direction is assumed. This means that the frequency of the vector V rotating at a low speed has decreased. At this time, the frequency of the vector V multiplied by the reverse rotation, which is the output of the inverse vector multiplication unit 5, also decreases. Accordingly, the output of the phase time difference detection unit 71 becomes a large value when the calculation is valid because the difference between the set frequency and the output frequency is still large, but gradually decreases (the negative speed is reduced). And the added value of the second adder 72 that adds the output (phase difference) and the fine adjustment amount of the frequency becomes smaller.

  Further, the output frequency of the voltage controlled oscillator 1 rises, the frequency after frequency division becomes 36 MHz, and the speed of the vector V taken out from the carrier remove 4 comes to a timing. Here, if the adjustment frequency is ΔF (n · fa) and the fine adjustment frequency is Δf (m · fb), the frequency of the vector V extracted from the carrier remove 4 is still smaller than the frequency adjustment ΔF + Δf, and the frequency Since the difference (output of the second adder 72) is a negative value, the frequency of the vector V increases. Eventually, the frequency of the vector V becomes the same as the frequency adjustment ΔF + Δf. As a result, the output of the phase time difference detection unit 71 eventually converges to Δf (19 Hz in the above specific example), and the output of the second addition unit 72, that is, the frequency difference extracted by the frequency difference extraction means becomes zero. As a result, the PLL is locked, and the output frequency of the voltage controlled oscillator 1 is locked to the set frequency of 520.0001 MHz. Since the loop filter 8 has a complete integration function in this example, the loop filter 8 converges to a positive DC voltage. In the simulation, the time from when the operation of the voltage controlled oscillator 1 was started until the PLL was locked was about 150 msec.

According to the above-described embodiment, while the output frequency from the voltage controlled oscillator 1 is small and there is a large opening with respect to the set frequency, the first constant is integrated by the integrating circuit unit 102 and the voltage controlled oscillator 1 The output frequency is increased by outputting as a control voltage. Then, after the PLL is locked, the control voltage from the loop filter 8 is monitored, and when the control voltage deviates from the preset range, the second constant is set so as to fall within the range. And is output to the coupler 11 as a frequency pull-in voltage. Therefore, since the frequency pull-in range is wide, the frequency of the voltage-controlled oscillation unit varies, and even if the frequency changes due to temperature characteristics or the like, the frequency pull-in can be performed, so that a stable operation can be obtained.

  Further, according to the control method of the main body of the frequency synthesizer adopted by the present invention, the following effects are obtained. A vector that rotates at a speed (frequency) corresponding to the output frequency of the voltage controlled oscillator 1 is extracted, and the difference between the frequency of this vector and the vector frequency when the output frequency reaches the set frequency is extracted to the voltage controlled oscillator 1. Since the PLL is formed by feedback, fine frequency setting can be performed with low noise over a wide frequency band. When extracting the frequency difference, the speed of the vector is reduced using a reverse vector that rotates in reverse with a coarse frequency setting, the speed of the fine speed vector is detected, and the detected value and a pre-calculated amount are added. At the same time, the difference is taken out. Therefore, as described above, it is possible to provide a frequency synthesizer in which the amount of data is suppressed and the vector frequency can be detected by a simple calculation, and therefore the memory capacity is small and the calculation load is small.

  The frequency division ratio N is determined by dividing the set value of the output frequency of the voltage controlled oscillator 1 by N and the frequency of the reference clock signal used in the A / D converter 3 and ω0 / 2π used in the vector extracting means. It is not limited to determining the frequency closest to the difference.

  In the present invention, the output obtained by adding the outputs of the two D / A converters 80 and 104 becomes the control voltage of the voltage controlled oscillator 1, and the configuration thereof is the coupler 11 as in the previous embodiment. 13 is used, and the output of the D / A converter 80 and the output 104 of the D / A converter 104 are input to the ports 12a and 12b, respectively, as shown in FIG. You may do it.

  Another embodiment of the invention will be described. In this embodiment, after the switch unit 101 is switched to a in the previous embodiment, an offset of several bits is applied to the D / A converter 104 in the frequency pulling means when the PLL is locked. . This point will be described in detail.

When the D / A converter 80 included in the feedback means is a ladder resistor type as shown in FIG. 14, glitch noise is generated by switching the internal switches, and the amount of noise increases as the number of switches that are switched simultaneously increases. . Therefore, when the input value of the D / A converter 80 crosses the center value of the full range, the number of switches that are simultaneously switched is maximized, and the amount of noise generation is also maximized. Crossing the center value of the full range is, for example, when switching from “01111111” to “10000000” in the case of 8 bits shown in FIG. In particular, as in the above-described embodiment, the rough frequency is determined by the frequency pull-in means (the part from the switch 101 to the D / A converter 104), and the D / A converter 80 is finely incorporated with, for example, PWM control. In the case of a smooth gradation expression, if the set value of the D / A converter 104 of the frequency pulling means is set near the center, the probability that the D / A converter 80 switches at high speed near the center value of the full range increases. There is a fear. Incorporating PWM control means that a pulse train having a duty ratio corresponding to a digital value that is an input value is output at each sampling timing, and is smoothed and output as a control voltage. When a fine gradation expression is performed by the D / A converter, the output change is small, so that the glitch noise becomes relatively conspicuous.

  FIG. 15 is a characteristic diagram showing the relationship between the control voltage of the voltage controlled oscillator 1 and the output frequency, and the black circles indicate the D / A converter 80 when the PLL is locked so that the output frequency matches the set frequency fs. Output voltage. That is, in this case, the D / A converter 80 is set to obtain this voltage Vs when the duty ratio of the internal PWM signal is 50%. Therefore, the center of the full range AD1 of the D / A converter 80 becomes a black circle position.

  Therefore, in this embodiment, the D / A converter 104 of the frequency pull-in means when the PLL is locked can be adjusted more than the control voltage at which the output frequency is closest to the set frequency among the settable control voltages. The value is shifted (applied with an offset) by an amount corresponding to an integer multiple of a small frequency increment. For example, if the frequency variable amount corresponding to the full range of the D / A converter 80 is 4.5 MHz, for example, and the frequency change amount per bit of the D / A converter 104 of the frequency pull-in means is about 750 kHz. In simple calculation, the D / A converter 104 can be offset by a maximum of ± 3 bits.

  In this way, as shown in FIG. 15, the full range of the D / A converter 80 changes from AD1 to AD2, so that the output value of the D / A converter 80 when the output frequency matches the set frequency fs is the full range. Displace from the center of As a result, the probability that the D / A converter 80 switches at high speed near the center value of the full range is reduced, and glitch noise can be reduced.

It is a block diagram which shows the basic composition of the frequency synthesizer which concerns on this invention. 1 is a block diagram showing an embodiment of a frequency synthesizer according to the present invention. It is a block diagram which shows the carrier remove used for said embodiment. It is explanatory drawing which shows the vector obtained by a carrier remove. It is a block diagram which shows the structure of an inverse vector multiplication part. It is explanatory drawing which shows the data table for generating a reverse vector in a parameter generation part. It is explanatory drawing which shows a mode that a vector obtained by carrier removal and an inverse vector are mutually multiplied by a frequency difference extraction means. It is explanatory drawing which shows the phase difference of the vector sampled at the timing which precedes and follows. FIG. 2 is a configuration diagram illustrating a phase difference cumulative addition unit in the block diagram of FIG. 1. It is a block diagram which shows the loop filter in the block diagram of FIG. It is a flowchart which shows the effect | action of said embodiment. It is a time chart which shows the effect | action in said embodiment. It is a circuit diagram which shows the other example of a voltage control oscillation part. It is a circuit diagram which shows the structural example of a D / A converter. It is explanatory drawing which shows a mode that the center value of the output of the D / A converter in an original feedback means is shifted by offsetting the output of a frequency drawing means. It is a block diagram which shows the structure of the conventional frequency synthesizer.

Explanation of symbols

1 Voltage Control Oscillator 11 Coupler 2 Frequency Divider 3 A / D Converter 31 Reference Clock Generating Unit 4 Carrier Remove 5 Inverse Vector Computing Unit 6 Parameter Output Unit 71 Phase Time Difference Detection Unit 72 Addition Unit 73 Phase Difference Accumulation Addition Unit 8 Loop filter 80 D / A
101 switch
102 integration circuit unit 104 D / A converter 105 operation control unit

Claims (12)

A voltage-controlled oscillator that oscillates a frequency signal having a frequency corresponding to the supplied voltage;
Frequency dividing means for dividing the frequency signal into 1 / N (N is an integer) according to the set frequency of the voltage controlled oscillation unit;
An analog / digital converter that samples a sine wave signal having a frequency corresponding to 1 / N of the output frequency of the voltage-controlled oscillator based on a reference clock signal and outputs the sampled value as a digital signal;
The frequency signal corresponding to the output signal from the analog / digital converter is subjected to quadrature detection using a digital signal of a sine wave signal having a frequency of ω0 / 2π, and the frequency difference between the frequency signal and ω0 / 2π is detected. Vector extracting means for extracting a real part and an imaginary part when a vector rotating at a frequency corresponding to
A parameter output unit for calculating the frequency of the vector when the output frequency of the voltage controlled oscillation unit reaches a set value;
A frequency difference extracting means for extracting a difference between the frequency of the vector and the frequency calculated by the parameter output unit;
Means for integrating a voltage signal corresponding to the frequency difference extracted by the frequency difference extracting means and feeding it back to the voltage controlled oscillator as a control voltage via a digital / analog converter;
A) At the start of the operation of the apparatus, while the voltage signal cannot be obtained from the frequency difference extracting means due to the output frequency from the voltage controlled oscillator being too low, the first constant is integrated by the integrating circuit. The voltage for raising is output as the control voltage of the voltage controlled oscillator,
B) After the PLL is locked, when the control voltage from the means for returning deviates from a preset range, a second constant set smaller than the first constant is set so as to fall within the range. Output the frequency pull-in voltage integrated by the integration circuit ,
C) Frequency pulling means for stopping the integration operation after the control voltage from the feedback means falls within a preset range, and
The control voltage of the voltage controlled oscillating unit is an added value of the control voltage from the feedback means and the control voltage from the frequency pulling means,
A PLL is formed by the voltage controlled oscillation unit, the vector extracting unit, and the feedback unit that feeds back the voltage signal to the voltage controlled oscillation unit. When the PLL is locked, the output frequency of the voltage controlled oscillation unit is adjusted to the set frequency. This is a frequency synthesizer.   The frequency pulling means outputs the start-up voltage at the start of operation of the apparatus, so that the output frequency from the voltage controlled oscillation unit rises and a voltage signal is obtained from the frequency difference extracting means. 2. The frequency synthesizer according to claim 1, wherein the frequency difference extracted by the frequency difference extracting means is integrated in place of the voltage for starting up and the control voltage of the voltage controlled oscillator is output. The frequency pull means, after outputting a voltage for raising a control voltage for the voltage controlled oscillator, the frequency difference extracting means by the frequency difference between the output frequency from the set frequency and the voltage controlled oscillator is reduced After the voltage signal is output, the voltage signal is integrated by the integration circuit unit and converted into an analog signal at a frequency step larger than that of the feedback means, and the analog signal is output as a control voltage of the voltage controlled oscillation unit. The frequency synthesizer according to claim 1, wherein the frequency synthesizer is configured. A voltage-controlled oscillator that oscillates a frequency signal having a frequency corresponding to the supplied voltage;
Frequency dividing means for dividing the frequency signal into 1 / N (N is an integer) according to the set frequency of the voltage controlled oscillation unit;
An analog / digital converter that samples a sine wave signal having a frequency corresponding to 1 / N of the output frequency of the voltage-controlled oscillator based on a reference clock signal and outputs the sampled value as a digital signal;
The frequency signal corresponding to the output signal from the analog / digital converter is subjected to quadrature detection using a digital signal of a sine wave signal having a frequency of ω0 / 2π, and the frequency difference between the frequency signal and ω0 / 2π is detected. Vector extracting means for extracting a real part and an imaginary part when a vector rotating at a frequency corresponding to
A parameter output unit for calculating the frequency of the vector when the output frequency of the voltage controlled oscillation unit reaches a set value;
A frequency difference extracting means for extracting a difference between the frequency of the vector and the frequency calculated by the parameter output unit;
Means for integrating a voltage signal corresponding to the frequency difference extracted by the frequency difference extracting means and feeding it back to the voltage controlled oscillator as a control voltage via a digital / analog converter;
A frequency pulling means,
The frequency pulling means is
A) At the start of operation of the apparatus, while the voltage signal cannot be obtained from the frequency difference extracting means due to the output frequency from the voltage controlled oscillator being too small, the voltage for starting up is controlled by the voltage controlled oscillator. Output as voltage,
B) After the voltage signal is output from the frequency difference extracting means, the voltage signal is integrated by the integrating circuit section and converted into an analog signal at a frequency step larger than that of the feedback means, and this analog signal is converted into the voltage controlled oscillator section. Output as control voltage,
C) After the frequency difference between the set frequency and the output frequency from the voltage controlled oscillation unit falls within a preset range, the integration operation of the integration circuit unit is stopped, and the control voltage from the frequency pulling means is A fixed value,
D) In order to reduce glitch noise by reducing simultaneous switching of the digital / analog converter in the feedback means, the fixed value is output within a control voltage that can be set by the digital / analog converter in the frequency pull-in means. The frequency is set to a value that deviates from the control voltage closest to the set frequency by an amount corresponding to an integral multiple of the adjustable frequency increment.
A PLL is formed by the voltage controlled oscillation unit, the vector extracting unit, and a feedback unit that feeds back the voltage signal to the voltage controlled oscillation unit. When the PLL is locked, the output frequency of the voltage controlled oscillation unit is adjusted to a set frequency. ,
The frequency synthesizer according to claim 1, wherein the control voltage of the voltage controlled oscillator is an added value of the control voltage from the feedback means and the control voltage from the frequency pulling means.   5. A coupler for adding the control voltage from the feedback means and the control voltage from the frequency pulling means and supplying the sum to the voltage controlled oscillation unit. The frequency synthesizer described in 1.   6. The voltage controlled oscillation unit according to claim 1, further comprising a port to which a control voltage from the feedback unit and a control voltage from the frequency pulling unit are respectively input. The described frequency synthesizer.   The parameter output unit calculates the difference between the frequency of the reference clock signal used in the analog / digital conversion unit and ω0 / 2π used in the vector extraction unit when the set value of the output frequency of the voltage controlled oscillation unit is divided by N. 7. The value of N that is the closest frequency is calculated, and the frequency dividing means divides the frequency signal from the voltage controlled oscillator using this value. The described frequency synthesizer. The parameter output unit has a frequency n · fa (n) that is closest to the frequency of the vector when the output frequency of the voltage-controlled oscillation unit reaches a set value among frequencies that are integral multiples of the frequency increment fa for coarse adjustment. And an integer multiple of the frequency increment fb for fine adjustment smaller than the frequency increment fa, and the frequency of the vector when the output frequency of the voltage controlled oscillation unit becomes a set value and the frequency n · frequency m · fb (m is an integer) closest to the difference from fa,
The frequency difference extraction means multiplies the vector obtained by the vector extraction means by an inverse vector that rotates in reverse at a frequency n · fa, and subtracts the frequency of the inverse vector from the frequency of the vector. Means for taking out the frequency of the slow vector, a slow speed detecting means for the slow vector obtained from the values of the real part and imaginary part at the time of each sampling of the slow vector, and the frequency of the slow vector detected by the slow speed detecting means, The frequency synthesizer according to claim 1, further comprising: means for outputting a signal corresponding to a difference between the frequency m · fb.   9. The frequency synthesizer according to claim 8, wherein the frequency of the slow vector is low enough that the phase [theta] on the complex plane representing the vector can be regarded as sin [theta] and the frequency can be obtained by approximate calculation.   The slow speed vector slow speed detection means includes a position on a complex plane determined by a real part and an imaginary part of a slow vector at a certain sampling time, and a position on a complex plane determined by a real part and an imaginary part of a slow speed vector at the next sampling time. 10. The frequency synthesizer according to claim 9, further comprising means for calculating the distance of, and regarding the calculated value as a phase difference between the slow vectors at the time of both samplings.   9. The means for feeding back a voltage signal corresponding to a frequency difference to the voltage controlled oscillator includes means for accumulating a signal corresponding to the difference between the frequency of the fine vector and the frequency m · fb. The frequency synthesizer according to any one of 10.   A vector consists of a data table in which pairs of real and imaginary parts that define the position of the inverse vector on the complex surface are arranged in order along the direction of rotation, and the number of increments or decrements corresponding to the direction and frequency of rotation of the inverse vector. 12. The frequency synthesizer according to claim 8, wherein the frequency synthesizer is generated by means for generating an address of the data table.

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