JP2014150107A - Electronic element mounting substrate and electronic device - Google Patents

Electronic element mounting substrate and electronic device Download PDF

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JP2014150107A
JP2014150107A JP2013016831A JP2013016831A JP2014150107A JP 2014150107 A JP2014150107 A JP 2014150107A JP 2013016831 A JP2013016831 A JP 2013016831A JP 2013016831 A JP2013016831 A JP 2013016831A JP 2014150107 A JP2014150107 A JP 2014150107A
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conductor
via conductors
electronic element
conductor portion
electronic device
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JP6174327B2 (en
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Akihiko Funahashi
明彦 舟橋
Kanae Horiuchi
加奈江 堀内
Yosuke Moriyama
陽介 森山
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Kyocera Corp
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Kyocera Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

PROBLEM TO BE SOLVED: To provide an electronic element mounting substrate which can be made compact, and to provide an electronic device.SOLUTION: The electronic element mounting substrate has an insulation base 2, and a plurality of via conductors 5 provided on the insulation base 2. Each of the plurality of via conductors 5 includes a first conductor 5a, and a second conductor 5b connected with the first conductor 5a and having a width narrower than that of the first conductor 5a. The plurality of via conductors 5 are arranged so that the first conductor 5a and the second conductor 5b are arranged at the same height position in adjacent via conductors 5, some of the second conductors 5b in adjacent via conductors 5 are arranged at the same height position, and the interval of some of the second conductors 5b is larger than the interval of the first conductor 5a and the second conductor 5b in adjacent via conductors 5.

Description

本発明は、例えばCCD(Charge Coupled Device)型またはCMOS(Complementary Metal Oxide Semiconductor)型等の撮像素子、LED(Light Emitting Diode
)等の発光素子が搭載される電子素子搭載用基板および電子装置に関するものである。
The present invention relates to an imaging device such as a CCD (Charge Coupled Device) type or a CMOS (Complementary Metal Oxide Semiconductor) type, and an LED (Light Emitting Diode).
The present invention relates to an electronic device mounting substrate and an electronic device on which a light emitting device such as) is mounted.

従来から、CCD型またはCMOS型等の撮像素子、LED等の発光素子を絶縁基体に搭載した電子装置が知られている。このような電子装置として、枠部を有している絶縁基体と、枠部の内側もしくは枠部の下面に実装された電子素子とを有しているものが知られている(例えば、特許文献1を参照)。絶縁基体の上面には電極パッドが配置されている。   2. Description of the Related Art Conventionally, an electronic device in which an image pickup element such as a CCD type or a CMOS type and a light emitting element such as an LED are mounted on an insulating substrate is known. As such an electronic device, one having an insulating base having a frame portion and an electronic element mounted on the inner side of the frame portion or the lower surface of the frame portion is known (for example, Patent Documents). 1). An electrode pad is disposed on the upper surface of the insulating substrate.

特開2006−201427号公報JP 2006-201427

近年、電子装置の小型化に伴い、電子素子搭載用基板の絶縁基体が小さくなってきており、それに伴い隣接するビア導体同士の間隔が狭くなってきている。そのため、例えば電子素子の実装時、または電子素子の動作時に発生する熱等により、電子素子搭載用基板が変形し、隣接するビア導体同士の間にクラックが発生しやすいものとなる。   In recent years, with the miniaturization of electronic devices, the insulating base of an electronic element mounting substrate has become smaller, and accordingly, the distance between adjacent via conductors has become narrower. Therefore, for example, due to heat generated when the electronic element is mounted or when the electronic element is operated, the electronic element mounting substrate is deformed, and cracks are easily generated between adjacent via conductors.

本発明の一つの態様による電子素子搭載用基板は、絶縁基体と、絶縁基体に設けられた複数のビア導体とを有し、複数のビア導体のそれぞれは、第1の導体部と第1の導体部に接続されており第1の導体部よりも狭い幅を有している第2の導体部とを含んでいる。複数のビア導体は、隣り合うビア導体において、第1の導体部と第2の導体部とが同じ高さ位置に並ぶように配置されており、隣り合うビア導体の第2の導体部同士の一部が同じ高さ位置に並んでいるとともに、貫通第2の導体部同士の一部の間隔が隣り合うビア導体の第1の導体部と第2の導体部との間隔より大きい。   An electronic element mounting substrate according to an aspect of the present invention includes an insulating base and a plurality of via conductors provided on the insulating base, and each of the plurality of via conductors includes a first conductor portion and a first conductor. And a second conductor part connected to the conductor part and having a narrower width than the first conductor part. The plurality of via conductors are arranged so that the first conductor portion and the second conductor portion are arranged at the same height in adjacent via conductors, and the second conductor portions of the adjacent via conductors Some of them are arranged at the same height position, and the interval between the part of the penetrating second conductors is larger than the interval between the first conductor part and the second conductor part of the adjacent via conductors.

本発明の他の態様によれば、電子装置は、上記構成の電子素子搭載用基板と、電子素子搭載用基板に実装された電子素子とを有している。   According to another aspect of the present invention, an electronic device includes the electronic element mounting substrate having the above-described configuration and an electronic element mounted on the electronic element mounting substrate.

本実施形態の電子素子搭載用基板は、絶縁基体に設けられた複数のビア導体を有しており、ビア導体は第1の導体部と第1の導体部に接続されており第1の導体部よりも狭い幅を有している第2の導体部から形成されている。ビア導体は隣り合うビア導体において、第1の導体部と第2の導体部とが同じ高さ位置に並ぶように配置されており、ビア導体の第2の導体部同士の一部が同じ高さ位置に並んでいるとともに、第2の導体部同士の一部の間隔が隣り合うビア導体の第1の導体部と第2の導体部との間隔より大きい。これらによって、絶縁基体において、隣り合うビア導体同士のピッチが狭くなっても、隣り合うビア導体同士の間隔を十分に確保することができ、例えば電子素子の実装時、または電子素子の動作時に発生する熱等により、電子素子搭載用基板が変形した場合においても、隣接するビア導体の間にクラックが発生することを抑制することが可能となる。   The electronic element mounting board of the present embodiment has a plurality of via conductors provided on an insulating base, and the via conductors are connected to the first conductor portion and the first conductor portion, and the first conductor. It is formed from the 2nd conductor part which has a width | variety narrower than a part. The via conductors are arranged so that the first conductor portion and the second conductor portion are arranged at the same height in adjacent via conductors, and a part of the second conductor portions of the via conductor is the same height. In addition, the gaps between the second conductor portions are larger than the gap between the first conductor portion and the second conductor portion of the adjacent via conductors. As a result, even if the pitch between adjacent via conductors in the insulating substrate is reduced, a sufficient interval between adjacent via conductors can be ensured, for example, when an electronic element is mounted or when an electronic element is operated. Even when the electronic element mounting substrate is deformed due to heat or the like, it is possible to suppress the occurrence of cracks between adjacent via conductors.

本発明の他の態様によれば、電子装置は、上記構成の電子素子搭載用基板を有していることによって、信頼性を保ったまま小型化が可能となるものである。   According to another aspect of the present invention, the electronic device includes the electronic element mounting substrate having the above-described configuration, so that the electronic device can be miniaturized while maintaining reliability.

(a)は本発明の実施形態における電子装置を示す平面透視図であり、(b)は図1(a)に示された電子装置のA−A線における縦断面を示している。(A) is a plane perspective view which shows the electronic device in embodiment of this invention, (b) has shown the longitudinal cross-section in the AA of the electronic device shown by Fig.1 (a). (a)は本発明の実施形態における電子素子搭載用基板を示す平面透視図であり、(b)は図2(a)に示された電子素子搭載用基板のA−A線における縦断面図を示している。(A) is a plane perspective view which shows the board | substrate for electronic element mounting in embodiment of this invention, (b) is a longitudinal cross-sectional view in the AA line of the board | substrate for electronic element mounting shown to Fig.2 (a). Is shown. は本発明の実施形態における電子素子搭載用基板の縦断面図の変形例を示している。These show the modification of the longitudinal cross-sectional view of the board | substrate for electronic element mounting in embodiment of this invention. は本発明の実施形態における電子素子搭載用基板の縦断面図の変形例を示している。These show the modification of the longitudinal cross-sectional view of the board | substrate for electronic element mounting in embodiment of this invention. は本発明の実施形態における電子素子搭載用基板の縦断面図の変形例を示している。These show the modification of the longitudinal cross-sectional view of the board | substrate for electronic element mounting in embodiment of this invention. は本発明の実施形態における電子素子搭載用基板の縦断面図の変形例を示している。These show the modification of the longitudinal cross-sectional view of the board | substrate for electronic element mounting in embodiment of this invention. は本発明の実施形態における電子素子搭載用基板の縦断面図の変形例を示している。These show the modification of the longitudinal cross-sectional view of the board | substrate for electronic element mounting in embodiment of this invention. (a)は本発明の実施形態における電子素子搭載用基板の変形例を示す平面透視図であり、(b)は図8(a)に示された電子素子搭載用基板のA−A線における縦断面図を示している。(A) is a plane perspective view which shows the modification of the electronic element mounting board | substrate in embodiment of this invention, (b) is in the AA line of the electronic element mounting board | substrate shown by Fig.8 (a). A longitudinal sectional view is shown. (a)は本発明の他の実施形態における電子装置を示す平面透視図であり、(b)は図9(a)に示された電子装置のA−A線における縦断面図を示している。(A) is a plane perspective view which shows the electronic device in other embodiment of this invention, (b) has shown the longitudinal cross-sectional view in the AA line of the electronic device shown by Fig.9 (a). .

以下、本発明の例示的な実施形態について図面を参照して説明する。   Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings.

図1に示されているように、本実施形態における電子装置は、電子素子搭載用基板1と、電子素子搭載用基板1に実装された電子素子11を有している。   As shown in FIG. 1, the electronic device according to this embodiment includes an electronic element mounting substrate 1 and an electronic element 11 mounted on the electronic element mounting substrate 1.

本実施形態における電子素子搭載用基板1は、枠部2aを有する絶縁基体2と、枠部2aの上面に設けられた複数の電極パッド3と、枠部2aに設けられた第1の導体部5aおよび第1の導体部5aの幅より狭い幅をもつ第2の導体部5bを有しているビア導体5と、絶縁基体2に設けられた配線導体6とを有している。   An electronic element mounting substrate 1 according to the present embodiment includes an insulating base 2 having a frame portion 2a, a plurality of electrode pads 3 provided on the upper surface of the frame portion 2a, and a first conductor portion provided on the frame portion 2a. 5a and a via conductor 5 having a second conductor portion 5b having a width narrower than that of the first conductor portion 5a, and a wiring conductor 6 provided on the insulating base 2.

絶縁基体2は、例えば枠部2aおよび基部2bを有し、例えば、酸化アルミニウム質焼結体,ムライト質焼結体,炭化珪素質焼結体,窒化アルミニウム質焼結体,窒化珪素質焼結体,ガラスセラミックス焼結体等の電気絶縁性セラミックス、またはエポキシ樹脂,ポリイミド樹脂,アクリル樹脂,フェノール樹脂,ポリエステル樹脂または四フッ化エチレン樹脂を始めとするフッ素系樹脂等の樹脂(プラスティックス)から成る略四角形の絶縁層を複数上下に積層して形成されている。   The insulating base 2 has, for example, a frame 2a and a base 2b. For example, an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, and a silicon nitride sintered body. Body, electrically insulating ceramics such as sintered glass ceramics, or resins (plastics) such as epoxy resin, polyimide resin, acrylic resin, phenol resin, polyester resin or tetrafluoroethylene resin A plurality of substantially rectangular insulating layers are stacked one above the other.

複数の電極パッド3は、絶縁基体2の枠部2aの上面に設けられており、図1に示される例では、ボンディングワイヤ11a等により電子素子11の各電極にそれぞれ電気的に接続されている。電極パッド3は、絶縁基体2が電気絶縁性セラミックスから成る場合には、タングステン(W),モリブデン(Mo),マンガン(Mn),銀(Ag)または銅(Cu)等のメタライズから成る。   The plurality of electrode pads 3 are provided on the upper surface of the frame portion 2a of the insulating base 2. In the example shown in FIG. 1, each electrode pad 3 is electrically connected to each electrode of the electronic element 11 by a bonding wire 11a or the like. . When the insulating base 2 is made of an electrically insulating ceramic, the electrode pad 3 is made of metallization such as tungsten (W), molybdenum (Mo), manganese (Mn), silver (Ag), or copper (Cu).

また、電極パッド3は、絶縁基体2が樹脂から成る場合には、銅(Cu),金(Au)
,アルミニウム(Al),ニッケル(Ni),クロム(Cr),モリブデン(Mo)またはチタン(Ti)およびそれらの合金等の金属材料から成る。
The electrode pad 3 is made of copper (Cu), gold (Au) when the insulating base 2 is made of resin.
, Aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), and alloys thereof.

本実施形態の電子素子搭載用基板1は、絶縁基体2の枠部2aの内壁面または内部に、複数の電極パッド3のそれぞれに電気的に接続された複数のビア導体5を有している。ビア導体5は、第1の導体部5aと第1の導体部5aの上端または下端に接続されて、第1の導体部5aよりも狭い幅を有している第2の導体部5bとを含んでいる。隣り合うビア導体5同士の第1の導体部5aと第2の導体部5bとは同じ高さ位置に並ぶように配置されており、隣り合うビア導体5の第2の導体部5bの一部B同士が同じ高さ位置にならんでいる。また、第2の導体部5bの一部B同士の間隔が隣り合うビア導体5の第1の導体部5aと第2の導体部5bとの間隔より大きくなるように設けられている。このように、ビア導体5を幅の違う第1の導体部5aと第2の導体部5bとで形成し、隣り合うビア導体5同士の間隔を広げることにより、例えば、電子素子搭載用基板1が小型化し、絶縁基体2の枠部2aが小型化したとしても隣り合うビア導体5の間にクラックが入ることを抑制することが可能となる。   The electronic element mounting substrate 1 of the present embodiment has a plurality of via conductors 5 electrically connected to each of the plurality of electrode pads 3 on the inner wall surface or inside of the frame portion 2 a of the insulating base 2. . The via conductor 5 includes a first conductor portion 5a and a second conductor portion 5b connected to the upper end or the lower end of the first conductor portion 5a and having a width narrower than that of the first conductor portion 5a. Contains. The first conductor portion 5a and the second conductor portion 5b of the adjacent via conductors 5 are arranged so as to be aligned at the same height, and a part of the second conductor portion 5b of the adjacent via conductor 5 B are lined up at the same height. Further, the second conductor portions 5b are provided such that the distance between the portions B of the second conductor portions 5b is larger than the distance between the first conductor portions 5a and the second conductor portions 5b of the adjacent via conductors 5. As described above, the via conductor 5 is formed of the first conductor portion 5a and the second conductor portion 5b having different widths, and the interval between the adjacent via conductors 5 is increased, for example, the electronic element mounting substrate 1 However, even if the frame portion 2a of the insulating base 2 is reduced in size, it is possible to prevent cracks from occurring between the adjacent via conductors 5.

なお、ビア導体5は、絶縁基体2が電気絶縁性セラミックスから成る場合は、電極パッド3と同様のメタライズから成る。また、ビア導体5は、絶縁基体2が樹脂から成る場合には、銅,金,アルミニウム,ニッケル,クロム,モリブデン,チタンおよびそれらの合金等の金属材料から成る。   The via conductor 5 is made of metallization similar to the electrode pad 3 when the insulating base 2 is made of electrically insulating ceramics. Further, when the insulating base 2 is made of resin, the via conductor 5 is made of a metal material such as copper, gold, aluminum, nickel, chromium, molybdenum, titanium, or an alloy thereof.

図1に示された例では、電子素子搭載用基板1に電子素子11が実装されている例である。電子素子11は、絶縁基体2の枠部2aおよび基部2bから形成される凹部に収納されており、枠部2aの上面に設けられている複数の電極パッド3とボンディングワイヤ11aを介して実装されている電子装置である。このように、本発明の電子素子搭載用基板1に電子素子11を実装していることで、電子装置を小型化した場合においても、実装時や電子装置作動時の熱によるクラックが発生しにくいものとなる。そのため、より信頼性の高い電子装置とすることが可能となる。   In the example shown in FIG. 1, an electronic element 11 is mounted on the electronic element mounting substrate 1. The electronic element 11 is housed in a recess formed from the frame 2a and the base 2b of the insulating base 2, and is mounted via a plurality of electrode pads 3 provided on the upper surface of the frame 2a and bonding wires 11a. Electronic device. As described above, since the electronic element 11 is mounted on the electronic element mounting substrate 1 of the present invention, even when the electronic device is downsized, cracks due to heat during mounting or operation of the electronic device are less likely to occur. It will be a thing. Therefore, it is possible to obtain a more reliable electronic device.

図2に示された例では、複数のビア導体5は、隣り合うビア導体5において、第1の導体部5a同士が異なる高さ位置に配置されている。このことにより、第2の導体部5bより広い幅を有している第1の導体部5a同士が同じ高さ位置で隣り合うことはなく、隣り合うビア導体5同士がより離間するものとなり、ビア導体5の間にクラックが発生することを効果的に抑制することが可能となる。   In the example shown in FIG. 2, the plurality of via conductors 5 are arranged at different height positions in the adjacent via conductors 5 where the first conductor portions 5 a are different from each other. Thus, the first conductor portions 5a having a width wider than the second conductor portion 5b are not adjacent to each other at the same height position, and the adjacent via conductors 5 are further separated from each other, It is possible to effectively suppress the occurrence of cracks between the via conductors 5.

また、隣り合うビア導体5の第1の導体部5aの高さの差は、40μm〜100μm程度設
けておくと、より良好に抑制することが可能となる。
Further, the difference in height between the first conductor portions 5a of the adjacent via conductors 5 can be suppressed more satisfactorily by providing about 40 μm to 100 μm.

また、隣り合うビア導体のいずれか一方、あるいは両方の幅を小さくする場合と比較して、隣り合うビア導体5のいずれか一方、あるいは両方の電気抵抗値が小さくなったり、ビア導体5が枠体2から脱落することを抑制することができる。また、第2の導体部5bの大きさは、平面視で第1の導体部5aの大きさの20%〜80%程度にしておくことが好ましい。   Further, compared to the case where the width of either one or both of the adjacent via conductors is reduced, the electrical resistance value of either one or both of the adjacent via conductors 5 becomes smaller, or the via conductor 5 has a frame. Dropping from the body 2 can be suppressed. The size of the second conductor portion 5b is preferably set to about 20% to 80% of the size of the first conductor portion 5a in plan view.

ビア導体5は絶縁基体2の枠部2aの内壁面に露出していると、電極パッド3や配線導体6と同様に、露出する表面に酸化防止のためのNiやAu等のめっき層を被着させて、ビア導体5の電気抵抗値を下げることができるので好ましい。また、ビア導体5が、枠部2の内壁面側に偏倚して配置させて、枠部2a内にビア導体5が占める割合を小さくすることができるので、絶縁基体2内に設けられる配線導体6の設計を容易とすることができ、電子素子搭載用基板の小型化、高密度配線化を図ることができる。また、平面視におい
て、ビア導体5が、枠部2の内壁面側に偏倚して配置させているので、電極パッド3のボンディングワイヤ11aとの接続領域をビア導体5よりも枠体2の外壁面側に広く形成することができ、電極パッド3とボンディングワイヤ11aとを良好に接続することが可能となる。
If the via conductor 5 is exposed on the inner wall surface of the frame portion 2a of the insulating base 2, the exposed surface is covered with a plating layer such as Ni or Au for preventing oxidation like the electrode pad 3 and the wiring conductor 6. This is preferable because the electrical resistance value of the via conductor 5 can be lowered. In addition, since the via conductor 5 can be biased and arranged on the inner wall surface side of the frame portion 2 to reduce the proportion of the via conductor 5 in the frame portion 2a, the wiring conductor provided in the insulating base 2 can be reduced. 6 can be facilitated, and the electronic element mounting substrate can be miniaturized and the wiring density can be increased. Further, in the plan view, the via conductor 5 is arranged to be biased toward the inner wall surface side of the frame portion 2, so that the connection region of the electrode pad 3 with the bonding wire 11 a is more outside the frame body 2 than the via conductor 5. It can be widely formed on the wall surface side, and the electrode pad 3 and the bonding wire 11a can be connected well.

また、絶縁基体2において、例えば枠部2aおよび基部2bに、ビア導体5に電気的に接続され、基部2bの下面に導出された配線導体6が設けられている。配線導体6は、ビア導体5に電気的に接続された内部配線と、枠部2aおよび基部2bを厚み方向に貫通しており、内部配線に電気的に接続された貫通導体と、基部2bの下面に設けられており、貫通導体に電気的に接続された外部端子とを含んでいる。これにより、電極パッド3がビア導体5および配線導体6を介して外部回路21に電気的に接続される。なお、配線導体6は、絶縁基体2が電気絶縁性セラミックスから成る場合は、電極パッド3と同様のメタライズから成る。また、配線導体6は、上述の構成においては絶縁基体2の下面に導出されるように設けられているが、例えば絶縁基体2の側面または上面に導出されるように設けられていてもよい。   In addition, in the insulating base 2, for example, a frame conductor 2a and a base 2b are provided with a wiring conductor 6 that is electrically connected to the via conductor 5 and led out to the lower surface of the base 2b. The wiring conductor 6 penetrates the internal wiring electrically connected to the via conductor 5, the frame portion 2 a and the base portion 2 b in the thickness direction, and the through-conductor electrically connected to the internal wiring and the base portion 2 b An external terminal is provided on the lower surface and electrically connected to the through conductor. As a result, the electrode pad 3 is electrically connected to the external circuit 21 via the via conductor 5 and the wiring conductor 6. The wiring conductor 6 is made of metallization similar to the electrode pad 3 when the insulating base 2 is made of electrically insulating ceramics. Further, in the configuration described above, the wiring conductor 6 is provided so as to be led out to the lower surface of the insulating base 2, but may be provided so as to be led out to the side surface or the upper surface of the insulating base 2, for example.

配線導体6は絶縁基体2が電気絶縁性セラミックスから成る場合は、電極パッド3と同様のメタライズから成る。また、配線導体6は、絶縁基体2が樹脂から成る場合には、銅,金,アルミニウム,ニッケル,クロム,モリブデン,チタンおよびそれらの合金等の金属材料から成る。   The wiring conductor 6 is made of metallization similar to the electrode pad 3 when the insulating base 2 is made of electrically insulating ceramics. Further, when the insulating base 2 is made of resin, the wiring conductor 6 is made of a metal material such as copper, gold, aluminum, nickel, chromium, molybdenum, titanium and alloys thereof.

図3に示された例では、第1の導体部5aが絶縁基体2の枠部2aの高さ方向の中央Nを跨がないように形成されている。このことにより、隣り合うビア導体5の一方の第1の導体部5aのみを大きくする場合と比較し、隣り合うビア導体5の体積の差が大きくなることを抑制するので、それぞれのビア導体5の電気抵抗値の差が大きくなることを抑制することができる。   In the example shown in FIG. 3, the first conductor portion 5 a is formed so as not to straddle the center N in the height direction of the frame portion 2 a of the insulating base 2. This suppresses an increase in the volume difference between the adjacent via conductors 5 as compared with the case where only one of the first conductor portions 5a of the adjacent via conductors 5 is increased. An increase in the difference in electrical resistance value can be suppressed.

図4に示された例では、絶縁基体2の枠部2aを形成する絶縁層4が枠部2aの高さ方向の中央Nで線対称となっている。また、隣り合うビア導体5同士は反転したら同じ形状となるように設けられている。このことにより、枠部2aの上面と下面とで、ビア導体5を形成するメタライズの量を同等にすることで、電子素子を実装する時の熱や電子素子が動作した際発生した熱による熱収縮および熱膨張を枠部2aの上面側と下面側とで同等にすることができ、枠部2aの一部だけの変形を低減させて、クラックの発生をより低減することができる。さらにそれぞれのビア導体5の電気抵抗値を同等にすることも容易となる。なお、絶縁基体2が電気絶縁性セラミックスから形成される場合、枠部2aの上面側と下面側とでビア導体5を形成するメタライズの量を同等にすることで、製造工程時の枠部2aの変形を低減することが可能となる。   In the example shown in FIG. 4, the insulating layer 4 forming the frame 2 a of the insulating base 2 is line symmetric at the center N in the height direction of the frame 2 a. Further, adjacent via conductors 5 are provided so as to have the same shape when inverted. Thus, by equalizing the amount of metallization forming the via conductor 5 between the upper surface and the lower surface of the frame portion 2a, heat due to heat generated when the electronic element is mounted or heat generated when the electronic element is operated. Shrinkage and thermal expansion can be made equal between the upper surface side and the lower surface side of the frame portion 2a, and deformation of only a part of the frame portion 2a can be reduced to further reduce the occurrence of cracks. Furthermore, it is easy to make the electrical resistance values of the respective via conductors 5 equal. When the insulating base 2 is formed of an electrically insulating ceramic, the amount of metallization for forming the via conductors 5 on the upper surface side and the lower surface side of the frame portion 2a is made equal, so that the frame portion 2a during the manufacturing process is made. It becomes possible to reduce the deformation.

図5に示された例では、第2の導体部5bに設けられており、隣接する第1の導体部5aと第2の導体部5bとの接続箇所と同じ高さに設けられ、厚み方向に接続しているビア導体5同士を良好に接続するために設けられているランド6aを有しており、ランド6aは縦断面視において第1の導体部5aの幅より狭くなっている。このことにより、第1の導体部5aと第2の導体部5bとの間隔を広くするために第2の導体部5bを細いものにしたとしても、ランド6aにより第2の導体部5b同士の電気的接続を良好にするとともに、第1の導体部5aと第2の導体部5bとの間で短絡が発生することを抑制することができる。ランド6aは、電極パッド3と同様の材料および方法から形成される。   In the example shown in FIG. 5, the second conductor portion 5 b is provided at the same height as the connection portion between the adjacent first conductor portion 5 a and the second conductor portion 5 b, in the thickness direction. The via conductors 5 connected to each other have a land 6a provided for good connection, and the land 6a is narrower than the width of the first conductor portion 5a in a longitudinal sectional view. As a result, even if the second conductor 5b is made thin in order to widen the distance between the first conductor 5a and the second conductor 5b, the land 6a can prevent the second conductor 5b from While making electrical connection favorable, it can suppress that a short circuit generate | occur | produces between the 1st conductor part 5a and the 2nd conductor part 5b. The land 6 a is formed from the same material and method as the electrode pad 3.

図6に示された例では、第2の導体5bが第1の導体5aから離れるに従って、幅が広くなっている。また、第2の導体部5bの最も広い幅は第1の導体部5aの幅よりも小さい。このことにより、クラックの発生の起点となりやすい第2の導体部5bと接続してい
る側の第1導体部5aの角部と隣り合うビア導体5の第2の導体部5bとの距離を広くすることができる。また、第2の導電部5bと電極パッド3とが接続される際、接合部分の第2の導電部5bが広くなるため、電極パッド3とビア導体5との接続を良好に行うことができる。また、第1の導体部5aも同様に第2の導体5bから離れる従って、幅が広くなっていてもかまわない。
In the example shown in FIG. 6, the width is increased as the second conductor 5b is separated from the first conductor 5a. The widest width of the second conductor portion 5b is smaller than the width of the first conductor portion 5a. As a result, the distance between the corner portion of the first conductor portion 5a on the side connected to the second conductor portion 5b, which is likely to be the starting point of cracks, and the second conductor portion 5b of the adjacent via conductor 5 is increased. can do. Further, when the second conductive portion 5b and the electrode pad 3 are connected, the second conductive portion 5b at the joint portion is widened, so that the connection between the electrode pad 3 and the via conductor 5 can be satisfactorily performed. . Similarly, the first conductor portion 5a is also separated from the second conductor 5b, so that the width may be increased.

図7に示された例では、ビア導体5の左端の第1の導体部5aの中心が第2の導体部5bの中心からずれて配置されている。第1の導体部5aと第2の導体部5bとは偏心して配置してもよい。このことによって、例えば、ビア導体5が信号回路の役割を持っていた際、第1の導体部5aの幅の範囲内にて第2の導体部5bと隣り合うビア導体5との間の距離を変更することができ、インピーダンスの整合を容易に行うことができる。   In the example shown in FIG. 7, the center of the first conductor portion 5a at the left end of the via conductor 5 is arranged so as to be shifted from the center of the second conductor portion 5b. The first conductor portion 5a and the second conductor portion 5b may be arranged eccentrically. Thus, for example, when the via conductor 5 has a role of a signal circuit, the distance between the second conductor portion 5b and the adjacent via conductor 5 within the range of the width of the first conductor portion 5a. Thus, impedance matching can be easily performed.

図8に示された例では、ビア導体5は、枠部2aの内部に設けられている。また、隣接するビア導体5の一方のビア導体5は枠部2aの上面と下面側とに第1の導体部5aを有しており、他方のビア導体5は枠部2aの中間部分に第1の導体部5aを有している。このような形状でビア導体5を設け、一方のビア導体5の第1の導体部5aの体積の総和と他方のビア導体5の第1の導体部5aの体積とを等しくすることにより、隣り合うビア導体5同士の間隔を広くし、クラックの発生を抑制するとともに隣り合うビア導体5同士の電気抵抗値を同等にすることが容易となる。   In the example shown in FIG. 8, the via conductor 5 is provided inside the frame 2a. In addition, one via conductor 5 of the adjacent via conductor 5 has a first conductor portion 5a on the upper surface and the lower surface side of the frame portion 2a, and the other via conductor 5 is formed in the middle portion of the frame portion 2a. 1 conductor portion 5a. By providing the via conductor 5 in such a shape and making the sum of the volumes of the first conductor portions 5a of one via conductor 5 equal to the volume of the first conductor portion 5a of the other via conductor 5, It is easy to widen the interval between the matching via conductors 5 to suppress the occurrence of cracks and to equalize the electrical resistance values of the adjacent via conductors 5.

図9に示された例では、枠部2aの上面に電子素子11がフリップチップ実装され、電子素子11が実装された電子装置は外部回路21に電子素子と同じ面高さで接合されている。電子素子11の各電極は金バンプ、はんだ等の接続端子11bにより電極パッド3に電気的に接続され、電子装置と外部回路21とははんだ等の導電性の接合材22で接合されている。電子素子11が例えばCCD型撮像素子またはCMOS型撮像素子の場合、電子装置の上方からの光が電子素子11で受像される。また、電子素子11をフリップチップ実装した部位にいわゆるアンダーフィルとして例えばエポキシ樹脂等の樹脂からなる接合材22を用いて、電気的接続をより確実なものとしてもよい。なお、電子素子11の各電極と複数の電極パッド3との電気的な接続や電子装置と外部回路21との電気的な接続に、上述の金バンプまたははんだ等の接続端子11bやはんだ等の接合材22を用いる代わりに導電性樹脂(異方性導電樹脂等)から成る接続部材を用いてもよい。このような本実施形態の電子素子搭載用基板1を用いた電子装置は、電子素子を実装する際や、製品を使用した際に発生する熱などによるクラックの発生を抑制できる信頼性の高い電子装置となる。また、基部2bを有しない枠部2aの電子素子搭載用基板1を外部回路21等に接続しているため、薄型化を図ることができる。   In the example shown in FIG. 9, the electronic element 11 is flip-chip mounted on the upper surface of the frame portion 2a, and the electronic device on which the electronic element 11 is mounted is joined to the external circuit 21 at the same surface height as the electronic element. . Each electrode of the electronic element 11 is electrically connected to the electrode pad 3 by connection terminals 11b such as gold bumps and solder, and the electronic device and the external circuit 21 are joined by a conductive joining material 22 such as solder. When the electronic element 11 is, for example, a CCD image sensor or a CMOS image sensor, light from above the electronic device is received by the electronic element 11. Moreover, it is good also as a more reliable electrical connection using the joining material 22 which consists of resin, such as an epoxy resin, as what is called an underfill in the site | part which carried out the flip chip mounting of the electronic element 11. FIG. For the electrical connection between each electrode of the electronic element 11 and the plurality of electrode pads 3 and the electrical connection between the electronic device and the external circuit 21, the connection terminals 11b such as the above-described gold bump or solder, solder, etc. Instead of using the bonding material 22, a connecting member made of conductive resin (anisotropic conductive resin or the like) may be used. Such an electronic device using the electronic element mounting substrate 1 of the present embodiment is a highly reliable electron that can suppress the generation of cracks due to heat generated when the electronic element is mounted or a product is used. It becomes a device. Further, since the electronic element mounting substrate 1 of the frame portion 2a that does not have the base portion 2b is connected to the external circuit 21 or the like, the thickness can be reduced.

次に、本実施形態の電子素子搭載用基板1の製造方法について説明する。   Next, a method for manufacturing the electronic element mounting substrate 1 of the present embodiment will be described.

絶縁基体2は、例えば酸化アルミニウム(Al)質焼結体等の電気絶縁性セラミックスからなり、例えば枠部2aおよび基部2bを有している。この絶縁基体2は、主成分が酸化アルミニウム(Al)である酸化アルミニウム質焼結体から成る場合、Alの粉末に焼結助材としてシリカ(SiO),マグネシア(MgO)またはカルシア(CaO)等の粉末を添加し、さらに適当なバインダー、溶剤および可塑剤を添加し、次にこれらの混合物を混錬してスラリー状となす。その後、従来周知のドクターブレード法またはカレンダーロール法等の成形方法によって多数個取り用のセラミックグリーンシートを得る。 The insulating base 2 is made of an electrically insulating ceramic such as an aluminum oxide (Al 2 O 3 ) -based sintered body, and has a frame portion 2a and a base portion 2b, for example. When the insulating base 2 is made of an aluminum oxide sintered body whose main component is aluminum oxide (Al 2 O 3 ), silica (SiO 2 ), magnesia (MgO) is used as a sintering aid for Al 2 O 3 powder. ) Or calcia (CaO) or the like, and further an appropriate binder, solvent and plasticizer are added, and then the mixture is kneaded to form a slurry. Thereafter, a ceramic green sheet for multi-piece production is obtained by a conventionally known forming method such as a doctor blade method or a calender roll method.

このセラミックグリーンシートを用いて、以下の(1)〜(6)の工程により電子素子搭載用パッケージ1が作製される。   Using this ceramic green sheet, the electronic device mounting package 1 is manufactured by the following steps (1) to (6).

(1)枠部2aの上面となる部位に形成される電極パッド3、枠部2aに第1の導体部5aと第2の導体部5bと配線導体6とをそれぞれ形成するための金属ペーストをセラミックグリーンシートに印刷塗布する工程と、枠部2aおよび基部2bの所定の部位に配線導体6をそれぞれ形成するための金属ペーストをセラミックグリーンシートに印刷塗布する工程。   (1) An electrode pad 3 formed on the upper surface of the frame portion 2a, and a metal paste for forming the first conductor portion 5a, the second conductor portion 5b, and the wiring conductor 6 on the frame portion 2a. A step of printing and applying to the ceramic green sheet, and a step of printing and applying to the ceramic green sheet a metal paste for forming the wiring conductors 6 at predetermined portions of the frame portion 2a and the base portion 2b.

(2)枠部2aの各絶縁層となるセラミックグリーンシートを積層して第1の導体部5aの金属ペーストと第2の導体部5bの金属ペーストとが互いに重なるようにしてビア導体5となる金属ペーストを有する積層体を形成する工程。   (2) The ceramic green sheets to be the respective insulating layers of the frame portion 2a are laminated to form the via conductor 5 so that the metal paste of the first conductor portion 5a and the metal paste of the second conductor portion 5b overlap each other. Forming a laminate having a metal paste;

図3に示された例のように、枠部2aは、3層以上の絶縁層からなるものであってもよく、積層体は絶縁層の層数に合せて積層されて形成される。   As in the example shown in FIG. 3, the frame portion 2 a may be composed of three or more insulating layers, and the laminate is formed by being laminated in accordance with the number of insulating layers.

(3)ビア導体5が露出するようにして形成するための枠部2aの内壁面となる部位の打ち抜き金型を用いた打ち抜きまたはレーザー加工工程。   (3) A punching or laser processing step using a punching die at a portion that becomes the inner wall surface of the frame portion 2a for forming the via conductor 5 so as to be exposed.

(4)枠部2aとなるセラミックグリーンシートを積層した積層体と基部2bとなるセラミックグリーンシートとを積層してセラミックグリーンシート積層体を作製する工程。   (4) The process of producing the ceramic green sheet laminated body by laminating | stacking the laminated body which laminated | stacked the ceramic green sheet used as the frame part 2a, and the ceramic green sheet used as the base 2b.

なお、基部2bは、複数枚のセラミックグリーンシートを積層した積層体であっても構わない。   The base 2b may be a laminated body in which a plurality of ceramic green sheets are laminated.

(5)このセラミックグリーンシート積層体を約1500〜1800℃の温度で焼成して、各基部2bと各枠部2aの内壁面に露出したビア導体5および電極パッド3ならびに配線導体6を有する絶縁基体2が複数配列された多数個取り基板を得る工程。   (5) This ceramic green sheet laminate is fired at a temperature of about 1500 to 1800 ° C., and has insulation having via conductors 5, electrode pads 3, and wiring conductors 6 exposed on the inner wall surfaces of the base portions 2 b and the frame portions 2 a. A step of obtaining a multi-piece substrate in which a plurality of substrates 2 are arranged.

(6)焼成して得られた多数個取り基板に電子素子搭載用基板1の外縁となる箇所に沿って分割溝を形成しておき、この分割溝に沿って破断させて分割する方法、またはスライシング法等により電子素子搭載用基板1の外縁となる箇所に沿って切断する工程。   (6) A method in which a dividing groove is formed along a portion serving as the outer edge of the electronic element mounting substrate 1 on the multi-piece substrate obtained by baking, and the dividing is performed by breaking along the dividing groove, or A step of cutting along the outer edge of the electronic element mounting substrate 1 by a slicing method or the like.

なお、分割溝は、焼成後にスライシング装置により多数個取り基板の厚みより小さく切り込むことによって形成することができるが、多数個取り基板用の生成形体にカッター刃を押し当てたり、スライシング装置により生成形体の厚みより小さく切り込んだりすることによって形成してもよい。   The dividing grooves can be formed by cutting the multi-cavity substrate smaller than the thickness of the multi-cavity substrate after firing, but the cutter blade is pressed against the multi-cavity substrate generation shape or the slicing device generates the It may be formed by cutting smaller than the thickness.

上述の(1)の工程において、電極パッド3および配線導体6は、絶縁基体2用のセラミックグリーンシートに金属ペーストスクリーン印刷法等によって所定形状で印刷して、絶縁基体2用のセラミックグリーンシートと同時に焼成することによって、複数の絶縁基体2のそれぞれの所定位置に形成される。配線導体6のうち、セラミックグリーンシートを厚み方向に貫通する貫通配線導体は、金属ペーストを印刷することによってセラミックグリーンシートに形成した貫通孔を充填しておけばよい。このような金属ペーストは、タングステン,モリブデン,マンガン,銀または銅等の金属粉末に適当な溶剤およびバインダーを加えて混練することによって、適度な粘度に調整して作製される。なお、金属ペーストは、絶縁基体2との接合強度を高めるために、ガラス、セラミックスを含んでいても構わない。   In the step (1) described above, the electrode pad 3 and the wiring conductor 6 are printed on the ceramic green sheet for the insulating base 2 in a predetermined shape by a metal paste screen printing method or the like, By baking simultaneously, it forms in each predetermined position of the some insulation base | substrate 2. FIG. Of the wiring conductors 6, the through wiring conductors that penetrate the ceramic green sheet in the thickness direction may be filled with through holes formed in the ceramic green sheet by printing a metal paste. Such a metal paste is prepared by adjusting an appropriate viscosity by adding an appropriate solvent and binder to a metal powder such as tungsten, molybdenum, manganese, silver or copper and kneading them. The metal paste may contain glass or ceramics in order to increase the bonding strength with the insulating substrate 2.

また、枠部2aに露出したビア導体5は、ビア導体5用の金属ペーストをスクリーン印刷法等によって印刷することによってセラミックグリーンシートに形成した貫通孔を充填した後の、上述の(3)の工程の打ち抜きまたはレーザー加工時に、ビア導体5が露出するように枠部2a用の貫通孔を形成して、セラミックグリーンシートと同時に焼成するこ
とによって形成される。上述の金属ペースト、電極パッド3に用いた金属ペーストと同様の方法により作製され、絶縁基体2との接合強度を高めるために、ガラスまたはセラミックスを含んでいても構わない。
The via conductor 5 exposed in the frame 2a is filled with the through hole formed in the ceramic green sheet by printing a metal paste for the via conductor 5 by a screen printing method or the like. At the time of stamping or laser processing, a through hole for the frame portion 2a is formed so that the via conductor 5 is exposed, and is fired simultaneously with the ceramic green sheet. In order to increase the bonding strength with the insulating substrate 2, it may be produced by the same method as the above-described metal paste and the metal paste used for the electrode pad 3.

また、上述の(3)の工程において、枠部2aを含んでいる絶縁基体2を形成するには、上述の打ち抜きまたはレーザー加工時に、絶縁基体2用のセラミックグリーンシートのいくつかに、枠部2a用の貫通孔を金型、パンチングによる打ち抜きまたはレーザー加工等により形成しておけばよい。   Further, in the step (3) described above, in order to form the insulating substrate 2 including the frame portion 2a, the frame portion is added to some of the ceramic green sheets for the insulating substrate 2 during the punching or laser processing described above. The through hole for 2a may be formed by a die, punching by punching, laser processing or the like.

なお、絶縁基体2が、例えば樹脂から成る場合は、所定の形状に成形できるような金型を用いて、トランスファーモールド法またはインジェクションモールド法等によって成形することによって形成することができる。また、例えばガラスエポキシ樹脂のように、ガラス繊維から成る基材に樹脂を含浸させたものであってもよい。この場合は、ガラス繊維から成る基材にエポキシ樹脂の前駆体を含浸させ、このエポキシ樹脂前駆体を所定の温度で熱硬化させることによって形成することができる。   When the insulating substrate 2 is made of, for example, a resin, it can be formed by molding by a transfer molding method or an injection molding method using a mold that can be molded into a predetermined shape. Moreover, what impregnated resin to the base material which consists of glass fiber like glass epoxy resin, for example may be used. In this case, it can be formed by impregnating a substrate made of glass fiber with an epoxy resin precursor and thermally curing the epoxy resin precursor at a predetermined temperature.

また、電極パッド3および配線導体6は、絶縁基体2が樹脂から成る場合には、銅(Cu),金(Au),アルミニウム(Al),ニッケル(Ni),クロム(Cr),モリブデン(Mo)またはチタン(Ti)およびそれらの合金等の金属材料から成る。例えば、ガラスエポキシ樹脂から成る樹脂シート上に配線導体の形状に加工した銅箔を転写し、銅箔が転写された樹脂シートを積層して接着剤で接着することによって形成する。また、金属箔または金属柱を樹脂から成る絶縁基体に一体化させたり、絶縁基体2にスパッタリング法,蒸着法等またはめっき法等を用いて被着させたりして形成される。   The electrode pad 3 and the wiring conductor 6 are made of copper (Cu), gold (Au), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo) when the insulating base 2 is made of resin. ) Or titanium (Ti) and their alloys. For example, the copper foil processed into the shape of the wiring conductor is transferred onto a resin sheet made of glass epoxy resin, and the resin sheet on which the copper foil is transferred is laminated and bonded with an adhesive. Further, it is formed by integrating a metal foil or a metal column with an insulating base made of resin, or by depositing the insulating base 2 using a sputtering method, a vapor deposition method or a plating method.

また、ビア導体5および配線導体6の一部である貫通導体は、絶縁基体2が樹脂から成る場合には、銅,金,アルミニウム,ニッケル,クロム,モリブデン,チタンおよびそれらの合金等の金属材料から成る。例えば、ガラスエポキシ樹脂から成る樹脂シート上に配線導体6の形状に加工した銅箔を転写し、銅箔が転写された樹脂シートを積層して接着剤で接着することによって形成する。樹脂シートを厚み方向に貫通するビア導体5は、金属ペーストの印刷またはめっき法によって樹脂シートに形成した貫通孔の内面に形成するか、貫通孔を充填して形成すればよい。また、金属箔または金属柱を樹脂から成る絶縁基体に一体化させたり、絶縁基体2にスパッタリング法,蒸着法等またはめっき法等を用いて被着させたりして形成される。   In addition, the through conductor which is a part of the via conductor 5 and the wiring conductor 6 is a metal material such as copper, gold, aluminum, nickel, chromium, molybdenum, titanium, and alloys thereof when the insulating base 2 is made of resin. Consists of. For example, the copper foil processed into the shape of the wiring conductor 6 is transferred onto a resin sheet made of glass epoxy resin, and the resin sheet on which the copper foil is transferred is laminated and bonded with an adhesive. The via conductor 5 penetrating the resin sheet in the thickness direction may be formed on the inner surface of the through hole formed in the resin sheet by printing or plating a metal paste, or may be formed by filling the through hole. Further, it is formed by integrating a metal foil or a metal column with an insulating base made of resin, or by depositing the insulating base 2 using a sputtering method, a vapor deposition method or a plating method.

また、電極パッド3、ビア導体5、配線導体6を保護して酸化防止をするために、電極パッド3、ビア導体5、配線導体6の露出した表面に、厚さ0.5〜10μmのNiめっき層を被着させるか、またはこのNiめっき層および厚さ0.5〜3μmの金(Au)めっき層を順次被着させてもよい。   Further, in order to protect the electrode pad 3, the via conductor 5, and the wiring conductor 6 and prevent oxidation, the Ni pad having a thickness of 0.5 to 10 μm is formed on the exposed surface of the electrode pad 3, the via conductor 5 and the wiring conductor 6. A plating layer may be deposited, or this Ni plating layer and a gold (Au) plating layer having a thickness of 0.5 to 3 μm may be sequentially deposited.

このようにして形成された電子素子搭載用基板1に、電子素子11が枠部2aの内側もしくは、下面に電子素子11を実装した電子装置を半田等の導電性の接合材22を介して外部回路21に搭載することで、電子素子11が電極パッド3、ビア導体5、配線導体6を介して外部回路21に電気的に接続される。電子素子11は例えば、CCD型撮像素子またはCMOS型撮像素子、半導体素子、LED等の発光素子等である。なお、電子素子11の各電極は、ボンディングワイヤ11aまたは金バンプ、はんだ等の接続端子11b等により電子素子搭載用パッケージ1の電極パッド3に電気的に接続されている。   An electronic device in which the electronic element 11 is mounted on the inner side or the lower surface of the frame portion 2a on the electronic element mounting substrate 1 thus formed is externally connected via a conductive bonding material 22 such as solder. By mounting on the circuit 21, the electronic element 11 is electrically connected to the external circuit 21 via the electrode pad 3, the via conductor 5, and the wiring conductor 6. The electronic element 11 is, for example, a CCD image sensor or a CMOS image sensor, a semiconductor element, a light emitting element such as an LED, or the like. Each electrode of the electronic element 11 is electrically connected to the electrode pad 3 of the electronic element mounting package 1 by a bonding wire 11a, a gold bump, a connection terminal 11b such as solder, or the like.

本実施形態の電子素子搭載用基板1は、絶縁基体2に設けられた複数のビア導体5を有しており、ビア導体5は第1の導体部5aと第1の導体部5aに接続されており第1の導体部5aよりも狭い幅を有している第2の導体部5bから形成される。ビア導体5は隣り
合うビア導体5において、第1の導体部5aと第2の導体部5bとが同じ高さ位置に並ぶように配置されており、ビア導体5の第2の導体部5bの一部B同士が同じ高さ位置に並んでいるとともに、第2の導体部5bの一部B同士の間隔が隣り合うビア導体5の第1の導体部5aと第2の導体部5bとの間隔より大きいことを特徴としている。これにより、電子素子搭載用基板1が小型化し、例えば、隣り合うビア導体5同士の間隔が狭くなったとしても、実装時や電子素子11が作動時に発生する熱により、隣接するビア導体の間にクラックが発生することを抑制することが可能となる。
The electronic element mounting substrate 1 of the present embodiment has a plurality of via conductors 5 provided on the insulating base 2, and the via conductors 5 are connected to the first conductor portion 5a and the first conductor portion 5a. The second conductor portion 5b has a narrower width than the first conductor portion 5a. The via conductor 5 is arranged so that the first conductor portion 5a and the second conductor portion 5b are arranged at the same height in the adjacent via conductors 5, and the via conductors 5 The portions B are arranged at the same height position, and the distance between the portions B of the second conductor portion 5b is between the first conductor portion 5a and the second conductor portion 5b of the adjacent via conductors 5b. It is characterized by being larger than the interval. As a result, the electronic element mounting substrate 1 is reduced in size, for example, even if the interval between the adjacent via conductors 5 is narrowed, the heat generated between the adjacent via conductors during mounting and the operation of the electronic element 11 may cause a gap between adjacent via conductors. It is possible to suppress the occurrence of cracks.

本発明の他の態様によれば、電子装置は上記構成の電子素子搭載用基板1を有していることによって、信頼性を保ったまま小型化が可能となるものである。   According to another aspect of the present invention, the electronic device includes the electronic element mounting substrate 1 having the above-described configuration, so that the electronic device can be downsized while maintaining reliability.

1・・・・電子素子搭載用基板
2・・・・絶縁基体
2a・・・枠部
2b・・・基部
3・・・・電極パッド
4・・・・絶縁層
5・・・・ビア導体
5a・・・第1の導体部
5b・・・第2の導体部
6・・・・配線導体
6a・・・ランド
11・・・電子素子
11a・・ボンディングワイヤ
11b・・接続端子
12・・・電子部品
21・・・外部回路
22・・・接合材
DESCRIPTION OF SYMBOLS 1 ... Electronic device mounting substrate 2 ... Insulation base 2a ... Frame part 2b ... Base part 3 ... Electrode pad 4 ... Insulating layer 5 ... Via conductor 5a ... 1st conductor part 5b ... 2nd conductor part 6 ... Wiring conductor 6a ... Land 11 ... Electronic element 11a ... Bonding wire 11b ... Connection terminal 12 ... Electron Component 21 ... External circuit 22 ... Bonding material

Claims (4)

絶縁基体と、
前記絶縁基体に設けられた複数のビア導体とを有し、
前記複数のビア導体のそれぞれは、第1の導体部と該第1の導体部に接続されており前記第1の導体部よりも狭い幅を有している第2の導体部とを含んでおり、
前記複数のビア導体は、隣り合うビア導体において、前記第1の導体部と前記第2の導体部とが同じ高さ位置に並ぶように配置されており、
前記隣り合うビア導体の前記第2の導体部の一部同士が同じ高さ位置に並んでいるとともに、前記第2の導体部の一部同士の間隔が前記隣り合うビア導体の前記第1の導体部と前記第2の導体部との間隔より大きいことを特徴とする電子素子搭載用基板。
An insulating substrate;
A plurality of via conductors provided on the insulating substrate;
Each of the plurality of via conductors includes a first conductor portion and a second conductor portion connected to the first conductor portion and having a narrower width than the first conductor portion. And
The plurality of via conductors are arranged such that in the adjacent via conductors, the first conductor portion and the second conductor portion are arranged at the same height position,
A part of the second conductor portions of the adjacent via conductors are arranged at the same height position, and a distance between a part of the second conductor portions is the first of the adjacent via conductors. An electronic element mounting substrate, wherein the distance between the conductor portion and the second conductor portion is larger.
前記複数のビア導体は、隣り合うビア導体において、前記第1の導体部同士が異なる高さ位置に配置されていることを特徴とする請求項1記載の電子素子搭載用基板。   2. The electronic device mounting board according to claim 1, wherein the plurality of via conductors are arranged at different height positions in adjacent via conductors, wherein the first conductor portions are different from each other. 平面透視において、前記複数のビア導体は、前記第1の導体部の中心と前記第2の導体部の中心とが異なる位置となるように配置されていることを特徴とする請求項1記載の電子素子搭載用基板。   The plurality of via conductors are arranged so that a center of the first conductor portion and a center of the second conductor portion are different from each other in a plan view. Electronic device mounting board. 請求項1に記載の電子素子搭載用基板と、
該電子素子搭載用基板に実装されており、前記複数のビア導体に電気的に接続された電子素子とを備えていることを特徴とする電子装置。
The electronic element mounting substrate according to claim 1;
An electronic device comprising: an electronic device mounted on the electronic device mounting board and electrically connected to the plurality of via conductors.
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