JP2014106322A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a load applied on gate wiring and prevent degradation in display quality due to lower contrast.SOLUTION: A liquid crystal display device 1 comprises: a liquid crystal layer 23 arranged between a first substrate 21 and a second substrate 22; a plurality of source wires 223 arranged so as to intersect with a plurality of gate wires 221 on a main surface 22a of the second substrate 22; a thin film transistor TFT having a semiconductor layer, a source electrode and a drain electrode for each pixel; a first insulator film 226 provided covering the semiconductor layer, the source electrode and the drain electrode; and a common electrode 227 generating an electric field between the common electrode and a signal electrode positioned at the pixel on the first insulator film 226. The semiconductor layer includes a channel region CH that is arranged on the gate wires 221 via a second insulator film 223 and contains a first conductivity type impurity. A second light-blocking film BM2 is provided on the channel region CH with a third insulator film 225 interposed therebetween. A first light-blocking film BM1 is provided on a main surface 21a of the first substrate 21 so as to overlap the gate wires 221.

Description

  The present invention relates to a liquid crystal display device used for various applications such as a mobile phone, a digital camera, a portable game machine, or a portable information terminal.

  The liquid crystal display device includes a pair of substrates facing each other and a liquid crystal layer interposed between the pair of substrates. On the main surface of one of the pair of substrates, a thin film transistor, a plurality of gate wirings, a plurality of source wirings provided so as to intersect the plurality of gate wirings, a thin film transistor, a plurality of gate wirings, and An insulating film provided so as to cover the plurality of source wirings, a signal electrode provided on the insulating film, and the like are formed.

  Further, there is a black matrix on array (hereinafter referred to as BOA) technique for forming a black matrix on one substrate side on which a thin film transistor or the like is formed (see Patent Document 1). In the BOA technique, a black matrix is formed on one substrate side so as to cover wiring such as thin film transistors and gate wiring.

JP 2006-301505 A

  However, since the black matrix is generally formed by containing carbon in an insulating material, the black matrix is unlikely to function as a complete insulator. For this reason, when the black matrix covers the gate wiring, the capacitance between the black matrix and the gate wiring increases, which may increase the load applied to the gate wiring.

  On the other hand, when the black matrix is provided only on the other substrate side, the black matrix is separated from the thin film transistor, so that the light reflected between the pair of substrates out of the external light and the light emitted from the light source device is a semiconductor in the thin film transistor. It becomes easy to enter the channel region of the layer. When light enters the channel region, a leak current is likely to be generated between the source region and the drain region due to the photoconductive effect. Due to this leakage current, the voltage of the image signal applied to the signal electrode through the thin film transistor fluctuates, and the brightness differs for each pixel, so that the contrast is lowered and the display quality can be lowered. There was a problem that there was.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce the load applied to the gate wiring and to suppress the deterioration of display quality due to the decrease of contrast.

  The liquid crystal display device according to the present invention includes a first substrate and a second substrate disposed so that main surfaces thereof are opposed to each other, a liquid crystal layer disposed between the first substrate and the second substrate, and the second substrate. A plurality of gate wirings provided on the main surface, a plurality of source wirings provided on the main surface of the second substrate so as to intersect the gate wirings, the gate wiring and the source A plurality of thin film transistors each including a semiconductor layer, a source electrode, and a drain electrode provided for each pixel surrounded by the wiring, and the second wiring so as to cover the plurality of gate wirings, the plurality of source wirings, and the plurality of thin film transistors. A first insulating film provided on the main surface of the substrate, a signal electrode located on the pixel and electrically connected to the thin film transistor on the first insulating film, and the signal electrode A common electrode for generating a boundary, and the semiconductor layer is located on the gate wiring via a second insulating film, and a channel region containing a first conductivity type impurity and the source electrode are located And a source region containing a second conductivity type impurity and a drain region where the drain electrode is located and containing a second conductivity type impurity, and the gate wiring is formed on the main surface of the first substrate. A first light-shielding film is provided so as to overlap the channel region, and a second light-shielding film is provided on the thin film transistor so as to overlap the channel region with a third insulating film interposed therebetween.

  According to the liquid crystal display device of the present invention, it is possible to reduce the load applied to the gate wiring and to suppress display quality due to a decrease in contrast.

It is a top view which shows the liquid crystal display device in the 1st Embodiment of this invention. It is sectional drawing along the II line | wire of FIG. It is a top view showing the wiring on the 2nd substrate in a pixel, an electrode, the 2nd light shielding film, and the 1st light shielding film on the 1st substrate. It is a top view showing the relationship between a thin-film transistor and a 2nd light shielding film. It is sectional drawing along the II-II line of FIG. It is sectional drawing along the III-III line of FIG. FIG. 4 is a sectional view taken along line IV-IV in FIG. 3. It is a top view which shows the liquid crystal display device in the 2nd Embodiment of this invention. FIG. 9 is a cross-sectional view illustrating a peripheral wiring, a contact hole, a thin film transistor, a fourth light shielding film, and a fifth light shielding film located in an outer region of the display region in the liquid crystal display device of FIG. 8. It is a top view showing the relationship between the thin-film transistor and the 5th light shielding film in the outer region of the display region.

[First Embodiment]
A liquid crystal display device 1 according to a first embodiment of the present invention will be described with reference to FIGS.

The liquid crystal display device 1 includes a liquid crystal panel 2 having a display area E _D composed of a plurality of pixels P, a light source apparatus 3 that emits light toward the liquid crystal panel 2, a first polarizing plate disposed on the liquid crystal panel 2 4 and a second polarizing plate 5 disposed between the liquid crystal panel 2 and the light source device 3.

  In the liquid crystal panel 2, the first substrate 21 and the second substrate 22 are arranged to face each other, and a liquid crystal layer 23 and a plurality of columnar spacers 24 are provided between the first substrate 21 and the second substrate 22. In addition, a sealing material 25 for joining the first substrate 21 and the second substrate 22 is provided so as to surround the plurality of columnar spacers 24.

  Each member of the liquid crystal panel 2 will be described with reference to FIGS.

  The first substrate 21 has a first main surface 21a used as a display surface when displaying an image, and a second main surface 21b located on the opposite side of the first main surface 21a. The first substrate 21 is made of, for example, glass or plastic.

On the second main surface 21b of the first substrate 21, a first light shielding film BM1, a color filter 211, and a first planarization film 212 are provided.

The first light shielding film BM1 has a function of shielding light. The first light shielding film BM1 is provided on the second main surface 21b of the first substrate 21. The first light shielding film BM1 is positioned so as to overlap the gate wiring 211, the contact holes C1 and C2, and the columnar spacer 24 in plan view. Examples of the material of the first light shielding film BM1 include a resin or a metal such as chromium to which a dye or pigment having a high light shielding property (for example, black) is added. As will be described in the second embodiment, the fourth light blocking film BM4 is arranged in the region located outside the display region E _D. In FIG. 3, a region overlapping with the first light shielding film BM1 is indicated by a hatched line (broken line).

The color filter 211 has a function of transmitting only a specific wavelength of visible light. The plurality of color filters 211 are located on the second main surface 21 b of the first substrate 21 and are provided for each pixel P. Each color filter 211 has one of red (R), green (G), and blue (B). Further, the color filter 211 is not limited to the above-described color, for example, yellow (
Y), white (W) and the like. Examples of the material of the color filter 211 include a resin to which a dye or pigment is added.

The first planarization film 212 covers the first substrate 21 so as to cover the color filter 211 and the first light shielding film BM1.
The second main surface 21b is provided. The first planarization film 212 is formed of an organic material,
An acrylic resin, an epoxy resin, a polyimide resin, etc. are mentioned. The film thickness of the first planarization film 212 is set in the range of 1 μm to 5 μm, for example.

  The second substrate 22 has a first main surface 22a facing the second main surface 21b of the first substrate 21, and a second main surface 22b located on the opposite side of the first main surface 22a. The second substrate 22 can be formed of the same material as the first substrate 21.

A plurality of gate wirings 221 and auxiliary capacitance wirings 222 are provided on the first main surface 22 a of the second substrate 22, and the gate insulating film 223 covers the plurality of gate wirings 221 and auxiliary capacitance wirings 222.
Is provided. A plurality of source wirings 224 are provided on the gate insulating film 223. An interlayer insulating film 225 is provided on the gate insulating film 223 so as to cover the plurality of source wirings 224. A second light shielding film BM2 and a third light shielding film BM3 are provided on the interlayer insulating film 225. A second planarization film 226 is provided on the interlayer insulating film 225 so as to cover the second light shielding film BM2 and the third light shielding film BM3. On the second planarizing film 226, a common electrode 227 and a signal electrode 228 are provided.

The gate wiring 221 has a function of applying a gate voltage supplied from a driving IC (not shown) to the thin film transistor TFT. As shown in FIG. 3, the gate wiring 221 is located on the first main surface 22 a of the second substrate 22 and extends in the X direction. In addition, a plurality of gate wirings 221
Are arranged along the Y direction. The gate wiring 221 is formed of a conductive material, for example, aluminum, molybdenum, titanium, neodymium, chromium, copper, or an alloy containing these.

  The gate wiring 221 is formed by the following method, for example.

  First, a material is formed as a film on the first main surface 22a of the second substrate 22 by sputtering, vapor deposition, or chemical vapor deposition. A photosensitive resin is applied to the surface of the film, and a pattern having a desired shape is formed on the photosensitive resin by performing an exposure process and a development process on the applied photosensitive resin. Next, this film is etched with an etching solution to obtain a desired shape, and then the applied photosensitive resin is peeled off. Thus, the gate wiring 221 can be formed by forming and patterning the material.

  The auxiliary capacitance line 222 is provided on the first main surface 22 a of the second substrate 22. The auxiliary capacitance line 222 is located on the same plane as the gate line 221. As shown in FIG. 3, the auxiliary capacitance line 222 extends in the X direction. Further, the auxiliary capacitance wiring 222 may be formed of the same material as the gate wiring 221. In the present embodiment, the auxiliary capacitance line 222 is formed on the same surface as the gate line 221, but the present invention is not limited to this. That is, the auxiliary capacitance line 222 may be formed in a different layer from the gate line 221.

The gate insulating film 223 covers the first main surface 22a so as to cover the gate wiring 221 and the auxiliary capacitance wiring 222.
It is provided above. The gate insulating film 223 is formed using an insulating material such as silicon nitride or silicon oxide. Note that the gate insulating film 223 is formed by the above sputtering method,
It can be formed on the first main surface 22a of the second substrate 22 by vapor deposition or chemical vapor deposition.

  The source wiring 224 has a function of applying a signal voltage supplied from the driving IC to the signal electrode 228 through the thin film transistor TFT. As shown in FIG. 3, the plurality of source lines 224 extend in the Y direction. The plurality of source lines 224 are provided on the gate insulating film 223 and arranged along the X direction. The source wiring 224 may be formed using the same material as the gate wiring 221. The source wiring 224 can be formed by a method similar to that for the gate wiring 221.

  Note that the source wiring 224 is provided in a straight line, but may be provided by being bent.

The thin film transistor TFT includes a semiconductor layer SC, a source electrode SE, and a drain electrode DE. The semiconductor layer SC has a channel region CH, a source region SA, and a drain region DA.

  The channel region CH, the source region SA, and the drain region DA are regions formed by implanting impurities into silicon or germanium.

  The first conductivity type impurity implanted into the channel region CH is, for example, a P-type impurity, and examples of the P-type impurity include B and Al. The second conductivity type impurity implanted into the source region SA and the drain region DA is, for example, an N-type impurity, and examples of the N-type impurity include P and As. The thin film transistor TFT may have a channel region CH containing an N-type impurity, a source region SA containing a P-type impurity, and a drain region DA.

  The source electrode SE is located in the source region SA of the semiconductor layer SC. The source electrode SE is connected to the source region SA. The source electrode SE is connected to the source line 224.

The drain electrode DE is located in the drain region DA of the semiconductor layer SC. The drain electrode DE is connected to the drain region DA. The drain electrode DE is connected to the drain wiring DL, and the drain wiring DL is connected to the signal electrode 228 via the contact hole C1. That is, the thin film transistor TFT and the signal electrode 228 are electrically connected via the drain wiring DL and the contact hole C1.

The contact hole C1 connecting the thin film transistor TFT and the signal electrode 228 is positioned so as to overlap the first light shielding film BM1. Since the contact hole C1 is connected to the signal electrode 228 located on the second planarization film 226, the contact hole C1 is formed in the second light shielding film BM2 or the third light shielding film BM3 located below the second planarization film 226. It is difficult to block the incident light to the light and the reflected light from the contact hole C1. On the other hand, by providing the contact hole C1 so as to overlap the first light shielding film BM1 located on the second main surface 21b of the first substrate 21, the incident light to the contact hole C1 is caused by the first light shielding film BM1. And it becomes easy to block the reflected light in the contact hole C1.

The interlayer insulating film 225 covers the first main surface 22 so as to cover the source wiring 224 and the thin film transistor TFT.
a. The interlayer insulating film 225 can be formed using a material similar to that of the gate insulating film 223.

The second light shielding film BM2 has a function of shielding light. The second light shielding film BM2 is provided on the interlayer insulating film 225, and is positioned so as to overlap with the channel region CH of the thin film transistor TFT. In the present embodiment, the second light shielding film BM2 is provided so as to overlap the entire thin film transistor TFT, but is not limited thereto. The second light shielding film BM2 only needs to overlap the channel region CH of the thin film transistor TFT. In FIG. 3, the formation region of the second light-shielding film BM2 is indicated by hatching (solid line). The second light shielding film BM2 can be formed of the same material as the first light shielding film BM1.

The third light shielding film BM3 has a function of shielding light. The third light shielding film BM3 is provided on the interlayer insulating film 225. Further, the third light shielding film BM3 is positioned so as to overlap with the formation region of the source wiring 224. In the present embodiment, the source wiring 224 is provided so as to be located in the formation region of the third light shielding film BM3. In FIG. 3, the formation region of the third light-shielding film BM3 is indicated by hatching (solid line). The third light shielding film BM3 can be formed of the same material as the first light shielding film BM1. In the present embodiment, the second light shielding film BM2 and the third light shielding film BM3 are not in contact with each other.

The second planarizing film 226 is provided on the interlayer insulating film 225 so as to cover the second light shielding film BM2 and the third light shielding film BM3. The second planarizing film 226 can be formed of the same material as the first planarizing film 212. The film thickness of the second planarizing film 226 is set in the range of 1 μm to 5 μm, for example. In addition,
From the viewpoint of reducing the parasitic capacitance, it is preferable to increase the thickness of the second planarization film 226.

The common electrode 227 has a function of generating an electric field with the signal electrode 228 by a voltage applied from the driving IC. The common electrode 227 is provided on the second planarization film 226. Common electrode 227
Is formed of a transparent material having conductivity, for example, ITO, IZO, ATO, AZO, tin oxide, zinc oxide, or a conductive polymer.

  The common electrode 227 is connected to the auxiliary capacitance line 222 through the contact hole C2. The contact hole C2 is located in a region overlapping the storage capacitor line 222 and the common electrode 228.

The contact hole C2 connecting the common electrode 227 and the auxiliary capacitance line 222 is positioned so as to overlap the first light shielding film BM1. Since the contact hole C2 is connected to the common electrode 227 located on the second planarization film 226, the contact hole C2 is not formed in the second light shielding film BM2 or the third light shielding film BM3 located below the second planarization film 226. It is difficult to block light incident on the light and reflected light from the contact hole C2. In contrast, by providing the contact hole C2 so as to overlap the first light shielding film BM1 located on the second main surface 21b of the first substrate 21, the incident light to the contact hole C2 is caused by the first light shielding film BM1. And it becomes easy to block the reflected light in the contact hole C2.

  The signal electrode 228 has a function of generating an electric field with the common electrode 227 by a voltage applied from the driving IC. The plurality of signal electrodes 228 are provided on the second planarizing film 226 and arranged along the X direction. Further, common electrodes 227 are located on both sides of the signal electrode 228 in the X direction. That is, the signal electrodes 228 and the common electrodes 227 are alternately arranged in the X direction.

The width of the signal electrode 228 is set in the range of 2 μm to 5 μm, for example. The distance between the signal electrode 228 and the common electrode 227 is set in the range of 5 μm to 20 μm, for example.

  The columnar spacer 24 has a function of controlling the distance between the first substrate 21 and the second substrate 22. The plurality of columnar spacers 24 are provided between the first substrate 21 and the second substrate 22. One end of the columnar spacer 24 is fixed to the first substrate 21. In this embodiment, one end of the columnar spacer 24 is fixed to the first substrate 21. However, the present invention is not limited to this, and one end of the columnar spacer 24 may be fixed to the second substrate 22.

  The columnar spacer 24 is located so as to overlap the first light shielding film BM1. On the other hand, the columnar spacer 24 does not overlap the second light shielding film BM2 and the third light shielding film BM3. In addition, as a material of the columnar spacer 24, for example, a photosensitive resin is exemplified, and an acrylic resin is used.

  In the liquid crystal display device 1, the first light shielding film BM <b> 1 positioned on the second main surface 21 b of the first substrate 21 is provided so as to overlap the gate wiring 221, and the second light shielding is positioned on the interlayer insulating film 225. The film BM2 is provided so as to overlap with the channel region CH of the thin film transistor TFT. By providing the first light shielding film BM1 located on the second main surface 21b of the first substrate 21 so as to overlap the gate wiring 221, the distance between the first light shielding film BM1 and the gate wiring 221 can be increased. The capacitance between the first light shielding film BM1 and the gate wiring 221 can be reduced, and the load applied to the gate wiring 221 can be reduced. Further, since the channel region CH of the thin film transistor TFT is provided in the formation region of the second light shielding film BM2 located on the interlayer insulating film 225, the distance between the second light shielding film BM2 and the channel region CH of the thin film transistor TFT is short. Thus, the light incident on the channel region CH can be easily blocked by the second light shielding film BM2, and the decrease in contrast due to the leakage current can be reduced, and the deterioration in display quality can be suppressed. Furthermore, since the occurrence of leakage current can be reduced, the signal voltage of the signal electrode 228 can be prevented from fluctuating due to the leakage current, so that the occurrence of flicker can be reduced and display quality can be prevented from deteriorating.

In the liquid crystal display device 1, the third light shielding film BM <b> 3 is provided on the first main surface 22 a of the second substrate 22 so as to cover the source wiring 224. Since the pixel P of the present embodiment has a rectangular shape with the Y direction as the long side direction, the light reflected by the source wiring 224 extending in the long side direction of the pixel P is easily visible. On the other hand, by covering the source wiring 224 with the third light shielding film BM3 provided on the first main surface 22a of the second substrate 22, the distance between the third light shielding film BM3 and the source wiring 224 is reduced, Since the third light shielding film BM3 can block light such as external light incident on the source wiring 224, a decrease in contrast can be reduced, and a reduction in display quality can be suppressed.

  Further, in the liquid crystal display device 1, the second light shielding film BM2 and the third light shielding film BM3 are not in contact with each other. When the second light-shielding film BM2 and the third light-shielding film BM3 are brought into contact with each other, the second light-shielding film BM2 may increase the capacitance between the source wiring 224 and the third light-shielding film BM3. The film BM3 may increase the capacitance between the signal electrode 228 and the second light shielding film BM2, and further, the capacitance between the source wiring 224 (or source electrode SE) and the signal electrode 228 (or drain electrode DE) may be increased. May increase. Therefore, by preventing the second light shielding film BM2 and the third light shielding film BM3 from coming into contact with each other, an increase in the load applied to the source wiring 224 and the signal electrode 228 is suppressed.

In the liquid crystal display device 1, the first light shielding film BM1 located on the second main surface 21b of the first substrate 21 overlaps the columnar spacer 24, and the columnar spacer 24 is the second light shielding film BM2 or the third light shielding. It does not overlap with membrane BM3. When the columnar spacer 24 is overlapped with the second light shielding film BM2 or the third light shielding film BM3, the variation in the film thickness of the second light shielding film BM2 or the third light shielding film BM3 is the distance between the first substrate 21 and the second substrate 22. The distance between the first substrate 21 and the second substrate 22 tends to be non-uniform. On the other hand, in the liquid crystal display device 1, the columnar spacer 24 does not overlap the second light shielding film BM2 and the third light shielding film BM3 located on the first main surface 22a of the second substrate 22, and Since it overlaps the first light shielding film BM1 located on the second main surface 21b, the second light shielding film BM2 or the third
It is possible to reduce the influence of the variation in the thickness of the light shielding film BM3 on the distance between the first substrate 21 and the second substrate 22, and to reduce the visibility of the columnar spacer 24.

  The liquid crystal layer 23 is provided between the first substrate 21 and the second substrate 22. The liquid crystal layer 23 includes liquid crystal molecules such as nematic liquid crystal.

The sealing material 25 has a function of bonding the first substrate 21 and the second substrate 22 together. Sealing material 25 is provided between the first substrate 21 as in a plan view to surround the display region E _D and the second substrate 22. This sealing material 25 is formed of an epoxy resin or the like.

The light source device 3 has a function of emitting light toward the display region E _D of the liquid crystal panel 2. The light source device 3 includes a light source 31 and a light guide plate 32. In the light source device 3 according to the present embodiment, a point light source such as an LED is employed as the light source 31, but a linear light source such as a cold cathode tube may be employed.

  The first polarizing plate 4 has a function of selectively transmitting light in a predetermined vibration direction. The first polarizing plate 4 is disposed so as to face the first main surface 21 a of the first substrate 21 of the liquid crystal panel 2.

  The second polarizing plate 5 has a function of selectively transmitting light in a predetermined vibration direction. The second polarizing plate 5 is disposed so as to face the second main surface 22 b of the second substrate 22.

[Second Embodiment]
8 to 10 are diagrams showing the main part of the liquid crystal display device 1A according to the second embodiment.

  The liquid crystal display device 1A is different from the liquid crystal display device 1 in the first embodiment in the following points.

On the second major surface 22b of the second substrate 22 outside the display region E _D, a plurality of peripheral wires 229 are provided. Further, the peripheral wiring 229 is electrically connected to a conductor located in each layer through a contact hole C3.

The fourth light blocking film BM4 in the region located outside the display region E _D overlaps the plurality of peripheral wiring 229 and the contact hole C3. That is, since the contact hole C3 region located outside the display region E _D is overlapped with the first light-shielding film BM1 located on the second major surface 21b of the first substrate 21, the fourth light blocking film BM4, It becomes easy to block the incident light to the contact hole C3 and the reflected light from the contact hole C3. In FIG. 8, the formation region of the fourth light-shielding film BM4 is indicated by oblique lines (solid lines).

Further, on the first main surface 22a of the second substrate 22 in the region located outside the display area E _D, the thin film transistor TFT is provided. Incidentally, the thin film transistor TFT in the region located outside the display area E _D has the same configuration as the thin film transistor TFT described in the first embodiment. Further, as shown in FIGS. 9 and 10, the thin film transistor TFT which is located outside the display area E _D the peripheral wiring functions as a gate electrode to the thin film transistor TFT 229
It is provided above.

Further, the fifth light shielding film BM5 is provided on the interlayer insulating film 225 and is positioned so as to overlap with the channel region CH of the thin film transistor TFT. In FIG. 10, the formation region of the fifth light-shielding film BM5 is indicated by oblique lines (solid lines).

In the liquid crystal display device 1A, in the region located outside the display area E _D, fourth light blocking film BM4 located on the second major surface 21b of the first substrate 21 is provided so as to overlap the peripheral wires 229.
By providing the fourth light shielding film BM4 located on the second main surface 21b of the first substrate 21 so as to overlap the peripheral wiring 229, the distance between the fourth light shielding film BM4 and the peripheral wiring 229 can be increased. The capacitance between the fourth light shielding film BM4 and the peripheral wiring 229 can be reduced, and the load applied to the peripheral wiring 229 can be reduced.

Further, since the channel region CH of the thin film transistor TFT is provided in the formation region of the fifth light shielding film BM5 located on the interlayer insulating film 225, the distance between the fifth light shielding film BM5 and the channel region CH of the thin film transistor TFT is short. Thus, the light incident on the channel region CH can be easily blocked by the fifth light shielding film BM5, and the generation of leakage current can be reduced.

  The present invention is not particularly limited to the first and second embodiments described above, and various modifications and improvements can be made within the scope of the gist of the present invention.

In the liquid crystal display devices 1 and 1A, an electric field is generated between the signal electrode provided on one of the pair of substrates (second substrate 22) and the common electrode to change the direction of the liquid crystal molecules in the liquid crystal layer. Although the so-called lateral electric field method of controlling is adopted, the present invention is not limited to this, and any method may be used. For example, a vertical electric field method may be adopted.

1,1A liquid crystal display device 2 liquid crystal panel E _D display region P pixels
21 First board
21a 1st main surface
21b Second main surface (main surface)
211 Color filter
212 First planarization film
22 Second board
22a First main surface (main surface)
22b 2nd main surface
221 Gate wiring
222 Auxiliary capacitance wiring
223 Gate insulation film (second insulation film)
224 source wiring
225 First interlayer insulating film (third insulating film)
226 Second planarizing film (first insulating film)
227 Common electrode
228 Signal electrode
229 Peripheral wiring
TFT thin film transistor
SC semiconductor layer
CH channel area
SA source area
DA drain region
SE source electrode
DE drain electrode C1, C2, C3 Contact hole
BM1 1st light shielding film
BM2 Second light shielding film
BM3 3rd light shielding film
BM4 4th light shielding film
BM5 5th light shielding film
DL drain wiring
23 Liquid crystal layer
24 Columnar spacer
25 Sealing material 3 Light source device
31 Light source
32 Light guide plate 4 First polarizing plate 5 Second polarizing plate

Claims (5)

Provided on the main surface of the second substrate, a first substrate and a second substrate disposed with the main surfaces facing each other, a liquid crystal layer disposed between the first substrate and the second substrate, A plurality of gate lines, a plurality of source lines provided on the main surface of the second substrate so as to cross the plurality of gate lines, and each pixel surrounded by the gate lines and the source lines A plurality of thin film transistors having a semiconductor layer, a source electrode, and a drain electrode, and a plurality of the gate wirings, the plurality of source wirings, and the plurality of thin film transistors provided on the main surface of the second substrate so as to cover A first insulating film formed on the first insulating film, a signal electrode located on the pixel and electrically connected to the thin film transistor, and a common electrode for generating an electric field between the signal electrode and the signal electrode. And an electrode,
The semiconductor layer is located on the gate wiring through a second insulating film and includes a channel region containing a first conductivity type impurity, a source region where the source electrode is located and a second conductivity type impurity is contained, The drain electrode is located, and has a drain region containing a second conductivity type impurity,
On the main surface of the first substrate, a first light shielding film is provided so as to overlap the gate wiring,
A liquid crystal display device, wherein a second light shielding film is provided on the thin film transistor so as to overlap the channel region with a third insulating film interposed therebetween.   The liquid crystal display device according to claim 1, wherein a columnar spacer is provided on the main surface of the first substrate via the first light shielding film. The thin film transistor and the signal electrode are electrically connected through a contact hole,
The liquid crystal display device according to claim 1, wherein the first light shielding film is positioned so as to overlap the contact hole.   The liquid crystal display device according to claim 1, wherein a third light shielding film is provided on the main surface of the second substrate so as to cover the source wiring.   The liquid crystal display device according to claim 4, wherein the second light shielding film and the third light shielding film are not in contact with each other.

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