JP2014053372A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve flatness of an insulating film in a method of manufacturing a semiconductor device.SOLUTION: A method of manufacturing a semiconductor device includes the steps of: forming a first insulating film 10 in a first region I including a peripheral edge of a semiconductor substrate 1 and in a second region II located closer toward the center of the semiconductor substrate 1 than the first region I; forming slots 10a on the first insulating film 10 in the second region II ; forming a barrier metal film 14 on the first insulating film 10 after the step of forming the slots 10a; forming a second metal film 16 on the barrier metal film 14 in the second region II; forming a first film 20 whose polishing rate is smaller than the second metal film 16, on the first metal film 14 in the first region I; and removing the second metal film 16 by polishing after the step of forming the first film 20 so that the second metal film 16 is left within the slots 10a in the second region II.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Along with the high integration of semiconductor devices such as LSIs, the damascene method is being adopted as a method for forming wiring of semiconductor devices. The damascene method is a method of forming a wiring in a wiring groove by embedding a metal film in a wiring groove formed in an insulating film, and polishing the metal film, and it is not necessary to pattern the metal film by etching. This is advantageous for miniaturization.

  A CMP (Chemical Mechanical Polishing) method is used to polish a metal film by the damascene method. In the CMP method, in addition to the metal film to be polished, the insulating film around the wiring trench is also polished, so that the flatness of the upper surface of the insulating film is lowered, and consequently the yield of the semiconductor device is lowered.

  An object of the method for manufacturing a semiconductor device is to improve the flatness of an insulating film.

  According to one aspect of the following disclosure, a first insulating film is formed in a first region including a peripheral edge of a semiconductor substrate and a second region located closer to the center of the semiconductor substrate than the first region. Forming a groove in the first insulating film in at least the second region, and forming a first metal film in the first insulating film after the step of forming the groove. Forming a second metal film on the first metal film in the second region, and forming the second metal film on the first metal film in the first region. After the step of forming a first film having a lower polishing rate and the step of forming the first film, the second metal film is left in the groove in the second region. And a step of polishing and removing the second metal film.

  According to the following disclosure, when the second metal film is polished, the insulating film in the first region is protected by the first film, so that the flatness of the upper surface of the insulating film is prevented from being deteriorated by the polishing. it can.

FIGS. 1A and 1B are cross-sectional views (part 1) in the course of manufacturing the semiconductor device used in the study. 2A and 2B are cross-sectional views (part 2) of the semiconductor device used for the examination in the middle of manufacture. FIGS. 3A and 3B are cross-sectional views (part 3) in the middle of manufacturing the semiconductor device used for the study. 4A and 4B are cross-sectional views (part 4) in the middle of manufacturing the semiconductor device used for the study. FIGS. 5A and 5B are enlarged plan views (part 1) in the middle of manufacturing the semiconductor device used for the study. 6A and 6B are enlarged plan views (part 2) of the semiconductor device used for the examination in the middle of manufacture. 7A and 7B are cross-sectional views (part 1) in the middle of manufacturing the semiconductor device according to the present embodiment. 8A and 8B are cross-sectional views (part 2) of the semiconductor device according to the present embodiment during manufacture. 9A and 9B are cross-sectional views (part 3) in the middle of manufacturing the semiconductor device according to the present embodiment. FIGS. 10A and 10B are enlarged plan views (part 1) in the middle of manufacturing the semiconductor device according to this embodiment. FIG. 11 is an enlarged plan view (part 2) of the semiconductor device according to the present embodiment during manufacture. 12A and 12B are enlarged sectional views (No. 1) for explaining another example of the method of laminating the wiring and the insulating film in the present embodiment. FIGS. 13A and 13B are enlarged sectional views (No. 2) for explaining another example of the method of laminating the wiring and the insulating film in the present embodiment. FIG. 14 is an enlarged cross-sectional view (part 3) for explaining another example of the method of laminating the wiring and the insulating film in the present embodiment. FIG. 15 is a cross-sectional view of a semiconductor device obtained by further increasing the number of stacked layers of wirings and insulating films in this embodiment.

  Prior to the description of the present embodiment, the results of studies conducted by the inventors will be described.

  1 to 4 are cross-sectional views of the semiconductor device used for this study, which are in the process of manufacturing, and FIGS. 5 to 6 are enlarged plan views thereof.

  This semiconductor device includes wiring formed by the damascene method, and is manufactured as follows.

  First, as shown in FIG. 1A, a silicon substrate is prepared as the semiconductor substrate 1. The semiconductor substrate 1 has a first region I including its periphery and a second region II closer to the center of the substrate than the first region I.

  Among these regions, the first region I is a region that enters the inside of the substrate by 1 mm to 4 mm, for example, 2 mm from the end 1e of the semiconductor substrate 1, and a semiconductor device for a product is not manufactured in the region. . In order to prevent the semiconductor substrate 1 from being chipped, the semiconductor substrate 1 in the first region I is chamfered.

  On the other hand, the second region II is a region where semiconductor devices for a plurality of products are cut out, and a MOS (Metal Oxide Semiconductor) transistor TR is formed in advance.

  The transistor TR includes a gate electrode 4 formed by patterning a polysilicon film on a gate insulating film 2 formed by thermally oxidizing the surface of the semiconductor substrate 1, and an insulating sidewall 6 is provided beside the gate electrode 4. As a result, a silicon oxide film is formed. Then, for example, an n-type impurity is ion-implanted into the semiconductor substrate 1 using the gate electrode 4 and the insulating sidewall 6 as a mask, so that the n-type conductivity type source region 8a and the semiconductor substrate 1 beside the gate electrode 4 are formed. An n-type conductivity type drain region 8b is formed. Note that the source region 8a and the drain region 8b may have p-type conductivity instead of n-type conductivity.

  Next, a silicon oxide film is formed as a lower insulating film on the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method, and if necessary, the silicon oxide film is planarized by a CMP method to a thickness of about 400 nm, for example. (Not shown).

  Next, contact plugs (not shown) connected to the gate electrode 4 and each of the source region 8a and the drain region 8b are formed in the lower insulating film.

  Next, a silicon oxide film having a thickness of, for example, about 400 nm is formed as an insulating film 10 on the lower insulating film by a CVD (Chemical Vapor Deposition) method.

  FIG. 5A is a plan view after the completion of this step, and FIG. 1A corresponds to a cross-sectional view taken along the line A1-A1 in FIG.

  Subsequently, as shown in FIG. 1B, a photoresist is applied on the insulating film 10, and the resist film 12 is formed by exposing and developing it.

  FIG. 5B is a plan view after the process is completed, and FIG. 1A corresponds to a cross-sectional view taken along line A2-A2 in FIG. 5B.

  As shown in FIG. 5B, the photoresist exposure is performed for each chip region C, and the chip region C is also set in the first region I on the periphery of the semiconductor substrate 1.

  Then, as shown in FIG. 2A, the insulating film 10 is etched by RIE (Reactive Ion Etching) using, for example, a fluorocarbon (CF) etching gas while using the resist film 12 as a mask. For example, a trench 10a having a depth of about 250 nm is formed in each insulating film 10 in the first region I and the second region II.

  As described with reference to FIG. 5B, in this example, since the chip region C serving as an exposure unit is also set at the periphery of the semiconductor substrate 1, a groove is formed between the first region I and the second region II. There is no difference in density of 10a. Therefore, there is no difference in the etching rate between the first region I and the second region II due to the difference in density, and the width and depth of the groove 10a are not uniform in the second region II. Can be prevented.

  After this etching is finished, as shown in FIG. 2B, the resist film 12 is removed by ashing using oxygen plasma.

  Next, as shown in FIG. 3A, for example, a tantalum film is formed as a barrier metal film 14 on the insulating film 10 and in the groove 10a by a sputtering method to a thickness of about 30 nm.

  The barrier metal film 14 is an example of a first metal film, and has a function of preventing diffusion of copper in the wiring formed later in the trench 10a into the insulating film 10. Examples of the material having such a function include titanium, tantalum, and nitrides thereof.

  Then, a copper seed layer 16s is formed on the barrier metal film 14 to a thickness of about 50 nm by sputtering. Thereafter, a copper film having a thickness of about 800 nm is formed on the barrier metal film 14 as the second conductor 16x by an electrolytic plating method using the seed layer 16s as a power feeding layer, and the second conductor 16x forms a groove. Fill 10a completely.

  Here, when moving the semiconductor substrate 1 in the clean room, a cassette (not shown) is used. The cassette accommodates one lot of semiconductor substrates 1 together, and the first region I of the semiconductor substrate 1 is rubbed against the cassette by vibration during movement or the like.

  In particular, since the second conductor 16x made of copper is softer than other metals, the cassette is contaminated with copper by rubbing the second conductor 16x.

  In order to prevent such contamination, in the next step, as shown in FIG. 3B, the second conductor 16x in the first region I is removed by wet etching, and the second region II is removed. The second conductor 16x in the remaining portion is used as the second metal film 16. This wet etching is also called EBR (Edge Bevel Rinse).

  As an etching solution that can be used in this EBR, for example, there is an acidic solution such as a mixed solution of sulfuric acid and hydrogen peroxide. By dropping this etching solution only on the first region I, the second conductor 16x that causes the cassette to be contaminated is left in the first region I while leaving the second metal film 16 in the second region II. Can be removed from region I.

  Note that the barrier metal film 14 remains in the first region I because the barrier metal film 14 has etching resistance against the etching solution. Since the barrier metal film 14 is harder than the second metal film 16 made of copper, the barrier metal film 14 is less likely to be contaminated than the second metal film 16.

  FIG. 6A is a plan view after the process is completed, and FIG. 3B corresponds to a cross-sectional view taken along the line A3-A3 in FIG. 6A.

  As shown in FIG. 6A, the barrier metal film 14 is exposed in the first region I by performing EBR in this step.

  Next, as shown in FIG. 4A, the excess second metal film 16 and barrier metal film 14 on the insulating film 10 are polished and removed by the CMP method, and these films are removed from the second film. The wiring 16a is left only in the trench 10a in the region II. A method of forming the wiring 16a in the groove 10a by the CMP method is called a damascene method.

  Here, in this example, since the second metal film 16 is removed from the first region I by EBR, the groove 10a is not covered with the second metal film 16 in the first region I. The insulating film 10 around the groove 10a is easily polished.

  As a result, the insulating film 10 in the first region I is polished more excessively than in the second region II by CMP in this step, and the flatness of the upper surface of the insulating film 10 in the first region I is deteriorated. become.

  FIG. 6B is a plan view after the process is completed, and FIG. 4B corresponds to a cross-sectional view taken along the line A4-A4 in FIG.

  As shown in FIG. 6B, in the first region I, the groove 10a is not filled with the wiring 16a, and the groove 10a is in a hollow state.

  Thereafter, the cross-sectional structure shown in FIG. 4B is obtained by repeating the steps of FIG. 1A to FIG. 4A.

  FIG. 4B illustrates a multilayer structure in which three layers of the insulating film 10 and the wiring 16a are stacked. However, when the insulating film 10 is stacked in this way, the above-described deterioration in flatness is caused by the uppermost insulating film. 10, the flatness of the insulating film 10 is deteriorated also in the second region II.

  For this reason, the shape of the wiring 16a in the second region II is collapsed, the number of semiconductor devices satisfying the product specifications in the second region II is reduced, and the yield of the semiconductor devices is reduced.

  Hereinafter, an embodiment capable of preventing such a decrease in flatness of the insulating film 10 will be described.

(This embodiment)
7 to 9 are cross-sectional views in the course of manufacturing the semiconductor device according to the present embodiment, and FIGS. 10 to 11 are enlarged plan views thereof. 7 to 11, the same elements as those described in FIGS. 1 to 6 are denoted by the same reference numerals, and the description thereof is omitted below.

  First, as shown in FIG. 7A, the copper film formed as the second metal film 16 is an EBR in the first region by performing the above-described steps of FIG. 1A to FIG. 3B. It is assumed that it has been removed from I.

  Then, as shown in FIG. 7B, a tantalum film having a thickness of about 50 nm is formed by sputtering on the second metal film 16, on the barrier metal film 14 in the first region I, and in the groove 10a. Then, the tantalum film is used as the first conductor 20x.

  The first conductor 20x is not limited to the tantalum film, and any material that causes a difference in CMP polishing rate with the second metal film 16 is adopted as the material of the first conductor 20x. Can do. Examples of such a material include the same type of metal as the barrier metal film 14, such as titanium, tantalum, and nitrides thereof. Further, an insulator may be formed instead of the first conductor 20x.

  In the subsequent processes, the second metal film 16 and the first conductor 20x are polished in the following first to third steps, and the first conductor 20x is removed from the second region II.

  In the first first step, as shown in FIG. 8A, the first conductor 20x is removed from the second region II by polishing the first conductor 20x by the CMP method. The portion of the first conductor 20 x remaining in the region I is the first film 20.

  In the CMP, a polishing pad (not shown) is used, but the second region II is more strongly pressed against the polishing pad than the first region I by the thickness of the second metal film 16. Therefore, in this CMP, the first film 20 in the second region II is preferentially polished, and the first film 20 can be left in the first region I.

  The slurry used in this CMP is not particularly limited, but it is preferable to use a silica-based slurry for barrier metal. By using a silica-based slurry, the polishing rate of the first film 20 becomes higher than the polishing rate of the second metal film 16, so that the second metal film 16 is left and the second film II in the second region II is left. One film 20 can be selectively polished.

  If the first film 20 is too thick, it is difficult to remove the first film 20 from the second region II in this step. Therefore, for example, the first film 20 is formed thinner than the second metal film 16 and more preferably about the same thickness as the barrier metal film 14 so that the first film 20 can be easily removed in this step. Is preferable.

  At the end of this step, the total film thickness of the barrier metal film 14 and the first film 20 in the first region I is larger than the film thickness of the barrier metal film 14 in the second region II.

  FIG. 10A is a plan view after the end of this step, and FIG. 8A corresponds to a cross-sectional view taken along line A4-A4 of FIG.

  As shown in FIG. 10A, by performing this step, the second metal film 16 is exposed in the second region II.

  In the next second step, as shown in FIG. 8 (b), the first remaining in the second region II using a colloidal silica slurry having a lower abrasive concentration than in the first step. The second metal film 16 is polished.

  For the colloidal silica slurry used in this step, the polishing rate of the first film 20 is lower than the polishing rate of the second metal film 16. Therefore, in this step, the second metal film 16 can be selectively polished while leaving the first film 20 in the first region I so that the insulating film 10 is not exposed in the first region I. . As a result, in the second region II, the excessive second metal film 16 on the insulating film 10 can be removed, and the second metal film 16 can be left as the wiring 16a only in the trench 10a.

  If the above colloidal silica slurry is used, the polishing rate of the barrier metal film 14 becomes smaller than the polishing rate of the second metal film 16, so that the barrier metal 14 is not formed in the second region II after the end of this step. Remains.

  FIG. 10B is a plan view after the end of this step, and FIG. 8B corresponds to a cross-sectional view taken along the line A5-A5 in FIG. 10B.

  As shown in FIG. 10B, the first region I is protected by the first film 20.

  In the next third step, as shown in FIG. 9A, the barrier metal film 14 remaining in the second region II is polished. As a result, in the second region II, the barrier metal film 14 is removed from above the insulating film 10 while leaving the barrier metal film 14 inside the trench 10a.

  Examples of the slurry that can be used in this step include silica-based slurry.

  Here, since the insulating film 10 in the first region I is protected by the first film 20 (see FIG. 8B) at the start of this step, the insulating film 10 is not polished with a polishing pad (not shown). Can be prevented by the first film 20. As a result, the insulating film 10 is not exposed in the first region I. Therefore, it is possible to prevent the upper surface of the insulating film 10 from being lowered in the first region I, and even after this step is completed. It is possible to maintain the flatness of the film.

Since the thin first film 20 cannot protect the insulating film 10 in the first region I from the polishing pad, in order to effectively protect the second metal film 16 by the first film 20, the first film 20 A certain thickness of the film 20 is required. For this reason, it is preferable that the first film 20 is approximately the same as or slightly thicker than the barrier metal film 14.

  FIG. 11 is a plan view after this step is completed, and FIG. 9A corresponds to a cross-sectional view taken along line A6-A6 of FIG.

  As shown in FIG. 11, even if this step is performed, the barrier metal film 14 remains in the first region I, but part of the barrier metal film 14 may be removed depending on the polishing conditions of this step. .

  Thereafter, by repeating the steps of FIGS. 7A to 9A, a laminated structure of the insulating film 10 and the wiring 16a as shown in FIG. 9B is obtained.

  As described above, in this embodiment, the flatness of the upper surface of each insulating film 10 is maintained by the first film 20 (see FIG. 8B), and thus a plurality of insulating films 10 are laminated in this manner. However, the flatness of the upper surface of the uppermost insulating film 10 is not significantly lowered in the second region II.

  Therefore, it is possible to prevent the shape of the wiring 16a from being broken in the second region II due to a decrease in flatness of the insulating film 10, and to improve the yield of the semiconductor device manufactured in the second region II.

  Note that the method of stacking the wiring 16a and the insulating film 10 is not limited to the above. Another example of these lamination methods will be described with reference to FIGS. 12-14 is a figure corresponded in the expanded sectional view of the A section of Fig.9 (a).

  First, after obtaining the cross-sectional structure of FIG. 9A as described above, another insulating film 10 is newly formed on the insulating film 10 and the wiring 16a as shown in FIG. 12A. To do. The insulating film 10 is a silicon oxide film having a thickness of about 500 nm formed by a CVD method using, for example, TEOS (Tetraethyl Orthosilicate) gas.

  Next, as shown in FIG. 12B, the insulating film 10 is patterned to form a hole 10b having a depth reaching the wiring 16a.

  Thereafter, as shown in FIG. 13A, the insulating film 10 is patterned again to form a groove 10a overlapping the hole 10b.

  Next, as shown in FIG. 13B, a tantalum film is formed to a thickness of about 30 nm by sputtering on the inner surface of each of the trench 10a and the hole 10b and on the insulating film 10, and the tantalum film is barriered. The metal film 14 is used.

  Then, a copper seed layer 16s is formed on the barrier metal film 14 to a thickness of about 50 nm by sputtering. Thereafter, a copper film having a thickness of about 1000 nm is formed as a second metal film 16 on the barrier metal film 14 by electrolytic plating using the seed layer 16s as a power feeding layer. 10a and hole 10b are completely filled.

  Thereafter, the same steps as those shown in FIGS. 7A to 9A are performed to obtain the cross-sectional structure shown in FIG.

  In this example, since the hole 10b is formed under the groove 10a, the wiring 16a in the groove 10a is electrically connected to the wiring 16a under the hole 10b.

  FIG. 15 is a cross-sectional view of a semiconductor device obtained by further increasing the number of stacked layers of the wiring 16 a and the insulating film 10. In FIG. 15, the same elements as those described in FIGS. 1 to 14 are denoted by the same reference numerals as those in FIGS.

  In this semiconductor device, a contact plug 30 made of tungsten is formed in the hole 10 b of the uppermost insulating film 10, and an electrode pad 31 is formed on the contact plug 30 and the insulating film 10.

  The electrode pad 31 is formed by laminating a first titanium nitride film 31a, a copper-containing aluminum film 31b, and a second titanium nitride film 31c formed in this order by a sputtering method, and in the vicinity of the center, a copper-containing aluminum film is formed. 31b is exposed.

  A first passivation film 33 such as a silicon oxide film and a second passivation film 34 such as a silicon nitride film are formed in this order on the electrode pad 31 by the CVD method. These passivation films 33 and 34 are formed in this order. The electrode pad 31 is exposed from the opening 33a.

  According to the present embodiment described above, as shown in FIG. 7B, the insulating film 10 in the first region I is protected by the first film 20 formed after EBR. Therefore, when the wiring 16a is formed by the damascene method as shown in FIGS. 8A to 9A, the insulating film 10 in the first region I can be prevented from being polished by CMP. As a result, the flatness of the upper surface of the insulating film 10 does not deteriorate in the first region I due to polishing, and the upper surface of the insulating film 10 is also flat in the second region II adjacent to the first region I. Can be maintained.

  As a result, even if a plurality of insulating films 10 are stacked as shown in FIG. 9B and FIG. 15, the flatness of the uppermost insulating film 10 does not deteriorate. Thus, the yield of the semiconductor device can be improved.

  Although the present embodiment has been described in detail above, the present embodiment is not limited to the above.

  For example, FIG. 15 illustrates the contact plug 35 connected to the source region 8a and the drain region 8b, but the above embodiment may be applied when the contact plug 35 is formed.

  The contact plug 35 is formed by sequentially forming a barrier metal film 35a such as a titanium film and a tungsten film 35b in the contact hole 10a, and polishing and removing these films 35a and 35b other than the contact hole 10a by CMP. Can be done. By applying this embodiment at the time of polishing, the flatness of the lowermost insulating film 10 can be maintained.

  The following additional notes are disclosed for each embodiment described above.

(Additional remark 1) The process of forming a 1st insulating film in the 1st area | region including the periphery of a semiconductor substrate, and the 2nd area | region located in the center side of the said semiconductor substrate rather than this 1st area | region,
Forming a groove in the first insulating film at least in the second region;
After the step of forming the groove, forming a first metal film on the first insulating film;
Forming a second metal film on the first metal film in the second region;
Forming a first film having a polishing rate lower than that of the second metal film on the first metal film in the first region;
Polishing and removing the second metal film so as to leave the second metal film in the trench in the second region after the step of forming the first film;
A method for manufacturing a semiconductor device comprising:

(Appendix 2) The first film is a metal film of the same type as the first metal film,
The semiconductor according to claim 1, wherein a total film thickness of the first metal film and the first film in the first region is larger than a film thickness of the first metal film in the second region. Device manufacturing method.

(Supplementary Note 3) The step of forming the first film includes:
Forming a first conductor on the first metal film in the first region and on the second metal film in the second region;
Removing the first conductor on the second metal film in the second region to form the first film;
The method for manufacturing a semiconductor device according to appendix 1 or 2, wherein:

(Supplementary Note 4) The step of removing the second metal film includes:
4. The method according to claim 1, further comprising a step of polishing the second metal film in the second region so that the first insulating film is not exposed in the first region. The manufacturing method of the semiconductor device of description.

(Supplementary Note 5) The step of forming the second metal film includes:
Forming a second conductor on the first metal film in the first region and the second region;
Removing the second conductor in the first region to form the second metal film;
The method of manufacturing a semiconductor device according to any one of appendices 1 to 4, wherein:

(Supplementary Note 6) The manufacturing method of the semiconductor device includes:
The first metal film is polished after the step of removing the second metal film, thereby leaving the first metal film in the groove while leaving the first metal film in the second region. Further comprising removing the film,
The step of removing the first metal film includes
The semiconductor according to any one of appendices 1 to 5, further comprising a step of polishing the first metal film in the second region so that the first insulating film is not exposed in the first region. Device manufacturing method.

  (Supplementary note 7) In the step of forming the first film, the first film is formed to be thinner than the second metal film and thicker than the first metal film. 1. A method for manufacturing a semiconductor device according to claim 1.

  (Supplementary note 8) The semiconductor device according to any one of supplementary notes 1 to 7, wherein in the step of forming the groove, the groove is also formed in the first insulating film in the first region. Manufacturing method.

  (Supplementary note 9) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 8, wherein a copper film is formed as the second metal film.

  (Supplementary Note 10) The method for manufacturing a semiconductor device according to any one of Supplementary notes 1 to 9, wherein any one of a titanium film, a tantalum film, and a nitride film thereof is formed as the first film. .

  (Supplementary Note 11) The step of forming the first insulating film, the step of forming the groove, the step of forming the first metal film, the step of forming the second metal film, and the first film A laminated structure of the second metal film and the first insulating film left in the groove is formed by performing the step of forming and the step of polishing and removing the second metal film a plurality of times. The method of manufacturing a semiconductor device according to any one of appendices 1 to 10, wherein the semiconductor device is formed.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1e ... End, 2 ... Gate insulating film, 4 ... Gate electrode, 6 ... Insulating sidewall, 8a ... Source region, 8b ... Drain region, 10 ... Insulating film, 10a ... Groove, 10b ... Hole, DESCRIPTION OF SYMBOLS 12 ... Resist film, 14 ... Barrier metal film, 16 ... 2nd metal film, 16a ... Wiring, 16s ... Seed layer, 20 ... 1st film | membrane, 30 ... Contact plug, 31 ... Electrode pad, 31a ... 1st Titanium nitride film, 31b ... copper-containing aluminum film, 31c ... second titanium nitride film, 33 ... first passivation film, 33a ... opening, 34 ... second passivation film.

Claims (6)

Forming a first insulating film in a first region including the periphery of the semiconductor substrate and a second region located closer to the center of the semiconductor substrate than the first region;
Forming a groove in the first insulating film at least in the second region;
A step of forming a first metal film on the first insulating film after the step of forming the groove;
Forming a second metal film on the first metal film in the second region;
Forming a first film having a polishing rate lower than that of the second metal film on the first metal film in the first region;
Polishing and removing the second metal film so as to leave the second metal film in the trench in the second region after the step of forming the first film;
A method for manufacturing a semiconductor device comprising: The first film is a metal film of the same type as the first metal film,
The total film thickness of the first metal film and the first film in the first region is larger than the film thickness of the first metal film in the second region. A method for manufacturing a semiconductor device. The step of forming the first film includes
Forming a first conductor on the first metal film in the first region and on the second metal film in the second region;
Removing the first conductor on the second metal film in the second region to form the first film;
The method of manufacturing a semiconductor device according to claim 1, wherein: The step of removing the second metal film includes
4. The method according to claim 1, further comprising a step of polishing the second metal film in the second region so that the first insulating film is not exposed in the first region. 5. A method for manufacturing a semiconductor device according to item. The step of forming the second metal film includes
Forming a second conductor on the first metal film in the first region and the second region;
Removing the second conductor in the first region to form the second metal film;
5. The method of manufacturing a semiconductor device according to claim 1, wherein: The method for manufacturing the semiconductor device includes:
The first metal film is polished after the step of removing the second metal film, thereby leaving the first metal film in the groove while leaving the first metal film in the second region. Further comprising removing the film,
The step of removing the first metal film includes
6. The method according to claim 1, further comprising a step of polishing the first metal film in the second region so that the first insulating film is not exposed in the first region. A method for manufacturing a semiconductor device.

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