JP2005217320A - Method for forming wiring, fabrication process of semiconductor device and process for manufacturing semiconductor packaging equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress stripping of a low dielectric constant film in polishing a conductive film. <P>SOLUTION: A diffusion prevention film 2 is formed on a silicon substrate 1 and a low dielectric constant film 3 having a dielectric constant not larger than 3 is formed. The low dielectric constant film 3 is then removed by a removal width A from the edge 10 of the silicon substrate 1. A cap film 4 is formed on the low dielectric constant film 3 and a trench 5 for wiring is formed in the cap film 4, the low dielectric constant film 3 and the diffusion prevention film 2. After a barrier film 6 and a Cu film 7 are formed, the Cu film 7 is removed from the edge 10 by a removal width B which is different from the removal width A by 1 mm or more. The unnecessary Cu film 7 and the barrier metal film 6 on the cap film 4 are removed by CMP. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of forming a wiring, a method of manufacturing a semiconductor device, and a method of manufacturing a semiconductor mounting device, and more particularly to formation of a buried wiring combining a low dielectric constant film and a Cu wiring.

Along with higher integration and higher performance of semiconductor integrated circuits (hereinafter referred to as “LSI”), new microfabrication techniques have been proposed. One of them is a chemical mechanical polishing (hereinafter referred to as “CMP”) method, which is particularly used for flattening an interlayer insulating film, forming a metal plug, and forming a buried wiring in a multilayer wiring forming process (for example, (See Patent Document 1).
In recent years, signal delay of wiring has become a problem, and the movement to change the wiring material from a conventional Al alloy to a low-resistance Cu alloy is progressing. Since Cu alloy is difficult to finely process by dry etching, a groove is formed in the insulating film, a Cu film is deposited in the groove, and unnecessary Cu film other than the groove is removed by CMP. A so-called damascene method for forming a buried Cu wiring is employed (see, for example, Patent Document 2).
Further, in order to reduce the parasitic capacitance between wirings, an LSI using a low dielectric constant film (hereinafter also referred to as “low-k film”) having a relative dielectric constant lower than that of the SiO ₂ film has been developed. Yes. That is, a low dielectric constant film having k of 1.5 to 3.5 is used in place of the SiO ₂ film having a relative dielectric constant k of about 4.2. Development of a low dielectric constant film material having k of 2.5 or less is also underway. The material of which k is 2.5 or less is often a porous low-k film material into which pores are introduced.

However, the low dielectric constant film has a lower mechanical strength than the SiO ₂ film. For this reason, when forming a multilayer wiring structure in which a low dielectric constant film and a Cu wiring are combined, there is a problem that structural breakdown occurs in the low dielectric constant film due to the polishing load of CMP, or a cap film in contact with the low dielectric constant film or There was a problem that the base insulating film peeled off. In particular, when a low dielectric constant film material having a low Young's modulus and hardness, or a low dielectric constant film material having a low adhesiveness to the cap film is used, the above-described problem occurs remarkably. In particular, it has been reported that peeling occurs easily when the Young's modulus of the low dielectric constant film is 5 GPa or less (for example, see Non-Patent Document 1).
Such peeling of the low dielectric constant film that occurs during Cu-CMP often starts at the wafer edge (see, for example, Non-Patent Document 2). Further, as the polishing time becomes longer, the peeling area tends to increase toward the center of the wafer.

  Therefore, conventionally, peeling of the low dielectric constant film has been reduced by lowering the polishing load of CMP. On the other hand, the use of a low dielectric constant film material having a high Young's modulus and hardness is effective in suppressing peeling of the low dielectric constant film.

US Pat. No. 4,944,836 JP-A-2-278822 Simon Lin, 11 others, “Low-k Dielectrics Characterization for Damascene Integration”, 2001, IITC2001 Stan Tsai, 6 others, “Copper CMP at Low Shear Force for Low-k Compatibility”, 2002, IITC2002

However, when the polishing load of CMP is lowered, there is a problem that the polishing rate is lowered and the throughput is lowered. Further, when the Young's modulus and hardness are increased, there is a problem that the relative dielectric constant k increases.
The peeling of the low dielectric constant film during Cu-CMP has become a big problem in Cu wiring development, and even if the peeling area is reduced, the peeling of the low dielectric constant film at the wafer edge has hardly been solved.

  The present invention has been made to solve the above-described conventional problems, and an object thereof is to suppress peeling of a low dielectric constant film when a conductive film is polished.

A wiring forming method according to the present invention is a method of forming a buried wiring in a low dielectric constant film,
Forming a low dielectric constant film having a relative dielectric constant of 3 or less on the ground;
Removing the low dielectric constant film with a first width from the underlying edge;
Forming a cap film on the low dielectric constant film after removing the low dielectric constant film in the first width;
Forming a groove in the cap film and the low dielectric constant film;
Forming a conductive film inside the groove and on the cap film;
Removing the conductive film from the edge of the base with a second width different from the first width by 1 mm or more;
And polishing the unnecessary conductive film formed on the cap film after removing the conductive film with the second width.

  In the wiring formation method according to the present invention, it is preferable that the first width is not less than 4 mm and not more than 15 mm.

  In the wiring formation method according to the present invention, it is preferable that the second width is smaller than the first width.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor element having a diffusion layer on a substrate,
Forming an interlayer insulating film covering the semiconductor element;
Forming a contact connected to the diffusion layer in the interlayer insulating film;
Forming a low dielectric constant film having a relative dielectric constant of 3 or less on the contact and the interlayer insulating film;
Removing the low dielectric constant film with a first width from an edge of the substrate;
Forming a cap film on the low dielectric constant film after removing the low dielectric constant film;
Forming a groove reaching the surface of the contact in the cap film and the low dielectric constant film;
Forming a conductive film inside the groove and on the cap;
Removing the conductive film with a second width different from the first width by 1 mm or more from the edge of the substrate;
And polishing the unnecessary conductive film formed on the cap film after removing the conductive film.

  In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the first width is not less than 4 mm and not more than 15 mm.

  In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the second width is smaller than the first width.

A method of manufacturing a semiconductor mounting device according to the present invention includes a step of forming a low dielectric constant film having a relative dielectric constant of 3 or less on a semiconductor device having a semiconductor element;
Removing the low dielectric constant film with a first width from an edge of the semiconductor device;
Forming a cap film on the low dielectric constant film after removing the low dielectric constant film;
Forming a groove in the cap film and the low dielectric constant film;
Forming a conductive film inside the groove and on the cap;
Removing the conductive film with a second width different from the first width by 1 mm or more from an edge of the semiconductor device;
And polishing the unnecessary conductive film formed on the cap film after removing the conductive film.

  In the method for manufacturing a semiconductor mounting device according to the present invention, it is preferable that the first width is not less than 4 mm and not more than 15 mm.

  In the method for manufacturing a semiconductor mounting device according to the present invention, it is preferable that the second width is smaller than the first width.

  According to the present invention, as described above, the removal width of the conductive film and the removal width of the low dielectric constant film are made different by 1 mm or more, thereby suppressing the peeling of the low dielectric constant film when the conductive film is polished. be able to.

  The inventor first investigated the precise starting point of the low-k film peeling in Cu-CMP. According to this investigation, the starting point of the low-k film peeling was where the low-k film was formed on the outer periphery of the wafer, that is, at the edge of the low-k film. More specifically, since the low-k film is removed with a width of about 2 mm from the wafer edge immediately after the low-k film is spin-coated, the actual peeling start point is 2 mm inside the wafer edge. As described above, the reason for removing the low-k film at the wafer edge is that the unevenness of the low-k film generated around the notch or orientation flat of the wafer is removed and the low-k film formed on the wafer edge is removed from the wafer. There are two purposes for preventing particles from peeling off when contacting a case or wafer carrier. Therefore, it is necessary to remove the wafer edge of the low-k film, but this is the starting point of peeling of the low-k film in Cu-CMP.

Not only the low-k film, but also the Cu film formed by the electrolytic plating method is removed with a width of about 2 mm at the wafer edge. The reason is that if a Cu film is formed on the wafer edge, Cu adheres to the wafer case or the wafer carrier, which moves to another wafer during the process, and finally causes a problem of metal contamination. In addition, the Cu film formed by the electrolytic plating method is not formed outside the plating electrode, but the seed Cu film formed by the sputtering method is formed up to the outermost periphery of the wafer. The film thickness of the plated Cu film becomes non-uniform, and this portion is removed after plating so that no polishing residue is generated in the Cu-CMP process.
Therefore, both the low-k film and the Cu film were removed to a distance of about 2 mm from the wafer edge, and the low-k film was peeled off from the portion that was about 2 mm inside from the wafer edge in Cu-CMP.

A strong stress is applied to the edge portion of the wafer during Cu-CMP. For example, even when Cu-CMP is performed with the polishing load set to 3 psi, a load of 3.5 psi to 7 psi is applied in an area of about 2 mm from the wafer edge. This is because the wafer edge portion is strongly pressed against the polishing pad. If there is an edge of the low-k film in an area of about 2 mm from the wafer edge, the low-k film is polished with a substantially high polishing load, and the low-k film is easily peeled off. Further, since there is a step corresponding to the film thickness of the low-k film at the edge of the low-k film, the polishing load is concentrated. Once the low-k film is peeled off, the peeled area increases with the polishing time and finally peels off to the center of the wafer.
On the other hand, a strong stress is applied to the Cu film during CMP. In particular, CMP stress is concentrated at the Cu film edge in an area of about 2 mm from the wafer edge. When the low-k film edge exists at the same position as the Cu film edge, the low-k film is easily peeled off. Further, since a step corresponding to the film thickness of the Cu film is generated at the edge of the Cu film, the CMP load is concentrated. Furthermore, if the edge of the low-k film exists there, a step corresponding to the total film thickness of the low-k film and the Cu film exists on the wafer edge, and the stress of CMP is extremely concentrated on the step portion. become. That is, the outermost peripheral portion of the wafer is polished with a substantially high polishing load, and the low-k film is easily peeled off. Once the low-k film is peeled off, the peeled area expands with the polishing time, and finally the whole wafer is peeled off.

  In the present invention, the wafer edge removal width of the low-k film after applying the low-k film is separated from the wafer edge removal width of the Cu film after the Cu film is deposited by electrolytic plating. It suppresses peeling of the low-k film.

Embodiment 1 FIG.
FIG. 1 is a process sectional view for explaining the wiring forming method according to the first embodiment of the present invention.
As shown in FIG. 1A, a diffusion prevention film 2 is formed with a film thickness of, for example, 30 nm to 200 nm on a substrate as a base 1 by a CVD method. For example, a printed circuit board or a semiconductor chip can be used as the base 1 in addition to a substrate such as a silicon substrate. As the diffusion preventing film 2, for example, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, or a SiN film can be used.
Next, the low-k film 3 is formed with a film thickness of, for example, 100 nm to 1000 mm on the diffusion prevention film 2 by spin coating. Immediately thereafter, the low-k film 3 on the outer peripheral portion of the substrate is removed by a width A with a chemical solution. The removal width A, that is, the length from the substrate edge 10 to the low-k film 3 edge is preferably 4 mm or more and 15 mm or less. After the removal of the low-k film 3, baking treatment and curing are performed in an inert gas atmosphere, and further, surface modification of the low-k film 13 is performed by irradiating He plasma. As the low-k film 3, for example, an MSQ (Methyl Silsesquioxane) film, an HSQ (Hydrogen Silsesquioxane) film, or a polymer (for example, SiLK (registered trademark) manufactured by Dow Chemical Co., Ltd.), or a film in which pores are introduced is used. Alternatively, a stacked film of them can be used.

Next, as shown in FIG. 1B, a cap film 4 is formed on the low-k film 3 by a CVD method to a film thickness of, for example, 30 nm to 200 nm. As the cap film 4, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, a SiN film, or a laminated film thereof can be used.
Then, a damascene wiring groove 5 is formed in the cap film 4, the low-k film 3, and the diffusion prevention film 4 by lithography and dry etching. Then, a barrier metal film 6 is formed on the inner wall of the groove 5 and the cap film 4 by a sputtering method, and a seed Cu film is formed on the barrier metal film 6 by a sputtering method. As the barrier metal film 6, for example, a Ta film, a Ti film, a TaN film, a TiN film, a WN film, a WSiN film, or a laminated film thereof can be used. Further, a Cu film 7 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. Thereby, the inside of the trench 5 is filled with the conductive film made of the barrier metal film 6, the seed Cu film, and the Cu film 7. The annealing treatment may be performed after removing the chemical solution from the Cu film 7.

  Next, as shown in FIG. 1C, the Cu film 7 (including the seed Cu film; hereinafter the same) is removed from the outer periphery of the substrate with a chemical solution. The removal width B of the Cu film 7, that is, the length from the substrate edge 10 to the Cu film 7 edge is made 1 mm or more larger than the above-described removal width A.

Next, as shown in FIG. 1D, the unnecessary Cu film 7 and barrier metal film 6 formed on the cap film 4 are removed using an orbital CMP apparatus (not shown). As described above, since the removal width B is 1 mm or more larger than the removal width A, it is possible to avoid applying a high CMP load to the edge of the low-k film 3. The Cu film 7 remaining outside the edge of the low-k film 3 may be removed with a chemical solution.
Through the above steps, Cu damascene wiring is formed in the low-k film 3.

(Example 1)
Next, Example 1 which explains the wiring formation method according to the first embodiment in more detail will be described. The first embodiment will be described with reference to FIG.
First, as shown in FIG. 1A, an SiC film 2 having a thickness of 50 nm is formed on a silicon substrate 1 having a diameter of 300 mm by a CVD method. Then, the MSQ film 3 is formed with a film thickness of 250 nm on the SiC film 2 by spin coating. The substrate rotation speed was 900 rpm. Immediately after the application of the MSQ film 3, N-methyl-2-pyrrolidinone (CH ₃ NC ₄ H ₆ O) is dropped on the outer periphery of the wafer to remove the MSQ film 3 at the wafer edge portion by the removal width A.
Here, 14 types of samples were prepared by changing the removal width A of the MSQ film 3 from the wafer edge 10 by 1 mm from 2 mm to 15 mm. All these samples were baked at 250 ° C. in a nitrogen atmosphere using a hot plate, and then cured at 450 ° C. for 10 minutes in a nitrogen atmosphere using a hot plate. Further, a film having the same removal width A and changing the Young's modulus of the MSQ film 3 by 1 GPa from 2 GPa to 14 GPa was further prepared. The Young's modulus was changed by changing the porosity (porosity) of the MSQ film 3. The chemical composition of the MSQ film 3 was all the same.
After baking and curing, these MSQ films 3 were irradiated with helium plasma using a CVD apparatus. Thereby, the surface modification of the MSQ film 3 was performed. By the He plasma treatment, the adhesion between the MSQ film 3 and the SiO ₂ film 4 described below can be improved.

Next, as shown in FIG. 1B, a SiO ₂ film 4 having a thickness of 50 nm is formed on the MSQ film 3 by a CVD method. Subsequently, a groove 5 for damascene wiring is formed in the SiO ₂ film 4, the MSQ film 3, and the SiC film 2 by lithography and dry etching. Next, a TaN film / Ta film 6 having a thickness of 10 nm / 15 nm is formed in the trench 5 and on the SiO ₂ film 4 by a sputtering method, respectively, and a seed Cu film (not shown; the same applies hereinafter) is formed thereon by a sputtering method. Is formed with a film thickness of 75 nm. Then, a Cu film 7 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed at a temperature of 250 ° C. for 30 minutes.

Next, as shown in FIG. 1C, the Cu film 7 in the vicinity of the wafer edge 10 is removed from the wafer edge 10 by the removal width B using an aqueous solution containing 3% HF and 30% H ₂ O ₂ . The removal width B of the Cu film 7 is made 1 mm larger than the removal width A of the MSQ film 3.

Next, as shown in FIG. 1D, the unnecessary Cu film 7 and TaN film / Ta film 6 on the SiO ₂ film 4 are removed by CMP. The CMP apparatus used was an orbital type (for example, Momentum300 manufactured by Novellus), the polishing pad used was IC1000 manufactured by Rodale, and the CMP slurry used was abrasive-free slurry (HS-C430-TU) manufactured by Hitachi Chemical. The polishing conditions were CMP load: 1.5 psi, orbital rotation speed: 600 rpm, head rotation speed: 24 rpm, and slurry supply speed: 300 cc / min.

As a result of performing Cu-CMP under these conditions, it was found that the larger the removal width A of the MSQ film 3, the more the peeling of the MSQ film 3 during Cu-CMP can be suppressed. For example, in the case of a sample having the MSQ film 3 having a Young's modulus of 3 GPa, the following results were obtained.
When the removal width A of the MSQ film 3 was 2 mm, the MSQ film 3 was peeled off in just 10 seconds immediately after the start of Cu-CMP. On the other hand, when the removal width A was 3 mm, the MSQ film 3 was not peeled until 50 seconds after the start of Cu-CMP. Furthermore, when the removal width A was 4 mm, the MSQ film 3 was not peeled until 100 seconds after the start of Cu-CMP. Furthermore, as the removal width A is increased to 5 mm, 6 mm, 7 mm, 8 mm, and 9 mm, the time from the start of Cu-CMP to the separation of the MSQ film 3 is 500 seconds, 1000 seconds, 5000 seconds, 10000 seconds, and 50000 seconds. It became long. When the removal width A was 10 mm or more, the MSQ film 3 was not finally peeled off.

In the case of the sample having the MSQ film 3 having a Young's modulus of 10 GPa, if the removal width A of the MSQ film 3 is 3 mm or more, peeling of the MSQ film 3 during Cu-CMP can be suppressed. In the case of the sample having the MSQ film 3 having a Young's modulus of 9 GPa, if the removal width A is 4 mm or more, peeling of the MSQ film 3 during Cu-CMP can be suppressed. Furthermore, when the Young's modulus of the MSQ film 3 is as low as 8 GPa, 7 GPa, 6 GPa, 5 GPa, 4 GPa, and 3 GPa, the removal width A is 5 mm or more, 6 mm or more, 7 mm or more, 8 mm or more, 9 mm or more, 10 mm or more, respectively. As a result, peeling of the MSQ film 3 during Cu-CMP could be suppressed.
Accordingly, considering the Young's modulus of the low-k film and the polishing time, the removal width A is preferably 4 mm or more. Further, from the viewpoint of chip yield, it is preferable that the removal width A is within 15 mm.

(Example 2)
In Example 1 described above, the removal width B of the Cu film 7 was made 1 mm larger than the removal width A of the MSQ film 3. In Example 2, the removal width B of the Cu film 7 was relatively changed with respect to the removal width A of the MSQ film 3, and the peeling of the MSQ film 3 in Cu-CMP was examined. Hereinafter, the difference from the first embodiment will be mainly described.

  In Example 2, four types of samples were prepared in which the removal width A of the MSQ film 3 from the wafer edge 10 was set to 2 mm, 4 mm, 6 mm, and 8 mm. Further, as in Example 1, by changing the porosity (porosity) of the MSQ film 3, the removal width A is the same and the Young's modulus of the MSQ film 3 is changed by 1 GPa from 2 GPa to 14 GPa. Prepared. Moreover, what removed the removal width | variety B of Cu film | membrane 7 1 mm each from 2 mm to 15 mm was prepared. Other methods are the same as those in the first embodiment.

When a sample having the MSQ film 3 having a Young's modulus of 3 GPa was subjected to Cu-CMP for 1 minute, the following results were obtained.
It was found that when the removal width A of the MSQ film 3 and the removal width B of the Cu film 7 are equal, the peeling area of the MSQ film 3 from the wafer edge 10 increases. Further, when the removal widths A and B were 2 mm, the maximum peeling area was obtained, and as the removal widths A and B were increased to 4 mm, 6 mm, and 8 mm, the peeling area was reduced.
In contrast, it was found that when the removal width B of the Cu film 7 was made 1 mm or more larger than the removal width A of the MSQ film 3, peeling of the MSQ film 3 during Cu-CMP was suppressed. When the difference between the removal width A and the removal width B (hereinafter referred to as “edge removal width difference”) is 1 mm, peeling of the MSQ film 3 is suppressed when Cu-CMP is performed on a sample whose MSQ film 3 has a Young's modulus of 10 GPa. We were able to. In addition, when the edge removal width difference was 2 mm, it was possible to suppress peeling of the MSQ film 3 when Cu-CMP was performed on a sample whose MSQ film 3 had a Young's modulus of 6 GPa. Further, as the edge removal width difference becomes large as 3 mm, 4 mm, and 5 mm, it was possible to suppress the peeling of the MSQ film 3 when Cu-CMP was performed on the samples whose Young's modulus of the MSQ film 3 was 5 GPa, 4 GPa, and 3 GPa. .

  As described above, in the first embodiment, by setting the difference between the removal width A of the low-k film 3 and the removal width B of the Cu film 7 to 1 mm or more, the edge of the low-k film 3 and the Cu The distance to the edge of the film 7 was made wider than before. Thereby, the CMP load applied to the edge of the low-k film 3 in Cu-CMP can be significantly reduced, and the peeling of the low-k film 3 in Cu-CMP can be remarkably suppressed. Further, when the removal width A of the low-k film 3 is set to 4 mm or more, peeling of the low-k film 3 can be further suppressed.

Similar results were obtained when this experiment was performed on a wafer on which a device was mounted. The present invention can be applied not only to the first Cu wiring layer but also to the second and higher Cu wiring layers. Since the upper wiring layer is more likely to peel off the low-k film, the present invention is particularly suitable for forming the upper Cu wiring layer.
In the first embodiment, a low-k film applied as a single layer is used, but a laminated film of a applied low-k film and a low-k film formed by a CVD method may be used.

Embodiment 2. FIG.
In the first embodiment, when the removal width B of the Cu film 7 is larger than the removal width A of the low-k film 3, that is, when the edge of the low-k film 3 is closer to the outer periphery of the substrate than the edge of the Cu film 7. Explained. In the second embodiment, the removal width B of the Cu film 7 is made smaller than the removal width A of the low-k film 3, that is, the edge of the low-k film 3 is closer to the substrate center than the edge of the Cu film 7. Will be described. Since other than that is the same as that of Embodiment 1, it demonstrates below centering on difference with Embodiment 1 with reference to FIG. FIG. 2 is a process sectional view for explaining a wiring forming method according to the second embodiment of the present invention.

First, as shown in FIGS. 2A and 2B, the steps described in FIGS. 1A and 1B in the first embodiment are performed.
Next, as shown in FIG. 2C, the Cu film 7 on the outer periphery of the substrate is removed with a chemical solution. The removal width B of the Cu film 7 is 1 mm or more smaller than the removal width A of the low-k film 3.

Thereafter, as shown in FIG. 2D, the unnecessary Cu film 7 and the barrier metal film 6 formed on the cap film 4 are removed using an orbital CMP apparatus as in the first embodiment. As described above, since the removal width B is 1 mm or more smaller than the removal width A, it is possible to avoid a high CMP load from being applied to the edge of the low-k film 3.
Through the above steps, Cu damascene wiring is formed in the low-k film 3.

Also in the second embodiment, the difference between the removal width A of the low-k film 3 and the removal width B of the Cu film 7 is set to 1 mm or more in the same manner as in the first embodiment. The distance from the edge of the Cu film 7 is made wider than before. As a result, similar to the first embodiment, the CMP load applied to the edge of the low-k film 3 in Cu-CMP can be greatly reduced, and the peeling of the low-k film 3 in Cu-CMP is remarkably suppressed. can do. Further, when the removal width A of the low-k film 3 is set to 4 mm or more, peeling of the low-k film 3 can be further suppressed.
In the second embodiment, when the Cu film 7 is removed with the chemical solution, the edge of the Cu film 7 is located outside the edge of the low-k film 3. That is, the edge of the low-k film 3 is covered with the Cu film 7 in Cu-CMP. Therefore, peeling of the low-k film 3 in Cu-CMP can be further suppressed than in the first embodiment due to the anchor effect.

Embodiment 3 FIG.
In the third embodiment of the present invention, the wiring formation method of the first embodiment described above is applied to the first-layer Cu wiring of the semiconductor device.
FIG. 3 is a process sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention.
First, as shown in FIG. 3A, a semiconductor element having a diffusion layer such as a MIS transistor is formed on a substrate 1. Although a detailed description is omitted, after a gate insulating film 11 and a conductive film 12 are formed on a silicon substrate as the substrate 1, the films 12 and 11 are patterned to form the gate electrode 12. A low concentration diffusion layer (extension region) 14 is formed by implanting impurities into the substrate 1 using the gate electrode 12 as a mask, and a sidewall 13 is formed on the side wall of the gate electrode 12. High concentration diffusion layers (source / drain regions) 15 are formed by implanting impurities into the substrate 1 using the sidewalls 13 and the gate electrodes 12 as masks.

By performing such a process, an insulating film 16 is formed so as to cover the formed transistor, and a contact 17 connected to the high concentration diffusion layer 15 is formed in the insulating film 16.
Next, the diffusion prevention film 2 is formed with a film thickness of, for example, 30 nm to 200 nm on the insulating film 16 and the contact 17 by a CVD method. As the diffusion preventing film 2, for example, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, or a SiN film can be used.

  Next, the low-k film 3 is formed with a film thickness of, for example, 100 nm to 1000 mm on the diffusion prevention film 2 by spin coating. Immediately thereafter, the low-k film 3 on the outer peripheral portion of the substrate is removed by a width A with a chemical solution. The removal width A, that is, the length from the substrate edge 10 to the edge of the low-k film 3 is preferably 3 mm or more. After the low-k film 3 is removed, baking and curing are performed in an inert gas atmosphere, and surface modification of the low-k film 13 is performed by irradiation with He plasma. As the low-k film 3, for example, an MSQ (Methyl Silsesquioxane) film, an HSQ (Hydrogen Silsesquioxane) film, or a polymer (for example, SiLK (registered trademark) manufactured by Dow Chemical Co., Ltd.), or a film in which pores are introduced is used. Alternatively, a stacked film of them can be used.

Next, as illustrated in FIG. 3B, the cap film 4 is formed on the low-k film 3 with a film thickness of, for example, 30 nm to 200 nm by the CVD method. As the cap film 4, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, a SiN film, or a laminated film thereof can be used.
Then, a damascene wiring groove 5 is formed in the cap film 4, the low-k film 3, and the diffusion prevention film 2 by lithography and dry etching. Then, a barrier metal film 6 is formed on the inner wall of the groove 5 and the cap film 4 by a sputtering method, and a seed Cu film is formed on the barrier metal film 6 by a sputtering method. As the barrier metal film 6, for example, a Ta film, a Ti film, a TaN film, a TiN film, a WN film, a WSiN film, or a laminated film thereof can be used. Further, a Cu film 7 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. Thereby, the inside of the trench 5 is filled with the conductive film made of the barrier metal film 6, the seed Cu film, and the Cu film 7. The annealing treatment may be performed after removing the chemical solution from the Cu film 7.

  Next, as shown in FIG. 3C, the Cu film 7 on the outer periphery of the substrate is removed with a chemical solution. The removal width B of the Cu film 7, that is, the length from the substrate edge 10 to the Cu film 7 edge is set to be 1 mm or more larger than the removal width A described above.

  Next, as shown in FIG. 3D, the unnecessary Cu film 7 and barrier metal film 6 formed on the cap film 4 are removed using an orbital CMP apparatus as in the first embodiment. . Through the above steps, a first-layer Cu damascene wiring that is electrically connected to the diffusion layer 15 via the contact 7 is formed.

  As described above, in the third embodiment, the difference between the removal width A of the low-k film 3 and the removal width B of the Cu film 7 is set to 1 mm or more, so that the edge of the low-k film 3 and the Cu The distance to the edge of the film 7 was made wider than before. As a result, the CMP load applied to the edge of the low-k film 3 in the Cu-CMP for the first layer Cu wiring can be greatly reduced, and the peeling of the low-k film 3 in the Cu-CMP is remarkably suppressed. can do. Further, when the removal width A of the low-k film 3 is set to 4 mm or more, peeling of the low-k film 3 can be further suppressed. Therefore, the yield of the semiconductor device can be improved and the reliability of the semiconductor device can be improved.

  The third embodiment can be applied not only to the first Cu wiring layer but also to the second and higher Cu wiring layers. Since the lower wiring layer is more likely to peel off the low-k film, the present invention is particularly suitable when forming the upper Cu wiring layer (the same applies to the fourth embodiment described later).

Embodiment 4 FIG.
In the fourth embodiment of the present invention, the wiring forming method of the second embodiment described above is applied to the first-layer Cu wiring of the semiconductor device.
In the third embodiment, when the removal width B of the Cu film 7 is larger than the removal width A of the low-k film 3, that is, when the edge of the low-k film 3 is closer to the outer peripheral side of the substrate than the edge of the Cu film 7. Explained. In the fourth embodiment, when the removal width A of the low-k film 3 is larger than the removal width B of the Cu film 7, that is, when the edge of the low-k film 3 is closer to the substrate center than the edge of the Cu film 7. Will be described. Since the other points are the same as in the third embodiment, the following description will focus on the differences from the third embodiment with reference to FIG. FIG. 4 is a process sectional view for explaining the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

First, as shown in FIGS. 4A and 4B, the steps described in FIGS. 3A and 3B in the third embodiment are performed.
Next, as shown in FIG. 4C, the Cu film 7 on the outer periphery of the substrate is removed with a chemical solution. The removal width B of the Cu film 7 is 1 mm or more smaller than the removal width A of the low-k film 3.

Thereafter, as shown in FIG. 2D, the unnecessary Cu film 7 and the barrier metal film 6 formed on the cap film 4 are removed using an orbital CMP apparatus as in the first embodiment. As described above, since the removal width B is 1 mm or more smaller than the removal width A, it is possible to avoid a high CMP load from being applied to the edge of the low-k film 3.
Through the above steps, Cu damascene wiring is formed in the low-k film 3.

Also in the fourth embodiment, as in the third embodiment, the difference between the removal width A of the low-k film 3 and the removal width B of the Cu film 7 is 1 mm or more, so that the edge of the low-k film 3 The distance from the edge of the Cu film 7 is made wider than before. As a result, similar to the third embodiment, the CMP load applied to the edge of the low-k film 3 in Cu-CMP for the first layer Cu wiring can be greatly reduced, and the low-k film in Cu-CMP can be reduced. 3 can be remarkably suppressed. Further, when the removal width A of the low-k film 3 is set to 4 mm or more, peeling of the low-k film 3 can be further suppressed. Therefore, the yield of the semiconductor device can be improved and the reliability of the semiconductor device can be improved.
In the fourth embodiment, when the Cu film 7 is removed with the chemical solution, the edge of the Cu film 7 is positioned outside the edge of the low-k film 3. That is, the edge of the low-k film 3 is covered with the Cu film 7 in Cu-CMP. Therefore, peeling of the low-k film 3 in Cu-CMP can be further suppressed than in the third embodiment due to the anchor effect.

Embodiment 5 FIG.
In the fifth embodiment of the present invention, the wiring forming method of the first embodiment described above is applied to Cu wiring of a semiconductor mounting apparatus. Specifically, the semiconductor chip is applied to Cu wiring on the semiconductor chip when the semiconductor chip is packaged into a module.
FIG. 5 is a process sectional view for explaining the method for manufacturing a semiconductor mounting apparatus according to the fifth embodiment of the present invention.
First, as shown in FIG. 5A, a multilayer wiring structure 22 having multilayer wiring layers 23a, 23b, 23c, and 23d on a substrate 21 and via contacts 24a, 24b, and 24c for connecting them in an insulating film. A semiconductor chip (semiconductor device) 20 provided with is formed. The semiconductor element (for example, MIS transistor) in the multilayer wiring structure 22 is the same as that described in the third embodiment, and illustration and description thereof are omitted.

Next, the diffusion barrier film 2 is formed on the multilayer wiring structure 22 with a film thickness of, for example, 30 nm to 200 nm by the CVD method. As the diffusion preventing film 2, for example, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, or a SiN film can be used.
Next, the low-k film 3 is formed with a film thickness of, for example, 100 nm to 1000 mm on the diffusion prevention film 2 by spin coating. Immediately thereafter, the low-k film 3 on the outer peripheral portion of the substrate is removed by a width A with a chemical solution. The removal width A, that is, the length from the substrate edge 21a to the edge of the low-k film 3 is preferably 3 mm or more. After the low-k film 3 is removed, baking treatment and curing are performed in an inert gas atmosphere, and further, surface modification of the low-k film 13 is performed by irradiating He plasma. As the low-k film 3, for example, an MSQ (Methyl Silsesquioxane) film, an HSQ (Hydrogen Silsesquioxane) film, or a polymer (for example, SiLK (registered trademark) manufactured by Dow Chemical Co., Ltd.), or a film in which pores are introduced is used. Alternatively, a stacked film of them can be used.

Next, the cap film 4 is formed with a film thickness of, for example, 30 nm to 200 nm on the low-k film 3 by the CVD method. As the cap film 4, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, a SiN film, or a laminated film thereof can be used.
Then, a damascene wiring groove 5 is formed in the cap film 4, the low-k film 3, and the diffusion prevention film 2 by lithography and dry etching. Then, a barrier metal film 6 is formed on the inner wall of the groove 5 and the cap film 4 by a sputtering method, and a seed Cu film is formed on the barrier metal film 6 by a sputtering method. As the barrier metal film 6, for example, a Ta film, a Ti film, a TaN film, a TiN film, a WN film, a WSiN film, or a laminated film thereof can be used. Further, a Cu film 7 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. Thereby, the inside of the trench 5 is filled with the conductive film made of the barrier metal film 6, the seed Cu film, and the Cu film 7. The annealing treatment may be performed after removing the chemical solution from the Cu film 7.

  Next, the Cu film 7 on the outer periphery of the substrate is removed with a chemical solution. The removal width B of the Cu film 7, that is, the length from the substrate edge 21a to the Cu film 7 edge is made 1 mm or more larger than the removal width A described above.

  Next, as shown in FIG. 5B, the unnecessary Cu film 7 and barrier metal film 6 formed on the cap film 4 are removed using an orbital CMP apparatus as in the first embodiment. . Through the above steps, a Cu damascene wiring electrically connected to the wiring layer 23a is formed on the semiconductor chip 20.

  As described above, in the fifth embodiment, by setting the difference between the removal width A of the low-k film 3 and the removal width B of the Cu film 7 to 1 mm or more, the edge of the low-k film 3 and the Cu The distance to the edge of the film 7 was made wider than before. As a result, the CMP load applied to the edge of the low-k film 3 in Cu-CMP for Cu wiring formed on the semiconductor chip 20 can be greatly reduced, and peeling of the low-k film 3 in Cu-CMP can be reduced. It can be drastically suppressed. Further, when the removal width A of the low-k film 3 is set to 4 mm or more, peeling of the low-k film 3 can be further suppressed. Therefore, the yield of the semiconductor mounting apparatus can be improved, and the reliability of the semiconductor mounting apparatus can be improved.

  Although the case of forming the first Cu wiring layer on the semiconductor chip 20 has been described in the fifth embodiment, the present invention can also be applied to the case of forming a multilayer Cu wiring layer. Since the upper wiring layer is more likely to peel off the low-k film, the present invention is particularly suitable when forming the upper Cu wiring layer (the same applies to Embodiment 6 described later).

Embodiment 6 FIG.
In the sixth embodiment of the present invention, the wiring forming method of the second embodiment described above is applied to Cu wiring of a semiconductor mounting apparatus.
In the fifth embodiment, when the removal width B of the Cu film 7 is larger than the removal width A of the low-k film 3, that is, when the edge of the low-k film 3 is closer to the substrate outer side than the edge of the Cu film 7. Explained. In the sixth embodiment, when the removal width A of the low-k film 3 is larger than the removal width B of the Cu film 7, that is, when the edge of the low-k film 3 is closer to the substrate center than the edge of the Cu film 7. Will be described. Since the other points are the same as those in the fifth embodiment, the following description will focus on differences from the fifth embodiment with reference to FIG. FIG. 6 is a process sectional view for explaining the method for manufacturing the semiconductor mounting apparatus according to the sixth embodiment of the present invention.

First, as shown in FIG. 6A, the formation of the Cu film 7 is performed using the same method as in the fifth embodiment.
Next, the Cu film 7 on the outer periphery of the substrate is removed with a chemical solution. The removal width B of the Cu film 7 is 1 mm or more smaller than the removal width A of the low-k film 3.

Thereafter, as shown in FIG. 6B, the unnecessary Cu film 7 and the barrier metal film 6 formed on the cap film 4 are removed using an orbital CMP apparatus as in the first embodiment. As described above, since the removal width B is 1 mm or more smaller than the removal width A, it is possible to avoid a high CMP load from being applied to the edge of the low-k film 3.
Through the above steps, a Cu damascene wiring electrically connected to the wiring layer 23a is formed on the semiconductor chip 20.

Also in the sixth embodiment, as in the fifth embodiment, the difference between the removal width A of the low-k film 3 and the removal width B of the Cu film 7 is set to 1 mm or more, so that the edges of the low-k film 3 and The distance from the edge of the Cu film 7 is made wider than before. As a result, as in the fifth embodiment, the CMP load applied to the edge of the low-k film 3 in Cu-CMP for Cu wiring formed on the semiconductor chip 20 can be significantly reduced. The peeling of the low-k film 3 can be remarkably suppressed. Further, when the removal width A of the low-k film 3 is set to 4 mm or more, peeling of the low-k film 3 can be further suppressed. Therefore, the yield of the semiconductor mounting apparatus can be improved, and the reliability of the semiconductor mounting apparatus can be improved.
In the sixth embodiment, when the Cu film 7 is removed with the chemical solution, the edge of the Cu film 7 is located outside the edge of the low-k film 3. That is, the edge of the low-k film 3 is covered with the Cu film 7 in Cu-CMP. Therefore, peeling of the low-k film 3 in Cu-CMP can be further suppressed by the anchor effect as compared with the fifth embodiment.

Embodiment 7 FIG.
In the seventh embodiment of the present invention, the wiring forming method of the first or second embodiment described above is applied to Cu wiring of a semiconductor mounting apparatus configured with a multilayer substrate. FIG. 7 is a cross-sectional view for explaining a semiconductor mounting apparatus manufactured by the semiconductor mounting apparatus manufacturing method according to the seventh embodiment.

  As shown in FIG. 7, the semiconductor mounting apparatus includes a first layer semiconductor chip (hereinafter abbreviated as “chip”) having a substrate 31 and a multilayer wiring structure 32, a substrate 33 and a multilayer wiring structure 34. A layer chip and a third layer chip having a substrate 35 and a multilayer wiring structure 36 are stacked. The first-layer chip and the second-layer chip are face-to-face connected using a low-k film 42 as an adhesive layer, and the low-k film 45 is bonded to the second-layer chip and the third-layer chip. Face-to-back connection as a layer. Insulating layers 41 and 43 and insulating layers 44 and 46 functioning as diffusion preventing films are formed below and above the low-k films 42 and 45, respectively. A wiring layer 52 is formed in the insulating film 44. Further, the bridge via 51 connected to the wiring layer 52 is formed in the first and second layer chips, and the bridge via 53 is formed in the third layer chip, so that the three layers are stacked. The chip is electrically connected.

  By using the same method as in the fifth and sixth embodiments, Cu damascene wiring electrically connected to the bridge via 53 is formed on the third layer chip.

  Also in the seventh embodiment, as in the fifth and sixth embodiments, the difference between the removal width A of the low-k film 3 and the removal width B of the Cu film 7 is set to 1 mm or more, so that the third layer In Cu-CMP for Cu wiring formed on a chip, the CMP load applied to the edge of the low-k film 3 can be greatly reduced, and the peeling of the low-k film 3 in Cu-CMP is remarkably suppressed. be able to. Further, when the removal width A of the low-k film 3 is set to 4 mm or more, peeling of the low-k film 3 can be further suppressed. Therefore, the yield of the semiconductor mounting apparatus can be improved, and the reliability of the semiconductor mounting apparatus can be improved.

It is process sectional drawing for demonstrating the wiring formation method by Embodiment 1 of this invention. It is process sectional drawing for demonstrating the wiring formation method by Embodiment 2 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device by Embodiment 3 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device by Embodiment 4 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor mounting apparatus by Embodiment 5 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor mounting apparatus by Embodiment 6 of this invention. It is sectional drawing for demonstrating the semiconductor mounting apparatus manufactured by the manufacturing method of the semiconductor mounting apparatus by Embodiment 7 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate, substrate 2 Diffusion prevention film 3 Low-k film (MSQ film)
4 Cap film 5 Groove 6 Barrier metal film 7 Cu film 10 Wafer edge 11 Gate insulating film 12 Gate electrode 13 Side wall 14 Low concentration diffusion layer 15 High concentration diffusion layer 16 Insulating film 17 Contact 20 Semiconductor device (semiconductor chip)
21 substrate 21a substrate edge 22 multilayer wiring structure 23a, 23b, 23c, 23d, wiring layer 24a, 24b, 24c via contact 31, 33, 35 substrate 32, 34, 36 multilayer wiring structure 41, 43, 44, 46 insulating layer 42 44 low-k film 51, 53 Bridge via 52 Wiring layer

Claims (9)

A method of forming a buried wiring in a low dielectric constant film,
Forming a low dielectric constant film having a relative dielectric constant of 3 or less on the ground;
Removing the low dielectric constant film with a first width from the underlying edge;
Forming a cap film on the low dielectric constant film after removing the low dielectric constant film in the first width;
Forming a groove in the cap film and the low dielectric constant film;
Forming a conductive film inside the groove and on the cap film;
Removing the conductive film with a second width different from the first width by 1 mm or more from the edge of the foundation;
And a step of polishing the unnecessary conductive film formed on the cap film after removing the conductive film with the second width. In the wiring formation method according to claim 1,
The wiring forming method, wherein the first width is 4 mm or more and 15 mm or less. In the wiring formation method according to claim 1 or 2,
The wiring forming method, wherein the second width is smaller than the first width. Forming a semiconductor element having a diffusion layer on a substrate;
Forming an interlayer insulating film covering the semiconductor element;
Forming a contact connected to the diffusion layer in the interlayer insulating film;
Forming a low dielectric constant film having a relative dielectric constant of 3 or less on the contact and the interlayer insulating film;
Removing the low dielectric constant film with a first width from an edge of the substrate;
Forming a cap film on the low dielectric constant film after removing the low dielectric constant film;
Forming a groove reaching the surface of the contact in the cap film and the low dielectric constant film;
Forming a conductive film inside the groove and on the cap;
Removing the conductive film with a second width different from the first width by 1 mm or more from the edge of the substrate;
And polishing the unnecessary conductive film formed on the cap film after removing the conductive film. In the manufacturing method of the semiconductor device according to claim 4,
The method for manufacturing a semiconductor device, wherein the first width is not less than 4 mm and not more than 15 mm. In the manufacturing method of the semiconductor device according to claim 4 or 5,
The method for manufacturing a semiconductor device, wherein the second width is smaller than the first width. Forming a low dielectric constant film having a relative dielectric constant of 3 or less on a semiconductor device having a semiconductor element;
Removing the low dielectric constant film with a first width from an edge of the semiconductor device;
Forming a cap film on the low dielectric constant film after removing the low dielectric constant film;
Forming a groove in the cap film and the low dielectric constant film;
Forming a conductive film inside the groove and on the cap;
Removing the conductive film with a second width different from the first width by 1 mm or more from an edge of the semiconductor device;
And a step of polishing the unnecessary conductive film formed on the cap film after removing the conductive film. In the manufacturing method of the semiconductor mounting device according to claim 7,
The method for manufacturing a semiconductor mounting device, wherein the first width is 4 mm or more and 15 mm or less. In the manufacturing method of the semiconductor mounting device according to claim 7 or 8,
The method for manufacturing a semiconductor mounting device, wherein the second width is smaller than the first width.

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