JP2006294770A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the adhesiveness of the second insulating film laminated on the first insulating film and to prevent peeling when a second insulating film is ground, by irradiating a plasma at the periphery of the first insulting film. <P>SOLUTION: In the semiconductor device 1 having a multilevel metallization texture is set on the substrate 11 at the semiconductor device 1, the insulating film which insulates electrically between interconnect lines of the above multilevel metallization structure consists of the lamination of the first insulating film 21 and the second insulating film 22, and a plasma exposure region 31 is formed on the periphery of the substrate 11 and on the first insulating film 21 between the above first insulating film 21 and the above second insulating film 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device and a method of manufacturing the same, in which peeling of an insulating film does not occur at the time of chemical mechanical polishing (hereinafter referred to as CMP) in which copper as a wiring material is embedded in a wiring groove or via hole. The present invention relates to a semiconductor device manufactured by:

  In the manufacturing method of a semiconductor device having a multilayer wiring structure, an insulating film that electrically insulates between wirings is formed in a structure in which two or more kinds of insulating films are stacked. In particular, in order to reduce the value of dielectric constant (k) of the insulating film, various insulating films having weaker adhesion than those of conventionally used silicon oxide films and silicon nitride films are used.

  As a technique for manufacturing the multilayer wiring structure, there is disclosed a so-called dual damascene method in which copper serving as a conductive material is embedded in grooves and holes formed in an insulating layer (see, for example, Patent Document 1). The insulating layer disclosed in Patent Document 1 has a laminated structure, and in FIG. 3 of Patent Document 1 and paragraph number 0032 of the specification, “dielectric insulating layers 2, 3 and 4 are attached to form a high conductivity interconnect. The pair of insulating layers can be deposited by ECR, sputtering, plasma CVD, CVD, spin coating, or any combination of these methods, for example, these insulating layers can be polyimide, It can be made of silicon nitride, alumina, silicon dioxide, phosphosilicate glass, yttrium oxide, magnesium oxide, aerogel, or any combination of these materials.

  Also, it has a laminated structure of an insulating film of a wiring (line) layer and an insulating film of a via layer, the insulating film of the via layer is a laminated film of a TEOS oxide film / organic polymer spin-on material film, and insulation of the wiring layer A semiconductor device in which the film is a laminated film of a TEOS oxide film / organic polymer spin-on material film is disclosed (for example, see Non-Patent Document 1).

  Also disclosed is a semiconductor device having a laminated structure of an insulating film of a wiring (line) layer and an insulating film of a via layer, and further having an insulating film of a wiring layer having a laminated structure (see, for example, Patent Document 2). ). Specifically, as the insulating film for the via layer, the passivation film 111 is formed of a silicon nitride film, the first interlayer insulating film 112 is formed of a silicon oxide film thereon, and the insulating film of the wiring layer is It is disclosed that the second interlayer insulating film 114 is formed of an organic polymer and the mask layer 115 is formed of a silicon oxide film.

  When such thin films having low adhesion are used in a stacked manner, there has been a problem that peeling occurs in the mechanical force in the semiconductor device manufacturing process or the thermal process. Specifically, as a process in which adhesion is a problem, a CMP process for planarizing an oxide film, a CMP process for forming a trench wiring structure in which wiring is embedded in a trench, and a low dielectric constant film ( Among those skilled in the semiconductor process technology, there are an annealing step for crosslinking (also referred to as a low-k film), a copper film annealing step, a packaging step, and the like.

  In particular, in the CMP process, it is difficult to avoid peeling because a mechanical force is applied to the film, and as the dielectric constant is reduced and the relative dielectric constant k <3.0 is entered, it becomes large. It has become a problem. As a method for suppressing such film peeling, the following solutions have been proposed.

Its solution is a method of improving the adhesion of the insulating film of SiO ₂ and SiOCH, between SiO ₂ and SiOCH, carbon (C) concentration and the hydrogen (H) concentration is low oxygen in the film (O ) A technique for improving adhesion by having a SiOCH film having a high concentration is disclosed (for example, see Patent Document 3).

However, it is generally known that a SiOCH film having a low carbon concentration and a low hydrogen concentration and a high oxygen concentration in the film has a higher relative dielectric constant (k) value than a normal SiOCH film. Paragraph No. 0041 of FIGS. 4 (a), (b), (c) and related description of Patent Document 3 includes dinitrogen monoxide (N ₂ O), ammonia (NH ₃ ), hydrogen (H ₂ ) It is described that when the SiOCH film is formed by modifying the underlying SiOCH film using a plasma such as ₂ ), the relative dielectric constant increases. Further, in claim 25 of Patent Document 3, as a method of forming the SiOCH, a gas containing helium (He) or argon (Ar) and not oxygen (O), hydrogen (H), or nitrogen (N) is used. It describes that the underlying SiOCH is altered by using a step of processing in a plasma atmosphere using hydrogen and a step of performing a heat treatment in an atmosphere using a gas containing oxygen (O). As this effect, as described in paragraph No. 0024 of the specification of Patent Document 3 and paragraph No. 0041 of the specification of Patent Document 3, the modification reaction is suppressed to only about 20 nm of the underlying SiOCH. It is disclosed that the increase in the relative dielectric constant value can be suppressed because the control in the depth direction can be easily performed.

  As described above, in the technique disclosed in Patent Document 3, it is necessary to select a gas type of plasma so as not to cause an increase in the relative dielectric constant value by the plasma processing. Therefore, depending on the selection of the insulating film, sufficient adhesion may not be ensured. Further, even when the modified layer is 20 nm, the relative dielectric constant value is increased in the modified layer. When the semiconductor device is miniaturized, the vertical structure size is further reduced, and the dielectric constant is further reduced. Even a thickness of 20 nm is a problem.

Another method for improving the adhesion between the SiO ₂ film and the SiOCH film is disclosed (for example, see Patent Document 4). This Patent Document 4 discloses a method in which an intermediate layer having a C concentration of 10% to 90% is inserted between the SiO ₂ film and the SiOC film as compared with the underlying SiOC, as in the above Patent Document 3. Yes. Regarding the film thickness of the intermediate layer (corresponding to the modified layer), in paragraph Nos. 0029 and 0030 of the specification of Patent Document 4, it is possible to sufficiently suppress film peeling at 10 nm or more, and if it is 50 nm or less, the leakage current increases. It is described that it is suppressed. As a method for forming the intermediate layer, a plasma treatment using a rare gas such as He gas or Ar gas is described in paragraph No. 0033 of the specification of Patent Document 4. Further, it is suggested that when the treatment is performed by plasma treatment containing oxygen and nitrogen active species (ions, radicals) (for example, O ₂ , N ₂ O), the number of modified layers increases and the leakage current increases. Yes.

  As described above, in the technique disclosed in Patent Document 4, it is necessary to select a gas type of plasma so as not to cause an increase in leakage current by plasma processing. In addition, a sufficient effect cannot be obtained as the distance between wirings is reduced as the semiconductor device is miniaturized and the plasma resistance of the insulating film is deteriorated as the dielectric constant is lowered.

  In addition, a method for improving film peeling at the time of CMP when an organic material is used is disclosed (for example, see Patent Document 5). This Patent Document 5 discloses a method for improving film peeling during CMP by curing an organic insulating material at the periphery of a wafer, and ultraviolet irradiation is disclosed as a method for curing the organic insulating material. . However, in the case of an inorganic insulating material, there is a problem that the effect of improving the adhesion is not generated by ultraviolet irradiation.

Japanese Patent No. 3057054 JP 2001-44189 A JP 2004-253790 A JP 2004-207604 A JP 2000-100894 A Yasutaka Nishioka "Organic Low-k / Cu integration technology based on CD control", sponsored by Global Net Co., Ltd. "Basic theory and wiring application technology of Low-k film damascene process for k <2.5" p. 4-1-1 to 4-1-8, February 20, 2002

  The problem to be solved is that the insulating film is peeled off in the CMP process. In particular, it is impossible to prevent the peeling of the insulating film near the edge of the wafer or the edge of the insulating film where pressure is concentrated during CMP.

  In view of the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device that do not cause film peeling during CMP without adversely affecting a chip formation region that is a product.

  The semiconductor device of the present invention is a semiconductor device having a multilayer wiring structure on a substrate, and the insulating film that electrically insulates between the wirings of the multilayer wiring structure is formed by laminating a first insulating film and a second insulating film. The main feature is that a plasma irradiation region is formed on the first insulating film between the first insulating film and the second insulating film on the periphery of the substrate.

  The method of manufacturing a semiconductor device according to the present invention is the method of manufacturing a semiconductor device in which a multilayer wiring structure is formed on a substrate, wherein the step of forming an insulating film that electrically insulates the wirings of the multilayer wiring structure Forming a first insulating film, irradiating only the first insulating film on the periphery of the substrate with plasma, and forming the second insulating film on the first insulating film. Is the most important feature.

  In the semiconductor device of the present invention, the insulating film that electrically insulates the wirings of the multilayer wiring structure is formed by stacking the first insulating film and the second insulating film, and the first insulating film and the second insulating film are formed on the periphery of the substrate. Since the plasma irradiation region is formed on the first insulating film between the two insulating films, the adhesion of the first insulating film to the plasma irradiation region is enhanced, and only on the first insulating film on the periphery of the substrate. Since the plasma irradiation region is formed, the region where the product chip is formed is not irradiated with plasma. For this reason, in the region where the product chip of the first insulating film is formed, the relative dielectric constant does not increase, so the problem of increase in inter-wiring capacitance does not occur, and it is not weakened by plasma irradiation. There is an advantage that the problem of an increase in leakage current is eliminated. Furthermore, plasma irradiation is performed only on the peripheral part of the substrate to improve the adhesion between the first insulating film and the second insulating film in the peripheral part of the substrate, so that the peripheral part of the substrate where the polishing pressure is concentrated is the starting point. The film peeling at the time of CMP which generate | occur | produces is prevented. Furthermore, the manufacturing method of the present invention has an advantage that the same effect can be obtained regardless of whether the first insulating film is an organic insulating film or an inorganic insulating film.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming an insulating film that insulates the wirings of the multilayer wiring structure includes the step of forming the first insulating film and the first insulating film on the periphery of the substrate. And the step of forming the second insulating film on the first insulating film, the film quality of the portion of the first insulating film irradiated with the plasma is modified, and the adhesiveness is high. In addition, since only the first insulating film on the periphery of the substrate is irradiated with plasma, the region where the product chip is formed is not irradiated with plasma. For this reason, the first dielectric film in the region where the product chip is formed does not increase in relative dielectric constant, so that the problem of increase in inter-wiring capacitance does not occur and is not weakened by plasma irradiation. There is an advantage that the problem of an increase in leakage current is eliminated. Furthermore, film peeling during CMP occurs from the periphery of the substrate where the polishing pressure is concentrated, so that only the periphery of the substrate is irradiated with plasma, and the first insulating film and the second insulating film in the periphery of the substrate are exposed. By increasing the adhesion between the insulating films, peeling of the entire surface of the insulating film can be prevented. Furthermore, the manufacturing method of the present invention has an advantage that the same effect can be obtained regardless of whether the first insulating film is an organic insulating film or an inorganic insulating film.

  An embodiment according to a semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG.

  As shown in FIG. 1, an insulating film 12 is formed on a substrate (wafer) 11 on which a semiconductor element such as a transistor, wiring, etc., not shown, is formed. For example, a silicon substrate is used as the substrate 11. The insulating film 12 is made of a silicon oxide film and has a thickness of, for example, 500 nm. A first insulating film 21 that forms an insulating film between the wirings is formed on the insulating film 12. Here, the first insulating film 21 is a film having a relative dielectric constant of 3.0 or less, and is formed of, for example, a SiC-based film containing silicon and carbon. For example, there are a SiOC film and a film containing nitrogen or hydrogen in the SiOC film. The first insulating film 21 is formed to a thickness of 200 nm by, for example, plasma CVD.

  On the peripheral portion of the first insulating film 21 (for example, a range within 5 mm from the outer periphery of the wafer), a plasma processing region 31 formed by irradiating plasma is formed. The plasma processing region 22 is a region for improving the adhesion with the second insulating film 22 formed on the first insulating film 21. Therefore, a plasma irradiation region 31 having improved adhesion from the surface of the other first insulating film 21 is formed in an annular shape around the first insulating film 21. For the plasma irradiation, for example, plasma of a rare gas such as helium (He) or argon (Ar) is irradiated. Or you may irradiate oxygen plasma and nitrogen plasma. The plasma irradiation region 31 is preferably a region where a product chip is not formed.

Further, a second insulating film 22 that forms an insulating film between the wirings is formed on the first insulating film 21. The second insulating film 22 is formed of, for example, a silicon oxide (SiO ₂ ) film, and has a thickness of 200 nm, for example.

  Next, FIG. 2 shows a cross-sectional structure in the vicinity of the wafer peripheral portion where the trench wiring structure is formed.

  As shown in FIG. 2, a trench wiring structure is formed in the first insulating film 21 and the second insulating film 22. For example, a via 41 connected to a wiring or element (not shown) formed below the first insulating film 21 is formed in the first insulating film 21, and the via is formed in the second insulating film 22. A trench wiring 42 to be connected is formed. Note that a wiring structure similar to that shown in the figure can be formed even on the wafer center side.

The semiconductor device 1 irradiates the periphery of the first insulating film 21 with plasma before forming the second insulating film 22 after forming the first insulating film 21 constituting the insulating film between the wirings. Therefore, the adhesion between the first insulating film 21 and the second insulating film 22 is improved.
The reason for this is that when oxygen plasma is used, the surface of the first insulating film is oxidized to improve adhesion to the second insulating film, and when nitrogen plasma is used, the surface of the first insulating film is nitrided. As a result, the adhesion with the second insulating film is enhanced, and when a rare gas is used, the CH group (for example, CH ₃ etc.) in the vicinity of the surface is eliminated by impact on the surface of the first insulating film, thereby This is because the adhesion to the second insulating film is enhanced by being brought close to the surface state. As a result, the adhesion of the second insulating film 22 to the first insulating film 21 can be enhanced at the peripheral portion. Therefore, after the second insulating film 22 is formed, for example, a CMP process is performed to perform the first and second insulating films. Even if a load in a direction substantially parallel to the surface of the first insulating film 21 is applied between the films 21 and 22, there is an advantage that it is possible to prevent the second insulating film 22 from being peeled off from the first insulating film 21. In particular, the adhesion at the periphery of the film where film peeling is likely to occur is enhanced, which is effective in preventing film peeling. Therefore, the yield can be improved and the reliability of the insulating film can be improved.

  In the semiconductor device 1, since the plasma irradiation region is formed on the first insulating film 21 between the first insulating film 21 and the second insulating film 22 on the periphery of the substrate 11, a product chip is formed. The region to be subjected is not irradiated with plasma. For this reason, in the region where the product chip of the first insulating film 21 is formed, the relative dielectric constant does not increase, so that the problem of increase in inter-wiring capacitance does not occur, and it is not weakened by plasma irradiation. Therefore, there is an advantage that the problem that the leakage current increases is eliminated.

  Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to manufacturing process diagrams of FIGS.

  As shown in FIG. 3A, an insulating film 12 is formed on a substrate (wafer) 11. For example, a silicon substrate is used as the substrate 11. The insulating film 12 is made of a silicon oxide film and has a thickness of, for example, 500 nm. The film forming method is based on, for example, a plasma CVD method. Next, a first insulating film 21 is formed on the insulating film 12. Here, the first insulating film 21 is a film having a relative dielectric constant of 3.0 or less, and is formed of, for example, a SiC-based film containing silicon and carbon. For example, there are a SiOC film, a film containing nitrogen or hydrogen in the SiOC film, and the like. The first insulating film 21 is formed to a thickness of 200 nm, for example. In this film forming method, for example, a parallel plate type plasma CVD apparatus is used, and methylsilane is used as a silicon source of the source gas. As film forming conditions, the substrate temperature is set to 300 ° C. to 400 ° C., the plasma power is set to 150 W to 350 W, and the pressure of the film forming atmosphere is set to about 100 Pa to 1000 Pa.

  Next, as shown in FIG. 3B, a protective film 23 is formed on the first insulating film 21. For example, a resist film is used as the protective film 23. For example, after a resist film is formed to a thickness of, for example, 500 nm on the first insulating film 21 by a normal resist coating technique, exposure, development, and so on are performed so that the peripheral portion of the resist film is removed by a normal lithography technique. Bake. For example, the resist film was removed with a width of 4 mm inward from the edge of the first insulating film 21 (substrate 11). Here, the reason why the removal width of the resist film from the edge of the substrate 11 is set to 4 mm is that the chip as the product cannot be removed in the semiconductor process, and the width is the size of the chip as the product and the chip. It depends on layout, semiconductor process, etc. Therefore, depending on the case, it may be about 5 mm, and about 3 mm may be sufficient. Further, the thickness of the protective film 23 needs to be set such that the first insulating film 21 covered with the protective film 23 is not damaged by plasma in the next plasma irradiation step.

  Next, as shown in FIG. 4C, the protective film 23 is used as a plasma irradiation mask to irradiate the peripheral portion of the exposed first insulating film 21 with plasma. For this plasma irradiation, for example, plasma of a rare gas such as helium (He) or argon (Ar) can be used. Alternatively, oxygen plasma or nitrogen plasma can be used. In the case of using oxygen plasma and nitrogen plasma, when the protective film 23 is formed of a resist, the resist is oxidized, so that long-time plasma irradiation becomes difficult. In this case, in addition to increasing the resist thickness to 1 μm, for example, an inorganic insulating film such as a silicon oxide film or a silicon nitride film can be used for the protective film 23, and the influence of stress on the base is taken into consideration. It is preferable to use a silicon oxide film. As a result of the plasma irradiation, a plasma irradiation region 31 having improved adhesion from the surface of the other first insulating film 21 is formed in an annular shape around the first insulating film 21.

Thereafter, the protective film 23 is removed. At this time, plasma treatment may be used, but it is desirable to use a method using chemical treatment in order to reduce the influence on the first insulating film 21. When the protective film 23 is a resist, for example, sulfuric acid / hydrogen peroxide (H ₂ SO ₄ + H ₂ O ₂ ) can be used as the chemical liquid used for the chemical treatment, and when the protective film 23 is a silicon oxide film, for example, hydrofluoric acid (HF ) Can be used. As a result, the first insulating film 21 is exposed as shown in FIG. In addition, after removing the protective film 23, the surface of the first insulating film 21 may be cleaned as necessary.

  Next, as shown in FIG. 5 (5), a second insulating film 22 is formed on the first insulating film 21. For example, a silicon oxide film is used for the second insulating film 22. The second insulating film 22 can be formed by depositing silicon oxide to a thickness of 200 nm on the first insulating film 21 by, for example, plasma CVD.

  Although not shown, a trench wiring structure can be formed in the first insulating film 21 and the second insulating film 22. For example, after forming a via hole penetrating from the second insulating film 22 to the first insulating film 21, a wiring groove is formed only in the second insulating film 22. Thereafter, the conductive film is formed so as to be embedded in the wiring trench and the via hole through an adhesion layer and a barrier layer. Thereafter, the excess conductive film, the barrier layer, the adhesion layer, and the like on the second insulating film 22 are removed. As a result, as shown in FIG. 6, a via 41 is formed in the via hole via the adhesion layer and the barrier layer, and the via 41 is formed in the wiring trench via the adhesion layer and the barrier layer. A trench wiring 42 connected to is formed. In the drawing, the peripheral portion side of the substrate is shown, but a similar wiring structure can be formed on the central portion side of the substrate.

  Note that the second insulating film 22 is not limited to the inorganic insulating film, and an organic insulating film can be used to improve the adhesion with the first insulating film 21. For example, as the organic film, a polyaryl ether film is formed to a thickness of 200 nm, for example. Examples of the polyaryl ether film include SiLK-J (Dow Chemical), and other examples include SiLK-Y from Dow Chemical, FLARE from Allied Signal, and VE from Schumacker. ing. For example, when the polyaryl ether film is formed of SiLK, it can be formed by depositing the precursor by spin coating and then performing a curing process at 400 ° C. to 450 ° C.

  When vias and groove wirings are formed in the first insulating film and the second insulating film 22, after the first to second insulating films 21 to 22 are formed, for example, patterning of wiring grooves, via holes, etc. is performed. Just do it. The structure of the present invention can also be used for an insulating film having a so-called dual damascene structure in which a trench wiring and a via are formed simultaneously. For example, connection portions (vias) that connect the wirings are formed in the first insulating film 21, and groove wirings are formed in the second insulating film 22. There are many known examples of the technology for simultaneously forming the trench wiring and the via. For example, JP 2001-44189A discloses a detailed description. Also for these known insulating films, as in the present invention, the peripheral portion of the first insulating film 21 in which the via is formed is subjected to plasma irradiation treatment to form the second insulating film 22 in which the trench wiring is formed. It is possible to adopt a configuration to Further, when the second insulating film 22 is formed of an organic film, a third insulating film made of an inorganic film is formed on the second insulating film 22 so that the second insulating film is not directly polished. May be.

  In the semiconductor device manufacturing method, since only the first insulating film 21 on the periphery of the substrate 11 is irradiated with plasma, the film quality of the plasma irradiation region 31 of the first insulating film 21 is modified and the adhesion becomes high. In addition, since only the first insulating film 21 on the periphery of the substrate 11 is irradiated with plasma, the region where the product chip is formed is not irradiated with plasma. For this reason, the first dielectric film 21 in the region where the product chip is formed does not increase in relative dielectric constant, so that the problem of increase in inter-wiring capacitance does not occur and is not weakened by plasma irradiation. Therefore, there is an advantage that the problem that the leakage current increases is eliminated. Furthermore, film peeling at the time of CMP occurs from the periphery of the substrate 11 where the polishing pressure is concentrated. Therefore, only the first insulating film 21 on the periphery of the substrate 11 is irradiated with plasma, and the film is peeled off at the periphery of the substrate 11. By improving the adhesion between the first insulating film 21 and the second insulating film 22, it is possible to prevent peeling of the entire insulating film. Therefore, since it is possible to ensure adhesion with the first insulating film 21 made of a SiOC film, which has conventionally been difficult to ensure adhesion, a wiring forming film formed on the second insulating film 22 is used. When polished, the second insulating film 22 does not peel off from the first insulating film 21. Furthermore, the manufacturing method of the present invention has an advantage that the same effect can be obtained regardless of whether the first insulating film is an organic insulating film or an inorganic insulating film.

  Next, an experiment for confirming the effect of the present invention was performed. As shown in FIG. 1, the method is to prepare an invention sample (Example) in which the first insulating film 21 and the second insulating film 22 are formed on the substrate 11 via an insulating film. CMP was performed on the second insulating film 22. As a comparison with the inventive sample, a comparative sample (comparative example) was prepared in which the first insulating film 21 was not irradiated with plasma and the second insulating film 22 was formed on the first insulating film 21.

Next, CMP was performed on each of the second insulating films 22 of the inventive sample (Example) and the comparative sample (Comparative Example). In this CMP, for example, a polishing pad having an upper layer made of foamed polyurethane and a lower layer made of PET (polyethylene terephthalate) was used. As an example of such a polishing pad, there is a laminated polishing pad in which the upper layer is a 1.2 mm thick IC1000 manufactured by Rodel and the lower layer is a 1.2 mm thick SUBA400 manufactured by the same company. A polishing liquid (polishing slurry) obtained by adding hydrogen peroxide (H ₂ O ₂ ) as an oxidizing agent to colloidal silica dispersed in an alkaline solvent is used. For example, there is CMS8301 manufactured by JSR. The supply flow rate of the polishing liquid is, for example, 150 ml / min, the rotation speed of the polishing pad is, for example, 100 rpm, the rotation speed of the wafer (substrate) is, for example: 110 rpm, the polishing pressure is, for example, 300 g / cm ² , and the polishing time is, for example, 60 seconds. Thereby, the thickness of the surface layer of the SiO ₂ film of the second insulating film 22 of about 70 nm was removed.

  The CMP was performed under the same conditions for both the inventive sample and the comparative sample. After polishing, the periphery of the insulating film was observed with a microscope, and the peeling state of the second insulating film 22 with respect to the first insulating film 21 was observed with a microscope. The results are shown in Table 1. In Table 1, ◎ indicates no peeling, and X indicates that there is peeling.

As is clear from Table 1 above, the comparative example was peeled inward from 4 mm from the periphery of the substrate, whereas in the example, 4 mm from the periphery of the substrate not subjected to the plasma irradiation treatment. No peeling at the inner part was found. From this result, according to the present invention, peeling is effective not only on the outer side of the substrate peripheral part 4 mm with improved adhesion but also on the inner side of the substrate peripheral part 4 mm not subjected to the adhesion improving process by plasma irradiation. It was found to be suppressed. This is because the adhesion of the SiO ₂ / SiOC interface in the peripheral part of the substrate is improved by the plasma irradiation treatment on the SiOC surface in the peripheral part of the substrate at the SiO ₂ / SiOC interface that originally had poor adhesion, and pressure is concentrated during CMP. It can be said that the periphery of the substrate is difficult to peel off, and as a result, the substrate surface is protected. Therefore, in the above-described embodiment, not only the wafer peripheral portion with improved adhesion (for example, the range in which the plasma irradiation processing is performed) but also the region inside the substrate peripheral portion that has not been subjected to the plasma irradiation processing for improved adhesion. Also, the effect of preventing film peeling was obtained.

  Further, when the second insulating film 22 is formed of, for example, an inorganic film or an organic film in addition to the silicon oxide film, and when the first insulating film 21 is formed of various SiOC-based films, the same result as described above is obtained. It became. Therefore, it can be said that the present invention is effective for an inorganic film or an organic film for the second insulating film using a SiOC-based film for the first insulating film 21.

1 is a schematic cross-sectional view showing an embodiment of a semiconductor device according to the present invention. 1 is a schematic cross-sectional view showing an example in which a trench wiring structure is applied to a semiconductor device of the present invention. It is manufacturing process sectional drawing which showed the example of 1 embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed the example of 1 embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed the example of 1 embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed an example which applied the groove wiring structure to the manufacturing method of the semiconductor device of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Board | substrate, 21 ... 1st insulating film, 22 ... 2nd insulating film, 31 ... Plasma irradiation area | region

Claims (10)

In a semiconductor device having a multilayer wiring structure on a substrate,
The insulating film that electrically insulates between the wirings of the multilayer wiring structure is formed by laminating a first insulating film and a second insulating film,
A semiconductor device, wherein a plasma irradiation region is formed on the first insulating film between the first insulating film and the second insulating film on the periphery of the substrate. The semiconductor device according to claim 1, wherein the peripheral portion of the substrate is formed of a region where a chip as a product does not exist. The semiconductor device according to claim 1, wherein the first insulating film is made of a low dielectric constant insulating film having a relative dielectric constant of 3.0 or less. The semiconductor device according to claim 1, wherein the first insulating film is made of an insulating material containing silicon and carbon. In a manufacturing method of a semiconductor device in which a multilayer wiring structure is formed on a substrate,
The step of forming an insulating film that electrically insulates the wiring of the multilayer wiring structure,
Forming the first insulating film;
Irradiating plasma only to the first insulating film on the periphery of the substrate;
Forming the second insulating film on the first insulating film. A method of manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 5, wherein the peripheral portion of the substrate is formed of a region where a chip to be a product does not exist. The method of manufacturing a semiconductor device according to claim 5, wherein a protective film is formed on the first insulating film to cover a region where a chip to be a product is formed before the plasma irradiation. The method for manufacturing a semiconductor device according to claim 5, wherein the plasma treatment for irradiating the plasma uses a plasma containing a rare gas. The method of manufacturing a semiconductor device according to claim 5, wherein the first insulating film is made of a low dielectric constant insulating film having a relative dielectric constant of 3.0 or less. The method for manufacturing a semiconductor device according to claim 5, wherein the first insulating film is made of an insulating material containing silicon and carbon.

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