JP2005217319A - Multilayer wiring structure, semiconductor device and semiconductor packaging equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress stripping of a low dielectric constant film in polishing a conductive film. <P>SOLUTION: A first diffusion prevention film 11, a first low-k film 12 and a first cap film 13 are formed on a silicon substrate 1, and a barrier film 15 and a Cu film 16 are buried in these films to form a first conductivity type layer. A second diffusion prevention film 21, a second low-k film 22 and a second cap film 23 are formed thereon, and a barrier film 25 and a Cu film 26 are buried in these films to form a second conductivity type layer. Difference between the edge removing width B of the second low-k film 22 in the upper layer and the edge removing width A of the first low-k film 12 in the lower layer is set at 0.4 mm or more. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a multilayer wiring structure, a semiconductor device, and a semiconductor mounting device, and more particularly to formation of a buried wiring in which a low dielectric constant film and a Cu wiring are combined.

Along with higher integration and higher performance of semiconductor integrated circuits (hereinafter referred to as “LSI”), new microfabrication techniques have been proposed. One of them is a chemical mechanical polishing (hereinafter referred to as “CMP”) method, which is particularly used for flattening an interlayer insulating film, forming a metal plug, and forming a buried wiring in a multilayer wiring forming process (for example, (See Patent Document 1).
In recent years, signal delay of wiring has become a problem, and the movement to change the wiring material from a conventional Al alloy to a low-resistance Cu alloy is progressing. Since Cu alloy is difficult to finely process by dry etching, a groove is formed in the insulating film, a Cu film is deposited in the groove, and unnecessary Cu film other than the groove is removed by CMP. A so-called damascene method for forming a buried Cu wiring is employed (see, for example, Patent Document 2).
Further, in order to reduce the parasitic capacitance between wirings, an LSI using a low dielectric constant film (hereinafter also referred to as “low-k film”) having a relative dielectric constant lower than that of the SiO ₂ film has been developed. Yes. That is, a low dielectric constant film having k of 1.5 to 3.5 is used in place of the SiO ₂ film having a relative dielectric constant k of about 4.2. Development of a low dielectric constant film material having k of 2.5 or less is also underway. The material of which k is 2.5 or less is often a porous low-k film material into which pores are introduced.

However, the low dielectric constant film has a lower mechanical strength than the SiO ₂ film. For this reason, when forming a multilayer wiring structure in which a low dielectric constant film and a Cu wiring are combined, there is a problem that structural breakdown occurs in the low dielectric constant film due to the polishing load of CMP, or a cap film in contact with the low dielectric constant film or There was a problem that the base insulating film peeled off. In particular, when a low dielectric constant film material having a low Young's modulus and hardness, or a low dielectric constant film material having a low adhesiveness to the cap film is used, the above-described problem occurs remarkably. In particular, it has been reported that peeling occurs easily when the Young's modulus of the low dielectric constant film is 5 GPa or less (for example, see Non-Patent Document 1).
Such peeling of the low dielectric constant film that occurs during Cu-CMP often starts from the substrate edge (see, for example, Non-Patent Document 2). Further, as the polishing time becomes longer, the peeling area tends to increase toward the center of the wafer.

  Therefore, conventionally, peeling of the low dielectric constant film has been reduced by lowering the polishing load of CMP. On the other hand, the use of a low dielectric constant film material having a high Young's modulus and hardness is effective in suppressing peeling of the low dielectric constant film.

US Pat. No. 4,944,836 JP-A-2-278822 Simon Lin, 11 others, “Low-k Dielectrics Characterization for Damascene Integration”, 2001, IITC2001 Stan Tsai, 6 others, “Copper CMP at Low Shear Force for Low-k Compatibility”, 2002, IITC2002

However, when the polishing load of CMP is lowered, there is a problem that the polishing rate is lowered and the throughput is lowered. Further, when the Young's modulus and hardness are increased, there is a problem that the relative dielectric constant k increases.
The peeling of the low dielectric constant film during Cu-CMP is a major problem in Cu wiring development, and even if the peeling area is reduced, the peeling of the low dielectric constant film at the substrate edge has hardly been solved.

  The present invention has been made to solve the above-described conventional problems, and an object thereof is to suppress peeling of a low dielectric constant film during polishing of a conductive film when a multilayer wiring is formed.

A multilayer wiring structure according to the present invention includes a first low dielectric constant film formed on a base and having a first width removed from an edge of the base;
A first conductive layer embedded in a first opening formed in the first low dielectric constant film;
A second low dielectric constant formed on the first conductive layer and the first low dielectric constant film and removed from the underlying edge by a second width different from the first width by 0.4 mm or more. A membrane,
And a second conductive layer embedded in a second opening formed in the second low dielectric constant film.

A semiconductor device according to the present invention includes a semiconductor element formed on a substrate and having a diffusion layer;
An interlayer insulating film covering the semiconductor element;
A contact formed in the interlayer insulating film and connected to the diffusion layer;
A first low dielectric constant film formed on the contact and the interlayer insulating film and removed from the edge of the substrate by a first width;
A first conductive layer embedded in a first opening formed in the first low dielectric constant film;
A second low dielectric constant formed on the first conductive layer and the first low dielectric constant film and removed from the edge of the substrate by a second width different from the first width by 0.4 mm or more. A membrane,
And a second conductive layer embedded in a second opening formed in the second low dielectric constant film.

  In the semiconductor device according to the present invention, when the thickness of the second low dielectric constant film is 300 nm or more and less than 600 nm, the first width and the second width are preferably different from each other by 0.7 mm or more. is there. In addition, when the thickness of the second low dielectric constant film is 600 nm or more, it is preferable that the first width and the second width are different from each other by 1.0 mm or more.

  In the semiconductor device according to the present invention, it is preferable that the second width is larger than the first width.

A semiconductor mounting apparatus according to the present invention includes a semiconductor chip having a semiconductor element and an upper layer wiring on a substrate,
A first low dielectric constant film formed on the semiconductor chip and removed from the edge of the semiconductor chip by a first width;
A first conductive layer embedded in a first opening formed in the first low dielectric constant film;
A second low dielectric constant formed on the first conductive layer and the first low dielectric constant film and removed from the edge of the substrate by a second width different from the first width by 0.4 mm or more. A membrane,
And a second conductive layer embedded in a second opening formed in the second low dielectric constant film.

  In the semiconductor mounting apparatus according to the present invention, when the film thickness of the second low dielectric constant film is 300 nm or more and less than 600 nm, the first width and the second width are preferably different from each other by 0.7 mm or more. It is. In addition, when the thickness of the second low dielectric constant film is 600 nm or more, it is preferable that the first width and the second width are different from each other by 1.0 mm or more.

  In the semiconductor mounting apparatus according to the present invention, it is preferable that the second width is larger than the first width.

  According to the present invention, as described above, the removal width of the conductive film and the removal width of the low dielectric constant film are made different by 1 mm or more, thereby suppressing the peeling of the low dielectric constant film when the conductive film is polished. be able to.

  The inventor first investigated the precise starting point of the low-k film peeling in Cu-CMP. According to this investigation, the starting point of the low-k film peeling was where the low-k film was formed on the outer periphery of the wafer, that is, at the edge of the low-k film. Specifically, immediately after the low-k film is spin-coated, the low-k film is removed with a width of about 2 mm from the substrate edge, so that the actual peeling start point is 2 mm inside the substrate edge. . As described above, the reason for removing the low-k film at the substrate edge is that the non-uniformity of the low-k film generated around the notch or orientation flat of the wafer is removed, and the low-k film formed on the substrate edge. There are two purposes for preventing particles from being peeled off when coming into contact with a wafer case or wafer carrier. Therefore, it is necessary to remove the substrate edge of the low-k film, but this is the starting point of peeling of the low-k film in Cu-CMP.

  A strong stress is applied to the edge portion of the wafer during Cu-CMP. For example, even when Cu-CMP is performed with the CMP load set to 3 psi, a high CMP load of 3.5 psi to 7 psi is applied in an area of about 5 mm from the substrate edge. This is because the substrate edge portion is strongly pressed against the polishing pad. If there is a high step in the low-k film in the region about 5 mm from the edge of the substrate, the low-k film is polished with a substantially high polishing load, and the low-k film can be easily peeled off. Occur. Since there is a step corresponding to the film thickness of the low-k film at the edge of the low-k film, the polishing load is concentrated. Once the low-k film is peeled off, the peeled area increases with the polishing time and finally peels off to the center of the wafer.

  Further, since the low-k film is formed as an interlayer insulating film in each wiring layer and each via layer, a low-k film having at least 6 layers, or more than 10 layers in many cases is formed to form a multilayer wiring. Is done. In addition, since the film thickness of the low-k film becomes thicker as the upper wiring layer is formed, the level difference of the low-k film at the substrate edge becomes higher as the upper wiring layer is formed. For this reason, the problem of peeling of the lower layer low-k film becomes more serious in Cu-CMP when forming the upper layer wiring.

  The present invention suppresses peeling of the low-k film in Cu-CMP by separating the substrate edge removal width of the lower low-k film from the substrate edge removal width of the upper low-k film. .

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view for explaining a multilayer wiring structure according to Embodiment 1 of the present invention.
As shown in FIG. 1, a first diffusion prevention film 11 is formed on a substrate as a base 1, and a first low-k film 12 having a relative dielectric constant of 3 or less is formed thereon. Here, the first low-k film 12 is removed from the substrate edge 10 by a width A (for example, 3 mm). As the base 1, for example, a printed board or a semiconductor chip (described later) can be used in addition to a substrate such as a silicon substrate. For example, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, or a SiN film can be used as the first diffusion prevention film 11 (the same applies to the diffusion prevention films 21 and 31 described later). As the first low-k film 12, for example, an MSQ (Methyl Silsesquioxane) film, an HSQ (Hydrogen Silsesquioxane) film or a polymer (for example, SiLK (registered trademark) manufactured by Dow Chemical Co., Ltd.), or a hole is introduced into them. Or a laminated film thereof can be used (the same applies to the low-k films 22 and 32 described later).
A first cap film 13 for preventing plasma damage is formed on the first low-k film 12. As the first cap film 13, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, a SiN film, or a laminated film thereof can be used (the same applies to cap films 23 and 33 described later).
An opening 14 is formed in the first cap film 13, the first low-k film 12, and the first diffusion prevention film 11, and a barrier metal film 15 is formed on the inner wall of the opening 14. Further, a metal film 16 is formed on the barrier metal film 15. That is, the opening 14 is filled with the conductive film made of the barrier metal film 15 and the metal film 16, thereby forming the first conductive layer in the opening 14. The opening 14 is a wiring groove, a via hole, or the like (the same applies to the openings 24 and 34 described later). As the barrier metal film 15, for example, a Ta film, a Ti film, a TaN film, a TiN film, a WN film, a WSiN film, or a laminated film thereof can be used (the same applies to barrier metal films 25 and 35 described later). ). As the metal film 16, an Al film, a W film, a Cu film, an alloy film thereof, or the like can be used (the same applies to metal films 26 and 36 described later).

A second diffusion barrier film 21 is formed on the first conductive layer and the first cap film 13, a second low-k film 22 is formed thereon, and a second cap film 23 is formed thereon. Yes. Here, the second low-k film 22 is removed from the substrate edge 10 by a width B (for example, 4 mm) larger than the removal width A of the first low-k film 12 by 0.4 mm or more. That is, the edge removal width B of the second low-k film 22 is 0.4 mm or more larger than the edge removal width A of the first low-k film 12. As a result, the edge of the second low-k film 22 and the edge of the first low-k film 12 are separated, and the CMP load is extremely concentrated on the edge of the first low-k film 12 when the metal film 26 described later is CMPed. Can be prevented. Although details will be described later, the difference between the removal width B and the removal width A (hereinafter referred to as “edge removal width difference”) is 0.7 mm or more and 1.0 mm or more in consideration of the relationship with the acquisition area of the LSI chip. The larger it is, the more effective the suppression of peeling of the low-k film in Cu-CMP.
It is optimal to change the edge removal width difference according to the film thickness of the low-k film. Usually, the film thickness of the low-k film is in the range of 150 nm to 2000 nm, and generally becomes thicker as the upper layer is formed. When the film thickness of the low-k film is less than 300 nm, the edge removal width difference is set to 0.4 mm or more. When the film thickness is 300 nm or more to less than 600 nm, the edge removal width difference is set to 0.7 mm or more. When the thickness is 600 nm or more, the edge removal width difference is preferably 1.0 mm or more.
An opening 24 is formed in the second cap film 23, the second low-k film 22 and the second diffusion prevention film 21, a barrier metal film 25 is formed on the inner wall of the opening 24, and the barrier metal film 25 is further formed. A metal film 26 is formed thereon. That is, the opening 24 is filled with the conductive film made of the barrier metal film 25 and the metal film 26, so that the second conductive layer is formed in the opening 24. The second conductive layer is connected to the first conductive layer.

A third diffusion prevention film 31 is formed on the second conductive layer and the second cap film 23, a third low-k film 32 is formed thereon, and a third cap film 33 is formed thereon. Yes. Here, the third low-k film 32 is removed from the substrate edge 10 by a width C (for example, 5 mm) larger than the removal width B of the second low-k film 22 by 0.4 mm or more. That is, the edge removal width C of the third low-k film 32 is 0.4 mm or more larger than the edge removal width B of the second low-k film 22. Accordingly, the edge of the third low-k film 32 is separated from the edge of the second low-k film 22 and the edge of the first low-k film 12, and when the metal film 36 to be described later is subjected to CMP, the edge of the second low-k film 22 and the first low-k film 22. It is possible to prevent the CMP load from being concentrated on the edge of the -k film 12.
An opening 34 is formed in the third cap film 33, the third low-k film 32, and the third diffusion prevention film 31, a barrier metal film 35 is formed on the inner wall of the opening 34, and the barrier metal film 35 is further formed. A metal film 36 is formed thereon. That is, the opening 34 is filled with the conductive film including the barrier metal film 35 and the metal film 36, so that the third conductive layer is formed in the opening 34. The third conductive layer is connected to the second conductive layer.

Next, a method for forming the multilayer wiring structure will be described.
FIG. 2 is a process cross-sectional view for explaining the multilayer wiring forming method according to the first embodiment.
First, as shown in FIG. 2A, the first diffusion prevention film 11 is formed on the base 1 with a film thickness of, for example, 30 nm to 200 nm by the CVD method.
Next, the first low-k film 12 is formed with a film thickness of, for example, 100 nm to 1000 mm on the first diffusion prevention film 11 by spin coating. Immediately thereafter, the first low-k film 12 at the outer peripheral portion of the substrate is removed by the width A by a chemical solution. The removal width A, that is, the length from the substrate edge 10 to the first low-k film 12 edge is, for example, 3 mm. After the chemical solution is removed from the first low-k film 12, the surface treatment of the first low-k film 12 is performed by performing baking and curing in an inert gas atmosphere and further irradiating with He plasma.

Next, as illustrated in FIG. 2B, the first cap film 13 is formed on the first low-k film 12 by a CVD method with a film thickness of, for example, 30 nm to 200 nm. Then, an opening 14 is formed in the first cap film 13, the first low-k film 12, and the first diffusion prevention film 11 by lithography and dry etching. Next, a barrier metal film 15 is formed on the inner wall of the opening 14 and the first cap film 13 by a sputtering method, and a seed Cu film is formed on the barrier metal film 15 by a sputtering method. Further, a Cu film 16 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. Thereby, the opening 14 is filled with the conductive film including the barrier metal film 15, the seed Cu film, and the Cu film 16. The annealing treatment may be performed after removing a chemical solution from the Cu film 16 described later.
Next, the Cu film 16 (including the seed Cu film; the same shall apply hereinafter) on the outer periphery of the substrate is removed with a chemical solution. The removal width of the Cu film 16, that is, the length from the substrate edge 10 to the Cu film 16 edge is, for example, 2 mm which is 1 mm smaller than the removal width A of the first low-k film 12 described above.

  Next, the unnecessary Cu film 16 and barrier metal film 15 formed on the first cap film 13 are removed using, for example, an orbital CMP apparatus (not shown). That is, the Cu film 16 and the barrier metal film 15 are removed by CMP using the first cap film 13 as a stopper film. As a result, a Cu wiring layer is formed as the first conductive layer.

  Next, the second diffusion prevention film 21 is formed with a film thickness of, for example, 30 nm to 200 nm on the first cap film 13 and the Cu wiring by the CVD method. Then, the second low-k film 22 is formed with a film thickness of, for example, 100 nm to 1000 nm on the second diffusion preventing film 21 by a spin coating method. Immediately thereafter, the second low-k film 22 on the outer peripheral portion of the substrate is removed by the width B by a chemical solution. The removal width B of the second low-k film 22 is 4 mm, which is 1 mm larger than the removal width A of the first low-k film 12, for example. Thereafter, the second low-k film 22 is subjected to surface modification treatment by performing baking and curing in an inert gas atmosphere and further irradiating with He plasma.

Next, as illustrated in FIG. 2C, the second cap film 23 is formed with a film thickness of, for example, 30 nm to 200 nm on the second low-k film 22 by a CVD method. Then, an opening 24 is formed in the second cap film 23, the second low-k film 22, and the second diffusion prevention film 21 by lithography and dry etching. Next, a barrier metal film 25 is formed on the inner wall of the opening 24 and the second cap film 23 by a sputtering method, and a seed Cu film is formed on the barrier metal film 25 by a sputtering method. Further, a Cu film 26 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. Thereby, the opening 24 is filled with the conductive film including the barrier metal film 25, the seed Cu film, and the Cu film 26.
Next, the Cu film 26 on the outer periphery of the substrate is removed with a chemical solution. The removal width of the Cu film 26 is 2 mm, which is 2 mm smaller than the removal width B of the second low-k film 22, for example. Then, unnecessary Cu film 26 and barrier metal film 25 formed on second cap film 23 are removed by performing CMP under the same conditions as the first-layer Cu wiring layer. Thereby, a via layer as a second conductive layer is formed.

  Next, the third diffusion prevention film 31 is formed on the second cap film 23 and the via with a film thickness of, for example, 30 nm to 200 nm by a CVD method. Then, the third low-k film 32 is formed with a film thickness of, for example, 100 nm to 1000 nm on the third diffusion preventing film 31 by spin coating. Immediately thereafter, the third low-k film 32 at the outer peripheral portion of the substrate is removed by the width C by a chemical solution. The removal width C of the third low-k film 32 is 5 mm, which is 1 mm larger than the removal width B of the second low-k film 22, for example. After that, baking treatment and curing are performed in an inert gas atmosphere, and further, surface modification treatment of the third low-k film 32 is performed by irradiating He plasma.

Next, as illustrated in FIG. 2D, the third cap film 33 is formed on the third low-k film 32 by a CVD method with a film thickness of, for example, 30 nm to 200 nm. Then, an opening 34 is formed in the third cap film 33, the third low-k film 32, and the third diffusion prevention film 31 by lithography and dry etching. Next, a barrier metal film 35 is formed on the inner wall of the opening 34 and the third cap film 33 by a sputtering method, and a seed Cu film is formed on the barrier metal film 35 by a sputtering method. Further, a Cu film 36 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. As a result, the opening 34 is filled with the conductive film including the barrier metal film 35, the seed Cu film, and the Cu film 36.
Next, the Cu film 36 on the outer periphery of the substrate is removed with a chemical solution. The removal width of the Cu film 36 is 2 mm, which is 3 mm smaller than the removal width C of the third low-k film 32. Then, unnecessary Cu film 36 and barrier metal film 35 formed on third cap film 33 are removed by performing CMP under the same conditions as those for the first-layer Cu wiring layer. As a result, a Cu wiring layer as a third conductive layer is formed.

(Example 1)
Next, Example 1 that more specifically describes Embodiment 1 will be described. The first embodiment will be described with reference to FIG.
First, as shown in FIG. 2A, an SiC film 11 having a thickness of 50 nm is formed on a silicon substrate 1 having a diameter of 300 mm by a CVD method. Then, the MSQ film 12 is formed with a film thickness of 250 nm on the SiC film 11 by spin coating. The substrate rotation speed is 900 rpm. Immediately after the application of the MSQ film 12, N-methyl-2-pyrrolidinone (CH ₃ NC ₄ H ₆ O) is dropped on the outer periphery of the wafer to remove the MSQ film 12 at the substrate edge portion by the removal width A. The removal width A of the MSQ film 12 was 3 mm. Then, it baked at the temperature of 250 degreeC in nitrogen atmosphere using the hotplate, and cured for 15 minutes at the temperature of 450 degreeC in the same atmosphere.
Here, a sample was prepared in which the Young's modulus of the MSQ film 12 was changed by 1 GPa from 2 GPa to 14 GPa. The Young's modulus was changed by changing the porosity (porosity) of the MSQ film 12. The chemical composition of the MSQ film 12 was all the same.
These MSQ films 12 were irradiated with helium plasma using a CVD apparatus. Thereby, the surface modification of the MSQ film 12 was performed. By the He plasma treatment, the adhesion between the MSQ film 12 and the SiO ₂ film 13 described below can be improved.

Next, as shown in FIG. 2B, a SiO ₂ film 13 having a thickness of 50 nm is formed on the MSQ film 12 by a CVD method. Subsequently, a wiring groove 14 is formed in the SiO ₂ film 13, the MSQ film 12, and the SiC film 11 by lithography and dry etching. Next, a TaN film / Ta film 15 with a thickness of 10 nm / 15 nm is formed in the wiring trench 14 and on the SiO ₂ film 13 by sputtering, respectively, and a seed Cu film (not shown) is formed thereon by sputtering. The same shall apply)) with a film thickness of 75 nm. Then, a Cu film 16 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed at a temperature of 250 ° C. for 30 minutes.
Next, the Cu film 16 in the vicinity of the substrate edge 10 is removed using an aqueous solution containing 3% HF and 30% H ₂ O ₂ . The removal width of the Cu film 16 was 2 mm, which is 1 mm smaller than the removal width A of the MSQ film 12.
Next, the unnecessary Cu film 16 and TaN film / Ta film 15 on the SiO ₂ film 13 are removed by CMP. The CMP apparatus is of an orbital type (for example, Momentum300 from Novellus), the polishing pad is a single-layer foamed urethane (for example, IC1000 from Rodel), and the CMP slurry for Cu is abrasive-free slurry (for example, Hitachi Chemical). Abrasive slurry (for example, HS-T605 manufactured by Hitachi Chemical Co., Ltd.) was used as the CMP slurry for TaN film / Ta film. The polishing conditions were CMP load: 1.5 psi, orbital rotation speed: 600 rpm, head rotation speed: 24 rpm, and slurry supply speed: 300 cc / min. The CMP of the Cu film 16 and the TaN film / Ta film 15 is performed in two steps by changing the slurry. Through the above steps, the first Cu wiring layer was formed.

Next, the SiC film 21 is formed with a thickness of 50 nm by the CVD method, and the MSQ film 22 is formed thereon with a thickness of 250 nm by the spin coating method. The substrate rotation speed is set to 900 rpm as in the formation of the MSQ film 12. Immediately after the application of the MSQ film 22, N-methyl-2-pyrrolidinone (CH ₃ NC ₄ H ₆ O) is dropped on the outer periphery of the wafer to remove the MSQ film 22 at the substrate edge portion by the removal width B. The removal width B of the MSQ film 22 was 4 mm, which is 1 mm larger than the removal width A (= 3 mm) of the MSQ film 12. Thereafter, baking and curing were performed under the same conditions as the MSQ film 12, and the surface modification of the MSQ film 22 was performed by He plasma treatment.

Next, as shown in FIG. 2C, a SiO ₂ film 23 is formed with a thickness of 50 nm on the MSQ film 22 by a CVD method, and the SiO ₂ film 23, the MSQ film 22 and the SiC are formed by lithography and dry etching. A via hole 24 is formed in the film 21. Next, a TaN film / Ta film 25 is formed in a thickness of 10 nm / 15 nm by sputtering in the hole 24 and on the SiO ₂ film 23, respectively, and a seed Cu film is formed in a thickness of 75 nm thereon by sputtering. Then, a Cu film 26 is formed thereon by electrolytic plating. Thereafter, annealing is performed at a temperature of 250 ° C. for 30 minutes.
Next, the Cu film 26 near the substrate edge 10 is removed using an aqueous solution containing 3% HF and 30% H ₂ O ₂ . The removal width of the Cu film 26 was 2 mm, which is 2 mm smaller than the removal width B of the MSQ film 22.
Next, the unnecessary Cu film 26 and TaN film / Ta film 25 on the SiO ₂ film 23 are removed by CMP using the above-described polishing conditions. As a result, a second via layer was formed.

Next, the SiC film 31 is formed with a thickness of 50 nm by a CVD method, and the MSQ film 32 is formed with a thickness of 250 nm thereon by a spin coating method. Immediately after the application of the MSQ film 32, N-methyl-2-pyrrolidinone (CH ₃ NC ₄ H ₆ O) is dropped on the outer periphery of the wafer to remove the MSQ film 32 at the substrate edge portion by the removal width C. The removal width C of the MSQ film 32 was 5 mm, which is 1 mm larger than the removal width B (= 4 mm) of the MSQ film 22. Thereafter, baking and curing were performed under the same conditions as the MSQ films 12 and 22, and the surface modification of the MSQ film 32 was performed by He plasma treatment.

Next, as shown in FIG. 2D, a SiO ₂ film 33 is formed with a thickness of 50 nm on the MSQ film 32 by a CVD method, and the SiO ₂ film 33, the MSQ film 32, and the SiC are formed by lithography and dry etching. A via hole 34 is formed in the film 31. Next, a TaN film / Ta film 35 is formed in a thickness of 10 nm / 15 nm by sputtering in the holes 34 and on the SiO ₂ film 33, and a seed Cu film is formed in a thickness of 75 nm thereon by sputtering. Then, a Cu film 36 is formed thereon by electrolytic plating. Thereafter, annealing is performed at a temperature of 250 ° C. for 30 minutes.
Next, the Cu film 36 near the substrate edge 10 is removed using an aqueous solution containing 3% HF and 30% H ₂ O ₂ . The removal width of the Cu film 36 was 2 mm, which is 3 mm smaller than the removal width C of the MSQ film 32.
Next, the unnecessary Cu film 36 and TaN film / Ta film 35 on the SiO ₂ film 33 are removed by CMP using the polishing conditions described above. As a result, a third Cu wiring layer was formed.

  As described above, in the substrate in which the edge removal widths A, B, and C of the low-k films 12, 22, and 32 of each conductive layer are increased stepwise, a steep low-k film step is formed in the vicinity of the substrate edge 10. not exist. For this reason, in Cu-CMP, it can be avoided that a CMP load is locally applied to the edge of the lower low-k film.

When the removal width of the upper low-k film is wider than the removal width of the lower low-k film by 0.4 mm or more, even a sample having the lower low-k film having a Young's modulus of 4 GPa is low-k in Cu-CMP. The peeling of the film could be suppressed. Further, when the removal width of the upper low-k film is made 0.7 mm or more larger than the removal width of the lower low-k film, even a sample having the lower low-k film having a Young's modulus of 2 GPa is low in Cu-CMP. -K film peeling could be suppressed. Furthermore, when the removal width of the upper layer low-k film is wider than the removal width of the lower layer low-k film by 1.0 mm or more, even a sample having the lower layer low-k film having a Young's modulus of 1 GPa is low in Cu-CMP. -K film peeling could be suppressed.
Further, as a result of examining the peeling of the low-k film while changing the relative dielectric constant of the low-k film, the substrate edge removal width of the low-k film of each layer is the substrate edge removal width of the low-k film immediately below it. Further, when the width was made 0.4 mm or more, even the sample having the lower low-k film having a relative dielectric constant of 3.0 could suppress the peeling of the low-k film in Cu-CMP. In addition, when the width was increased by 0.7 mm or more, even the sample having the lower low-k film having a relative dielectric constant of 2.6 could suppress the peeling of the low-k film in Cu-CMP. Furthermore, when the width was increased by 1.0 mm or more, even the sample having the lower low-k film having a relative dielectric constant of 2.3 could suppress the peeling of the low-k film in Cu-CMP.

(Comparative example)
FIG. 3 is a diagram illustrating a comparative example of the first embodiment. As shown in FIG. 3, when the substrate edge removal widths A, B, and C of the low-k film in each layer are the same width and 2 mm, even if the Young's modulus of the low-k film is 12 GPa, the first layer In the Cu-CMP of the eye, peeling of the low-k film 12 occurred. Further, when the substrate edge removal width of each layer was the same 3 mm, even if the Young-modulus of the low-k film was 12 GPa, peeling of the low-k film 12 occurred in the second layer of Cu-CMP. Further, when the substrate edge removal width of each layer was the same 4 mm, even if the Young's modulus of the low-k film was 12 GPa, peeling of the low-k film 12 occurred in the third layer of Cu-CMP.

  As described above, in the first embodiment, the difference (edge removal width difference) between the removal width of the lower low-k film and the removal width of the upper low-k film is set to 0.4 mm or more. The steep low-k film step is not present at the substrate edge. Thereby, the CMP load applied to the lower layer low-k film edge in the upper layer Cu-CMP can be significantly reduced, and the lower layer low-k film peeling in the Cu-CMP can be remarkably suppressed. Further, by increasing the edge removal width difference such as 0.7 mm or more and 1.0 mm or more, the step of the low-k film can be further reduced, and the low-k film or the relative dielectric constant having a low Young's modulus can be reduced. Even when a low-k film having a low thickness is used, peeling of the low-k film in Cu-CMP can be suppressed.

Although details will be described later, similar results were obtained even when this experiment was performed on a wafer on which a device was mounted.
Further, although the single damascene two-layer Cu wiring structure has been described in the first embodiment, it can be applied to a dual damascene two-layer Cu wiring structure, and in this case, the same effect as that of the first embodiment can be obtained. The present invention can also be applied to a Cu wiring structure having three or more layers, and in this case, the same effect as in the first embodiment can be obtained. In the first embodiment, a low-k film applied in a single layer is used. However, a laminated film of a coated low-k film and a low-k film formed by a CVD method may be used as an interlayer film. .

Embodiment 2. FIG.
In the first embodiment, when the removal width of the upper layer low-k film is larger than the removal width of the lower layer low-k film, that is, the lower layer low-k film edge is closer to the substrate outer side than the upper layer low-k film edge. Explained the case. In the second embodiment, when the removal width of the lower low-k film is larger than the removal width of the upper low-k film, that is, the upper low-k film edge is closer to the substrate outer side than the lower low-k film edge. A case will be described. Since other than that is the same as that of Embodiment 1, it demonstrates below centering on difference with Embodiment 1 with reference to FIG.4 and FIG.5. FIG. 4 is a cross-sectional view for explaining the multilayer wiring structure according to the second embodiment. FIG. 5 is a process cross-sectional view for explaining the wiring forming method according to the second embodiment.

  As shown in FIG. 4, the first low-k film 12 is removed by a removal width A (for example, 5 mm) in the vicinity of the substrate edge 10, and the second low-k film 22 is removed by 0.4 mm or more smaller than the removal width A. B (for example, 4 mm) is removed, and the third low-k film 32 is removed by a removal width C (for example, 3 mm) smaller than the removal width B by 0.4 mm or more. Accordingly, the second low-k film 22 edge is positioned on the outer peripheral side of the substrate with respect to the first low-k film 12 edge, and the third low-k film 32 edge is positioned on the outer peripheral side of the substrate with respect to the second low-k film 22 edge. To do. Therefore, the edge of the first low-k film 12 is covered with the second low-k film 22, and the edge of the second low-k film 22 is covered with the third low-k film 32. The rest is the same as in the first embodiment.

Next, a method for forming a multilayer wiring structure will be described.
First, as shown in FIG. 5A, a first diffusion prevention film 11 is formed on a base 1, and a first low-k film 12 is applied thereon. Immediately after the application, the first low-k film 12 on the outer peripheral portion of the substrate is removed from the substrate edge 10 by the width A with a chemical solution. The removal width A is, for example, 5 mm. Thereafter, a baking process and a curing process are performed, and a surface modification process of the first low-k film 12 using He plasma is performed.

Next, as shown in FIG. 5B, the first cap film 13 is formed on the first low-k film 12. Then, an opening 14 is formed in the first cap film 13, the first low-k film 12, and the first diffusion prevention film 11. By burying a barrier metal film 15 and a Cu film as the metal film 16 in the opening 14, a Cu wiring layer as a first conductive layer is formed. Note that the edge removal width of the Cu film 16 performed before Cu-CMP is 2 mm from the substrate edge 10 (the same applies to Cu films 26 and 36 described later).
Next, a second diffusion prevention film 21 is formed on the first cap film 13 and the Cu wiring, and a second low-k film 22 is applied thereon. Immediately after the application, the second low-k film 22 on the outer periphery of the substrate is removed by a chemical solution by a width B smaller by 0.4 mm or more than the removal width A of the first low-k film 12. The removal width B is 4 mm, for example. As a result, the edge of the second low-k film 22 is positioned on the outer peripheral side of the substrate by 0.4 mm or more than the edge of the first low-k film 12.

Next, as shown in FIG. 5C, a second cap film 23 is formed on the second low-k film 22. Then, a via hole as an opening 24 is formed in the second cap film 23, the second low-k film 22, and the second diffusion prevention film 21. By burying the barrier metal film 25 and the metal film 26 in the opening 24, a via layer as a second conductive layer is formed.
Next, the third diffusion prevention film 31 is formed on the second cap film 23 and the via, and the third low-k film 32 is applied thereon. Immediately after the application, the third low-k film 32 at the outer peripheral portion of the substrate is removed by a chemical solution by a width C smaller than the removal width B of the second low-k film 22 by 0.4 mm or more. The removal width C is 3 mm, for example. As a result, the edge of the third low-k film 32 is positioned 0.4 mm or more from the edge of the second low-k film 22 and 0.8 mm or more from the edge of the first low-k film 12.

  Next, as illustrated in FIG. 5D, the third cap film 33 is formed on the third low-k film 32. Then, an opening 34 is formed in the third cap film 33, the third low-k film 32, and the third diffusion prevention film 31. A Cu wiring layer as a third conductive layer is formed by embedding a barrier metal film 35 and a Cu film as the metal film 36 in the opening 34.

Also in the second embodiment, as in the first embodiment, the difference between the removal width of the lower low-k film and the removal width of the upper low-k film is set to 0.4 mm or more, so that the substrate edge is steep. The step of the low-k film was not allowed to exist. Thereby, the CMP load applied to the lower layer low-k film edge in the upper layer Cu-CMP can be significantly reduced, and the lower layer low-k film peeling in the Cu-CMP can be remarkably suppressed. Further, by increasing the edge removal width difference such as 0.7 mm or more and 1.0 mm or more, the step of the low-k film can be further reduced, and the low-k film or the relative dielectric constant having a low Young's modulus can be reduced. Even when a low-k film having a low thickness is used, peeling of the low-k film in Cu-CMP can be suppressed.
In the second embodiment, the upper low-k film edge is located outside the lower low-k film edge when the Cu film is removed with a chemical (immediately before Cu-CMP). That is, the lower low-k film edge is covered with the upper low-k film in Cu-CMP. Therefore, peeling of the lower layer low-k film in Cu-CMP can be further suppressed than in Embodiment 1 due to the anchor effect.

Embodiment 3 FIG.
In the third embodiment of the present invention, the multilayer wiring structure of the first embodiment described above is applied to the wiring of the first layer or higher in the semiconductor device.
FIG. 6 is a cross-sectional view for explaining a semiconductor device according to the third embodiment of the present invention.
As shown in FIG. 6, a semiconductor element having a diffusion layer 6 such as a MIS transistor is formed on a substrate 1. Specifically, a gate electrode 3 is formed on a silicon substrate as the substrate 1 via a gate insulating film 2, and a side wall 5 for forming an LDD structure is formed on the side wall of the gate electrode 3. A low-concentration diffusion layer (extension region) 4 is formed in the upper layer of the substrate 1 with a channel region (not shown) immediately below the gate insulating film 2 interposed therebetween, and a high-concentration diffusion layer (source / source) connected to the low-concentration diffusion layer 4 Drain region) 6 is formed.
An interlayer insulating film 7 is formed so as to cover the semiconductor element, and a contact 8 connected to the diffusion layer 6 is formed in the interlayer insulating film 7.

The multilayer wiring structure of the first embodiment is applied on the contact 8 and the interlayer insulating film 7.
Specifically, a first diffusion prevention film 11 is formed on the contact 8 and the interlayer insulating film 7, and a first low-k film 12 having a width A removed from the substrate edge 10 is formed thereon. For example, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, or a SiN film can be used as the first diffusion prevention film 11 (the same applies to the diffusion prevention films 21 and 31 described later). As the first low-k film 12, for example, an MSQ (Methyl Silsesquioxane) film, an HSQ (Hydrogen Silsesquioxane) film or a polymer (for example, SiLK (registered trademark) manufactured by Dow Chemical Co., Ltd.), or a hole is introduced into them. Or a laminated film thereof can be used (the same applies to the low-k films 22 and 32 described later).
A first cap film 13 for preventing plasma damage is formed on the first low-k film 12. As the first cap film 13, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, a SiN film, or a laminated film thereof can be used (the same applies to cap films 23 and 33 described later).
An opening 14 reaching the upper surface of the contact 8 is formed in the first cap film 13, the first low-k film 12 and the first diffusion prevention film 11, and a barrier metal film 15 is formed on the inner wall of the opening 14. . Further, a metal film 16 is formed on the barrier metal film 15. That is, the opening 14 is filled with the conductive film made of the barrier metal film 15 and the metal film 16, thereby forming the first conductive layer connected to the diffusion layer 6 through the contact 8 in the opening 14. The opening 14 is a wiring groove, a via hole, or the like (the same applies to the openings 24 and 34 described later). As the barrier metal film 15, for example, a Ta film, a Ti film, a TaN film, a TiN film, a WN film, a WSiN film, or a laminated film thereof can be used (the same applies to barrier metal films 25 and 35 described later). ). As the metal film 16, an Al film, a W film, a Cu film, an alloy film thereof, or the like can be used (the same applies to metal films 26 and 36 described later).

A second diffusion barrier film 21 is formed on the first conductive layer and the first cap film 13, a second low-k film 22 is formed thereon, and a second cap film 23 is formed thereon. Yes. Here, the second low-k film 22 is removed from the substrate edge 10 by a width B that is 0.4 mm or more larger than the removal width A of the first low-k film 12. That is, the edge removal width B of the second low-k film 22 is 0.4 mm or more larger than the edge removal width A of the first low-k film 12. As a result, the edge of the second low-k film 22 and the edge of the first low-k film 12 are separated from each other, and the CMP load is extremely concentrated on the edge of the first low-k film 12 when CMP of the metal film 26 described later is performed. Can be prevented. Although details will be described later, as the difference between the removal width B and the removal width A (hereinafter referred to as “edge removal width difference”) is increased to 0.7 mm or more and 1.0 mm or more, the low− in Cu-CMP It is effective in suppressing the peeling of the k film. As in the first embodiment, it is optimal to change the edge removal width difference according to the film thickness of the low-k film. When the film thickness of the low-k film is less than 300 nm, the edge removal width difference is set to 0.4 mm or more. When the film thickness is 300 nm or more to less than 600 nm, the edge removal width difference is set to 0.7 mm or more. When the thickness is 600 nm or more, the edge removal width difference is preferably 1.0 mm or more.
An opening 24 reaching the surface of the Cu film 15 is formed in the second cap film 23, the second low-k film 22, and the second diffusion prevention film 21, and a barrier metal film 25 is formed on the inner wall of the opening 24. Further, a metal film 26 is formed on the barrier metal film 25. That is, the opening 24 is filled with the conductive film made of the barrier metal film 25 and the metal film 26, so that the second conductive layer is formed in the opening 24. Therefore, the second conductive layer is connected to the first conductive layer.

A third diffusion prevention film 31 is formed on the second conductive layer and the second cap film 23, a third low-k film 32 is formed thereon, and a third cap film 33 is formed thereon. Yes. Here, the third low-k film 32 is removed from the substrate edge 10 by a width B larger by 0.4 mm or more than the removal width B of the second low-k film 22. That is, the edge removal width C of the third low-k film 32 is 0.4 mm or more larger than the edge removal width B of the second low-k film 22. Accordingly, the edge of the third low-k film 32 is separated from the edge of the second low-k film 22 and the edge of the first low-k film 12, and when the metal film 36 to be described later is subjected to CMP, the edge of the second low-k film 22 and the first low-k film 22. It is possible to prevent the CMP load from being concentrated on the edge of the -k film 12.
An opening 34 reaching the metal film 26 is formed in the third cap film 33, the third low-k film 32, and the third diffusion prevention film 31, and a barrier metal film 35 is formed on the inner wall of the opening 34. Further, a metal film 36 is formed on the barrier metal film 35. That is, the opening 34 is filled with the conductive film including the barrier metal film 35 and the metal film 36, so that the third conductive layer is formed in the opening 34. Therefore, the third conductive layer is connected to the second conductive layer.

Next, a method for manufacturing the semiconductor device will be described.
FIG. 7 is a process sectional view for explaining the method for manufacturing the semiconductor device according to the third embodiment of the present invention.
First, as shown in FIG. 7A, a semiconductor element having a diffusion layer such as a MIS transistor is formed on a substrate 1. Although a detailed description is omitted, after the gate insulating film 2 and the conductive film 3 are formed on the silicon substrate as the substrate 1, the films 3 and 2 are sequentially patterned to form the gate electrode 3. A low concentration diffusion layer (extension region) 4 is formed by implanting impurities into the substrate 1 using the gate electrode 3 as a mask, and a sidewall 5 is formed on the side wall of the gate electrode 3. High concentration diffusion layers (source / drain regions) 6 are formed by implanting impurities into the substrate 1 using the sidewalls 5 and the gate electrode 3 as a mask.
Then, an SiO ₂ film as an interlayer insulating film 7 is formed with a film thickness of, for example, 500 nm by the CVD method so as to cover the transistor formed by performing such a process, and the interlayer insulating film 7 is formed in the interlayer insulating film 7. A contact 8 connected to the high concentration diffusion layer 6 is formed.

Next, the first diffusion prevention film 11 is formed with a film thickness of, for example, 30 nm to 200 nm on the interlayer insulating film 7 and the contact 8 by the CVD method. Then, an MSQ film as the first low-k film 12 is formed with a film thickness of, for example, 100 nm to 1000 mm on the first diffusion prevention film 11 by a spin coating method. Immediately thereafter, the first low-k film 12 at the outer peripheral portion of the substrate is removed by the width A by a chemical solution. That is, the first low-k film 12 is removed from the substrate edge 10 by the removal width A. Thereafter, a baking process and a curing process are performed in an inert gas atmosphere, and a surface modification process of the first low-k film 12 is performed by irradiating He plasma.
Next, the first cap film 13 is formed on the first low-k film 12 with a film thickness of, for example, 30 nm to 200 nm by the CVD method. Then, an opening 14 reaching the upper surface of the contact 8 is formed in the first cap film 13, the first low-k film 12, and the first diffusion prevention film 11 by lithography and dry etching. Then, a barrier metal film 15 is formed on the inner wall of the opening 14 and the first cap film 13 by a sputtering method, and a seed Cu film is formed on the barrier metal film 15 by a sputtering method. Further, a Cu film 16 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. The annealing treatment may be performed after removing the chemical solution from the Cu film 16.

Next, the Cu film 16 on the outer periphery of the substrate is removed with a chemical solution. The removal width of the Cu film 16, that is, the length from the substrate edge 10 to the Cu film edge was 3 mm.
Thereafter, the unnecessary Cu film 16 and barrier metal film 15 formed on the first cap film 13 are removed using an orbital CMP apparatus as in the first embodiment. Through the above steps, a first Cu wiring layer that is electrically connected to the diffusion layer 6 through the contact 8 is formed.

  Next, the second diffusion prevention film 21 is formed with a film thickness of, for example, 30 nm to 200 nm on the first cap film 13 and the Cu wiring by the CVD method. Then, the second low-k film 22 is formed with a film thickness of, for example, 100 nm to 1000 nm on the second diffusion preventing film 21 by a spin coating method. Immediately thereafter, the second low-k film 22 on the outer peripheral portion of the substrate is removed by the width B by a chemical solution. The removal width B of the second low-k film 22 was 4 mm, which is 1 mm larger than the removal width A of the first low-k film 12. Thereafter, the second low-k film 22 is subjected to surface modification treatment by performing baking and curing in an inert gas atmosphere and further irradiating with He plasma.

Next, as illustrated in FIG. 7B, the second cap film 23 is formed on the second low-k film 22 with a film thickness of, for example, 30 nm to 200 nm by the CVD method. Then, an opening 24 is formed in the second cap film 23, the second low-k film 22, and the second diffusion prevention film 21 by lithography and dry etching. Next, a barrier metal film 25 is formed on the inner wall of the opening 24 and the second cap film 23 by a sputtering method, and a seed Cu film is formed on the barrier metal film 25 by a sputtering method. Further, a Cu film 26 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. Thereby, the opening 24 is filled with the conductive film including the barrier metal film 25, the seed Cu film, and the Cu film 26.
Next, the Cu film 26 on the outer periphery of the substrate is removed with a chemical solution. The removal width of the Cu film 26 is 2 mm, which is 2 mm smaller than the removal width B of the second low-k film 22. Then, unnecessary Cu film 26 and barrier metal film 25 formed on second cap film 23 are removed by performing CMP under the same conditions as the first-layer Cu wiring layer. Thereby, a via layer as a second conductive layer is formed.

  Next, the third diffusion prevention film 31 is formed on the second cap film 23 and the via with a film thickness of, for example, 30 nm to 200 nm by a CVD method. Then, the third low-k film 32 is formed with a film thickness of, for example, 100 nm to 1000 nm on the third diffusion preventing film 31 by spin coating. Immediately thereafter, the third low-k film 32 at the outer peripheral portion of the substrate is removed by the width C by a chemical solution. The removal width C of the third low-k film 32 is 5 mm, which is 1 mm larger than the removal width B of the second low-k film 22. After that, baking treatment and curing are performed in an inert gas atmosphere, and further, surface modification treatment of the third low-k film 32 is performed by irradiating He plasma.

Next, as illustrated in FIG. 7C, the third cap film 33 is formed on the third low-k film 32 by a CVD method with a film thickness of, for example, 30 nm to 200 nm. Then, an opening 34 is formed in the third cap film 33, the third low-k film 32, and the third diffusion prevention film 31 by lithography and dry etching. Next, a barrier metal film 35 is formed on the inner wall of the opening 34 and the third cap film 33 by a sputtering method, and a seed Cu film is formed on the barrier metal film 35 by a sputtering method. Further, a Cu film 36 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. As a result, the opening 34 is filled with the conductive film including the barrier metal film 35, the seed Cu film, and the Cu film 36.
Next, the Cu film 36 on the outer periphery of the substrate is removed with a chemical solution. The removal width of the Cu film 36 is 2 mm, which is 3 mm smaller than the removal width C of the third low-k film 32. Then, unnecessary Cu film 36 and barrier metal film 35 formed on third cap film 33 are removed by performing CMP under the same conditions as those for the first-layer Cu wiring layer. As a result, a Cu wiring layer as a third conductive layer is formed.

As described above, in the third embodiment, the difference between the edge removal width of the upper low-k film and the edge removal width of the lower low-k film is set to 0.4 mm or more, so that the substrate edge is steep. There was no step in the low-k film. Thereby, the CMP load applied to the lower layer low-k film edge in the upper layer Cu-CMP can be significantly reduced, and the lower layer low-k film peeling in the Cu-CMP can be remarkably suppressed. Further, by increasing the edge removal width difference such as 0.7 mm or more and 1.0 mm or more, the step of the low-k film can be further reduced, and the low-k film or the relative dielectric constant having a low Young's modulus can be reduced. Even when a low-k film having a low thickness is used, peeling of the low-k film in Cu-CMP can be suppressed.
Therefore, the yield can be improved and the reliability of the semiconductor device can be improved. In addition, Cu damascene wiring using a low-k film can be applied to the wiring of the semiconductor device, and the performance of the semiconductor device can be improved.

Embodiment 4 FIG.
In the fourth embodiment of the present invention, the multilayer wiring structure of the above-described second embodiment is applied to the wiring of the first layer or higher in the semiconductor device.
In the third embodiment, when the removal width of the upper layer low-k film is larger than the removal width of the lower layer low-k film, that is, the lower layer low-k film edge is closer to the substrate outer side than the upper layer low-k film edge. Explained the case. In the fourth embodiment, when the removal width of the lower low-k film is made larger than the removal width of the upper low-k film, that is, the upper low-k film edge is closer to the substrate outer side than the lower low-k film edge. A case will be described. Since other than that is the same as that of Embodiment 3, it demonstrates below centering on difference with Embodiment 3 with reference to FIG.8 and FIG.9. FIG. 8 is a cross-sectional view for explaining the semiconductor device according to the fourth embodiment. FIG. 9 is a process sectional view for explaining the method for manufacturing a semiconductor device according to the fourth embodiment.

As shown in FIG. 8, a MIS transistor is formed on a substrate 1 as a semiconductor element having a diffusion layer. Further, an interlayer insulating film 7 is formed so as to cover the transistor, and a contact 8 connected to the diffusion layer 6 is formed in the interlayer insulating film 7.
On the contact 8 and the interlayer insulating film 7, the multilayer wiring structure of the second embodiment is applied. Specifically, three low-k films 12, 22, and 32 are stacked, and a conductive layer is formed in each low-k film.
As shown in FIG. 8, the first low-k film 12 is removed by the removal width A in the vicinity of the substrate edge 10, and the second low-k film 22 is removed by the removal width B smaller than the removal width A by 0.4 mm or more. The third low-k film 32 is removed by a removal width C that is smaller than the removal width B by 0.4 mm or more. Accordingly, the second low-k film 22 edge is positioned on the outer peripheral side of the substrate with respect to the first low-k film 12 edge, and the third low-k film 32 edge is positioned on the outer peripheral side of the substrate with respect to the second low-k film 22 edge. To do. Therefore, the edge of the first low-k film 12 is covered with the second low-k film 22, and the edge of the second low-k film 22 is covered with the third low-k film 32. The rest is the same as in the third embodiment.

Next, a method for manufacturing the semiconductor device will be described.
First, as shown in FIG. 9A, a MIS transistor is formed on a substrate 1 using the method described in the third embodiment. Further, an interlayer insulating film 7 is formed so as to cover the transistor, and a contact 8 connected to the diffusion layer 6 is formed in the interlayer insulating film 7.
Next, a first diffusion prevention film 11 is formed on the contact 8 and the interlayer insulating film 7, and a first low-k film 12 is applied thereon. Immediately after the application, the first low-k film 12 on the outer peripheral portion of the substrate is removed from the substrate edge 10 by the width A with a chemical solution. Thereafter, a baking process and a curing process are performed, and a surface modification process of the first low-k film 12 using He plasma is performed.
Next, the first cap film 13 is formed on the first low-k film 12. Then, an opening 14 reaching the upper surface of the contact 8 is formed in the first cap film 13, the first low-k film 12, and the first diffusion prevention film 11. Thereafter, a Cu wiring layer as a first conductive layer is formed by embedding a barrier metal film 15 and a Cu film as the metal film 16 in the opening 14 using the same method as in the third embodiment. Is done.
Next, a second diffusion prevention film 21 is formed on the first cap film 13 and the Cu wiring, and a second low-k film 22 is applied thereon. Immediately after the application, the second low-k film 22 on the outer periphery of the substrate is removed by a chemical solution by a width B smaller by 0.4 mm or more than the removal width A of the first low-k film 12. As a result, the edge of the second low-k film 22 is positioned on the outer peripheral side of the substrate by 0.4 mm or more than the edge of the first low-k film 12.

Next, as shown in FIG. 9B, the second cap film 23 is formed on the second low-k film 12. Then, a via hole as an opening 24 is formed in the second cap film 23, the second low-k film 22, and the second diffusion prevention film 21. Thereafter, a barrier layer as a second conductive layer is formed by embedding the barrier metal film 25 and the metal film 26 in the opening 24 using the same method as in the third embodiment.
Next, the third diffusion prevention film 31 is formed on the second cap film 23 and the via, and the third low-k film 32 is applied thereon. Immediately after the application, the third low-k film 32 on the outer periphery of the substrate is removed by a chemical solution by a width C smaller by 0.4 mm or more than the removal width B of the second low-k film 32. As a result, the edge of the third low-k film 32 is positioned 0.4 mm or more from the edge of the second low-k film 22 and 0.8 mm or more from the edge of the first low-k film 12.

  Next, as shown in FIG. 9C, a third cap film 33 is formed on the third low-k film 32. Then, an opening 34 is formed in the third cap film 33, the third low-k film 32, and the third diffusion prevention film 31. Thereafter, a Cu wiring layer as a third conductive layer is formed by embedding a Cu film as a barrier metal film 35 and a metal film 36 in the opening 34 using the same method as in the third embodiment. Is done.

Also in the fourth embodiment, as in the third embodiment, by setting the difference between the edge removal width of the upper low-k film and the edge removal width of the lower low-k film to be 0.4 mm or more, the substrate edge No steep low-k step is present in FIG. Thereby, the CMP load applied to the lower layer low-k film edge in the upper layer Cu-CMP can be significantly reduced, and the lower layer low-k film peeling in the Cu-CMP can be remarkably suppressed. Further, by increasing the edge removal width difference such as 0.7 mm or more and 1.0 mm or more, the step of the low-k film can be further reduced, and the low-k film or the relative dielectric constant having a low Young's modulus can be reduced. Even when a low-k film having a low thickness is used, peeling of the low-k film in Cu-CMP can be suppressed.
In the fourth embodiment, the upper low-k film edge is positioned outside the lower low-k film edge at the time when the Cu film is removed with a chemical (immediately before Cu-CMP). That is, the lower low-k film edge is covered with the upper low-k film in Cu-CMP. Therefore, peeling of the lower layer low-k film in Cu-CMP can be further suppressed than in Embodiment 3 due to the anchor effect.
Therefore, the yield can be improved and the reliability of the semiconductor device can be improved. In addition, Cu damascene wiring using a low-k film can be applied to the wiring of the semiconductor device, and the performance of the semiconductor device can be improved.

Embodiment 5 FIG.
In the fifth embodiment of the present invention, the multilayer wiring structure of the first embodiment described above is applied to the wiring of a semiconductor mounting apparatus. Specifically, the semiconductor chip is applied to wiring on the semiconductor chip when the semiconductor chip is packaged in a module.
FIG. 10 is a cross-sectional view for explaining the semiconductor mounting apparatus according to the fifth embodiment. FIG. 11 is a process sectional view for explaining the method for manufacturing the semiconductor mounting apparatus according to the fifth embodiment.

As shown in FIG. 10, on a substrate 41, a semiconductor element (not shown), multilayer wiring layers 43a, 43b, 43c, 43d formed on the semiconductor element and via contacts 44a, 44b, A semiconductor chip (semiconductor device) 40 having a multilayer wiring structure 42 having 44c in the insulating film is formed. Note that the semiconductor elements are those described in Embodiment Mode 3.
The first diffusion prevention film 11 is formed on the wiring layer 43 a of the multilayer wiring structure 42, and the first low-k film 12 having a width A removed from the substrate edge 10 is formed thereon. For example, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, or a SiN film can be used as the first diffusion prevention film 11 (the same applies to the diffusion prevention films 21 and 31 described later). As the first low-k film 12, for example, an MSQ (Methyl Silsesquioxane) film, an HSQ (Hydrogen Silsesquioxane) film or a polymer (for example, SiLK (registered trademark) manufactured by Dow Chemical Co., Ltd.), or a hole is introduced into them. Or a laminated film thereof can be used (the same applies to the low-k films 22 and 32 described later).
A first cap film 13 for preventing plasma damage is formed on the first low-k film 12. As the first cap film 13, a SiO ₂ film, a SiC film, a SiCN film, a SiCO film, a SiN film, or a laminated film thereof can be used (the same applies to cap films 23 and 33 described later).
An opening 14 reaching the upper surface of the wiring layer 43 a is formed in the first cap film 13, the first low-k film 12 and the first diffusion prevention film 11, and a barrier metal film 15 is formed on the inner wall of the opening 14. Yes. Further, a metal film 16 is formed on the barrier metal film 15. That is, the opening 14 is filled with the conductive film made of the barrier metal film 15 and the metal film 16, thereby forming the first conductive layer connected to the diffusion layer 6 through the contact 8 in the opening 14. The opening 14 is a wiring groove, a via hole, or the like (the same applies to the openings 24 and 34 described later). As the barrier metal film 15, for example, a Ta film, a Ti film, a TaN film, a TiN film, a WN film, a WSiN film, or a laminated film thereof can be used (the same applies to barrier metal films 25 and 35 described later). ). As the metal film 16, an Al film, a W film, a Cu film, an alloy film thereof, or the like can be used (the same applies to metal films 26 and 36 described later).

A second diffusion barrier film 21 is formed on the first conductive layer and the first cap film 13, a second low-k film 22 is formed thereon, and a second cap film 23 is formed thereon. Yes. Here, the second low-k film 22 is removed from the substrate edge 10 by a width B that is 0.4 mm or more larger than the removal width A of the first low-k film 12. That is, the edge removal width B of the second low-k film 22 is 0.4 mm or more larger than the edge removal width A of the first low-k film 12. As a result, the edge of the second low-k film 22 and the edge of the first low-k film 12 are separated, and the CMP load is extremely concentrated on the edge of the first low-k film 12 when the metal film 26 described later is CMPed. Can be prevented. Although details will be described later, as the difference between the removal width B and the removal width A (hereinafter referred to as “edge removal width difference”) is increased to 0.7 mm or more and 1.0 mm or more, the low− in Cu-CMP It is effective in suppressing the peeling of the k film. As in the first and third embodiments, it is optimal to change the edge removal width difference according to the film thickness of the low-k film. When the film thickness of the low-k film is less than 300 nm, the edge removal width difference is set to 0.4 mm or more. When the film thickness is 300 nm or more to less than 600 nm, the edge removal width difference is set to 0.7 mm or more. When the thickness is 600 nm or more, the edge removal width difference is preferably 1.0 mm or more.
An opening 24 reaching the surface of the Cu film 15 is formed in the second cap film 23, the second low-k film 22, and the second diffusion prevention film 21, and a barrier metal film 25 is formed on the inner wall of the opening 24. Further, a metal film 26 is formed on the barrier metal film 25. That is, the opening 24 is filled with the conductive film made of the barrier metal film 25 and the metal film 26, so that the second conductive layer is formed in the opening 24. Therefore, the second conductive layer is connected to the first conductive layer.

A third diffusion prevention film 31 is formed on the second conductive layer and the second cap film 23, a third low-k film 32 is formed thereon, and a third cap film 33 is formed thereon. Yes. Here, the third low-k film 32 is removed from the substrate edge 10 by a width B larger by 0.4 mm or more than the removal width B of the second low-k film 22. That is, the edge removal width C of the third low-k film 32 is 0.4 mm or more larger than the edge removal width B of the second low-k film 22. Accordingly, the edge of the third low-k film 32 is separated from the edge of the second low-k film 22 and the edge of the first low-k film 12, and when the metal film 36 to be described later is subjected to CMP, the edge of the second low-k film 22 and the first low-k film 22. It is possible to prevent the CMP load from being concentrated on the edge of the -k film 12.
An opening 34 reaching the metal film 26 is formed in the third cap film 33, the third low-k film 32, and the third low-k film 31, and a barrier metal film 35 is formed on the inner wall of the opening 34. Further, a metal film 36 is formed on the barrier metal film 35. That is, the opening 34 is filled with the conductive film including the barrier metal film 35 and the metal film 36, so that the third conductive layer is formed in the opening 34. Therefore, the third conductive layer is connected to the second conductive layer.

Next, a method for manufacturing the semiconductor mounting apparatus will be described.
First, as shown in FIG. 11A, a multilayer wiring structure 42 having multilayer wiring layers 43a, 43b, 43c, and 43d on a substrate 41 and via contacts 44a, 44b, and 44c for connecting them in an insulating film. A semiconductor chip (semiconductor device) 40 provided with is formed. The semiconductor element (for example, MIS transistor) in the multilayer wiring structure 42 has been described in the third embodiment, and illustration and description thereof are omitted.

Next, the first diffusion prevention film 11 is formed on the multilayer wiring structure 42 with a film thickness of, for example, 30 nm to 200 nm by the CVD method. Then, an MSQ film as the first low-k film 12 is formed with a film thickness of, for example, 100 nm to 1000 mm on the first diffusion prevention film 11 by a spin coating method. Immediately thereafter, the first low-k film 12 at the outer peripheral portion of the substrate is removed by the width A by a chemical solution. That is, the first low-k film 12 is removed from the substrate edge 10 by the removal width A. Thereafter, a baking process and a curing process are performed in an inert gas atmosphere, and a surface modification process of the first low-k film 12 is performed by irradiating He plasma.
Next, the first cap film 13 is formed on the first low-k film 12 with a film thickness of, for example, 30 nm to 200 nm by the CVD method. Then, an opening 14 reaching the upper surface of the wiring layer 43a is formed in the first cap film 13, the first low-k film 12, and the first diffusion prevention film 11 by lithography and dry etching. Then, a barrier metal film 15 is formed on the inner wall of the opening 14 and the first cap film 13 by a sputtering method, and a seed Cu film is formed on the barrier metal film 15 by a sputtering method. Further, a Cu film 16 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. The annealing treatment may be performed after removing the chemical solution from the Cu film 16.

Next, the Cu film 16 on the outer periphery of the substrate is removed with a chemical solution. The removal width of the Cu film 16, that is, the length from the substrate edge 10 to the Cu film edge was 3 mm.
Thereafter, the unnecessary Cu film 16 and barrier metal film 15 formed on the first cap film 13 are removed using an orbital CMP apparatus as in the first embodiment. Through the above steps, a first Cu wiring layer connected to the wiring layer 43a is formed.

  Next, the second diffusion prevention film 21 is formed with a film thickness of, for example, 30 nm to 200 nm on the first cap film 13 and the Cu wiring by the CVD method. Then, the second low-k film 22 is formed with a film thickness of, for example, 100 nm to 1000 nm on the second diffusion preventing film 21 by a spin coating method. Immediately thereafter, the second low-k film 22 on the outer peripheral portion of the substrate is removed by the width B by a chemical solution. The removal width B of the second low-k film 22 was 4 mm, which is 1 mm larger than the removal width A of the first low-k film 12. Thereafter, the second low-k film 22 is subjected to surface modification treatment by performing baking and curing in an inert gas atmosphere and further irradiating with He plasma.

Next, as illustrated in FIG. 11B, the second cap film 23 is formed on the second low-k film 22 with a film thickness of, for example, 30 nm to 200 nm by the CVD method. Then, an opening 24 is formed in the second cap film 23, the second low-k film 22, and the second diffusion prevention film 21 by lithography and dry etching. Next, a barrier metal film 25 is formed on the inner wall of the opening 24 and the second cap film 23 by a sputtering method, and a seed Cu film is formed on the barrier metal film 25 by a sputtering method. Further, a Cu film 26 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. Thereby, the opening 24 is filled with the conductive film including the barrier metal film 25, the seed Cu film, and the Cu film 26.
Next, the Cu film 26 on the outer periphery of the substrate is removed with a chemical solution. The removal width of the Cu film 26 is 2 mm, which is 2 mm smaller than the removal width B of the second low-k film 22. Then, unnecessary Cu film 26 and barrier metal film 25 formed on second cap film 23 are removed by performing CMP under the same conditions as the first-layer Cu wiring layer. Thereby, a via layer as a second conductive layer is formed.

  Next, the third diffusion prevention film 31 is formed on the second cap film 23 and the via with a film thickness of, for example, 30 nm to 200 nm by a CVD method. Then, the third low-k film 32 is formed with a film thickness of, for example, 100 nm to 1000 nm on the third diffusion preventing film 31 by spin coating. Immediately thereafter, the third low-k film 32 at the outer peripheral portion of the substrate is removed by the width C by a chemical solution. The removal width C of the third low-k film 32 is 5 mm, which is 1 mm larger than the removal width B of the second low-k film 22. After that, baking treatment and curing are performed in an inert gas atmosphere, and further, surface modification treatment of the third low-k film 32 is performed by irradiating He plasma.

Next, as illustrated in FIG. 11C, the third cap film 33 is formed on the third low-k film 32 with a film thickness of, for example, 30 nm to 200 nm by the CVD method. Then, an opening 34 is formed in the third cap film 33, the third low-k film 32, and the third diffusion prevention film 31 by lithography and dry etching. Next, a barrier metal film 35 is formed on the inner wall of the opening 34 and the third cap film 33 by a sputtering method, and a seed Cu film is formed on the barrier metal film 35 by a sputtering method. Further, a Cu film 36 is formed on the seed Cu film by electrolytic plating. Thereafter, annealing is performed. Thereby, the opening 34 is filled with the conductive film including the barrier metal film 35, the seed Cu film, and the Cu film 36.
Next, the Cu film 36 on the outer periphery of the substrate is removed with a chemical solution. The removal width of the Cu film 36 is 2 mm, which is 3 mm smaller than the removal width C of the third low-k film 32. Then, unnecessary Cu film 36 and barrier metal film 35 formed on third cap film 33 are removed by performing CMP under the same conditions as those for the first-layer Cu wiring layer. As a result, a Cu wiring layer as a third conductive layer is formed.

As described above, in the fifth embodiment, the difference between the edge removal width of the upper low-k film and the edge removal width of the lower low-k film is set to 0.4 mm or more, so that the substrate edge is steep. There was no step in the low-k film. Thereby, the CMP load applied to the lower layer low-k film edge in the upper layer Cu-CMP can be significantly reduced, and the lower layer low-k film peeling in the Cu-CMP can be remarkably suppressed. Further, by increasing the edge removal width difference such as 0.7 mm or more and 1.0 mm or more, the step of the low-k film can be further reduced, and the low-k film or the relative dielectric constant having a low Young's modulus can be reduced. Even when a low-k film having a low thickness is used, peeling of the low-k film in Cu-CMP can be suppressed.
Therefore, the yield can be improved and the reliability of the semiconductor mounting apparatus can be improved. Also, Cu damascene wiring using a low-k film can be applied to the wiring on the semiconductor chip, and the performance of the semiconductor mounting apparatus can be improved.

Embodiment 6 FIG.
In the sixth embodiment of the present invention, the multilayer wiring structure of the second embodiment described above is applied to the wiring of a semiconductor mounting apparatus. Specifically, the semiconductor chip is applied to wiring on the semiconductor chip when the semiconductor chip is packaged in a module.
In the fifth embodiment, when the edge removal width of the upper layer low-k film is made larger than the edge removal width of the lower layer low-k film, that is, the lower layer low-k film edge is larger than the upper layer low-k film edge. The case of becoming a side was explained. In the sixth embodiment, when the edge removal width of the upper layer low-k film is made smaller than the edge removal width of the lower layer low-k film, that is, the upper layer low-k film edge is larger than the lower layer low-k film edge. The case where it becomes a side is demonstrated. Since the other points are the same as in the fifth embodiment, the following description will be made with a focus on differences from the fifth embodiment with reference to FIGS. 12 and 13. FIG. 12 is a cross-sectional view for explaining the semiconductor mounting apparatus according to the sixth embodiment. FIG. 13 is a process sectional view for explaining the method for manufacturing the semiconductor mounting apparatus according to the sixth embodiment.

As shown in FIG. 12, a semiconductor chip 40 having a semiconductor element on a substrate 41 and a wiring structure 42 having multilayer wiring layers 43a, 43b, 43c, 43d and via contacts 44a, 44b, 44c connecting them. Is formed. On the semiconductor chip 40, the multilayer wiring structure of the second embodiment is applied. Three low-k films 12, 22, and 32 are stacked on the semiconductor chip 40, and a conductive layer is formed in each low-k film.
As shown in FIG. 12, the first low-k film 12 is removed by the removal width A in the vicinity of the substrate edge 10, and the second low-k film 22 is removed by the removal width B smaller than the removal width A by 0.4 mm or more, The third low-k film 32 is removed by a removal width C that is smaller than the removal width B by 0.4 mm or more. Accordingly, the second low-k film 22 edge is positioned on the outer peripheral side of the substrate with respect to the first low-k film 12 edge, and the third low-k film 32 edge is positioned on the outer peripheral side of the substrate with respect to the second low-k film 22 edge. To do. Therefore, the edge of the first low-k film 12 is covered with the second low-k film 22, and the edge of the second low-k film 22 is covered with the third low-k film 32. The rest is the same as in the fifth embodiment.

Next, a method for manufacturing the semiconductor device will be described.
First, as shown in FIG. 13A, a semiconductor chip 40 is formed using the same method as in the fifth embodiment.
Next, the first diffusion barrier film 11 is formed on the semiconductor chip 40, and the first low-k film 12 is applied thereon. Immediately after the application, the first low-k film 12 on the outer peripheral portion of the substrate is removed from the substrate edge 10 by the width A with a chemical solution. Thereafter, a baking process and a curing process are performed, and a surface modification process of the first low-k film 12 using He plasma is performed.
Next, the first cap film 13 is formed on the first low-k film 12. Then, an opening 14 reaching the upper surface of the contact 8 is formed in the first cap film 13, the first low-k film 12, and the first diffusion prevention film 11. Thereafter, a Cu wiring layer as a first conductive layer is formed by embedding a barrier metal film 15 and a Cu film as the metal film 16 in the opening 14 using the same method as in the third embodiment. Is done.
Next, a second diffusion prevention film 21 is formed on the first cap film 13 and the Cu wiring, and a second low-k film 22 is applied thereon. Immediately after the application, the second low-k film 22 on the outer periphery of the substrate is removed by a chemical solution by a width B smaller by 0.4 mm or more than the removal width A of the first low-k film 12. As a result, the edge of the second low-k film 22 is positioned on the outer peripheral side of the substrate by 0.4 mm or more than the edge of the first low-k film 12.

Next, as shown in FIG. 13B, the second cap film 23 is formed on the second low-k film 12. Then, a via hole as an opening 24 is formed in the second cap film 23, the second low-k film 22, and the second diffusion prevention film 21. Thereafter, a barrier layer as a second conductive layer is formed by embedding the barrier metal film 25 and the metal film 26 in the opening 24 using the same method as in the third embodiment.
Next, the third diffusion prevention film 31 is formed on the second cap film 23 and the via, and the third low-k film 32 is applied thereon. Immediately after the application, the third low-k film 32 at the outer peripheral portion of the substrate is removed by a chemical solution by a width C smaller than the removal width B of the second low-k film 22 by 0.4 mm or more. As a result, the edge of the third low-k film 32 is positioned 0.4 mm or more from the edge of the second low-k film 22 and 0.8 mm or more from the edge of the first low-k film 12.

  Next, as shown in FIG. 13C, a third cap film 33 is formed on the third low-k film 32. Then, an opening 34 is formed in the third cap film 33, the third low-k film 32, and the third diffusion prevention film 31. Thereafter, a Cu wiring layer as a third conductive layer is formed by embedding a Cu film as a barrier metal film 35 and a metal film 36 in the opening 34 using the same method as in the third embodiment. Is done.

Also in the sixth embodiment, as in the fifth embodiment, the difference between the edge removal width of the upper low-k film and the edge removal width of the lower low-k film is set to 0.4 mm or more, so that the substrate edge No steep low-k step is present in FIG. Thereby, the CMP load applied to the lower layer low-k film edge in the upper layer Cu-CMP can be significantly reduced, and the lower layer low-k film peeling in the Cu-CMP can be remarkably suppressed. Further, by increasing the edge removal width difference such as 0.7 mm or more and 1.0 mm or more, the step of the low-k film can be further reduced, and the low-k film or the relative dielectric constant having a low Young's modulus can be reduced. Even when a low-k film having a low thickness is used, peeling of the low-k film in Cu-CMP can be suppressed.
In the sixth embodiment, the upper low-k film edge is located outside the lower low-k film edge at the time when the Cu film is removed with a chemical (immediately before Cu-CMP). That is, the lower low-k film edge is covered with the upper low-k film in Cu-CMP. Therefore, peeling of the lower layer low-k film in Cu-CMP can be further suppressed than in Embodiment 5 due to the anchor effect.
Therefore, the yield can be improved and the reliability of the semiconductor mounting apparatus can be improved. Also, Cu damascene wiring using a low-k film can be applied to the wiring on the semiconductor chip, and the performance of the semiconductor mounting apparatus can be improved.

Embodiment 7 FIG.
In the seventh embodiment of the present invention, the multilayer wiring structure of the first or second embodiment described above is applied to the wiring of a semiconductor mounting apparatus formed of a multilayer substrate. FIG. 14 is a cross-sectional view for explaining the semiconductor mounting apparatus according to the seventh embodiment.

As shown in FIG. 14, the semiconductor mounting apparatus includes a first-layer semiconductor chip (hereinafter simply referred to as “chip”) having a substrate 51 and a multilayer wiring structure 52, a substrate 53 and a multilayer wiring structure 54. A layer chip and a third layer chip having a substrate 55 and a multilayer wiring structure 56 are stacked. Specifically, the first layer chip and the second layer chip are face-to-face connected using a low-k film 62 as an adhesive layer, and the second layer chip and the third layer chip are low- Face-to-back connection is made using the k film 65 as an adhesive layer. Insulating layers 61 and 63 and insulating layers 64 and 66 functioning as diffusion preventing films are formed below and above the low-k films 62 and 65, respectively. A wiring layer 72 is formed in the insulating film 64. In addition, the bridge via 71 connected to the wiring layer 72 is formed in communication with the first and second layer chips, and the bridge via 73 is formed in the third layer chip. The stacked chips are electrically connected.
A multilayer wiring structure that is electrically connected to the bridge via 53 is formed on the third-layer chip.

Also in the seventh embodiment, as in the fifth and sixth embodiments, the difference between the edge removal width of the upper low-k film and the edge removal width of the lower low-k film is set to 0.4 mm or more. The steep low-k film step is not present at the substrate edge. Thereby, the CMP load applied to the lower layer low-k film edge in the upper layer Cu-CMP can be significantly reduced, and the lower layer low-k film peeling in the Cu-CMP can be remarkably suppressed. Further, by increasing the edge removal width difference such as 0.7 mm or more and 1.0 mm or more, the step of the low-k film can be further reduced, and the low-k film or the relative dielectric constant having a low Young's modulus can be reduced. Even when a low-k film having a low thickness is used, peeling of the low-k film in Cu-CMP can be suppressed.
Therefore, the yield can be improved and the reliability of the semiconductor mounting apparatus can be improved. Also, Cu damascene wiring using a low-k film can be applied to the wiring on the semiconductor chip, and the performance of the semiconductor mounting apparatus can be improved.

It is sectional drawing for demonstrating the multilayer wiring structure by Embodiment 1 of this invention. It is process sectional drawing for demonstrating the multilayer wiring formation method by Embodiment 1 of this invention. It is sectional drawing which shows the comparative example of Embodiment 1 of this invention. It is sectional drawing for demonstrating the multilayer wiring structure by Embodiment 2 of this invention. It is process sectional drawing for demonstrating the multilayer wiring formation method by Embodiment 2 of this invention. It is sectional drawing for demonstrating the semiconductor device by Embodiment 3 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device by Embodiment 3 of this invention. It is sectional drawing for demonstrating the semiconductor device by Embodiment 4 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device by Embodiment 4 of this invention. It is sectional drawing for demonstrating the semiconductor mounting apparatus by Embodiment 5 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor mounting apparatus by Embodiment 5 of this invention. It is sectional drawing for demonstrating the semiconductor mounting apparatus by Embodiment 6 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor mounting apparatus by Embodiment 6 of this invention. It is sectional drawing for demonstrating the semiconductor mounting apparatus by Embodiment 7 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Base | substrate, board | substrate 2 Gate insulating film 3 Gate electrode 4 Low concentration diffusion layer 5 Side wall 6 High concentration diffusion layer 7 Interlayer insulating film 8 Contact 10 Substrate edge 11 First diffusion prevention film 12 First low-k film (MSQ film)
13 First Cap Film 14, 24, 34 Opening 15, 25, 35 Barrier Metal Film 16, 26, 36 Metal Film (Cu Film)
21 Second diffusion prevention film 22 Second low-k film (MSQ film)
23 Second cap film 31 Third diffusion prevention film 32 Third low-k film (MSQ film)
33 Third cap film 40 Semiconductor device (semiconductor chip)
41 substrate 41a substrate edge 42 multilayer wiring structure 43a, 43b, 43c, 43d, wiring layer 44a, 44b, 44c via contact 51, 53, 55 substrate 52, 54, 56 multilayer wiring structure 61, 63, 64, 66 insulating layer 62 , 65 low-k film 71, 73 Bridge via 72 Wiring layer

Claims (9)

A first low dielectric constant film formed on the ground and removed from the edge of the base by a first width;
A first conductive layer embedded in a first opening formed in the first low dielectric constant film;
A second low dielectric constant formed on the first conductive layer and the first low dielectric constant film and removed from the underlying edge by a second width different from the first width by 0.4 mm or more. A membrane,
A multilayer wiring structure comprising: a second conductive layer embedded in a second opening formed in the second low dielectric constant film. A semiconductor element formed on a substrate and having a diffusion layer;
An interlayer insulating film covering the semiconductor element;
A contact formed in the interlayer insulating film and connected to the diffusion layer;
A first low dielectric constant film formed on the contact and the interlayer insulating film and removed from the edge of the substrate by a first width;
A first conductive layer embedded in a first opening formed in the first low dielectric constant film;
A second low dielectric constant formed on the first conductive layer and the first low dielectric constant film and removed from the edge of the substrate by a second width different from the first width by 0.4 mm or more. A membrane,
A semiconductor device comprising: a second conductive layer embedded in a second opening formed in the second low dielectric constant film. The semiconductor device according to claim 2,
When the thickness of the second low dielectric constant film is 300 nm or more and less than 600 nm, the first width and the second width are different from each other by 0.7 mm or more. The semiconductor device according to claim 2,
When the film thickness of the second low dielectric constant film is 600 nm or more, the first width and the second width are different from each other by 1.0 mm or more. The semiconductor device according to any one of claims 2 to 4,
The semiconductor device, wherein the second width is larger than the first width. A semiconductor chip having a semiconductor element and an upper layer wiring on the substrate;
A first low dielectric constant film formed on the semiconductor chip and removed from the edge of the semiconductor chip by a first width;
A first conductive layer embedded in a first opening formed in the first low dielectric constant film;
A second low dielectric constant formed on the first conductive layer and the first low dielectric constant film and removed from the edge of the substrate by a second width different from the first width by 0.4 mm or more. A membrane,
A semiconductor mounting device comprising: a second conductive layer embedded in a second opening formed in the second low dielectric constant film. The semiconductor device according to claim 6.
When the thickness of the second low dielectric constant film is 300 nm or more and less than 600 nm, the first width and the second width are different from each other by 0.7 mm or more. The semiconductor device according to claim 6.
When the film thickness of the second low dielectric constant film is 600 nm or more, the first width and the second width are different from each other by 1.0 mm or more. The semiconductor device according to any one of claims 6 to 8,
The semiconductor device, wherein the second width is larger than the first width.

Images