KR20100036100A - Method for fabricating landing plug in semicondutor device - Google Patents

Method for fabricating landing plug in semicondutor device Download PDF

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Publication number
KR20100036100A
KR20100036100A KR1020080095556A KR20080095556A KR20100036100A KR 20100036100 A KR20100036100 A KR 20100036100A KR 1020080095556 A KR1020080095556 A KR 1020080095556A KR 20080095556 A KR20080095556 A KR 20080095556A KR 20100036100 A KR20100036100 A KR 20100036100A
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KR
South Korea
Prior art keywords
landing plug
contact
forming
gate
hard mask
Prior art date
Application number
KR1020080095556A
Other languages
Korean (ko)
Inventor
이명신
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080095556A priority Critical patent/KR20100036100A/en
Publication of KR20100036100A publication Critical patent/KR20100036100A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

PURPOSE: A method for fabricating a landing plug in a semiconductor device is provided to reduce a landing plug contact resistance by restraining dopant loss by preventing out-diffusion in a following annealing process. CONSTITUTION: A gate stack(110) including a gate hard mask membrane(113) is formed on a substrate. An inter-layer insulating film(120) covering the gate stacks is formed. A contact hole selectively exposing a substrate portion between gate stacks by etching the inter-layer insulating film is formed. A polysilicon layer filling a contact hole on a substrate formed with the contact hole is formed. A planarization process for the polysilicon layer is implemented so that the top surface of the gate hard mask membrane is exposed. An anti oxidation layer(160) preventing the dopant loss is formed in the top surface.

Description

Landing plug contact formation method of semiconductor device {Method for fabricating landing plug in semicondutor device}

The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a landing plug of a semiconductor device.

As semiconductor devices are highly integrated, as the patterns are fine, various methods have been attempted to manufacture semiconductor devices having better characteristics. In particular, a landing plug contact (LPC) is introduced to secure stable contact between an upper conductor such as a bit line or a storage electrode and a lower conductor.

In order to form a landing plug contact, first, a gate electrode including a hard mask film is formed on a semiconductor substrate, an interlayer insulating film is deposited to separate the gate electrode, and then the interlayer insulating film is selectively etched to expose the semiconductor substrate. A contact hole is formed. After filling the contact hole with a landing plug polysilicon (LPP) film, a chemical mechanical polishing (CMP) process is performed on the polysilicon film until the surface of the hard mask film is exposed. Is done.

However, due to the characteristics of the CMP process using a slurry, such as chemical reaction and mechanical wearing, roughness is uneven at the upper interface of the landing plug polysilicon film. A layer is formed. In the damage layer interface, the dopant concentration in the polysilicon film is irregular and causes a dopant loss due to out diffusion in the subsequent heat treatment process. Accordingly, the landing plug contact resistance is increased, and the interface resistance with the upper conductive layer, for example, the storage node contact, is lowered, thereby reducing the electrical characteristics of the semiconductor device.

A method of forming a landing plug contact of a semiconductor device according to the present invention may include forming gate stacks including a gate hard mask layer on a substrate; Forming an interlayer insulating film covering the gate stacks; Etching the interlayer insulating film to form a contact hole for selectively exposing a portion of the substrate between the gate stacks; Forming a polysilicon layer filling the contact hole on the substrate on which the contact hole is formed; Forming a contact by performing a planarization process on the polysilicon layer so that the upper surface of the gate hard mask layer is exposed; And forming a oxide film of the resultant of the contact is formed, removing the damaged layer caused by the planarization process to the ozone treatment (O 3 treatment) and preventing the loss of the dopant in the contact upper surface.

The method may further include forming a hard mask layer pattern on the interlayer insulating layer to selectively expose a region where the contact is formed.

The morning treatment is preferably performed using a chemical solution containing ozone.

It is preferable that the chemical solution containing ozone consists of a washing | cleaning liquid which mixed ozone water and BOE solution.

The ozone water preferably contains an ozone concentration of 30 ppm.

The ozone treatment is preferably performed for 30 to 60 seconds.

The antioxidant film is preferably formed to a depth of 10Å from the contact upper surface.

Referring to FIG. 1, a gate insulating layer 111, a gate conductive layer 112, and a gate hard mask layer 113 are included on a semiconductor substrate 100 including a cell region A and a peripheral circuit region B. FIG. The gate stacks 110 are formed.

Specifically, after the gate insulating film 111 and the gate conductive film 112 are formed on the semiconductor substrate 100, an insulating material for a hard mask is formed. The gate stack 110 including the gate hard mask layer 113 is formed by patterning the gate conductive layer 112 and the gate insulating layer 111 by performing a photolithography process and an etching process. do. The gate insulating layer 111 may be formed to include a silicon oxide (SiO 2 ) film. The gate conductive film 112 may be formed by forming a polysilicon film or a metal film alone or by laminating it. The insulating material for the hard mask may be formed of a material layer having an etching selectivity with the gate insulating layer 111 and the gate conductive layer 112, for example, a silicon nitride (SiN) layer.

Spacers 120 are formed on sidewalls of the gate stacks 110. Specifically, after forming a spacer layer covering the gate stacks 110 on the semiconductor substrate 100, anisotropic etching, for example, an etch back process is performed to expose portions of the semiconductor substrate 100 between the gate stacks. While forming the spacers 120 on the sidewalls of the gate stacks 110.

After the interlayer insulating layer 130 is formed on the semiconductor substrate 100 having the spacers 120 formed therebetween, the planarization process may be performed until the upper surface of the gate hard mask layer 113 is exposed. Mechanical polishing (CMP) process is performed. The interlayer insulating film 130 may be formed of an oxide film, for example, a BPSG film, but is not limited thereto. In the chemical mechanical polishing process, the gate hard mask layer 113 pattern of the gate stacks 110 formed in the cell region A is performed as the end point of the etching using the cell region A as a target. That is, when the surface of the gate hard mask film 113 is exposed during the CMP process, the chemical mechanical polishing process is finished. Accordingly, the gate stacks 110 are separated by the interlayer insulating layer 130.

Referring to FIG. 2, a lantern lamp contact hard mask layer pattern 140 for forming a landing plug contact (LPC) is formed on the interlayer insulating layer 130 and the exposed gate hard mask layer 113. The landing plug contact hard mask layer pattern 140 may include a TEOS layer, but is not limited thereto. In this case, the landing plug contact hard mask layer pattern 140 is disposed to selectively expose a region in which the landing plug contact is to be formed in the cell region A. FIG.

Referring to FIG. 3, the semiconductor substrate between the gate stacks 110 may be formed by performing an etching process using the landing plug contact hard mask layer pattern 140 as an etch mask, for example, a self alignment contact (SAC) process. 100) form a landing plug contact hole (LPC hole) exposing the portion. Here, the gate hard mask layer 113 and the spacer 120 may act as a barrier layer for etching when the landing plug large contact hole is formed to prevent the gate conductive layer 112 from being exposed and damaged.

In this case, the gate hard mask layer 110 of the gate stacks exposed by the landing plug hard mask layer pattern 120 and the gate hard mask layer of the gate stacks 110 blocked by the landing plug hard mask layer pattern 120. Steps may occur between the 110. For example, the gate hard mask layer 113 of the exposed gate stacks 110 is lost by a certain thickness during the etching process for forming the landing plug contact hole, and is blocked by the landing plug hard mask layer pattern 120. the thickness of the gate stack 100, the gate hard mask layer 113 of (h 1) than the gate hard mask layer of the gate stack 110 is exposed (the thickness of 120 (h 2) becomes relatively low.

Referring to FIG. 4, a landing plug polysilicon (LPP) film 150 for landing plug contact is formed on the semiconductor substrate 100 on which the landing plug contact hole is formed. The landing plug layer may be formed of, for example, a doped polysilicon layer, but is not limited thereto.

Referring to FIG. 5, the landing plug hard mask layer pattern and the polysilicon layer may be planarized, for example, a chemical mechanical polishing process, to form a landing plug contact (LPC) 151. In this case, the chemical mechanical polishing process is performed such that the gate hard mask layers 113 of the gate stacks 110 have the same thickness. That is, a portion of the interlayer insulating layer 120 and the gate hard mask layer 113 in the region where the landing plug contact 151 is not formed are removed to planarize.

However, due to the characteristics of the CMP process, for example, chemical reaction and mechanical wear, the damage layer 152 having roughness unevenness at the upper interface of the landing plug contact 151 may be formed. It is being triggered.

In Figure 6, the chemical mechanical polishing is carried out results, ozone treatment (O 3 treatment) to the landing plug contacts (151) to remove the damaged layer (152 in Fig. 5) causing the upper interface and prevent dopant loss The anti-oxidation film 160 is formed. Ozone treatment can be performed for about 30 seconds to 60 seconds using a chemical solution containing ozone water, for example, a cleaning solution in which ozone water and BOE are mixed. At this time, it is preferable that ozone water consists of ozone water containing the ozone concentration of about 30 ppm. In particular, the ozone treatment controls the anti-oxidation film 160 to be formed 10 DEG deep from the upper surface of the landing plug contact 152.

For example, after the chemical mechanical polishing process, ozone treatment of the polished landing plug contact 151 interface is performed to remove the damaged layer 152 damaged by the chemical mechanical polishing, and oxidation is performed at the upper interface of the landing plug contact 151. A (SiO 2 ) film can be formed. The oxide layer serves to prevent the dopant from being lost by preventing the diffusion of the dopant within the landing plug contact 151, that is, the polysilicon layer during the subsequent heat treatment process.

In the method of forming a landing plug contact of a semiconductor device according to the present invention, after the chemical mechanical polishing process for forming the landing plug contact, the treatment is carried out in the morning, thereby the characteristics of the CMP process, for example, chemical reaction, mechanical wearing ) Removes the induced damage layer on the landing plug contact upper interface, and then forms an antioxidant film. The anti-oxidation film may prevent out diffusion in the subsequent heat treatment process to suppress dopant loss and reduce landing plug contact resistance. For example, the electrical resistance of the semiconductor device may be improved by improving an interface resistance with an upper conductive layer, for example, a storage node contact.

As mentioned above, although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiment, and various modifications may be made by those skilled in the art within the preferred technical spirit of the present invention. Of course.

1 to 6 are views illustrating a method of forming a landing plug contact of a semiconductor device according to the present invention.

Claims (7)

Forming gate stacks including a gate hard mask layer on the substrate; Forming an interlayer insulating film covering the gate stacks; Etching the interlayer insulating film to form a contact hole for selectively exposing a portion of the substrate between the gate stacks; Forming a polysilicon layer filling the contact hole on the substrate on which the contact hole is formed; Forming a contact by performing a planarization process on the polysilicon layer so that the upper surface of the gate hard mask layer is exposed; And A semiconductor device including the step of forming an oxide film of the resultant is the contact is formed, the ozone treatment (O 3 treatment) to remove a damaged layer caused by the planarization process, prevent dopant loss in the contact top surface Landing plug contact formation method. The method of claim 1, And forming a hard mask layer pattern on the interlayer insulating layer to selectively expose a region where the contact is formed. The method of claim 1, The morning treatment is a landing plug contact forming method of a semiconductor device is performed using a chemical solution containing ozone. The method of claim 1, And a chemical solution containing ozone, wherein the chemical solution comprises ozone water and a BOE solution. The method of claim 4, wherein The ozone water is a landing plug contact forming method of a semiconductor device comprising an ozone concentration of 30ppm. The method of claim 1, The ozone treatment is a landing plug contact forming method of a semiconductor device performed for 30 to 60 seconds. The method of claim 1, The anti-oxidation film is a landing plug contact forming method of a semiconductor device to form a depth 10Å from the contact upper surface.
KR1020080095556A 2008-09-29 2008-09-29 Method for fabricating landing plug in semicondutor device KR20100036100A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080095556A KR20100036100A (en) 2008-09-29 2008-09-29 Method for fabricating landing plug in semicondutor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080095556A KR20100036100A (en) 2008-09-29 2008-09-29 Method for fabricating landing plug in semicondutor device

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KR20100036100A true KR20100036100A (en) 2010-04-07

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008407B2 (en) 2014-12-04 2018-06-26 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices including conductive structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008407B2 (en) 2014-12-04 2018-06-26 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices including conductive structures

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