JP2014042050A5 - - Google Patents

Download PDF

Info

Publication number
JP2014042050A5
JP2014042050A5 JP2013214264A JP2013214264A JP2014042050A5 JP 2014042050 A5 JP2014042050 A5 JP 2014042050A5 JP 2013214264 A JP2013214264 A JP 2013214264A JP 2013214264 A JP2013214264 A JP 2013214264A JP 2014042050 A5 JP2014042050 A5 JP 2014042050A5
Authority
JP
Japan
Prior art keywords
layer
pad
solder joint
opening
passivation layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2013214264A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014042050A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2013214264A priority Critical patent/JP2014042050A/ja
Priority claimed from JP2013214264A external-priority patent/JP2014042050A/ja
Publication of JP2014042050A publication Critical patent/JP2014042050A/ja
Publication of JP2014042050A5 publication Critical patent/JP2014042050A5/ja
Withdrawn legal-status Critical Current

Links

JP2013214264A 2013-10-11 2013-10-11 ポストパッシベーション法を使用した高性能システムオンチップ Withdrawn JP2014042050A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013214264A JP2014042050A (ja) 2013-10-11 2013-10-11 ポストパッシベーション法を使用した高性能システムオンチップ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013214264A JP2014042050A (ja) 2013-10-11 2013-10-11 ポストパッシベーション法を使用した高性能システムオンチップ

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2001267522A Division JP5683765B2 (ja) 2001-09-04 2001-09-04 集積回路チップ及びその形成方法

Publications (2)

Publication Number Publication Date
JP2014042050A JP2014042050A (ja) 2014-03-06
JP2014042050A5 true JP2014042050A5 (cg-RX-API-DMAC7.html) 2014-04-17

Family

ID=50394010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013214264A Withdrawn JP2014042050A (ja) 2013-10-11 2013-10-11 ポストパッシベーション法を使用した高性能システムオンチップ

Country Status (1)

Country Link
JP (1) JP2014042050A (cg-RX-API-DMAC7.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116705758A (zh) * 2023-07-18 2023-09-05 江苏帝奥微电子股份有限公司 一种降低高速开关通道金属寄生电容金属结构及制备工艺

Similar Documents

Publication Publication Date Title
JP2017108019A5 (cg-RX-API-DMAC7.html)
SG152979A1 (en) Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
JP2014182397A5 (cg-RX-API-DMAC7.html)
TWI780081B (zh) 半導體元件及其製造方法
JP2014526149A5 (cg-RX-API-DMAC7.html)
WO2012061381A8 (en) Crack arrest vias for ic devices
EP2988325A3 (en) Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof
CN104867909B (zh) 用于有源装置的嵌入式管芯再分布层
CN110459519A (zh) 半导体装置封装及其制造方法
JP2015072996A5 (cg-RX-API-DMAC7.html)
JP2012004505A5 (cg-RX-API-DMAC7.html)
JP2014003292A5 (cg-RX-API-DMAC7.html)
JP2015149325A5 (cg-RX-API-DMAC7.html)
TWI633636B (zh) 電子裝置及其製造方法
TWI520278B (zh) 嵌埋有晶片之封裝結構的製法
US9899344B2 (en) Substrate structure, fabrication method thereof and conductive structure
EP2838114A3 (en) Chip package
JP2011071547A5 (ja) 半導体集積回路装置
JP2014112694A5 (cg-RX-API-DMAC7.html)
JP2014042050A5 (cg-RX-API-DMAC7.html)
TW200629438A (en) Chip structure with bumps and testing pads
JP2012004506A5 (cg-RX-API-DMAC7.html)
TWI541952B (zh) 半導體封裝件及其製法
TWI473228B (zh) 半導體封裝件之製法
JP2014167988A5 (cg-RX-API-DMAC7.html)