JP2014003077A - Package for high-frequency semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a package for a high-frequency semiconductor capable of performing external adjustment of an input output impedance.SOLUTION: A package for a high-frequency semiconductor comprises: a semiconductor device 24 arranged on a conductor base plate 200; a metal wall 16 arranged on the conductor base plate 200 and incorporating the semiconductor device 24 therein; a through-hole provided to the input output part of the metal wall 16; a feedthrough lower layer part 20 fitting into the through-hole and arranged on the conductor base plate 200; a feedthrough upper layer part 22 fitting into the through-hole and arranged on the feedthrough lower layer part 20; striplines 19a and 19b arranged between the feedthrough lower layer part 20 and the feedthrough upper layer part 22; leads 21a and 21b arranged on the striplines 19a and 19b; and capacity adjustment patterns 41, 42, 43, 44, 51, 52, 53, and 54 arranged so as to be adjacent to the striplines 19a and 19b provided outside the metal wall.

Description

  Embodiments described herein relate generally to a high-frequency semiconductor package.

  A high-frequency circuit used in a high-frequency band is composed of circuit elements such as a semiconductor element, a capacitor, a resistor, a coil, and a strip line, and is used in a package.

  In relation to this, the path length of the ground current between two substrates having different thicknesses, such as a MIC (Microwave Integrated Circuit) substrate and a LTCC (Low Temperature Co-fired Ceramic) substrate, for example. A high-frequency circuit device capable of reducing the deterioration of electrical characteristics by shortening the length of the circuit is disclosed.

JP 05-83010 A US Pat. No. 6,759,742

  In the case of such a structure, there is a problem that a gap (gap) or a step between the MIC substrate and the LTCC substrate becomes large, a ground current path between the two substrates becomes long, loss increases, and current characteristics deteriorate. .

  When a package is mounted, an unnecessary inductance component is generated because there are not a few gaps under the leads. In order to cancel this inductance component, it is effective to add capacitance to both sides of the inductance. However, since there is no capacitance adjustment pattern on the package side, the user cancels the inductance component by connecting the island pattern only on the board side and adding the capacitance component.

  A problem to be solved by the present embodiment is to provide a high-frequency semiconductor package in which input / output impedance can be externally adjusted.

  The high-frequency semiconductor package according to the present embodiment includes a conductor base plate, a semiconductor device, a metal wall, a through hole, a feedthrough lower layer, a feedthrough upper layer, a stripline, a lead, and a capacitance adjustment Pattern. The semiconductor device is disposed on the conductor base plate. The metal wall is disposed on the conductor base plate and contains the semiconductor device inside. The through hole is provided in the input / output part of the metal wall. The feedthrough lower layer portion is fitted into the through hole and disposed on the conductor base plate. The feedthrough upper layer portion is fitted into the through hole and is disposed on the feedthrough lower layer portion. The stripline is disposed between the feedthrough lower layer and the feedthrough upper layer. The lead is disposed on the strip line. The capacity adjustment pattern is disposed adjacent to the strip line outside the metal wall.

It is a typical bird's-eye view of the package for high frequency semiconductors concerning an embodiment, (a) metal cap 10, (b) metal seal ring 14a, (c) metal wall 16, (d) conductor base plate 200, feedthrough lower layer part 20, feedthrough upper layer 22, strip lines 19 a and 19 b disposed on feedthrough lower layer 20, and capacity adjustment patterns 41, 42, 43, 44, 51, 52, disposed on feedthrough lower layer 20 The schematic block diagram of 53 * 54. (A) a schematic planar pattern configuration diagram of a high-frequency semiconductor package according to the embodiment, (b) a package for the cancel it inductance component L _i of the input-side lead 21a of the high-frequency semiconductor package according to the embodiment side capacitive adjusting component C _i1 circuit diagram consisting of, (c) an inductance component of the output-side lead 21b of the high-frequency semiconductor package according to the embodiment of L _i and the package-side capacitance adjustment circuit components C _i2 to cancel it Diagram. The typical plane pattern block diagram of the package for high frequency semiconductors which concerns on embodiment mounted on the package base board. FIG. 5 is a schematic cross-sectional configuration diagram of the high-frequency semiconductor package according to the embodiment mounted on a package base board, and taken along line VV in FIG. 3. (A) Inductance component L _i of input-side lead 21a of the high-frequency semiconductor package according to the embodiment mounted on the package base board, package-side capacitance adjustment component C _i1 for canceling it, and on-board capacitance adjustment component Π-type circuit configuration diagram composed of C _o1 , (b) inductance component L _O of the output-side lead 21b of the high-frequency semiconductor package according to the embodiment, package-side capacitance adjusting component C _i2 for canceling it, and on-board capacitance The pi-type circuit block diagram which consists of adjustment component _Co2 . It is typical sectional structure of the package for high frequency semiconductors which concerns on embodiment, Comprising: Typical sectional structure drawing which follows the II line | wire of Fig.2 (a). It is typical sectional structure of the package for high frequency semiconductors concerning embodiment, Comprising: Typical sectional structure drawing which follows the II-II line | wire of Fig.2 (a). It is typical sectional structure of the package for high frequency semiconductors which concerns on embodiment, Comprising: Typical sectional structure drawing which follows the III-III line of Fig.2 (a). It is typical sectional structure of the package for high frequency semiconductors concerning embodiment, Comprising: Typical sectional structure drawing which follows the IV-IV line of Fig.2 (a). (A) The enlarged view of the typical plane pattern structure of the semiconductor device mounted in the package for high frequency semiconductors concerning embodiment, (b) The enlarged view of J part of Fig.10 (a). FIG. 11 is a schematic cross-sectional structure diagram illustrating a configuration example 1 of the semiconductor device mounted on the high-frequency semiconductor package according to the embodiment, taken along line VI-VI in FIG. FIG. 11 is a schematic cross-sectional configuration diagram illustrating a configuration example 2 of the semiconductor device mounted on the high-frequency semiconductor package according to the embodiment, taken along line VI-VI in FIG. 10 is a configuration example 3 of the semiconductor device mounted on the high-frequency semiconductor package according to the embodiment, and is a schematic cross-sectional configuration diagram taken along line VI-VI in FIG. FIG. 10 is a schematic cross-sectional structure diagram taken along line VI-VI in FIG. 10B, which is a configuration example 4 of the semiconductor device mounted on the high-frequency semiconductor package according to the embodiment. The typical plane pattern block diagram of another semiconductor device mounted in the package for high frequency semiconductors concerning embodiment. The typical plane pattern block diagram of the package for high frequency semiconductors which concerns on the modification 1 of embodiment. (A) A high-frequency semiconductor package according to Modification 2 of the embodiment, and is a schematic planar pattern configuration diagram of an example in which a capacitance adjustment pattern is formed on a resin substrate, (b) VII in FIG. The typical cross-section figure along a -VII line. FIG. 11 is a schematic planar pattern configuration diagram of an example of a high-frequency semiconductor package according to Modification 3 of the embodiment, in which a capacitance adjustment pattern is formed using a capacitive open stub. (A) A schematic planar pattern configuration diagram of an example of a package for a high-frequency semiconductor according to Modification 4 of the embodiment, in which a plurality of capacitance adjustment patterns are arranged in one row on both sides of the stripline 19a, (b) FIG. 16 is a schematic planar pattern configuration diagram showing an example in which a plurality of capacitance adjustment patterns are arranged in two rows on both sides of a strip line 19a in a high-frequency semiconductor package according to Modification 5 of the embodiment. The typical plane pattern block diagram of the package for high frequency semiconductors which concerns on a comparative example. FIG. 21 is a schematic sectional view taken along line VIII-VIII in FIG. 20. The typical plane pattern block diagram of the package for high frequency semiconductors concerning the comparative example mounted on the package base board. FIG. 23 is a schematic sectional view taken along line IX-IX in FIG. 22. (A) the circuit diagram consisting of the on-board capacity adjustment component C _o1 for inductance component L _i and cancel it the input side lead 21a of the high-frequency semiconductor package of the comparative example mounted on the package base board, ( b) A circuit configuration diagram including an inductance component L _O of the output-side lead 21b of the high-frequency semiconductor package according to the comparative example and an on-board capacitance adjusting component C _o2 for canceling it.

  Next, embodiments will be described with reference to the drawings. In the following, the same elements are denoted by the same reference numerals to avoid duplication of explanation and to simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and the embodiment does not specify the arrangement of each component as described below. This embodiment can be modified in various ways within the scope of the claims.

[Embodiment]
(High frequency semiconductor package structure)
FIG. 1 is a schematic bird's-eye view structure of a high-frequency semiconductor package according to an embodiment, in which a metal cap 10 is represented as shown in FIG. 1A, and a metal seal ring 14a is as shown in FIG. The metal wall 16 is represented as shown in FIG. Further, the conductor base plate 200, the feedthrough lower layer portion 20, the feedthrough upper layer portion 22, the strip lines 19a and 19b disposed on the feedthrough lower layer portion 20, and the capacity adjustment pattern 41 • disposed on the feedthrough lower layer portion 20 A schematic configuration of 42, 43, 44, 51, 52, 53, and 54 is expressed as shown in FIG.

A schematic planar pattern configuration of the high-frequency semiconductor package 1 according to the embodiment is expressed as shown in FIG. A circuit configuration including an inductance component L _i of the input-side lead 21a and a package-side capacitance adjusting component C _i1 for canceling the inductance component L _i is expressed as shown in FIG. 1B, and the inductance component of the output-side lead 21b. The circuit configuration of L _i and the package-side capacitance adjustment component C _i2 for canceling it is expressed as shown in FIG.

  A schematic plane pattern configuration of the high-frequency semiconductor package 1 according to the embodiment mounted on the package base board 70 is expressed as shown in FIG. 3, and a schematic cross-sectional structure taken along line VV in FIG. , As shown in FIG.

  When the high-frequency semiconductor package 1 is mounted, an unnecessary inductance component is generated under the leads 21a and 21b because of the gap represented by the gap width ΔW. In order to cancel this inductance component, it is effective to add capacitance to both sides of the inductance. In the high frequency semiconductor package 1 according to the embodiment, a capacitance adjusting pattern is provided on the high frequency semiconductor package 1 side. The user cancels the capacitance adjustment pattern on the high-frequency semiconductor package 1 side by connecting the island-shaped pattern on the board side to add a capacitance component, and adding the inductance components of the leads 21a and 21b to both sides of the inductance. Can do.

The inductance component L _i of the input-side lead 21a of the high-frequency semiconductor package 1 according to the embodiment mounted on the package base board 70, the package-side capacitance adjustment component C _i1 for canceling it, and the on-board capacitance adjustment component C _The π-type circuit configuration composed of _o1 is expressed as shown in FIG. 5A, and includes an inductance component L _O of the output-side lead 21b, a package-side capacitance adjusting component C _i2 for canceling it, and an on-board capacitance adjusting component. A π-type circuit configuration composed of C _o2 is expressed as shown in FIG.

  Moreover, it is typical sectional structure of the package 1 for high frequency semiconductors which concerns on embodiment, Comprising: Typical sectional structure which follows the II line | wire of Fig.2 (a) is represented as shown in FIG. A schematic cross-sectional structure taken along line II-II in (a) is represented as shown in FIG. 7, and a schematic cross-sectional structure taken along line III-III in FIG. 2 (a) is represented as shown in FIG. A schematic cross-sectional structure taken along the line IV-IV in FIG. 2A is expressed as shown in FIG.

  As shown in FIGS. 1 to 9, the high-frequency semiconductor package 1 according to the embodiment is disposed on the conductor base plate 200, the semiconductor device 24 disposed on the conductor base plate 200, and the conductor base plate 200. A metal wall 16 including the semiconductor device 24; a through hole 34 provided in an input / output part of the metal wall 16; a feedthrough lower layer part 20 fitted in the through hole 34 and disposed on the conductor base plate 200; A feedthrough upper layer portion 22 fitted into the through hole 34 and disposed on the feedthrough lower layer portion 20; strip lines 19a and 19b disposed between the feedthrough lower layer portion 20 and the feedthrough upper layer portion 22; Leads 21a and 21b arranged on the lines 19a and 19b, and feeds outside the metal wall 16 And a capacitance adjustment pattern 41, 42, 43, 44, 51, 52, 53, 54 disposed adjacent to the stripline 19a, 19b on the over lower section 20.

  The capacity adjustment patterns 41, 42, 43, 44, 51, 52, 53, 54 are arranged on both sides of the strip lines 19 a, 19 b on the feedthrough lower layer 20 outside the metal wall 16.

  Further, the capacity adjustment patterns 41, 42, 43, 44, 51, 52, 53, 54 and the strip lines 19a, 19b are arranged in a plurality of capacity adjustment patterns 41, 42, 43, 44, 51, 52, 53. 54, capacitance adjusting patterns 41, 42, 43, 44, 51, 52, 53, 54 arranged in proximity to the wires 21a, 21b to bonding wires 41a, 42a, 43a, 44a, 51b, 52b・ Connected at 53b and 54b.

  As shown in FIGS. 3 to 4, the high-frequency semiconductor package 1 according to the embodiment includes a package base board 70 on which the high-frequency semiconductor package 1 is mounted, and disposed on the package base board 70, and leads 21 a and 21 b. The on-board wiring patterns 80a and 80b to be connected and the on-board capacity adjustment patterns 61, 62, 63, 64, 71, 72, 73, and 74 disposed adjacent to the on-board wiring patterns 80a and 80b are provided. . Here, the on-board wiring patterns 80a and 80b and the on-board capacity adjustment patterns 61, 62, 63, 64, 71, 72, 73, and 74 are made of metal foils 61a, 62a, 63a, 64a, 71b, 72b, 73b, and so on. Connected at 74b.

  In FIG. 4, the structure in which the conductor base plate 200 is embedded in the package base board 70 is shown. The reason for this structure is that the height of the leads 21a and 21b is higher than the thickness of the wiring boards 60a and 60b on the package base board 70 on the mounting side, so that the package base board 70 on the mounting side is dug, This is to match the height. The leads 21a and 21b are connected to on-board wiring patterns 80a and 80b disposed on the wiring boards 60a and 60b. 6 to 9, the package base board 70 is not shown.

According to the present embodiment, capacitance components C ₀₁ , C _i1 , C _02, and C _i2 for canceling the inductance components L _i and L _o of the leads 21a and 21b are connected to both ends of the leads 21a and 21b, that is, the package. It can be provided on both the base board 70 and the high-frequency semiconductor package 1.

The inductances L _i and L _o of the leads 21a and 21b are canceled by providing capacitance components C _i1 and C _i2 on the package base board 70 on the user side, but can also be adjusted to the high frequency semiconductor package 1 side. By providing the capacitive components C ₀₁ and C ₀₂ , the frequency band can be expanded.

  In addition, as shown in FIGS. 1 to 9, the high-frequency semiconductor package 1 according to the embodiment includes an input circuit board 26 disposed adjacent to the semiconductor device 24 on the conductor base plate 200 surrounded by the metal wall 16. And an output circuit board 28, an input matching circuit 17 disposed on the input circuit board 26 and connected to the strip line 19 a via the bonding wire 11, and an output circuit board 28 disposed on the output circuit board 28 via the bonding wire 15. The output matching circuit 18 connected to the strip line 19b and the bonding wires 12 and 14 for connecting the semiconductor device 24 to the input matching circuit 17 and the output matching circuit 18 may be provided.

  Moreover, as shown in FIGS. 1-9, the high frequency semiconductor package 1 which concerns on embodiment has the metal seal ring 14a arrange | positioned on the metal wall 16, and the metal cap 10 arrange | positioned on the metal seal ring 14a. And may be provided.

  The conductor base plate 200 of the high-frequency semiconductor package 1 according to the embodiment is formed of a conductive metal such as molybdenum or copper molybdenum alloy, for example. Furthermore, a plated conductor such as Au, Ni, Ag, Ag—Pt alloy, or Ag—Pd alloy may be formed on the surface of the conductor base plate 200.

  The metal wall 16 is formed of a conductive metal such as aluminum, molybdenum, or copper molybdenum alloy.

  A solder metal layer (not shown) for soldering is formed on the upper surface of the metal wall 16 via a metal seal ring 14a. The solder metal layer can be formed from, for example, a gold germanium alloy, a gold tin alloy, or the like.

  In the high-frequency semiconductor package 1 according to the embodiment, the metal wall 16 is disposed on the conductor base plate 200 via an insulating or conductive adhesive. The insulating adhesive can be formed from, for example, an epoxy resin or glass, and the conductive adhesive can be formed from, for example, a gold germanium alloy or a gold-tin alloy.

  As shown in FIG. 1, the metal cap 10 has a flat plate shape. The metal cap 10 is formed of, for example, a conductive metal such as aluminum, molybdenum, or copper molybdenum alloy.

Further, the feedthrough lower layer portion 20 and the feedthrough upper layer portion 22 may be formed of ceramic, for example. The ceramic material can be formed from, for example, alumina (Al ₂ O ₃ ), aluminum nitride (AlN), beryllium oxide (BeO), or the like.

  Further, the thickness W2 of the feedthrough upper layer portion 22 may be formed thicker than the thickness W1 of the metal wall 16. That is, in the convex feedthrough 25 including the feedthrough lower layer portion 20 and the feedthrough upper layer portion 22 disposed on the feedthrough lower layer portion 20, the thickness W2 of the feedthrough upper layer portion 22 is set to be greater than the thickness W1 of the metal wall 16. By forming the thicker, the stress concentration point and the stress generation source (metal wall 16) at the overlapping edge of the feedthrough upper layer portion 22 and the feedthrough lower layer portion 20 can be separated, and the generated stress is reduced. This is because the occurrence of cracks at the stress concentration point can also be suppressed.

(Semiconductor element structure)
An enlarged view of a schematic planar pattern configuration of the semiconductor device 24 mounted on the high-frequency semiconductor package 1 according to the embodiment is expressed as shown in FIG. 10A, and an enlarged view of a portion J in FIG. The figure is represented as shown in FIG. Moreover, it is the structural examples 1-4 of the semiconductor device 24 mounted in the package for high frequency semiconductors which concerns on embodiment, Comprising: The typical cross-section structural examples 1-4 along the VI-VI line of FIG. They are represented as shown in FIGS.

  In the semiconductor device 24 mounted on the high-frequency semiconductor package 1 according to the embodiment, the plurality of FET cells FET1 to FET10 include a semi-insulating substrate 110 and a semi-insulating substrate 110, as shown in FIGS. A gate finger electrode 124 having a plurality of fingers, a source finger electrode 120 and a drain finger electrode 122, and a first surface of the semi-insulating substrate 110. , G10, a plurality of source terminal electrodes S11, S12, S21, S22,..., S101, S102, and a plurality of gate terminal electrodes G1, G2,. Drain terminal electrodes D1, D2,..., D1 VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102, and the first surface of the semi-insulating substrate 110, which are arranged below the source terminal electrodes S11, S12, S21, S22,. Are connected to the source terminal electrodes S11, S12, S21, S22,..., S101, S102 via the VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102. And a ground electrode (not shown).

  The bonding wire 12 is connected to the gate terminal electrodes G1, G2,..., G10, the bonding wire 14 is connected to the drain terminal electrodes D1, D2,..., D10, and the source terminal electrodes S11, S12, S21, S22. ,..., S101, S102, VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 are formed on the inner walls of the VIA holes SC11, SC12, SC21, SC22,. The source terminal electrodes S11, S12, S21, S22,..., S101, S102 are formed on the barrier metal layer (not shown) and the filling metal layer (not shown) that is formed on the barrier metal layer and fills the VIA hole. It is connected to a ground electrode (not shown).

  The semi-insulating substrate 110 is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or One of the diamond substrates.

(Structural example 1)
The configuration example 1 of the FET cell of the semiconductor device 24 mounted on the high-frequency semiconductor package 1 according to the embodiment is disposed on the semi-insulating substrate 110 and the semi-insulating substrate 110 as shown in FIG. Nitride-based compound semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride-based compound semiconductor layer 112, and aluminum gallium nitride layer A source finger electrode (S) 120, a gate finger electrode (G) 124, and a drain finger electrode (D) 122 disposed on (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. . A two-dimensional electron gas (2DEG) layer is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. 116 is formed. In the configuration example 1 shown in FIG. 11, a high electron mobility transistor (HEMT) is shown.

(Structural example 2)
A configuration example 2 of the FET cell of the semiconductor device 24 mounted on the high-frequency semiconductor package 1 according to the embodiment is arranged on the semi-insulating substrate 110 and the semi-insulating substrate 110 as shown in FIG. Nitride-based compound semiconductor layer 112, source region 126 and drain region 128 disposed on nitride-based compound semiconductor layer 112, source finger electrode (S) 120 disposed on source region 126, nitride-based compound A gate finger electrode (G) 124 disposed on the semiconductor layer 112 and a drain finger electrode (D) 122 disposed on the drain region 128 are provided. A Schottky contact is formed at the interface between the nitride-based compound semiconductor layer 112 and the gate finger electrode (G) 124. In the configuration example 2 shown in FIG. 12, a metal-semiconductor field effect transistor (MESFET) is shown.

(Structural example 3)
The configuration example 3 of the FET cell of the semiconductor device 24 mounted on the high-frequency semiconductor package 1 according to the embodiment is disposed on the semi-insulating substrate 110 and the semi-insulating substrate 110 as shown in FIG. Nitride-based compound semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride-based compound semiconductor layer 112, and aluminum gallium nitride layer A source finger electrode (S) 120 and a drain finger electrode (D) 122 disposed on (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 and an aluminum gallium nitride layer (Al _x Ga _{1 -x} N) (0.1 ≦ x ≦ 1) 118 and a gate finger electrode (G) 124 disposed in a recess portion. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In the configuration example 3 illustrated in FIG. 13, the HEMT is illustrated.

(Structural example 4)
The configuration example 4 of the FET cell of the semiconductor device 24 mounted on the high-frequency semiconductor package 1 according to the embodiment is arranged on the semi-insulating substrate 110 and the semi-insulating substrate 110 as shown in FIG. Nitride-based compound semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride-based compound semiconductor layer 112, and aluminum gallium nitride layer A source finger electrode (S) 120 and a drain finger electrode (D) 122 disposed on (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 and an aluminum gallium nitride layer (Al _x Ga _{1 -x} N) (0.1 ≦ x ≦ 1) 118 and a gate finger electrode 124 disposed in a two-stage recess portion. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In the configuration example 4 illustrated in FIG. 14, the HEMT is illustrated.

  Moreover, in the above configuration examples 1 to 4, the nitride-based compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region. Here, the active region refers to the 2DEG layer 116 immediately below the source finger electrode 120, the gate finger electrode 124, and the drain finger electrode 122, between the source finger electrode 120 and the gate finger electrode 124, and between the drain finger electrode 122 and the gate finger electrode 124. 2 DEG layer 116.

As another method for forming the element isolation region, the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a part of the nitride-based compound semiconductor layer 112 in the depth direction are used. It can also be formed by ion implantation. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. The dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer (not shown) is formed on the element isolation region and the device surface. As this insulating layer, for example, a nitride film, an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), an oxynitride film (SiON) or the like deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method is formed. be able to.

  The source finger electrode 120 and the drain finger electrode 122 are made of, for example, Ti / Al. The gate finger electrode 124 can be formed of, for example, Ni / Au.

  In the semiconductor device 24 mounted on the high-frequency semiconductor package 1 according to the embodiment, the longitudinal pattern lengths of the gate finger electrode 124, the source finger electrode 120, and the drain finger electrode 122 are microwaves / millimeter waves / submillimeters. As the wave and operating frequency increase, it is set shorter. For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  Further, the width of the source finger electrode 120 is, for example, about 40 μm, and the width of the source terminal electrodes S11, S12, S21, S22,..., S101, S102 is, for example, about 100 μm. Further, the formation width of the VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 is, for example, about 10 μm to 40 μm.

  A schematic planar pattern configuration of another semiconductor device 24 mounted on the high-frequency semiconductor package 1 according to the embodiment is arranged on a semi-insulating substrate 110 and has a plurality of fingers, as shown in FIG. Gate finger electrode 124, source finger electrode 120, drain finger electrode 122, and gate terminal electrode G disposed on semi-insulating substrate 110 and formed by bundling a plurality of fingers for each of gate finger electrode 124 and drain finger electrode 122 And a drain terminal electrode D and a source terminal electrode S disposed on the semi-insulating substrate 110 and having a plurality of fingers of the source finger electrode 120 connected by overlay contacts.

(Modification 1)
A schematic planar pattern configuration of the high-frequency semiconductor package 1 according to the first modification of the embodiment is expressed as shown in FIG.

  The high-frequency semiconductor package 1 according to the first modification of the embodiment includes capacitance adjusting patterns 41, 42, 43, 44, 45, 46, and the like that are disposed outside the metal wall 16 and adjacent to the strip lines 19 a, 19 b. 47, 48, 51, 52, 53, 54, 55, 56, 57, 58.

  Capacity adjustment patterns 41, 42, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54, 55, 56, 57, and 58 are formed on the feedthrough lower layer 20 on the outside of the metal wall 16. The strip lines 19a and 19b are arranged on both sides.

  Further, the capacity adjustment patterns 41, 42, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54, 55, 56, 57, 58 and the strip lines 19a, 19b are connected by bonding wires. The Other configurations are the same as those of the embodiment.

(Modification 2)
FIG. 17A shows a schematic planar pattern configuration of the example of the high-frequency semiconductor package according to the second modification of the embodiment in which the capacitance adjustment patterns 41 and 43 are formed on the resin substrates 40a and 40b. A schematic cross-sectional structure taken along line VII-VII in FIG. 17A is expressed as shown in FIG. In the example of FIGS. 17A and 17B, an example in which a pair of capacitance adjustment patterns 41 and 43 are formed on the resin substrates 40a and 40b is shown, but a plurality of pairs may be formed. .

  The high-frequency semiconductor package according to the second modification of the embodiment includes resin substrates 40a and 40b disposed on both sides of the strip line 19a, and the capacity adjustment patterns 41 and 43 are disposed on the resin substrates 40a and 40b. ing. In the example of FIGS. 17A and 17B, an example of the input-side strip line 19a is shown, but the output-side strip line 19b can be similarly configured. Other configurations are the same as those of the embodiment.

(Modification 3)
A schematic planar pattern configuration of the example of the high-frequency semiconductor package according to the third modification of the embodiment in which the capacitance adjustment pattern is formed using the capacitive open stubs 82a and 82b is shown in FIG. Is done.

  In the high-frequency semiconductor package according to the third modification of the embodiment, the capacitance adjustment pattern may be formed by capacitive open stubs 82a and 82b connected to the strip line 19a. In the example of FIG. 18, an example of the strip line 19a on the input side is shown, but the strip line 19b on the output side can be similarly configured. Other configurations are the same as those of the embodiment.

(Modification 4)
In the high frequency semiconductor package according to the fourth modification of the embodiment, a plurality of capacitance adjustment patterns 41 ₁ , 41 ₂ , 41 ₃ ... 43 ₁ , 43 ₂ , 43 ₃ . A schematic planar pattern configuration of an example arranged in a row is expressed as shown in FIG.

As shown in FIG. 19A, a plurality of capacitance adjustment patterns 41 ₁ , 41 ₂ , 41 ₃ ... 43 ₁ , 43 ₂ , 43 ₃ ,. May be. In the example of FIG. 19 (a), an example of the strip line 19a on the input side is shown, but the strip line 19b on the output side can be similarly configured. Other configurations are the same as those of the embodiment.

(Modification 5)
A high-frequency semiconductor package according to a fifth modification of the embodiment, the capacitance adjustment pattern 41 _1, 41 _2, 41 ₃ ..., 43 _1, 43 _2, 43 ₃ ... 45 _1, 45 _2, 45 ₃ ..., A schematic plane pattern configuration of an example in which a plurality of 47 ₁ , 47 ₂ , 47 _3, ... Are arranged in two rows on both sides of the strip line 19a is expressed as shown in FIG.

Figure 19 (b), the capacitance adjustment pattern 41 _1, 41 _2, 41 ₃ ..., 43 _1, 43 _2, 43 ₃ ... 45 _1, 45 _2, 45 ₃ ..., 47 _1, 47 _2, 47 ₃ may be arranged in a plurality of rows in an island shape. In the example of FIG. 19B, an example of the strip line 19a on the input side is shown, but the strip line 19b on the output side can be similarly configured. Other configurations are the same as those of the embodiment.

(Comparative example)
A schematic planar pattern configuration of the high-frequency semiconductor package 1a according to the comparative example is expressed as shown in FIG. 20, and a schematic cross-sectional structure taken along line VIII-VIII in FIG. 20 is expressed as shown in FIG. . Furthermore, a schematic planar pattern configuration of the high-frequency semiconductor package 1a according to the comparative example mounted on the package base board 70 is expressed as shown in FIG. 22, and a schematic cross-sectional structure taken along line IX-IX in FIG. Is expressed as shown in FIG.

The circuit configuration comprising the inductance component L _i of the input side lead 21a of the high frequency semiconductor package 1a according to the comparative example mounted on the package base board 70 and the on-board capacitance adjustment component C _o1 for canceling it is as follows. 24A, the circuit configuration including the inductance component L _O of the output-side lead 21b of the high-frequency semiconductor package 1a according to the comparative example and the on-board capacitance adjusting component _{Co 2} for canceling the inductance component L _O is as follows. This is expressed as shown in FIG.

  As shown in FIGS. 22 to 23, the high-frequency semiconductor package 1a according to the comparative example is disposed on the package base board 70 on which the high-frequency semiconductor package 1a is mounted and connected to the leads 21a and 21b. Board on-board wiring patterns 80a and 80b, and on-board capacity adjustment patterns 61, 62, 63, 64, 71, 72, 73 and 74 arranged adjacent to the on-board wiring patterns 80a and 80b. Here, the on-board wiring patterns 80a and 80b and the on-board capacity adjustment patterns 61, 62, 63, 64, 71, 72, 73, and 74 are connected by bonding wires.

The high-frequency semiconductor package 1a according to the comparative example does not have a capacitance component for canceling the inductance components L _i and L _O of the leads 21a and 21b outside the metal wall 16. Therefore, the capacitance components C _o1 and C _o2 for canceling the lead inductance components L _i and L _O are formed only by the on-board capacitance adjustment patterns 61, 62, 63, 64, 71, 72, 73, and 74. Is done.

  According to the present embodiment, a capacitance component for canceling the inductance component of the lead can be provided at both ends of the lead, that is, both the board and the high-frequency semiconductor package.

  The inductance of the lead portion is canceled by providing a capacitive component on the board on the user side, but according to the present embodiment, the frequency component can be adjusted by providing the adjustable capacitive component also on the high frequency semiconductor package side. Bandwidth can be expanded.

  According to the present embodiment, it is possible to provide a high-frequency semiconductor package in which input / output impedance can be externally adjusted.

[Other embodiments]
Although this embodiment has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  The semiconductor device mounted on the high-frequency semiconductor package according to the embodiment is not limited to the FET and the HEMT, but is also an LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor) or a heterojunction bipolar transistor (HBT). Needless to say, an amplifying element such as a junction bipolar transistor (MEMS) or a micro electro mechanical systems (MEMS) element can also be applied.

  As described above, various embodiments that are not described herein are included.

DESCRIPTION OF SYMBOLS 1 ... High frequency semiconductor package 10 ... Metal cap 11, 12, 14, 15, 41a, 42a, 43a, 44a, 51b, 52b, 53b, 54b ... Bonding wire 14a ... Metal seal ring 16 ... Metal wall (package outer wall)
DESCRIPTION OF SYMBOLS 17 ... Input matching circuit 18 ... Output matching circuit 19a, 19b ... Strip line 20 ... Feed through lower layer part 21a ... Input side lead 21b ... Output side lead 22 ... Feed through upper layer part 24 ... Semiconductor device 25 ... Convex feed through 26 ... Input circuit board 28 ... Output circuit board 34 ... Through holes 40a, 40b ... Resin boards 41, 42, 43, 44, 51, 52, 53, 54, 41 _{1 to} 41 ₃ , 43 ₁ to 43 ₃ , 45 _{1 to} 45 ₃ , 47 _{1 to} 47 ₃ ... capacity adjustment patterns 50a, 50b ... solder layers 60a, 60b ... wiring boards 61, 62, 63, 64, 71, 72, 73, 74 ... on-board capacity adjustment patterns 61a, 62a, ... 63a, 64a, 71b, 72b, 73b, 74b ... Metal foil 70 ... Package base board 80a, 80b ... On-board wiring pattern 82a, 8 b ... capacitive open stub 110 ... semi-insulating substrate 112 ... nitride compound semiconductor layer (GaN epitaxial layer)
116: Two-dimensional electron gas (2DEG) layer 118: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
120 ... Source finger electrode 122 ... Drain finger electrode 124 ... Gate finger electrode 126 ... Source region 128 ... Drain region 200 ... Conductor base plates G, G1, G2, ..., G10 ... Gate terminal electrodes S, S11, S12, ..., S101, S102 ... source terminal electrode D, D1, D2, ..., D10 ... drain terminal electrode SC11, SC12, ..., SC91, SC92, SC101, SC102 ... VIA holes [Delta] W ... gap width L _i ... inductance component L _o of the input-side lead 21a ... Inductance components C _i1 and C _{i2 of} output side lead 21b ... Package side capacitance adjustment components C _o1 and C _o2 ... Board capacitance adjustment components

Claims (14)

A conductor base plate;
A semiconductor device disposed on the conductor base plate;
A metal wall disposed on the conductor base plate and containing the semiconductor device inside;
A through hole provided in the input / output part of the metal wall;
A feedthrough lower layer portion fitted in the through hole and disposed on the conductor base plate;
A feedthrough upper layer part fitted into the through-hole and disposed on the feedthrough lower layer part;
A stripline disposed between the feedthrough lower layer and the feedthrough upper layer,
A lead disposed on the stripline;
A package for high frequency semiconductor, comprising: a capacitance adjusting pattern disposed adjacent to the strip line outside the metal wall.   2. The high frequency semiconductor package according to claim 1, wherein the capacitance adjusting pattern is disposed on both sides of the stripline on the feedthrough lower layer outside the metal wall. A resin substrate disposed on both sides of the strip line;
The high-frequency semiconductor package according to claim 1, wherein the capacitance adjustment pattern is disposed on the resin substrate.   4. The high-frequency semiconductor package according to claim 2, wherein a plurality of the capacitance adjustment patterns are arranged in a row in an island shape.   4. The high-frequency semiconductor package according to claim 2, wherein a plurality of capacitance adjusting patterns are arranged in a plurality of rows in an island shape.   The high-frequency semiconductor package according to claim 1, wherein the capacitance adjusting pattern and the strip line are connected by a bonding wire.   The capacitance adjusting pattern and the strip line are connected by a bonding wire from a plurality of the capacitance adjusting patterns arranged in proximity to the leads. The package for high-frequency semiconductors according to 4 or 5.   The high frequency semiconductor package according to claim 1, wherein the capacitance adjustment pattern is a capacitive open stub connected to the strip line. A package base board on which the high-frequency semiconductor package is mounted;
An on-board wiring pattern disposed on the package base board and connected to the leads;
The high-frequency semiconductor package according to claim 1, further comprising: an on-board capacitance adjusting pattern disposed adjacent to the on-board wiring pattern. An input circuit board and an output circuit board disposed adjacent to the semiconductor device on the conductor base plate surrounded by the metal wall;
An input matching circuit disposed on the input circuit board and connected to the stripline;
An output matching circuit disposed on the output circuit board and connected to the stripline;
The high-frequency semiconductor package according to claim 2, further comprising: a bonding wire that connects the semiconductor device to the input matching circuit and the output matching circuit. A metal seal ring disposed on the metal wall;
The high-frequency semiconductor package according to claim 10, further comprising: a metal cap disposed on the metal seal ring. The semiconductor device includes:
A semi-insulating substrate;
A gate finger electrode, a source finger electrode and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers;
A plurality of gate terminal electrodes arranged on the first surface of the semi-insulating substrate and formed by bundling a plurality of fingers for each of the gate finger electrode, the source finger electrode and the drain finger electrode; A drain terminal electrode;
A VIA hole disposed under the source terminal electrode;
3. A ground electrode disposed on a second surface opposite to the first surface of the semi-insulating substrate and connected to the source terminal electrode via the VIA hole. The package for high frequency semiconductors described. The semiconductor device includes:
A semi-insulating substrate;
A gate finger electrode, a source finger electrode and a drain finger electrode disposed on the semi-insulating substrate, each having a plurality of fingers;
A gate terminal electrode and a drain terminal electrode which are disposed on the semi-insulating substrate and formed by bundling a plurality of fingers for each of the gate finger electrode and the drain finger electrode;
The high-frequency semiconductor package according to claim 2, further comprising: a source terminal electrode disposed on the semi-insulating substrate and having a plurality of fingers of the source finger electrode connected by overlay contacts.   The semi-insulating substrate is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or 14. The high frequency semiconductor package according to claim 12, wherein the package is a diamond substrate.