JPH07130762A - Multifinger-type field effect transistor - Google Patents
Multifinger-type field effect transistorInfo
- Publication number
- JPH07130762A JPH07130762A JP5271095A JP27109593A JPH07130762A JP H07130762 A JPH07130762 A JP H07130762A JP 5271095 A JP5271095 A JP 5271095A JP 27109593 A JP27109593 A JP 27109593A JP H07130762 A JPH07130762 A JP H07130762A
- Authority
- JP
- Japan
- Prior art keywords
- electrode finger
- source electrode
- finger portion
- source
- parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はマルチフィンガー型電界
効果トランジスタ(以下マルチフィンガーFETと記
す)に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-finger type field effect transistor (hereinafter referred to as multi-finger FET).
【0002】[0002]
【従来の技術】従来のマルチフィンガーFETは、図3
に示すように、半絶縁性GaAs基板上に形成された活
性層上に櫛の歯状に配置されたゲート電極フィンガー部
2およびゲート電極フィンガー部2を挟んで対向させた
ドレイン電極フィンガー部3およびソース電極フィンガ
ー部4と、これらにそれぞれ接続したゲート電極引出部
2a,ドレイン電極引出部3a,ソース電極引出部4a
とを有し、半絶縁性GaAs基板に設けたバイアホール
9を介してソース電極引出部4aと裏面電極とを接続し
て接地していた。2. Description of the Related Art A conventional multi-finger FET is shown in FIG.
As shown in FIG. 2, a gate electrode finger portion 2 arranged in a comb-teeth shape on an active layer formed on a semi-insulating GaAs substrate, and a drain electrode finger portion 3 facing each other with the gate electrode finger portion 2 interposed therebetween. Source electrode finger portions 4 and gate electrode lead-out portions 2a, drain electrode lead-out portions 3a, source electrode lead-out portions 4a respectively connected to these.
And the source electrode lead-out portion 4a and the back surface electrode were connected to each other through the via hole 9 provided in the semi-insulating GaAs substrate and grounded.
【0003】マイクロ波帯,ミリ波帯のFETは、フィ
ンガー長が長くなると、ゲート電極フィンガーでの位相
ずれによる高周波特性の劣化や、チャネル温度の不均一
性の増大、活性層の材料的プロセス的不均一性の増大に
よる利得の低下等の問題が起こるので、ゲート幅を大き
くしたい場合には、マルチフィンガー構造にすることが
一般的に行われている。In the microwave band and millimeter wave band FETs, when the finger length becomes long, the high frequency characteristics are deteriorated due to the phase shift at the gate electrode fingers, the non-uniformity of the channel temperature is increased, and the material of the active layer is processed. Since problems such as a decrease in gain due to an increase in non-uniformity occur, a multi-finger structure is generally used to increase the gate width.
【0004】通常増幅器などの回路を構成する場合に
は、入力インピーダンスが高く、高利得が得られるソー
ス接地回路を使用する場合が多いが、ソースインダクタ
ンスが大きいと、利得が低下することが知られている。Usually, when a circuit such as an amplifier is constructed, a grounded source circuit which has a high input impedance and a high gain is often used, but it is known that the gain is lowered when the source inductance is large. ing.
【0005】[0005]
【発明が解決しようとする課題】この従来のマルチフィ
ンガーFETは、ソース電極フィンガー部の先端には何
も接続されず開放となっているので、ソース電極フィン
ガー部の先端から接地端までの経路が長くなりこの区間
のインダクタンスが低減されないという問題があった。In this conventional multi-finger FET, since nothing is connected to the tip of the source electrode finger portion and it is open, the path from the tip of the source electrode finger portion to the ground end is There is a problem that the inductance becomes longer and the inductance in this section is not reduced.
【0006】[0006]
【課題を解決するための手段】本発明のマルチフィンガ
ーFETは、半導体基板上に櫛の歯状に配置したゲート
電極フィンガー部と、前記ゲート電極フィンガー部を挟
んで対向させ櫛の歯状に配置したドレイン電極フィンガ
ー部およびソース電極フィンガー部を有するマルチフィ
ンガー型電界効果トランジスタにおいて、前記ソース電
極フィンガー部の各先端下の前記半導体基板上に形成し
且つその上に設けた絶縁膜のスルーホールを介して前記
ソース電極フィンガー部の各先端およびソース電極引出
部のそれぞれに電気的に接続した帯状電極を備えてい
る。A multi-finger FET according to the present invention is arranged in a comb-teeth shape so as to face a gate electrode finger section arranged in a comb-teeth shape on a semiconductor substrate with the gate electrode finger section interposed therebetween. In a multi-finger type field effect transistor having a drain electrode finger portion and a source electrode finger portion, the insulating film is formed on the semiconductor substrate below each tip of the source electrode finger portion and through a through hole of an insulating film provided thereon. And a strip-shaped electrode electrically connected to each tip of the source electrode finger portion and each of the source electrode lead portions.
【0007】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0008】図1(a),(b)は本発明の一実施例を
示す半導体チップの平面図およびA−A′線断面図であ
る。1A and 1B are a plan view and a sectional view taken along the line AA 'of a semiconductor chip showing an embodiment of the present invention.
【0009】図1(a),(b)に示すように、半絶縁
性GaAs基板1に形成した活性層の表面にショットキ
ー接合を有して櫛の歯状に形成したゲート電極フィンガ
ー部2と、このゲート電極フィンガー部2を挟んで対向
させたドレイン電極フィンガー部3およびソース電極フ
ィンガー部4とを有し、ソース電極フィンガー部4の各
先端の下面の半絶縁性GaAs基板1の表面に活性層か
ら隔離され且つソース電極フィンガー部4の各先端およ
びドレイン電極フィンガー部3のそれぞれと交差する金
膜等からなる帯状電極5を形成し帯状電極5の上に形成
した絶縁膜6に設けたスルーホール7を介して帯状電極
5と各ソース電極フィンガー部4およびソース電極引出
部4aのそれぞれを接続する。なお、ドレイン電極フィ
ンガー部3に接続してゲート電極フィンガー部2および
ソース電極フィンガー部4の先端側に引出されたドレイ
ン電極引出部3aの反対側にゲート電極フィンガー部2
に接続されたゲート電極引出部2aが形成されその上に
絶縁膜を介してソース電極フィンガー部4aに接続され
たソース電極引出部4aが横断して形成され、半絶縁性
GaAs基板1の裏面には裏面電極8が形成され半絶縁
性GaAs基板1に形成されたバイアホール(図示せ
ず)を介してソース電極引出部4aに接続されている。As shown in FIGS. 1A and 1B, a gate electrode finger portion 2 having a Schottky junction on the surface of an active layer formed on a semi-insulating GaAs substrate 1 and having a comb-teeth shape. And a drain electrode finger portion 3 and a source electrode finger portion 4 which are opposed to each other with the gate electrode finger portion 2 sandwiched therebetween, and on the surface of the semi-insulating GaAs substrate 1 on the lower surface of each tip of the source electrode finger portion 4. A strip electrode 5 made of a gold film or the like, which is isolated from the active layer and intersects each tip of the source electrode finger portion 4 and each of the drain electrode finger portions 3, is formed and provided on the insulating film 6 formed on the strip electrode 5. The strip electrodes 5 are connected to the source electrode finger portions 4 and the source electrode lead portions 4a via the through holes 7. It should be noted that the gate electrode finger portion 2 is provided on the opposite side of the drain electrode lead portion 3a connected to the drain electrode finger portion 3 and led to the tip side of the gate electrode finger portion 2 and the source electrode finger portion 4.
Is formed on the back surface of the semi-insulating GaAs substrate 1 by forming a gate electrode lead-out portion 2a connected to the source electrode lead-out portion 4a connected to the source electrode finger portion 4a via an insulating film. Is connected to the source electrode lead-out portion 4a through a via hole (not shown) formed in the semi-insulating GaAs substrate 1 on which the back surface electrode 8 is formed.
【0010】図2(a),(b)は本発明の一実施例の
ソースインダクタンスを示す等価回路図および従来の電
界効果トランジスタのソースインダクタンスを示す等価
回路図である。FIGS. 2A and 2B are an equivalent circuit diagram showing the source inductance of one embodiment of the present invention and an equivalent circuit diagram showing the source inductance of a conventional field effect transistor.
【0011】図2(a)に示すように、本発明の実施例
によればA点から接地までの最短経路は、インダクタン
ス51−32を通る経路となるが、図2(b)に示すよ
うに従来例ではA点から接地までの最短経路はインダク
タンス41−21−31を通る経路となり、本発明の方
がソース電極フィンガー部のインダクタンス41を通ら
ない分短くでき、ソースインダクタンスを減少できる。
同様にB点やC点から接地までの最短経路も、本発明で
はソース電極フィンガー部を通らない分短くでき、ソー
スインダクタンスを減少できる。As shown in FIG. 2A, according to the embodiment of the present invention, the shortest path from the point A to the ground is the path passing through the inductors 51-32, but as shown in FIG. In the conventional example, the shortest path from the point A to the ground is the path passing through the inductance 41-21-31, and the present invention can be shortened because it does not pass the inductance 41 of the source electrode finger portion, and the source inductance can be reduced.
Similarly, the shortest path from the point B or C to the ground can be shortened because the source electrode finger portion is not passed in the present invention, and the source inductance can be reduced.
【0012】なお、本実施例ではドレイン電極の下の層
に設けた帯状電極によりソース電極先端部を接続してい
るが、ドレイン電極をまたぐエアブリッジ配線でも同等
の効果を得られる。In this embodiment, the tip of the source electrode is connected by the strip-shaped electrode provided in the layer below the drain electrode, but the same effect can be obtained by using the air bridge wiring extending over the drain electrode.
【0013】[0013]
【発明の効果】以上説明したように本発明は、マルチフ
ィンガーFETの全てのソース電極フィンガー部の先端
をソース電極引出部に接続することにより、ソース電極
フィンガー部の先端からソース電極引出部の接地端まで
の経路を短くすることができ、ソースインダクタンスを
30〜70%減少させることができるという効果を有す
る。As described above, according to the present invention, by connecting the tips of all the source electrode finger portions of the multi-finger FET to the source electrode lead portions, the source electrode lead portions are grounded from the tip of the source electrode finger portions. This has the effect that the path to the end can be shortened and the source inductance can be reduced by 30 to 70%.
【図1】本発明の一実施例を示す半導体チップの平面図
およびA−A′線断面図。FIG. 1 is a plan view and a cross-sectional view taken along the line AA ′ of a semiconductor chip showing an embodiment of the present invention.
【図2】本発明の一実施例のソースインダクタンスを示
す等価回路図および従来例のソースインダクタンスを示
す等価回路図。FIG. 2 is an equivalent circuit diagram showing a source inductance of one embodiment of the present invention and an equivalent circuit diagram showing a source inductance of a conventional example.
【図3】従来のマルチフィンガーFETの一例を示す平
面図。FIG. 3 is a plan view showing an example of a conventional multi-finger FET.
1 半絶縁性GaAs基板 2 ゲート電極フィンガー部 2a ゲート電極引出部 3 ドレイン電極フィンガー部 3a ドレイン電極引出部 4 ソース電極フィンガー部 4a ソース電極引出部 5 帯状電極 6 絶縁膜 7 スルーホール 8 裏面電極 9 バイアホール 1 semi-insulating GaAs substrate 2 gate electrode finger portion 2a gate electrode lead-out portion 3 drain electrode finger portion 3a drain electrode lead-out portion 4 source electrode finger portion 4a source electrode lead-out portion 5 strip electrode 6 insulating film 7 through hole 8 back surface electrode 9 via hole
Claims (1)
ト電極フィンガー部と、前記ゲート電極フィンガー部を
挟んで対向させ櫛の歯状に配置したドレイン電極フィン
ガー部およびソース電極フィンガー部を有するマルチフ
ィンガー型電界効果トランジスタにおいて、前記ソース
電極フィンガー部の各先端下の前記半導体基板上に形成
し且つその上に設けた絶縁膜のスルーホールを介して前
記ソース電極フィンガー部の各先端およびソース電極引
出部のそれぞれに電気的に接続した帯状電極を備えたこ
とを特徴とするマルチフィンガー型電界効果トランジス
タ。1. A gate electrode finger portion arranged in a comb tooth shape on a semiconductor substrate, and a drain electrode finger portion and a source electrode finger portion arranged in a comb tooth shape facing each other with the gate electrode finger portion sandwiched therebetween. In a multi-finger type field effect transistor, each tip of the source electrode finger portion and the source electrode are formed through a through hole of an insulating film formed on the semiconductor substrate below each tip of the source electrode finger portion and provided on the semiconductor substrate. A multi-finger type field effect transistor characterized in that a strip-shaped electrode electrically connected to each of the lead-out portions is provided.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5271095A JP2576773B2 (en) | 1993-10-29 | 1993-10-29 | Multi-finger field effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5271095A JP2576773B2 (en) | 1993-10-29 | 1993-10-29 | Multi-finger field effect transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07130762A true JPH07130762A (en) | 1995-05-19 |
JP2576773B2 JP2576773B2 (en) | 1997-01-29 |
Family
ID=17495289
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5271095A Expired - Fee Related JP2576773B2 (en) | 1993-10-29 | 1993-10-29 | Multi-finger field effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2576773B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0817264A2 (en) * | 1996-07-04 | 1998-01-07 | Nec Corporation | Semiconductor device |
JP2014003077A (en) * | 2012-06-15 | 2014-01-09 | Toshiba Corp | Package for high-frequency semiconductor |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101877385A (en) * | 2010-04-04 | 2010-11-03 | 兰州大学 | A kind of organic field-effect tube with meandered source laminated structure |
-
1993
- 1993-10-29 JP JP5271095A patent/JP2576773B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0817264A2 (en) * | 1996-07-04 | 1998-01-07 | Nec Corporation | Semiconductor device |
EP0817264A3 (en) * | 1996-07-04 | 1998-12-09 | Nec Corporation | Semiconductor device |
JP2014003077A (en) * | 2012-06-15 | 2014-01-09 | Toshiba Corp | Package for high-frequency semiconductor |
Also Published As
Publication number | Publication date |
---|---|
JP2576773B2 (en) | 1997-01-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960917 |
|
LAPS | Cancellation because of no payment of annual fees |