JP2504503B2 - Semiconductor element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a semiconductor device provided with a plurality of unit cells each of which is formed of a field effect transistor in which comb-shaped drain electrodes, source electrodes and gate electrodes are formed so as to mesh with each other. For the purpose of improving and preventing self-oscillation, the drain electrodes of multiple unit cells and the tips of a single gate electrode are connected by high-impedance lines.

[Industrial applications]

The present invention relates to a semiconductor device, particularly a field effect transistor for ultra high frequency.

In the ultra-high frequency band such as microwaves, GaAs, which is a kind of III-V group compound semiconductors, has been widely used because of its advantage as a high-frequency element that electron mobility is higher than that of Si. . These GaAs FETs are currently in the process of high frequency operation and high gain. Therefore, various efforts have been made in the shapes of the source, drain, and gate electrodes.

[Conventional technology]

 FIG. 3 is a diagram showing a first conventional example.

In FIG. 3, 301 is a drain electrode pad, 302 is a drain bus line, 303 is a drain electrode, 304 is a source electrode, 305 is a gate electrode pad, 306 is a gate bus line, 3
Reference numeral 07 is a gate electrode and 308 is an operation region.

The drain electrode pad 301 is for taking out the drain electrode 303 to the outside.

The drain bus line 302 is for connecting the drain electrodes 303 and the drain electrode pad 301 formed in a comb shape.

The drain electrodes 303 are formed in a comb shape and are connected to each other by a drain bus line 302.

The source electrode 304 is a drain electrode 303 and a gate electrode
307 are distributed and arranged so as to sandwich 307 therebetween.

The gate electrode pad 305 is for taking out the gate electrode 307 to the outside.

The gate bus line 306 is for connecting each gate electrode 307 formed in a comb shape and the gate electrode pad 305.

The gate electrodes 307 are formed in a comb shape and are connected to each other by a gate bus line 306.

The operating region 308 is a field effect transistor (FET) including a drain electrode 303, a source electrode 304 and a gate electrode 307.
Is an area where

 Hereinafter, the conventional example 1 shown in FIG. 3 will be described in detail.

 GaAs is used as the semiconductor substrate.

The drain electrodes 303 are formed in a comb shape and are connected to each other by a drain bus line 302. The drain bus line 302 is provided with a drain electrode pad 301, and is connected to the outside by the drain electrode pad 301.

On the other hand, the gate electrodes 307 are also formed in a comb shape and are connected to each other by a gate bus line 306. A gate electrode pad 305 is provided on the gate bus line 306, and the gate electrode pad 305 is connected to the outside.

Further, the source electrodes 304 are dispersedly arranged so as to sandwich the pair of the comb-shaped drain electrode 303 and the gate electrode 307.

With the drain electrode 303, the source electrode 304, and the gate electrode 307 described above, a field effect transistor (FET)
And an operating region 308 is formed under the drain electrode 303, the source electrode 304 and the gate electrode 307.

The drain electrode 303 and the gate electrode 307 are formed in a comb shape, and the source electrode 304 is formed so as to sandwich the pair of the drain electrode 303 and the gate electrode 307.

When the frequency to be used is relatively low, the conventional example 1 can sufficiently cope with it, but when the frequency to be used is increased to 20 GHz, the wavelength becomes 4.3 mm, which is about the same as the length of the semiconductor chip. Therefore, each FET composed of comb-shaped electrodes does not operate in the same phase. As a result, the high frequency characteristics deteriorate.

The conventional example 2 is made to prevent the deterioration of the high frequency characteristics.

 FIG. 4 is a diagram showing a second conventional example.

In FIG. 4, 401 and 402 are unit cells, 403 is a drain electrode pad, 404 is a drain bus line, 405 is a drain electrode, 406 is a source electrode, 407 is a gate electrode pad, 408 is a gate bus line, and 409 is The gate electrode 410 is the operating area.

 The unit cells 401 and 402 are FET operation units.

Each unit cell 401 and 402 is composed of the following parts.

The drain electrode pad 403 is for taking out the drain electrode 405 to the outside.

The drain bus line 404 is for connecting the drain electrodes 405 and the drain electrode pad 403 formed in a comb shape.

The drain electrodes 405 are formed in a comb shape and are connected to each other by a drain bus line 404.

The source electrode 406 is a drain electrode 405 and a gate electrode
They are distributed and arranged so that 409 is sandwiched between them.

The gate electrode pad 407 is for taking out the gate electrode 409 to the outside.

The gate bus line 408 is for connecting each gate electrode 409 formed in a comb shape and the gate electrode pad 407.

The gate electrodes 409 are formed in a comb shape and are connected to each other by a gate bus line 408.

The operation region 410 is a field effect transistor (FET) including a drain electrode 405, a source electrode 406 and a gate electrode 409.
Is an area where

 Hereinafter, the conventional example 2 shown in FIG. 4 will be described in detail.

 GaAs is used as the semiconductor substrate.

The drain electrodes 405 are formed in a comb shape and are connected to each other by a drain bus line 404. The drain bus line 404 is provided with a drain electrode pad 403, and the drain electrode pad 403 connects to the outside.

On the other hand, the gate electrodes 409 are also formed in a comb shape and are connected to each other by a gate bus line 408. A gate electrode pad 407 is provided on the gate bus line 408, and the gate electrode pad 407 is connected to the outside.

Further, source electrodes 406 are dispersedly arranged so as to sandwich a pair of comb-shaped drain electrode 405 and gate electrode 409 therebetween.

Drain electrode 405, source electrode 406 and gate electrode 409
Thereby, a field effect transistor (FET) is formed, and an operating region 410 is formed under the drain electrode 405, the source electrode 406 and the gate electrode 409.

Since this conventional example is composed of a plurality of unit cells 401 and 402 having the same FET structure, the apparent length of the FET is small with respect to the wavelength of the used frequency. The FETs that make up the cell operate in approximately the same phase. Therefore, the high frequency characteristics are improved to some extent.

Although FIG. 4 shows only two unit cells, it goes without saying that three or more unit cells may be used.

The unit cells 401 and 402 are connected to each other by a drain bus line 404 and a gate bus line 408. This is a measure to prevent self-oscillation.

By the way, there is a technique for suppressing self-oscillation by connecting wires between the same electrodes in a multi-chip FET, but this involves additional steps and difficulty for wire connection.

[Problems to be Solved by the Invention]

Also in the conventional example 2 in which the FET is disassembled into unit cells each having a drain electrode pad and a gate electrode pad in order to improve high frequency characteristics, each unit cell is connected to each other by a drain bus line and a gate bus line. Therefore, since the input waves of each unit cell are mixed through the drain bus line and the gate bus line, each unit cell cannot operate completely in phase, and there is a problem that there is a limit to improvement of high frequency characteristics. It was happening.

The inventor of the present invention has previously developed an ultra-high frequency field effect transistor which solves the above-described problems of the ultra high frequency field effect transistors shown in Conventional Example 1 and Conventional Example 2. This will be described as a prior example.

 FIG. 1 is a diagram showing a prior art example.

In FIG. 1, 101 and 102 are unit cells, 103 is a drain electrode pad, 104 is a drain bus line, 105 is a drain electrode, 106 is a source electrode, 107 is a gate electrode pad, 108 is a gate bus line, and 109 is The gate electrode, 110 is an operating region, and 111 and 112 are high impedance lines.

 The unit cells 101 and 102 are FET operation units.

Each unit cell 101 and 102 is composed of the following parts.

The drain electrode pad 103 is for taking out the drain electrode 105 to the outside.

The drain bus line 104 is for connecting the drain electrodes 105 and the drain electrode pad 103 formed in a comb shape.

The drain electrodes 105 are formed in a comb shape and are connected to each other by a drain bus line 104.

The source electrode 106 is a drain electrode 105 and a gate electrode
They are distributed with 109 in between.

The gate electrode pad 107 is for taking out the gate electrode 109 to the outside.

The gate bus line 108 is for connecting each gate electrode 109 formed in a comb shape and the gate electrode pad 107.

The gate electrodes 109 are formed in a comb shape and are connected to each other by a gate bus line 108.

The operating region 110 is a field effect transistor (FET) including a drain electrode 105, a source electrode 106 and a gate electrode 109.
Is an area where

 Hereinafter, the prior art example shown in FIG. 1 will be described in detail.

 GaAs is used as the semiconductor substrate.

The drain electrodes 105 are formed in a comb shape and are connected to each other by a drain bus line 104. The drain bus line 104 is provided with a drain electrode pad 103, and the drain electrode pad 103 is connected to the outside.

On the other hand, the gate electrodes 109 are also formed in a comb shape and are connected to each other by the gate bus line 108. A gate electrode pad 107 is provided on the gate bus line 108, and the gate electrode pad 107 is connected to the outside.

Further, the source electrodes 106 are dispersedly arranged so as to sandwich the pair of comb-shaped drain electrode 105 and gate electrode 109 therebetween.

Drain electrode 105, source electrode 106 and gate electrode 109
Thereby, a field effect transistor (FET) is formed, and an operating region 110 is formed under the drain electrode 105, the source electrode 106 and the gate electrode 109.

Further, in each of the unit cells 101 and 102, the drain bus line 104 is connected by a high impedance line 111, and the gate bus line 108 is also connected by a high impedance line 112. The width of the drain bus line 104 and the gate bus line 108 is about 15 μm, and the width of the high impedance lines 111 and 112 is, for example, 2 to 3 μm.
If the width of the high impedance lines 111 and 112 is about half or less of the width of the bus lines 104 and 108, self-oscillation can be prevented.

In FIG. 1, high impedance lines 111 and 112 are
Drain bus line 104 and gate bus line 108
Although the width of the drain bus line 104 and the gate bus line 108 is thin, the upper electrode metal may be removed if the electrode thickness of the drain bus line 104 and the gate bus line 108 is thin.

This example shows multiple unit cells 1 with the same FET structure.
Since it is composed of 01 and 102, the apparent length of the FET is small with respect to the wavelength of the frequency to be used, so that the FETs forming each unit cell 101 and 102 operate in substantially the same phase. Therefore, the high frequency characteristics are improved.

Although only two unit cells are shown in FIG. 1, it goes without saying that three or more unit cells may be used.

In the ultra high frequency field effect transistor according to the above-described example, the unit cells 101 and 102 are connected by the high impedance lines 111 and 112 between the drain bus lines 104 and the gate bus lines 108, respectively. By connecting the bus lines to each other with a high impedance line in this way, self-oscillation can be prevented.

However, since the gate electrodes connected to the gate bus line affect each other, the inconvenience that occurs in one gate electrode affects all gate electrodes. In addition, a new problem occurs that loss talk occurs between all gate electrodes connected to the gate bus line.

It is an object of the present invention to solve the above problems and provide a field effect transistor for ultra high frequency, which improves high frequency characteristics and prevents self-oscillation.

[Means for solving the problem]

The present invention relates to a semiconductor device having a plurality of unit cells each including a field effect transistor in which comb-shaped drain electrodes, source electrodes and gate electrodes are formed so as to mesh with each other. The electrodes and the tips of a single gate electrode are connected to each other by high-impedance lines. As a result, a high-frequency field-effect transistor with improved high-frequency characteristics and self-oscillation prevention is provided.

[Action]

Field effect transistor (FET) for super high frequency of the present invention
Is formed so that the comb-teeth-shaped drain electrode, source electrode, and gate electrode mesh with each other, and is divided into a plurality of unit cells that perform the FET operation by themselves. By doing this, the apparent FET with respect to the wavelength of the frequency used
Since the length of can be ignored, it is possible to operate the ultra-high frequency field effect transistor in the same phase.
The high frequency characteristics can be improved.

Further, in each unit cell constituting the ultra high frequency field effect transistor of the present invention, the drain bus lines are connected by a high impedance line, and the tips of a single gate electrode are connected by a high impedance line. By doing so, it is possible to prevent self-oscillation that occurs because each unit cell is separated. Since each unit cell is separated in terms of high frequency, it is possible to improve the high frequency characteristics even if the FET is divided into multiple unit cells.

In particular, in the ultra high frequency field effect transistor according to the present invention, since the tips of the single gate electrodes between the unit cells are connected by the high impedance line, it is the gates to which the tips are connected that directly affect each other. Only the electrodes, other gate electrodes are less likely to be affected by each other's unit cells.

That is, when the gate bus lines between the unit cells are commonly connected by the high-impedance line as in the prior example, the effect of the high-impedance line reduces the influence between the gate electrodes. However, it is impossible to eliminate the crosstalk that occurs between all the gate electrodes connected to the gate bus line. In the present invention, since a single gate electrode is connected to the gate bus line, this is not the case, and the inconvenience that occurs in one gate electrode is less likely to affect other gate electrodes. . Therefore, the crosstalk between the gate electrodes is also significantly reduced.

〔Example〕

 FIG. 2 is a diagram showing an embodiment of the present invention.

In FIG. 2, 201 and 202 are unit cells, 203 is a drain electrode pad, 204 is a drain bus line, 205 is a drain electrode, 206 is a source electrode, 207 is a gate electrode pad, 208 is a gate bus line, and 209 is The gate electrode, 210 is the operating region, and 211 and 212 are high impedance lines.

 The unit cells 201 and 202 are FET operation units.

Each unit cell 201 and 202 is composed of the following parts.

The drain electrode pad 203 is for taking out the drain electrode 205 to the outside.

The drain bus line 204 is for connecting the drain electrodes 205 and the drain electrode pad 203 formed in a comb shape.

The drain electrodes 205 are formed in a comb shape and are connected to each other by a drain bus line 204.

The source electrode 206 is a drain electrode 205 and a gate electrode
209 are arranged in a dispersed manner so as to sandwich them.

The gate electrode pad 207 is for taking out the gate electrode 209 to the outside.

The gate bus line 208 is for connecting each gate electrode 209 formed in a comb shape and the gate electrode pad 207.

The gate electrodes 209 are formed in a comb shape and are connected to each other by a gate bus line 208.

The operating region 210 is a field effect transistor (FET) including a drain electrode 205, a source electrode 206 and a gate electrode 209.
Is an area where

The embodiment of the present invention shown in FIG. 2 will be described in detail below.

 GaAs is used as the semiconductor substrate.

The drain electrodes 205 are formed in a comb shape and are connected to each other by a drain bus line 204. A drain electrode pad 203 is provided on the drain bus line 204, and the drain electrode pad 203 connects the outside.

On the other hand, the gate electrodes 209 are also formed in a comb shape, and are connected to each other by a gate bus line 208. A gate electrode pad 207 is provided on the gate bus line 208, and the gate electrode pad 207 is connected to the outside.

Further, the source electrodes 206 are dispersedly arranged so as to sandwich the pair of comb-shaped drain electrode 205 and gate electrode 209 therebetween.

Drain electrode 205, source electrode 206 and gate electrode 209
Thereby, a field effect transistor (FET) is formed, and an operating region 210 is formed under the drain electrode 205, the source electrode 206 and the gate electrode 209.

Further, in each of the unit cells 201 and 202, the drain bus line 204 is connected by the high impedance line 211, and the tips of the adjacent gate electrodes 209 are connected by the high impedance line 212.

Since this embodiment is composed of a plurality of unit cells 201 and 202 having the same FET structure, the apparent length of the FET is small with respect to the wavelength of the used frequency. FEs that make up cells 201 and 202
T operates almost in phase. Therefore, the high frequency characteristics are improved.

Although FIG. 2 shows only two unit cells, it goes without saying that the number of unit cells may be three or more.

Further, in the unit cells 201 and 202, the drain bus lines 204 are connected by the high impedance line 211, and the tips of the adjacent single gate electrodes 209 are connected by the high impedance line 212. Self-oscillation can be prevented.

In particular, a single gate electrode 209 between the unit cells 201 and 202
Since the tips are connected to each other by the high impedance line 212, only the gate electrode 209 having the tips connected directly affects each other, and the other gate electrodes are less likely to be affected by the unit cells of each other. Bus line for gate 20
Since the single gate electrode 209 is connected to 8, the inconvenience that occurs in one gate electrode is less likely to affect other gate electrodes, and the crosstalk between the gate electrodes is significantly reduced.

〔The invention's effect〕

According to the present invention, in a semiconductor device provided with a plurality of unit cells composed of field effect transistors in which comb-shaped drain electrodes, source electrodes and gate electrodes are formed so as to mesh with each other, drain electrodes between unit cells are Since the tips of the single gate electrode are connected to each other by the high impedance line, the high frequency characteristics can be improved and self-oscillation can be prevented.

Further, since the gate electrodes are connected only by the high-impedance lines at their tips, and the bus lines for gates are not interconnected, the inconvenience that occurs in one gate electrode is less likely to affect other gate electrodes. Crosstalk between gate electrodes is also significantly reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a prior art example, FIG. 2 is a diagram showing an embodiment, FIG. 3 is a diagram showing a conventional example 1, and FIG. 4 is a diagram showing a conventional example 2. In FIG. 2, 201: unit cell 202: unit cell 203: drain electrode pad 204: drain bus line 205: drain electrode 206: source electrode 207: gate electrode pad 208: gate bus line 209: gate electrode 210: operating region 211: High impedance line 212: High impedance line

Claims (1)

(57) [Claims] 1. A semiconductor device having a plurality of unit cells each comprising a field effect transistor in which comb-shaped drain electrodes, source electrodes and gate electrodes are formed so as to mesh with each other. A semiconductor device characterized in that the drain electrodes are connected to each other and the tips of a single gate electrode are connected to each other by high-impedance lines.