JP2013545963A5 - - Google Patents

Download PDF

Info

Publication number
JP2013545963A5
JP2013545963A5 JP2013522002A JP2013522002A JP2013545963A5 JP 2013545963 A5 JP2013545963 A5 JP 2013545963A5 JP 2013522002 A JP2013522002 A JP 2013522002A JP 2013522002 A JP2013522002 A JP 2013522002A JP 2013545963 A5 JP2013545963 A5 JP 2013545963A5
Authority
JP
Japan
Prior art keywords
input
output
data register
input coupled
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2013522002A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013545963A (ja
JP5832535B2 (ja
Filing date
Publication date
Priority claimed from US13/188,078 external-priority patent/US8694844B2/en
Application filed filed Critical
Priority claimed from PCT/US2011/045904 external-priority patent/WO2012016151A2/en
Publication of JP2013545963A publication Critical patent/JP2013545963A/ja
Publication of JP2013545963A5 publication Critical patent/JP2013545963A5/ja
Application granted granted Critical
Publication of JP5832535B2 publication Critical patent/JP5832535B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2013522002A 2010-07-29 2011-07-29 アット・スピード・テストアクセスポート動作の改善 Active JP5832535B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US36190610P 2010-07-29 2010-07-29
US61/361,906 2010-07-29
US40667410P 2010-10-26 2010-10-26
US61/406,674 2010-10-26
US13/188,078 2011-07-21
US13/188,078 US8694844B2 (en) 2010-07-29 2011-07-21 AT speed TAP with dual port router and command circuit
PCT/US2011/045904 WO2012016151A2 (en) 2010-07-29 2011-07-29 Improving at-speed test access port operations

Publications (3)

Publication Number Publication Date
JP2013545963A JP2013545963A (ja) 2013-12-26
JP2013545963A5 true JP2013545963A5 (https=) 2014-08-07
JP5832535B2 JP5832535B2 (ja) 2015-12-16

Family

ID=48208630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013522002A Active JP5832535B2 (ja) 2010-07-29 2011-07-29 アット・スピード・テストアクセスポート動作の改善

Country Status (2)

Country Link
JP (1) JP5832535B2 (https=)
CN (1) CN103097902B (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7385651B2 (ja) * 2018-08-31 2023-11-22 エヌビディア コーポレーション 自動車用途のための配置中にビルトイン・セルフテストを実行するためのテスト・システム
US10866283B2 (en) * 2018-11-29 2020-12-15 Nxp B.V. Test system with embedded tester

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996041205A1 (en) * 1995-06-07 1996-12-19 Samsung Electronics Co., Ltd. Method and apparatus for testing a megacell in an asic using jtag
US6094729A (en) * 1997-04-08 2000-07-25 Advanced Micro Devices, Inc. Debug interface including a compact trace record storage
US7657810B2 (en) * 2006-02-03 2010-02-02 Texas Instruments Incorporated Scan testing using scan frames with embedded commands
US7185251B2 (en) * 2002-05-29 2007-02-27 Freescale Semiconductor, Inc. Method and apparatus for affecting a portion of an integrated circuit
EP1922555B1 (en) * 2005-08-09 2014-10-08 Texas Instruments Incorporated Selectable jtag or trace access with data store and output
JP4805134B2 (ja) * 2006-12-28 2011-11-02 富士通株式会社 集積回路の内部ラッチをスキャンする方法及び装置並びに集積回路
JP2008310792A (ja) * 2007-05-11 2008-12-25 Nec Electronics Corp テスト回路
JP4891892B2 (ja) * 2007-12-27 2012-03-07 ルネサスエレクトロニクス株式会社 半導体集積回路装置とそのテスト方法
JP5167904B2 (ja) * 2008-03-28 2013-03-21 富士通株式会社 スキャン制御方法、スキャン制御回路及び装置
US8006151B2 (en) * 2008-03-28 2011-08-23 Texas Instruments Incorporated TAP and shadow port operating on rising and falling TCK
US8255749B2 (en) * 2008-07-29 2012-08-28 Texas Instruments Incorporated Ascertaining configuration by storing data signals in a topology register

Similar Documents

Publication Publication Date Title
JP2010276479A5 (ja) 半導体集積回路
GB2508533A (en) Instruction and logic to provide vector scatter-op and gather-op functionality
JP2013092517A5 (https=)
GB2508312A (en) Instruction and logic to provide vector load-op/store-op with stride functionality
JP2011058847A5 (https=)
ATE514998T1 (de) Getaktete ports
WO2013098643A3 (en) Advanced processor architecture
GB2577943A8 (en) Systems, apparatuses, and methods for blending two source operands into a single destination using a writemask
JP2016537619A5 (https=)
GB2568816A8 (en) Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
JP2013512511A5 (https=)
WO2010141223A3 (en) Conditional operation in an internal processor of a memory device
JP2015531111A5 (https=)
WO2011116116A3 (en) Logic built-in self-test programmable pattern bit mask
JP2006020329A5 (https=)
WO2019079083A3 (en) Multi-processor core device with mbist
JP2011062366A5 (https=)
JP2012200267A5 (https=)
JP2014207434A5 (https=)
US9128149B2 (en) IC scan and test circuitry with up control circuitry
JP2013545963A5 (https=)
CN103091627B (zh) 一种可配置的边界扫描寄存器链电路
WO2007067275A3 (en) Vliw acceleration system using multi-state logic
DE602007011840D1 (de) Simultaner Codeprüfer und hardware-effiziente Eingabe/Ausgabe mit hoher Geschwindigkeit mit eingebautem Selbsttest und Fehlerbeseitigungsfunktionen
WO2015085036A3 (en) Programmable macros for metal/via programmable gate array integrated circuits