JP5832535B2 - アット・スピード・テストアクセスポート動作の改善 - Google Patents

アット・スピード・テストアクセスポート動作の改善 Download PDF

Info

Publication number
JP5832535B2
JP5832535B2 JP2013522002A JP2013522002A JP5832535B2 JP 5832535 B2 JP5832535 B2 JP 5832535B2 JP 2013522002 A JP2013522002 A JP 2013522002A JP 2013522002 A JP2013522002 A JP 2013522002A JP 5832535 B2 JP5832535 B2 JP 5832535B2
Authority
JP
Japan
Prior art keywords
circuit
data register
capture
cmd
tsm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013522002A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013545963A (ja
JP2013545963A5 (https=
Inventor
ディー ウェットセル リー
ディー ウェットセル リー
Original Assignee
日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/188,078 external-priority patent/US8694844B2/en
Application filed by 日本テキサス・インスツルメンツ株式会社, テキサス インスツルメンツ インコーポレイテッド, テキサス インスツルメンツ インコーポレイテッド filed Critical 日本テキサス・インスツルメンツ株式会社
Priority claimed from PCT/US2011/045904 external-priority patent/WO2012016151A2/en
Publication of JP2013545963A publication Critical patent/JP2013545963A/ja
Publication of JP2013545963A5 publication Critical patent/JP2013545963A5/ja
Application granted granted Critical
Publication of JP5832535B2 publication Critical patent/JP5832535B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2013522002A 2010-07-29 2011-07-29 アット・スピード・テストアクセスポート動作の改善 Active JP5832535B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US36190610P 2010-07-29 2010-07-29
US61/361,906 2010-07-29
US40667410P 2010-10-26 2010-10-26
US61/406,674 2010-10-26
US13/188,078 2011-07-21
US13/188,078 US8694844B2 (en) 2010-07-29 2011-07-21 AT speed TAP with dual port router and command circuit
PCT/US2011/045904 WO2012016151A2 (en) 2010-07-29 2011-07-29 Improving at-speed test access port operations

Publications (3)

Publication Number Publication Date
JP2013545963A JP2013545963A (ja) 2013-12-26
JP2013545963A5 JP2013545963A5 (https=) 2014-08-07
JP5832535B2 true JP5832535B2 (ja) 2015-12-16

Family

ID=48208630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013522002A Active JP5832535B2 (ja) 2010-07-29 2011-07-29 アット・スピード・テストアクセスポート動作の改善

Country Status (2)

Country Link
JP (1) JP5832535B2 (https=)
CN (1) CN103097902B (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7385651B2 (ja) * 2018-08-31 2023-11-22 エヌビディア コーポレーション 自動車用途のための配置中にビルトイン・セルフテストを実行するためのテスト・システム
US10866283B2 (en) * 2018-11-29 2020-12-15 Nxp B.V. Test system with embedded tester

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996041205A1 (en) * 1995-06-07 1996-12-19 Samsung Electronics Co., Ltd. Method and apparatus for testing a megacell in an asic using jtag
US6094729A (en) * 1997-04-08 2000-07-25 Advanced Micro Devices, Inc. Debug interface including a compact trace record storage
US7657810B2 (en) * 2006-02-03 2010-02-02 Texas Instruments Incorporated Scan testing using scan frames with embedded commands
US7185251B2 (en) * 2002-05-29 2007-02-27 Freescale Semiconductor, Inc. Method and apparatus for affecting a portion of an integrated circuit
EP1922555B1 (en) * 2005-08-09 2014-10-08 Texas Instruments Incorporated Selectable jtag or trace access with data store and output
JP4805134B2 (ja) * 2006-12-28 2011-11-02 富士通株式会社 集積回路の内部ラッチをスキャンする方法及び装置並びに集積回路
JP2008310792A (ja) * 2007-05-11 2008-12-25 Nec Electronics Corp テスト回路
JP4891892B2 (ja) * 2007-12-27 2012-03-07 ルネサスエレクトロニクス株式会社 半導体集積回路装置とそのテスト方法
JP5167904B2 (ja) * 2008-03-28 2013-03-21 富士通株式会社 スキャン制御方法、スキャン制御回路及び装置
US8006151B2 (en) * 2008-03-28 2011-08-23 Texas Instruments Incorporated TAP and shadow port operating on rising and falling TCK
US8255749B2 (en) * 2008-07-29 2012-08-28 Texas Instruments Incorporated Ascertaining configuration by storing data signals in a topology register

Also Published As

Publication number Publication date
JP2013545963A (ja) 2013-12-26
CN103097902B (zh) 2015-12-09
CN103097902A (zh) 2013-05-08

Similar Documents

Publication Publication Date Title
US11808810B2 (en) AT-speed test access port operations
US12153090B2 (en) Commanded JTAG test access port operations
US7284174B2 (en) Enhanced JTAG interface
JP5832535B2 (ja) アット・スピード・テストアクセスポート動作の改善
US20230376229A1 (en) Fast and flexible ram reader and writer
Whetse Commanded Test Access Port operations
WO2012016151A2 (en) Improving at-speed test access port operations

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140619

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140619

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150616

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20150916

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151001

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20151027

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20151027

R150 Certificate of patent or registration of utility model

Ref document number: 5832535

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313117

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250