CN103097902B - 改进全速测试访问端口操作 - Google Patents

改进全速测试访问端口操作 Download PDF

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Publication number
CN103097902B
CN103097902B CN201180037146.8A CN201180037146A CN103097902B CN 103097902 B CN103097902 B CN 103097902B CN 201180037146 A CN201180037146 A CN 201180037146A CN 103097902 B CN103097902 B CN 103097902B
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output
input
data
data register
circuit
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CN201180037146.8A
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Chinese (zh)
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CN103097902A (zh
Inventor
L·D·威特赛
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Texas Instruments Inc
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Texas Instruments Inc
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Priority claimed from US13/188,078 external-priority patent/US8694844B2/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority claimed from PCT/US2011/045904 external-priority patent/WO2012016151A2/en
Publication of CN103097902A publication Critical patent/CN103097902A/zh
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  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201180037146.8A 2010-07-29 2011-07-29 改进全速测试访问端口操作 Active CN103097902B (zh)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US36190610P 2010-07-29 2010-07-29
US61/361,906 2010-07-29
US40667410P 2010-10-26 2010-10-26
US61/406,674 2010-10-26
US13/188,078 2011-07-21
US13/188,078 US8694844B2 (en) 2010-07-29 2011-07-21 AT speed TAP with dual port router and command circuit
PCT/US2011/045904 WO2012016151A2 (en) 2010-07-29 2011-07-29 Improving at-speed test access port operations

Publications (2)

Publication Number Publication Date
CN103097902A CN103097902A (zh) 2013-05-08
CN103097902B true CN103097902B (zh) 2015-12-09

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JP (1) JP5832535B2 (https=)
CN (1) CN103097902B (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7385651B2 (ja) * 2018-08-31 2023-11-22 エヌビディア コーポレーション 自動車用途のための配置中にビルトイン・セルフテストを実行するためのテスト・システム
US10866283B2 (en) * 2018-11-29 2020-12-15 Nxp B.V. Test system with embedded tester

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1187244A (zh) * 1995-06-07 1998-07-08 三星电子株式会社 用于jtag测试asic中的兆单元的方法和装置
JP2001519947A (ja) * 1997-04-08 2001-10-23 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド コンパクトなトレースレコード記憶装置を含むデバッグインターフェイス
CN1656386A (zh) * 2002-05-29 2005-08-17 飞思卡尔半导体公司 用于经由单个测试访问端口访问多个测试访问端口的方法与控制电路
JP2008164470A (ja) * 2006-12-28 2008-07-17 Fujitsu Ltd 集積回路の内部ラッチをスキャンする方法及び装置並びに集積回路
CN101471142A (zh) * 2007-12-27 2009-07-01 恩益禧电子股份有限公司 半导体集成电路器件及其测试方法
CN101545951A (zh) * 2008-03-28 2009-09-30 富士通株式会社 扫描控制方法、扫描控制电路及装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7657810B2 (en) * 2006-02-03 2010-02-02 Texas Instruments Incorporated Scan testing using scan frames with embedded commands
EP1922555B1 (en) * 2005-08-09 2014-10-08 Texas Instruments Incorporated Selectable jtag or trace access with data store and output
JP2008310792A (ja) * 2007-05-11 2008-12-25 Nec Electronics Corp テスト回路
US8006151B2 (en) * 2008-03-28 2011-08-23 Texas Instruments Incorporated TAP and shadow port operating on rising and falling TCK
US8255749B2 (en) * 2008-07-29 2012-08-28 Texas Instruments Incorporated Ascertaining configuration by storing data signals in a topology register

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1187244A (zh) * 1995-06-07 1998-07-08 三星电子株式会社 用于jtag测试asic中的兆单元的方法和装置
JP2001519947A (ja) * 1997-04-08 2001-10-23 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド コンパクトなトレースレコード記憶装置を含むデバッグインターフェイス
CN1656386A (zh) * 2002-05-29 2005-08-17 飞思卡尔半导体公司 用于经由单个测试访问端口访问多个测试访问端口的方法与控制电路
JP2008164470A (ja) * 2006-12-28 2008-07-17 Fujitsu Ltd 集積回路の内部ラッチをスキャンする方法及び装置並びに集積回路
CN101471142A (zh) * 2007-12-27 2009-07-01 恩益禧电子股份有限公司 半导体集成电路器件及其测试方法
CN101545951A (zh) * 2008-03-28 2009-09-30 富士通株式会社 扫描控制方法、扫描控制电路及装置

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JP2013545963A (ja) 2013-12-26
JP5832535B2 (ja) 2015-12-16
CN103097902A (zh) 2013-05-08

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