JP2013512511A5 - - Google Patents

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Publication number
JP2013512511A5
JP2013512511A5 JP2012541208A JP2012541208A JP2013512511A5 JP 2013512511 A5 JP2013512511 A5 JP 2013512511A5 JP 2012541208 A JP2012541208 A JP 2012541208A JP 2012541208 A JP2012541208 A JP 2012541208A JP 2013512511 A5 JP2013512511 A5 JP 2013512511A5
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JP
Japan
Prior art keywords
digital signal
generating
circuit device
signal processors
integrated circuit
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Pending
Application number
JP2012541208A
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English (en)
Japanese (ja)
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JP2013512511A (ja
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Publication date
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Priority claimed from PCT/US2010/058100 external-priority patent/WO2011066459A2/en
Publication of JP2013512511A publication Critical patent/JP2013512511A/ja
Publication of JP2013512511A5 publication Critical patent/JP2013512511A5/ja
Pending legal-status Critical Current

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JP2012541208A 2009-11-25 2010-11-24 複数メモリ特定用途向けデジタル信号プロセッサ Pending JP2013512511A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US26433409P 2009-11-25 2009-11-25
US61/264,334 2009-11-25
PCT/US2010/058100 WO2011066459A2 (en) 2009-11-25 2010-11-24 Multiple-memory application-specific digital signal processor

Publications (2)

Publication Number Publication Date
JP2013512511A JP2013512511A (ja) 2013-04-11
JP2013512511A5 true JP2013512511A5 (https=) 2014-01-16

Family

ID=44067246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012541208A Pending JP2013512511A (ja) 2009-11-25 2010-11-24 複数メモリ特定用途向けデジタル信号プロセッサ

Country Status (4)

Country Link
US (1) US9111068B2 (https=)
EP (1) EP2504767A4 (https=)
JP (1) JP2013512511A (https=)
WO (1) WO2011066459A2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013512511A (ja) 2009-11-25 2013-04-11 ハワード ユニバーシティ 複数メモリ特定用途向けデジタル信号プロセッサ
WO2012167933A1 (en) * 2011-06-08 2012-12-13 Hyperion Core Inc. Tool-level and hardware-level code optimization and respective hardware modification
CN103186501A (zh) * 2011-12-29 2013-07-03 中兴通讯股份有限公司 一种多处理器共享存储方法及系统
CN103577266B (zh) 2012-07-31 2017-06-23 国际商业机器公司 用于对现场可编程门阵列资源进行分配的方法及系统
CN104424128B (zh) * 2013-08-19 2019-12-13 上海芯豪微电子有限公司 变长指令字处理器系统和方法
EP2843616A1 (de) * 2013-08-29 2015-03-04 Sick Ag Optoelektronische Vorrichtung und Verfahren zur Aufnahme entzerrter Bilder
JP6721911B2 (ja) * 2014-02-20 2020-07-15 スティルウォーター スーパーコンピューティング，インク． アフィン従属による単一割当プログラムを実行するための実行エンジン
US10320390B1 (en) 2016-11-17 2019-06-11 X Development Llc Field programmable gate array including coupled lookup tables
US20190050263A1 (en) * 2018-03-05 2019-02-14 Intel Corporation Technologies for scheduling acceleration of functions in a pool of accelerator devices

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5550839A (en) 1993-03-12 1996-08-27 Xilinx, Inc. Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays
US5933023A (en) 1996-09-03 1999-08-03 Xilinx, Inc. FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
US6047115A (en) 1997-05-29 2000-04-04 Xilinx, Inc. Method for configuring FPGA memory planes for virtual hardware computation
US6120551A (en) 1997-09-29 2000-09-19 Xilinx, Inc. Hardwire logic device emulating an FPGA
US5991908A (en) 1997-09-29 1999-11-23 Xilinx, Inc. Boundary scan chain with dedicated programmable routing
US7373440B2 (en) 1997-12-17 2008-05-13 Src Computers, Inc. Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format
GB0105357D0 (en) 2001-03-03 2001-04-18 Marconi Comm Ltd Evolutionary programming of configurable logic devices
US7133822B1 (en) 2001-03-29 2006-11-07 Xilinx, Inc. Network based diagnostic system and method for programmable hardware
US7840777B2 (en) * 2001-05-04 2010-11-23 Ascenium Corporation Method and apparatus for directing a computational array to execute a plurality of successive computational array instructions at runtime
US7072824B2 (en) 2001-05-09 2006-07-04 Lucent Technologies Inc. Method and apparatus for emulating a processor
EP1271783B1 (en) 2001-06-29 2013-07-31 Sicronic Remote KG, LLC FPGA with a simplified interface between the program memory and the programmable logic blocks
KR100912437B1 (ko) * 2001-07-12 2009-08-14 아이피플렉스 가부시키가이샤 집적회로장치
US7302667B1 (en) 2004-04-15 2007-11-27 Altera Corporation Methods and apparatus for generating programmable device layout information
US7546572B1 (en) 2005-09-20 2009-06-09 Xilinx, Inc. Shared memory interface in a programmable logic device using partial reconfiguration
JP2013512511A (ja) 2009-11-25 2013-04-11 ハワード ユニバーシティ 複数メモリ特定用途向けデジタル信号プロセッサ

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