JP2013539086A5 - - Google Patents

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Publication number
JP2013539086A5
JP2013539086A5 JP2013515811A JP2013515811A JP2013539086A5 JP 2013539086 A5 JP2013539086 A5 JP 2013539086A5 JP 2013515811 A JP2013515811 A JP 2013515811A JP 2013515811 A JP2013515811 A JP 2013515811A JP 2013539086 A5 JP2013539086 A5 JP 2013539086A5
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JP
Japan
Prior art keywords
lane
decoding
bus
syndromes
lanes
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JP2013515811A
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English (en)
Japanese (ja)
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JP2013539086A (ja
JP5623635B2 (ja
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Priority claimed from US12/822,498 external-priority patent/US8566682B2/en
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Publication of JP2013539086A publication Critical patent/JP2013539086A/ja
Publication of JP2013539086A5 publication Critical patent/JP2013539086A5/ja
Application granted granted Critical
Publication of JP5623635B2 publication Critical patent/JP5623635B2/ja
Expired - Fee Related legal-status Critical Current
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JP2013515811A 2010-06-24 2011-06-08 バス障害を検出するための方法、システム及びコンピュータ・プログラム Expired - Fee Related JP5623635B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/822,498 US8566682B2 (en) 2010-06-24 2010-06-24 Failing bus lane detection using syndrome analysis
US12/822,498 2010-06-24
PCT/EP2011/059533 WO2011160956A1 (en) 2010-06-24 2011-06-08 Failing bus lane detection using syndrome analysis

Publications (3)

Publication Number Publication Date
JP2013539086A JP2013539086A (ja) 2013-10-17
JP2013539086A5 true JP2013539086A5 (https=) 2014-09-04
JP5623635B2 JP5623635B2 (ja) 2014-11-12

Family

ID=44588269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013515811A Expired - Fee Related JP5623635B2 (ja) 2010-06-24 2011-06-08 バス障害を検出するための方法、システム及びコンピュータ・プログラム

Country Status (5)

Country Link
US (1) US8566682B2 (https=)
EP (1) EP2537095B1 (https=)
JP (1) JP5623635B2 (https=)
CN (1) CN102893262B (https=)
WO (1) WO2011160956A1 (https=)

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US12455701B2 (en) 2021-07-27 2025-10-28 Intel Corporation Scalable access control checking for cross-address-space data movement
US12541416B2 (en) * 2021-09-23 2026-02-03 Intel Corporation Lane based normalized historical error counter view for faulty lane isolation and disambiguation of transient versus persistent errors
US12487762B2 (en) 2022-05-10 2025-12-02 Intel Corporation Flexible provisioning of coherent memory address decoders in hardware
CN115346590B (zh) * 2022-08-12 2025-09-23 腾讯科技（深圳）有限公司 一种通道修复方法及相关装置
CN118890226B (zh) * 2024-10-08 2025-01-21 杭州艾力特数字科技有限公司 一种基于数据总线的空间声场数据传输系统及方法
CN120111120B (zh) * 2025-03-07 2025-11-28 中国人民解放军网络空间部队信息工程大学 一种面向异构协议转换功能的fpga原型验证装置与方法

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