JP5623635B2 - バス障害を検出するための方法、システム及びコンピュータ・プログラム - Google Patents

バス障害を検出するための方法、システム及びコンピュータ・プログラム Download PDF

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Publication number
JP5623635B2
JP5623635B2 JP2013515811A JP2013515811A JP5623635B2 JP 5623635 B2 JP5623635 B2 JP 5623635B2 JP 2013515811 A JP2013515811 A JP 2013515811A JP 2013515811 A JP2013515811 A JP 2013515811A JP 5623635 B2 JP5623635 B2 JP 5623635B2
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Japan
Prior art keywords
lane
error
bus
lanes
syndrome
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Japanese (ja)
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JP2013539086A (ja
JP2013539086A5 (https=
Inventor
ガウアー、ケヴィン
ラストラス−モンターノ、ルイス
ミーニー、パトリック、ジェームズ
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L2001/0092—Error control systems characterised by the topology of the transmission link
    • H04L2001/0094—Bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Probability & Statistics with Applications (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
JP2013515811A 2010-06-24 2011-06-08 バス障害を検出するための方法、システム及びコンピュータ・プログラム Expired - Fee Related JP5623635B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/822,498 US8566682B2 (en) 2010-06-24 2010-06-24 Failing bus lane detection using syndrome analysis
US12/822,498 2010-06-24
PCT/EP2011/059533 WO2011160956A1 (en) 2010-06-24 2011-06-08 Failing bus lane detection using syndrome analysis

Publications (3)

Publication Number Publication Date
JP2013539086A JP2013539086A (ja) 2013-10-17
JP2013539086A5 JP2013539086A5 (https=) 2014-09-04
JP5623635B2 true JP5623635B2 (ja) 2014-11-12

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ID=44588269

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JP2013515811A Expired - Fee Related JP5623635B2 (ja) 2010-06-24 2011-06-08 バス障害を検出するための方法、システム及びコンピュータ・プログラム

Country Status (5)

Country Link
US (1) US8566682B2 (https=)
EP (1) EP2537095B1 (https=)
JP (1) JP5623635B2 (https=)
CN (1) CN102893262B (https=)
WO (1) WO2011160956A1 (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8862944B2 (en) * 2010-06-24 2014-10-14 International Business Machines Corporation Isolation of faulty links in a transmission medium
US8681839B2 (en) 2010-10-27 2014-03-25 International Business Machines Corporation Calibration of multiple parallel data communications lines for high skew conditions
US8767531B2 (en) 2010-10-27 2014-07-01 International Business Machines Corporation Dynamic fault detection and repair in a data communications mechanism
EP2652911B1 (de) * 2010-12-15 2021-08-18 Hirschmann Automation and Control GmbH Aderbruch-diagnose
US8898504B2 (en) 2011-12-14 2014-11-25 International Business Machines Corporation Parallel data communications mechanism having reduced power continuously calibrated lines
US9411750B2 (en) 2012-07-30 2016-08-09 International Business Machines Corporation Efficient calibration of a low power parallel data communications channel
US9711240B2 (en) 2015-01-08 2017-07-18 Kabushiki Kaisha Toshiba Memory system
DE102015218882A1 (de) * 2015-09-30 2017-03-30 Robert Bosch Gmbh Verfahren und Vorrichtung zum Prüfen von Berechnungsergebnissen in einem System mit mehreren Recheneinheiten
US9474034B1 (en) 2015-11-30 2016-10-18 International Business Machines Corporation Power reduction in a parallel data communications interface using clock resynchronization
US10666540B2 (en) * 2017-07-17 2020-05-26 International Business Machines Corporation Dynamic time-domain reflectometry analysis for field replaceable unit isolation in a running system
KR102499794B1 (ko) 2018-05-21 2023-02-15 삼성전자주식회사 스토리지 장치 및 스토리지 장치의 동작 방법
DE102018115100A1 (de) * 2018-06-22 2019-12-24 Krohne Messtechnik Gmbh Verfahren zur Fehlerbehandlung bei Buskommunikation und Buskommunikationssystem
WO2022132184A1 (en) 2020-12-20 2022-06-23 Intel Corporation System, method and apparatus for total storage encryption
US12455701B2 (en) 2021-07-27 2025-10-28 Intel Corporation Scalable access control checking for cross-address-space data movement
US12541416B2 (en) * 2021-09-23 2026-02-03 Intel Corporation Lane based normalized historical error counter view for faulty lane isolation and disambiguation of transient versus persistent errors
US12487762B2 (en) 2022-05-10 2025-12-02 Intel Corporation Flexible provisioning of coherent memory address decoders in hardware
CN115346590B (zh) * 2022-08-12 2025-09-23 腾讯科技（深圳）有限公司 一种通道修复方法及相关装置
CN118890226B (zh) * 2024-10-08 2025-01-21 杭州艾力特数字科技有限公司 一种基于数据总线的空间声场数据传输系统及方法
CN120111120B (zh) * 2025-03-07 2025-11-28 中国人民解放军网络空间部队信息工程大学 一种面向异构协议转换功能的fpga原型验证装置与方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4360917A (en) 1979-02-07 1982-11-23 The Warner & Swasey Company Parity fault locating means
US4964129A (en) * 1988-12-21 1990-10-16 Bull Hn Information Systems Inc. Memory controller with error logging
US5010544A (en) 1989-01-09 1991-04-23 Wiltron Company Fault location operating system with loopback
US6024486A (en) 1996-06-05 2000-02-15 Compaq Computer Corporation Data error detection and correction
US6557121B1 (en) 1997-03-31 2003-04-29 International Business Machines Corporation Method and system for fault isolation for PCI bus errors
US7020076B1 (en) 1999-10-26 2006-03-28 California Institute Of Technology Fault-tolerant communication channel structures
US7027389B2 (en) 2000-12-11 2006-04-11 Cisco Technology, Inc. Fast failure detection using RTT time considerations on a non-retransmit medium
EP1292078B1 (en) 2001-09-10 2007-10-31 Alcatel Lucent Receiver with three decision circuits
US20040179527A1 (en) * 2003-03-10 2004-09-16 Cypher Robert E. Stripping packet routing prefixes in a computer system network
US7451362B2 (en) 2003-12-12 2008-11-11 Broadcom Corporation Method and system for onboard bit error rate (BER) estimation in a port bypass controller
JP2006072717A (ja) 2004-09-02 2006-03-16 Hitachi Ltd ディスクサブシステム
US7380161B2 (en) 2005-02-11 2008-05-27 International Business Machines Corporation Switching a defective signal line with a spare signal line without shutting down the computer system
US7412642B2 (en) 2005-03-09 2008-08-12 Sun Microsystems, Inc. System and method for tolerating communication lane failures
US7353443B2 (en) 2005-06-24 2008-04-01 Intel Corporation Providing high availability in a PCI-Express link in the presence of lane faults
JP2007150468A (ja) 2005-11-24 2007-06-14 Toshiba Corp ダイバーシチ受信装置
EP2052326B1 (en) * 2006-06-08 2012-08-15 Dot Hill Systems Corporation Fault-isolating sas expander
US7543190B2 (en) 2006-06-28 2009-06-02 Walker Don H System and method for detecting false positive information handling system device connection errors
US7836352B2 (en) * 2006-06-30 2010-11-16 Intel Corporation Method and apparatus for improving high availability in a PCI express link through predictive failure analysis
US7756053B2 (en) * 2006-06-30 2010-07-13 Intel Corporation Memory agent with error hardware
US8082474B2 (en) 2008-07-01 2011-12-20 International Business Machines Corporation Bit shadowing in a memory system
US8201069B2 (en) 2008-07-01 2012-06-12 International Business Machines Corporation Cyclical redundancy code for use in a high-speed serial link

Also Published As

Publication number Publication date
JP2013539086A (ja) 2013-10-17
US8566682B2 (en) 2013-10-22
CN102893262B (zh) 2015-08-26
EP2537095B1 (en) 2013-05-29
EP2537095A1 (en) 2012-12-26
CN102893262A (zh) 2013-01-23
US20110320921A1 (en) 2011-12-29
WO2011160956A1 (en) 2011-12-29

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