JP2013239548A - Sheet substrate, electronic component, electronic apparatus, electronic component testing method and electronic component manufacturing method - Google Patents

Sheet substrate, electronic component, electronic apparatus, electronic component testing method and electronic component manufacturing method Download PDF

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JP2013239548A
JP2013239548A JP2012111168A JP2012111168A JP2013239548A JP 2013239548 A JP2013239548 A JP 2013239548A JP 2012111168 A JP2012111168 A JP 2012111168A JP 2012111168 A JP2012111168 A JP 2012111168A JP 2013239548 A JP2013239548 A JP 2013239548A
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substrate
terminal
electrode
mounting
electronic
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JP2013239548A5 (en
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Kyo Horie
協 堀江
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Seiko Epson Corp
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Priority to US13/892,541 priority patent/US20130307560A1/en
Priority to CN201310177698XA priority patent/CN103427787A/en
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • H05K1/0268Marks, test patterns or identification means for electrical inspection or testing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2818Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/0538Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0542Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a lateral arrangement
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/301Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113Via provided in pad; Pad over filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10083Electromechanical or electro-acoustic component, e.g. microphone
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10371Shields or metal cases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49139Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Acoustics & Sound (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Oscillators With Electromechanical Resonators (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a sheet substrate, an electronic component, an electronic apparatus, an electronic component testing method and an electronic component manufacturing method, which avoid interference between electronic elements and facilitate testing in the electronic components which are structured by substrate region by respectively arranging the electronic elements in the substrate regions of the sheet substrate.SOLUTION: A sheet substrate 54 includes a plurality of substrate regions 56 arranged in a matrix, in each of which an integrated circuit 50 is arranged, and a mounting electrode 18A and a mounting electrode 18B are arranged to be electrically connected to each integrated circuit 50. The sheet substrate 54 of the present embodiment includes: first terminals 62A-62C for connecting the mounting electrodes 18A to the substrate regions 56 with respect to each row and in parallel with each other; and second terminals 66A-66C for connecting the mounting electrodes 18B to the substrate regions 56 with respect to each column and in parallel with each other. Any integrated circuit 50 among the integrated circuits 50 which is specified by the selected first terminal 62A-62C and the selected second terminal 66A-66C can be activated.

Description

本発明は、シート基板、電子部品、電子機器、電子部品の検査方法、及び電子部品の製造方法に関し、特に電子部品に搭載される電子素子の実装後の検査を容易に行うことが可能な技術に関するものである。   The present invention relates to a sheet substrate, an electronic component, an electronic device, an electronic component inspection method, and an electronic component manufacturing method, and in particular, a technique capable of easily performing an inspection after mounting an electronic element mounted on the electronic component. It is about.

従来より、電子部品の効率的な製造方法として、いわゆる多数個取りの手法が用いられている。具体的には、複数の基板領域を有するシート基板を用意し、各基板領域に圧電振動片やICなどの電子素子を配置した上、基板領域の境界に沿ってシート基板を個片に分割することにより、個々の電子部品を得るものである。   Conventionally, a so-called multi-cavity technique has been used as an efficient method for manufacturing electronic components. Specifically, a sheet substrate having a plurality of substrate regions is prepared, and an electronic element such as a piezoelectric vibrating piece or IC is arranged in each substrate region, and the sheet substrate is divided into individual pieces along the boundary of the substrate region. Thus, individual electronic components are obtained.

上記電子部品において、電子部品に搭載された電子素子に対して動作確認等の作業を行う場合がある。例えば電子素子が圧電振動片と圧電振動片に接続した集積回路である場合には、集積回路に電気的に接続する接続電極に検査用プローブを接触させ、圧電振動片が発振するか否か、または共振周波数やCI値等が適正な範囲内にあるか否か等を検査する場合がある。この作業により、検査に合格した電子部品のみをつぎの工程に進めることができる。   In the above electronic component, there are cases where operations such as operation confirmation are performed on an electronic element mounted on the electronic component. For example, when the electronic element is a piezoelectric vibrating piece and an integrated circuit connected to the piezoelectric vibrating piece, an inspection probe is brought into contact with a connection electrode electrically connected to the integrated circuit, and whether or not the piezoelectric vibrating piece oscillates, Alternatively, it may be inspected whether the resonance frequency, CI value, etc. are within an appropriate range. By this operation, only the electronic components that have passed the inspection can be advanced to the next step.

ところで、電子部品を低コスト化するためには、シート基板一枚あたりの電子部品の製造個数を増やす必要があるが、電子部品の個数を増やすほど個々の電子部品の検査が煩雑となる。
特許文献1においては、各基板領域の接続電極から配線が引き出され、基板領域の外部で配線を並列に接続するとともに、電子部品を並列に接続した配線から電力を投入して電子部品を複数同時に起動して電子部品を検査する構成が開示されている。
By the way, in order to reduce the cost of electronic components, it is necessary to increase the number of manufactured electronic components per sheet substrate, but the inspection of individual electronic components becomes more complicated as the number of electronic components is increased.
In Patent Document 1, wirings are drawn from the connection electrodes of each substrate region, the wirings are connected in parallel outside the substrate region, and electric power is supplied from the wirings connected in parallel to the electronic components, so that a plurality of electronic components are simultaneously connected. A configuration for starting and inspecting an electronic component is disclosed.

特開2004−328505号公報JP 2004-328505 A

しかし、特許文献1の構成の場合、各基板領域に配置した電子素子を同時に起動させることになるので、電子素子同士が互いに干渉するおそれがある。例えば、電子素子が圧電振動片に接続した集積回路である場合、圧電振動片同士が干渉して、圧電振動片の共振周波数が変化し、適正な検査が困難になる場合がある。   However, in the case of the configuration of Patent Document 1, since the electronic elements arranged in the respective substrate regions are activated simultaneously, the electronic elements may interfere with each other. For example, when the electronic element is an integrated circuit connected to the piezoelectric vibrating piece, the piezoelectric vibrating pieces interfere with each other, and the resonance frequency of the piezoelectric vibrating piece changes, which may make proper inspection difficult.

そこで、本発明は、上記問題点に着目し、シート基板の基板領域に電子素子配置することにより基板領域ごとに構築される電子部品について、電子素子同士の干渉を回避するとともに、検査を容易にするシート基板、電子部品、電子機器、電子部品の検査方法、及び電子部品の製造方法を提供することを目的とする。   Therefore, the present invention pays attention to the above-mentioned problems, and avoids interference between electronic elements and facilitates inspection of electronic components constructed for each board area by arranging electronic elements in the board area of the sheet substrate. An object of the present invention is to provide a sheet substrate, an electronic component, an electronic device, an electronic component inspection method, and an electronic component manufacturing method.

本発明は、上述の課題の少なくとも一部を解決するためになされたものであり、以下の適用例として実現することが可能である。
[適用例1]マトリックス状に複数配列された基板領域を有するとともに、各基板領域に電子素子が配置され、前記電子素子と電気的に接続する第1の実装電極及び第2の実装電極が各基板領域に配置されるシート基板であって、前記第1の実装電極を、前記基板領域の行ごとに並列に接続する第1の端子と、前記第2の実装電極を、前記基板領域の列ごとに並列に接続する第2の端子と、を有し、前記電子素子のうち、選択された前記第1の端子及び前記第2の端子により特定される任意の前記電子素子を起動可能としたことを特徴とするシート基板。
上記構成により、任意の電子素子を選択的に起動できるので、互いに隣接する電子素子同士の干渉を回避することができる。また、検査用プローブ等を、検査対象となる基板領域に配置された電極に接触させる必要もなくなるため、電子素子の検査を容易に行うことが可能なシート基板となる。
SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following application examples.
Application Example 1 A plurality of substrate regions arranged in a matrix, electronic elements are arranged in each substrate region, and a first mounting electrode and a second mounting electrode that are electrically connected to the electronic elements are A sheet substrate disposed in a substrate region, wherein the first mounting electrode is connected in parallel for each row of the substrate region, and the second mounting electrode is connected to a column of the substrate region. A second terminal connected in parallel to each other, and among the electronic elements, the electronic terminal specified by the selected first terminal and the second terminal can be activated. A sheet substrate characterized by that.
With the above configuration, an arbitrary electronic element can be selectively activated, so that interference between adjacent electronic elements can be avoided. In addition, since it is not necessary to bring an inspection probe or the like into contact with an electrode arranged in a substrate region to be inspected, a sheet substrate capable of easily inspecting an electronic element is obtained.

[適用例2]各基板領域に配置され、前記電子素子と電気的に接続する第3の実装電極及び第4の実装電極と、前記基板領域のうち、互いに隣接する行同士または列同士として一方向にそれぞれ配列された前記基板領域同士であって、一方の配列に含まれる前記基板領域に配置された前記第3の実装電極と、他方の配列に含まれる前記基板領域に配置された前記第4の実装電極と、をそれぞれ並列に接続する第3の端子と、を有することを特徴とする適用例1に記載のシート基板。
上記構成により、起動した電子素子の第3の実装電極に接続した第3の端子と、起動した電子素子の第4の実装電極に接続した第3の端子と、が互いに異なることになる。よって、第3の端子のみで、起動した電子素子に接続した第3の実装電極及び第4の実装電極に対する電気的接続を行なうことができる。
Application Example 2 A third mounting electrode and a fourth mounting electrode that are arranged in each substrate region and are electrically connected to the electronic element, and one of the substrate regions as adjacent rows or columns. The substrate regions arranged in the direction, the third mounting electrodes arranged in the substrate region included in one array, and the first region disposed in the substrate region included in the other array 4. The sheet substrate according to application example 1, further comprising a third terminal that connects the four mounting electrodes in parallel.
With the above configuration, the third terminal connected to the third mounting electrode of the activated electronic element is different from the third terminal connected to the fourth mounting electrode of the activated electronic element. Therefore, electrical connection to the third mounting electrode and the fourth mounting electrode connected to the activated electronic element can be performed with only the third terminal.

[適用例3]各基板領域には、前記電子素子に接合する第5の実装電極が配置され、前記第2の端子は、前記基板領域のうち、互いに隣接する列同士として一方向にそれぞれ配列された前記基板領域同士であって、一方の配列に含まれる前記基板領域に配置された前記第2の実装電極と、他方の配列に含まれる前記基板領域に配置された前記第5の実装電極と、をそれぞれ並列に接続していることを特徴とする適用例1または2に記載のシート基板。
上記構成により、起動した電子素子の第2の実装電極の接続先となる第2の端子と、起動した電子素子の第5の実装電極の接続先となる第2の端子と、が互いに異なることになる。よって、第2の端子のみで、起動した電子素子に接続した第2の実装電極及び第5の実装電極に電気的に接続することができる。
Application Example 3 In each substrate region, a fifth mounting electrode that is bonded to the electronic element is disposed, and the second terminals are arranged in one direction as adjacent rows in the substrate region. The second mounting electrodes disposed in the substrate region included in one array, and the fifth mounting electrode disposed in the substrate region included in the other array. And the sheet substrate according to Application Example 1 or 2, wherein the two are connected in parallel.
With the above configuration, the second terminal that is the connection destination of the second mounting electrode of the activated electronic element is different from the second terminal that is the connection destination of the fifth mounting electrode of the activated electronic element. become. Therefore, the second mounting electrode and the fifth mounting electrode connected to the activated electronic element can be electrically connected only by the second terminal.

[適用例4]適用例1乃至3のいずれか1例に記載のシート基板の各基板領域に前記電子素子を配置し、前記シート基板を前記基板領域の境界に沿って分割して個片化されたことを特徴とする電子部品。
適用例1と同様の理由により、電子素子同士の干渉を回避し、容易に電子素子の検査が可能な電子部品となる。
Application Example 4 The electronic element is arranged in each substrate region of the sheet substrate according to any one of Application Examples 1 to 3, and the sheet substrate is divided along the boundary of the substrate region to be separated into pieces. Electronic parts characterized by being made.
For the same reason as in Application Example 1, the electronic component can be easily inspected by avoiding interference between the electronic devices.

[適用例5]適用例4に記載の電子部品を搭載したことを特徴とする電子機器。
適用例1と同様の理由により、電子素子同士の干渉を回避し、容易に電子素子の検査が可能な電子機器となる。
Application Example 5 An electronic apparatus comprising the electronic component according to Application Example 4 mounted thereon.
For the same reason as in Application Example 1, the electronic device can avoid the interference between the electronic elements and can easily inspect the electronic elements.

[適用例6]マトリックス状に複数配列された基板領域を有するシート基板に対し、各基板領域に電子素子を配置し、前記電子素子と電気的に接続する第1の実装電極及び第2の実装電極を各基板領域に配置することにより、前記シート基板において基板領域ごとに構成された電子部品の検査方法であって、前記第1の実装電極を、前記基板領域の行ごとに第1の端子に接続し、前記第2の実装電極を、前記基板領域の列ごとに第2の端子に接続し、前記電子素子のうち、選択された前記第1の端子及び前記第2の端子により特定される任意の前記電子素子を起動することを特徴とする電子部品の検査方法。
適用例1と同様の理由により、電子素子同士の干渉を回避し、容易に電子素子の検査が可能な電子部品の検査方法となる。
Application Example 6 For a sheet substrate having a plurality of substrate regions arranged in a matrix, an electronic element is arranged in each substrate region, and a first mounting electrode and a second mounting are electrically connected to the electronic device. An electronic component inspection method configured for each substrate region in the sheet substrate by disposing an electrode in each substrate region, wherein the first mounting electrode is connected to a first terminal for each row of the substrate region. The second mounting electrode is connected to a second terminal for each column of the substrate region, and is specified by the selected first terminal and the second terminal among the electronic elements. A method for inspecting an electronic component, comprising: activating any of the electronic elements.
For the same reason as in Application Example 1, an electronic component inspection method is provided in which interference between electronic elements is avoided and the electronic elements can be easily inspected.

[適用例7]マトリックス状に複数配列された基板領域を有するシート基板に対し、各基板領域に電子素子を配置し、前記電子素子と電気的に接続する第1の実装電極及び第2の実装電極を各基板領域に配置することにより、前記シート基板において基板領域ごとに構成された電子部品の製造方法であって、前記第1の実装電極を、前記基板領域の行ごとに並列に接続する第1の端子と、前記第2の実装電極を、前記基板領域の列ごとに並列に接続する第2の端子と、を配置する第1工程と、前記電子素子のうち、選択された前記第1の端子及び前記第2の端子により特定される任意の前記電子素子を起動する第2工程と、前記シート基板を前記基板領域の境界に沿って分割する第3工程と、を有することを特徴とする電子部品の製造方法。
適用例1と同様の理由により、電子素子同士の干渉を回避し、容易に電子素子の検査が可能な電子部品の製造方法となる。
Application Example 7 With respect to a sheet substrate having a plurality of substrate regions arranged in a matrix, an electronic element is arranged in each substrate region, and a first mounting electrode and a second mounting are electrically connected to the electronic device. An electronic component manufacturing method configured for each substrate region on the sheet substrate by disposing electrodes in each substrate region, wherein the first mounting electrode is connected in parallel for each row of the substrate region A first step of arranging a first terminal and a second terminal for connecting the second mounting electrode in parallel for each column of the substrate region; and the first selected among the electronic elements. A second step of activating any of the electronic elements specified by one terminal and the second terminal, and a third step of dividing the sheet substrate along a boundary of the substrate region. A method for manufacturing electronic components.
For the same reason as in Application Example 1, an electronic component manufacturing method is provided in which interference between electronic elements is avoided and the electronic elements can be easily inspected.

第1実施形態のシート基板の回路図である。It is a circuit diagram of the sheet substrate of a 1st embodiment. 第1実施形態のシート基板の平面図である。It is a top view of the sheet substrate of a 1st embodiment. 図2のA−A線断面図である。It is the sectional view on the AA line of FIG. 第1実施形態のシート基板の裏面図である。It is a back view of the sheet substrate of a 1st embodiment. 図1の一点鎖線で囲まれた部分の拡大図である。It is an enlarged view of the part enclosed with the dashed-dotted line of FIG. 本実施形態の電子部品の模式図である。It is a schematic diagram of the electronic component of this embodiment. 第2実施形態のシート基板の回路図である。It is a circuit diagram of the sheet substrate of a 2nd embodiment. 第3実施形態のシート基板の回路図である。It is a circuit diagram of the sheet substrate of a 3rd embodiment. 第3実施形態のシート基板の平面図である。It is a top view of the sheet substrate of a 3rd embodiment. 本実施形態の電子部品を搭載した電子機器の模式図である。It is a schematic diagram of the electronic device carrying the electronic component of this embodiment.

以下、本発明を図に示した実施形態を用いて詳細に説明する。但し、この実施形態に記載される構成要素、種類、組み合わせ、形状、その相対配置などは特定的な記載がない限り、この発明の範囲をそれのみに限定する主旨ではなく単なる説明例に過ぎない。   Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .

図1に、第1実施形態のシート基板の回路図を示す。第1実施形態のシート基板54は、電子部品10(基板領域56)をマトリックス状に複数(本実施形態では3×3=9個)集合したものであって、配線を縦横に配置して、各電子部品10に配置された実装電極18A〜18Eを種類別に接続したものである。なお、図において、電子部品10には番号(1番〜9番)を付している。また、図において、縦方向を行方向とし、横方向を列方向とする。   FIG. 1 is a circuit diagram of a sheet substrate according to the first embodiment. The sheet substrate 54 of the first embodiment is a collection of a plurality of electronic components 10 (substrate regions 56) in a matrix (3 × 3 = 9 in this embodiment), and wiring is arranged vertically and horizontally, The mounting electrodes 18A to 18E arranged in each electronic component 10 are connected by type. In the figure, the electronic components 10 are numbered (Nos. 1 to 9). In the figure, the vertical direction is the row direction, and the horizontal direction is the column direction.

電子部品10には、後述のように集積回路50が配置され、この集積回路50に電気的に接続する実装電極18A〜18Eが電子部品10の実装面16に配置されている。実装電極18A(第1の実装電極)は電源端子(Vdd)、実装電極18B(第2の実装電極)はグランド端子(GND)、実装電極18C(第3の実装電極)は出力端子(OUT)、実装電極18D(第4の実装電極)は後述の調整端子(Vc)、実装電極18E(第5の実装電極)は後述の温度情報出力端子(T)となっている。   As will be described later, an integrated circuit 50 is disposed on the electronic component 10, and mounting electrodes 18 </ b> A to 18 </ b> E that are electrically connected to the integrated circuit 50 are disposed on the mounting surface 16 of the electronic component 10. The mounting electrode 18A (first mounting electrode) is a power supply terminal (Vdd), the mounting electrode 18B (second mounting electrode) is a ground terminal (GND), and the mounting electrode 18C (third mounting electrode) is an output terminal (OUT). The mounting electrode 18D (fourth mounting electrode) is an adjustment terminal (Vc) described later, and the mounting electrode 18E (fifth mounting electrode) is a temperature information output terminal (T) described later.

第1の配線60A,60B,60Cは、同一行内の電子部品10の実装電極18Aを並列に接続するものである。第1の配線60Aは、1番、2番、3番の実装電極18Aを並列に接続し、第1の配線60Bは、4番、5番、6番の実装電極18Aを並列に接続し、第1の配線60Cは、7番、8番、9番の実装電極18Aを並列に接続している。第1の配線60A,60B,60Cは、それぞれ第1の端子62A,62B,62Cに接続されている。第1の端子62A,62B,62Cは、外部の切替制御等により、そのいずれか一つがオン状態となって電源電圧が印加され、残りがオフ状態となって電源電圧の印加が停止される。   The first wirings 60A, 60B, and 60C connect the mounting electrodes 18A of the electronic components 10 in the same row in parallel. The first wiring 60A connects the first, second, and third mounting electrodes 18A in parallel, and the first wiring 60B connects the fourth, fifth, and sixth mounting electrodes 18A in parallel, The first wiring 60C connects the seventh, eighth, and ninth mounting electrodes 18A in parallel. The first wirings 60A, 60B, and 60C are connected to the first terminals 62A, 62B, and 62C, respectively. Any one of the first terminals 62A, 62B, and 62C is turned on to apply the power supply voltage, and the rest is turned off to stop the application of the power supply voltage by an external switching control or the like.

第2の配線64A,64B,64Cは、同一列内の電子部品10の実装電極18B、及び同一列内の電子部品10の実装電極18Eを並列に接続するものである。ここで、第2の配線64A,64Bは、電子部品10のうち、互いに隣接する列同士として一方向にそれぞれ配列された電子部品10同士であって、一方の配列に含まれる電子部品10に配置された実装電極18Bと、他方の配列に含まれる電子部品10に配置された実装電極18Eと、をそれぞれ並列に接続している。   The second wirings 64A, 64B, 64C connect the mounting electrodes 18B of the electronic components 10 in the same column and the mounting electrodes 18E of the electronic components 10 in the same column in parallel. Here, the second wirings 64 </ b> A and 64 </ b> B are the electronic components 10 arranged in one direction as adjacent columns among the electronic components 10, and are arranged in the electronic components 10 included in one arrangement. The mounted electrodes 18B and the mounted electrodes 18E arranged on the electronic component 10 included in the other array are connected in parallel.

よって、第2の配線64Aは、1番、4番、7番の電子部品10の実装電極18Bと、2番、5番、8番の電子部品10の実装電極18Eと、それぞれ並列に接続している。第2の配線64Bは、2番、5番、8番の電子部品10の実装電極18Bと、3番、6番、9番の電子部品10の実装電極18Eと、をそれぞれ並列に接続している。第2の配線64Cは、3番、6番、9番の電子部品10の実装電極18Bを並列に接続している。   Therefore, the second wiring 64A is connected in parallel to the mounting electrode 18B of the electronic component 10 of No. 1, 4, and 7 and the mounting electrode 18E of the electronic component 10 of No. 2, 5, and 8. ing. The second wiring 64B is formed by connecting the mounting electrodes 18B of the second, fifth, and eighth electronic components 10 and the mounting electrodes 18E of the third, sixth, and ninth electronic components 10 in parallel. Yes. The second wiring 64C connects the mounting electrodes 18B of the third, sixth, and ninth electronic components 10 in parallel.

第2の配線64A,64B,64Cは、それぞれ第2の端子66A,66B,66Cに接続されている。第2の端子66A,66B,66Cは、外部の切替制御等により、そのいずれか一つがオン状態となって接地され、残りがオフ状態となって接地が解除される。また第2の端子66A,66Bには、実装電極18Eから出力される温度情報を取得するための外部端子(不図示)を接続することができる。   The second wirings 64A, 64B, and 64C are connected to the second terminals 66A, 66B, and 66C, respectively. Any one of the second terminals 66A, 66B, and 66C is turned on and grounded by an external switching control or the like, and the remaining terminals are turned off and the grounding is released. An external terminal (not shown) for acquiring temperature information output from the mounting electrode 18E can be connected to the second terminals 66A and 66B.

第3の配線68A,68Bは、同一列内の電子部品10の実装電極18C、及び同一列内の電子部品10の実装電極18Dを並列に接続するものである。ここで、第3の配線68A,68Bは、電子部品10のうち、互いに隣接する列同士として一方向にそれぞれ配列された電子部品10同士であって、一方の配列に含まれる電子部品10に配置された実装電極18Cと、他方の配列に含まれる電子部品10に配置された実装電極18Dと、をそれぞれ並列に接続している。   The third wirings 68A and 68B connect the mounting electrode 18C of the electronic component 10 in the same column and the mounting electrode 18D of the electronic component 10 in the same column in parallel. Here, the third wirings 68 </ b> A and 68 </ b> B are the electronic components 10 arranged in one direction as adjacent columns among the electronic components 10, and are arranged on the electronic components 10 included in one arrangement. The mounted electrodes 18C and the mounted electrodes 18D disposed on the electronic component 10 included in the other array are connected in parallel.

よって、第3の配線68Aは、1番、4番、7番の電子部品10の実装電極18Cと、2番、5番、8番の電子部品10の実装電極18Dと、をそれぞれ並列に接続している。第3の配線68Bは、2番、5番、8番の電子部品10の実装電極18Cと、3番、6番、9番の電子部品10の実装電極18Dと、をそれぞれ並列に接続している。   Therefore, the third wiring 68A connects the mounting electrode 18C of the electronic component 10 of No. 1, 4, and 7 and the mounting electrode 18D of the electronic component 10 of No. 2, 5, and 8 in parallel. doing. The third wiring 68B connects the mounting electrode 18C of the second, fifth, and eighth electronic components 10 and the mounting electrode 18D of the third, sixth, and ninth electronic components 10 in parallel. Yes.

第3の配線68A,68Bは、それぞれ第3の端子70A,70Bに接続されている。第3の端子70A,70Bには、実装電極18Cからの出力を取り出すための外部端子(不図示)、または実装電極18Dに調整電圧を印加するための外部端子(不図示)を接続することができる。   The third wirings 68A and 68B are connected to the third terminals 70A and 70B, respectively. An external terminal (not shown) for taking out an output from the mounting electrode 18C or an external terminal (not shown) for applying an adjustment voltage to the mounting electrode 18D may be connected to the third terminals 70A and 70B. it can.

補助配線72Aは、1番、4番、7番の電子部品10の実装電極18Eを並列に接続するものであり、補助配線72Bは、1番、4番、7番の電子部品10の実装電極18Dを並列に接続するものである。また、補助配線72Cは、3番、6番、9番の電子部品10の実装電極18Bを並列に接続するものである。   The auxiliary wiring 72A connects the mounting electrodes 18E of the first, fourth, and seventh electronic components 10 in parallel, and the auxiliary wiring 72B is the mounting electrode of the first, fourth, and seventh electronic components 10 18D is connected in parallel. The auxiliary wiring 72C connects the mounting electrodes 18B of the third, sixth, and ninth electronic components 10 in parallel.

補助配線72A,72B,72Cは、それぞれ補助端子74A,74B,74Cに接続されている。補助端子74Aには、実装電極18Eから出力される温度情報を取得するための外部端子(不図示)が、補助端子74Bには、実装電極18Dに調整電圧を印加するための外部端子(不図示)が、補助端子74Cには、実装電極18Cからの出力を取り出すための外部端子(不図示)が、それぞれ接続される。   The auxiliary wirings 72A, 72B, 72C are connected to auxiliary terminals 74A, 74B, 74C, respectively. The auxiliary terminal 74A has an external terminal (not shown) for acquiring temperature information output from the mounting electrode 18E, and the auxiliary terminal 74B has an external terminal (not shown) for applying an adjustment voltage to the mounting electrode 18D. However, external terminals (not shown) for taking out the output from the mounting electrode 18C are connected to the auxiliary terminals 74C, respectively.

電子部品10は、実装電極18Aに電源電圧が印加され、実装電極18Bが接地されることにより起動する。例えば、図1に示すように5番の電子部品10を起動する場合は、第1の端子62B(図中、矢印付)と第2の端子66B(図中、矢印付)をオン状態にする。このとき、4番と、6番の電子部品10にも第1の端子62Bから電源電圧が印加されるが、このとき、これらの電子部品10は接地されておらず起動することはない。   The electronic component 10 is activated when a power supply voltage is applied to the mounting electrode 18A and the mounting electrode 18B is grounded. For example, as shown in FIG. 1, when starting the electronic component 10 of No. 5, the first terminal 62B (with an arrow in the figure) and the second terminal 66B (with an arrow in the figure) are turned on. . At this time, the power supply voltage is applied to the fourth and sixth electronic components 10 from the first terminal 62B. At this time, these electronic components 10 are not grounded and do not start.

また、5番の電子部品10には、第2の端子66A、第3の端子70A、及び第3の端子70Bが接続している。よって、第2の端子66A(図中、矢印付)から5番の電子部品10の温度情報を取り出すことができ、第3の端子70A(図中、矢印付)から5番の電子部品10に対して調整電圧を印加することができ、第3の端子70B(図中、矢印付)から5番の電子部品10の出力を取り出すことができる。   The fifth electronic component 10 is connected to the second terminal 66A, the third terminal 70A, and the third terminal 70B. Therefore, the temperature information of the fifth electronic component 10 can be taken out from the second terminal 66A (with arrow in the figure), and the fifth electronic component 10 can be taken from the third terminal 70A (with arrow in the figure). On the other hand, an adjustment voltage can be applied, and the output of the fifth electronic component 10 can be taken out from the third terminal 70B (with an arrow in the figure).

上記構成において、第1の端子62Bをオフ状態とし、第1の端子62A(60C)をオン状態に切り替えると、5番の電子部品10の作動を停止させるとともに、2番(8番)の電子部品10を起動させることができる。そして、上述の同一の配置で、温度情報の取り出し、調整電圧の印加、電子部品の出力の検知を行うことができる。   In the above configuration, when the first terminal 62B is turned off and the first terminal 62A (60C) is switched to the on state, the operation of the fifth electronic component 10 is stopped and the second (eighth) electronic device is stopped. The component 10 can be activated. The temperature information can be extracted, the adjustment voltage can be applied, and the output of the electronic component can be detected with the same arrangement described above.

また第1の端子62Bをオン状態とし、第2の端子66Bをオフ状態として第2の端子66A(C)をオン状態に切り替えると、5番の電子部品10の作動を停止させるとともに、4番(6番)の電子部品10を起動することができる。このとき、温度情報を取り出すための外部端子(不図示)、調整電圧を印加するための外部端子(不図示)、電子部品10の出力を取り出すための外部端子(不図示)の接続先を、それぞれ左隣(右隣)の端子に切り替えることにより、温度情報の取り出し、調整電圧の印加、電子部品10の出力の取り出しを行うことができる。よって、本実施形態のシート基板54では、オン状態にする第1の端子62A〜62C及び第2の端子66A〜66Cを任意に選択することにより全ての電子部品10を個別に起動して、各種検査を行なうことができる。   When the first terminal 62B is turned on, the second terminal 66B is turned off, and the second terminal 66A (C) is switched to the on state, the operation of the fifth electronic component 10 is stopped and the fourth terminal 66B is turned on. The (No. 6) electronic component 10 can be activated. At this time, an external terminal (not shown) for extracting temperature information, an external terminal (not shown) for applying an adjustment voltage, and a connection destination of an external terminal (not shown) for extracting the output of the electronic component 10 are By switching to the terminals on the left (right adjacent), temperature information can be extracted, adjustment voltage can be applied, and the output of the electronic component 10 can be extracted. Therefore, in the sheet substrate 54 of the present embodiment, all the electronic components 10 are individually activated by arbitrarily selecting the first terminals 62A to 62C and the second terminals 66A to 66C to be turned on, Inspection can be performed.

このように、本実施形態では、任意の電子部品10(集積回路50)を選択的に起動するので、互いに隣接する電子部品10同士の干渉を回避することができる。また、検査用プローブ等を、検査対象となる電子部品10(基板領域56)に配置された実装電極18A〜18Eに接触させる必要もなくなるため、電子部品10(集積回路50)の検査を容易に行うことが可能なシート基板54となる。   Thus, in this embodiment, since the arbitrary electronic component 10 (integrated circuit 50) is selectively activated, interference between the electronic components 10 adjacent to each other can be avoided. Further, since it is not necessary to bring the inspection probe or the like into contact with the mounting electrodes 18A to 18E disposed on the electronic component 10 (substrate region 56) to be inspected, the electronic component 10 (integrated circuit 50) can be easily inspected. This is a sheet substrate 54 that can be used.

第2の端子66A,66Bは、接地用と温度情報取得用とで同時に使用されることはない。すなわち、起動した電子部品10(集積回路50)の実装電極18Bの接続先となる第2の端子と、起動した電子部品10の実装電極18Eの接続先となる第2の端子と、が互いに異なることになる。よって、第2の端子のみで、起動した電子部品10に接続した実装電極18B及び実装電極18Eに電気的に接続することができる。   The second terminals 66A and 66B are not used simultaneously for grounding and for obtaining temperature information. That is, the second terminal to which the mounting electrode 18B of the activated electronic component 10 (integrated circuit 50) is connected is different from the second terminal to which the mounting electrode 18E of the activated electronic component 10 is connected. It will be. Therefore, it is possible to electrically connect to the mounting electrode 18B and the mounting electrode 18E connected to the activated electronic component 10 with only the second terminal.

同様に、第3の端子70A,70Bは、出力取り出し用と調整電圧印加用とで同時に使用されることはない。すなわち、起動した電子部品10(集積回路50)の実装電極18Cに接続した第3の端子と、起動した電子部品10の実装電極18Dに接続した第3の端子と、が互いに異なることになる。よって、第3の端子のみで、起動した電子部品10(集積回路50)に接続した実装電極18C及び実装電極18Dに対する電気的接続を行なうことができる。   Similarly, the third terminals 70A and 70B are not used simultaneously for output extraction and adjustment voltage application. That is, the third terminal connected to the mounting electrode 18C of the activated electronic component 10 (integrated circuit 50) and the third terminal connected to the mounting electrode 18D of the activated electronic component 10 are different from each other. Therefore, electrical connection to the mounting electrode 18C and the mounting electrode 18D connected to the activated electronic component 10 (integrated circuit 50) can be performed with only the third terminal.

次に、図1に示す配線図に基づいて構築されるシート基板54と、シート基板54で複数構築される電子部品10の構造について説明する。図2に、第1実施形態のシート基板の平面図を示し、図3に、図2のA−A線断面図を示し、図4に、第1実施形態のシート基板の裏面図を示す。また、図5に、図1の一点鎖線で囲まれた部分の拡大図を示し、図6に、本実施形態の電子部品の模式図を示す。なお、図2においては、キャップ32を省略するとともに、一部の基板領域56において、圧電振動片38及び集積回路50を省略している。   Next, the structure of the sheet substrate 54 constructed based on the wiring diagram shown in FIG. 1 and a plurality of electronic components 10 constructed by the sheet substrate 54 will be described. 2 is a plan view of the sheet substrate of the first embodiment, FIG. 3 is a sectional view taken along line AA of FIG. 2, and FIG. 4 is a back view of the sheet substrate of the first embodiment. FIG. 5 shows an enlarged view of a portion surrounded by a one-dot chain line in FIG. 1, and FIG. 6 shows a schematic diagram of the electronic component of this embodiment. In FIG. 2, the cap 32 is omitted, and the piezoelectric vibrating piece 38 and the integrated circuit 50 are omitted in a part of the substrate region 56.

図2に示すように、本実施形態のシート基板54は、セラミック等の絶縁体により形成されており、マトリックス状に配置された複数(3×3=9個)の基板領域56と、その周囲の配置された端子領域58と、を有する。基板領域56同士は、互いに接することはなく所定の間隔を有して互いに離間しており、その間に第1の配線60A〜60C、第2の配線64A〜64C、第3の配線68A〜68Cが配置されている。   As shown in FIG. 2, the sheet substrate 54 of the present embodiment is formed of an insulator such as ceramic, and a plurality (3 × 3 = 9) of substrate regions 56 arranged in a matrix and its surroundings The terminal region 58 is arranged. The substrate regions 56 are not in contact with each other and are separated from each other with a predetermined interval, and the first wirings 60A to 60C, the second wirings 64A to 64C, and the third wirings 68A to 68C are interposed therebetween. Is arranged.

シート基板54の上面(搭載面14)の各基板領域56には、圧電振動片38や集積回路50が配置され、裏面(実装面16)の各基板領域56には実装電極18A〜18Eが配置されている。このように、本実施形態のシート基板54では、基板領域56ごとに本実施形態の電子部品10が構築されており、シート基板54を基板領域56の境界に沿って分割することにより、ベース基板12を土台とした電子部品10が個片化される。   The piezoelectric vibrating piece 38 and the integrated circuit 50 are disposed in each substrate region 56 on the upper surface (mounting surface 14) of the sheet substrate 54, and the mounting electrodes 18A to 18E are disposed in each substrate region 56 on the back surface (mounting surface 16). Has been. As described above, in the sheet substrate 54 of the present embodiment, the electronic component 10 of the present embodiment is constructed for each substrate region 56, and the base substrate is obtained by dividing the sheet substrate 54 along the boundary of the substrate region 56. The electronic component 10 based on 12 is singulated.

図6等に示すように、電子部品10は、ベース基板12上に圧電振動片38と集積回路50が横並びに配置され、キャップ32(図3)が圧電振動片38及び集積回路50を収容する形でベース基板12に接合された形態を有している。そして、電子部品10は、外部から給電を受けることにより自ら発振する圧電デバイスとなっている。   As shown in FIG. 6 and the like, in the electronic component 10, the piezoelectric vibrating piece 38 and the integrated circuit 50 are arranged side by side on the base substrate 12, and the cap 32 (FIG. 3) accommodates the piezoelectric vibrating piece 38 and the integrated circuit 50. It has a form joined to the base substrate 12 in the form. The electronic component 10 is a piezoelectric device that oscillates itself by receiving power from outside.

圧電振動片38は、水晶等の圧電材料により形成されている。本実施形態では、例えば水晶のATカット基板を用いた厚みすべり振動片としている。圧電振動片38は、厚みすべり振動をする振動部40(図3拡大図参照)と、ベース基板12に接合されるマウント部42と、を有する。振動部40の上面には励振電極44A(X1)が配置され、下面には励振電極44B(X2)が配置されている。励振電極44Aからは引出電極46Aが引き出され、励振電極44Bからは引出電極46Bが引き出されている。引出電極46Bは、マウント部42の下面にまで引き出されている。引出電極46Aは、マウント部42の上面及び側面を経由してマウント部42の下面に引き出されている。なお、圧電振動片38としては、これ以外に音叉型振動片、双音叉型振動片、SAW共振片、ジャイロ振動片等を適用できる。   The piezoelectric vibrating piece 38 is made of a piezoelectric material such as quartz. In the present embodiment, for example, a thickness-shear vibrating piece using a quartz AT-cut substrate is used. The piezoelectric vibrating piece 38 includes a vibrating portion 40 (see an enlarged view in FIG. 3) that vibrates in thickness and a mount portion 42 that is bonded to the base substrate 12. An excitation electrode 44A (X1) is disposed on the upper surface of the vibration unit 40, and an excitation electrode 44B (X2) is disposed on the lower surface. An extraction electrode 46A is extracted from the excitation electrode 44A, and an extraction electrode 46B is extracted from the excitation electrode 44B. The extraction electrode 46 </ b> B is extracted to the lower surface of the mount portion 42. The extraction electrode 46 </ b> A is extracted to the lower surface of the mount portion 42 via the upper surface and side surfaces of the mount portion 42. As the piezoelectric vibrating piece 38, a tuning fork type vibrating piece, a double tuning fork type vibrating piece, a SAW resonance piece, a gyro vibrating piece, or the like can be applied.

集積回路50は、圧電振動片38を発振源として駆動する発振回路や発振回路の発振信号の温度補償を行なう温度補償回路等が一体で形成された電子素子である。集積回路50の能動面(下面)には、パッド電極52が配置されている。パッド電極52としては、圧電振動片38に電気的に接続する接続端子(X1、X2)、外部からの給電を受ける電源端子(Vdd)、グランド端子(GND)、出力信号の出力端子(OUT)が配置される。またパッド電極52としては、集積回路50に内蔵された発振回路の出力信号の発振周波数を調整するための調整電圧を入力するための調整電圧入力端子(Vc)が配置される。また集積回路50にはサーミスタが内蔵され、このサーミスタに基づいて温度情報が生成される。これを出力するため、集積回路50には、パッド電極52の一つとして温度情報出力端子(T)が配置される。   The integrated circuit 50 is an electronic element in which an oscillation circuit that drives the piezoelectric vibrating piece 38 as an oscillation source, a temperature compensation circuit that performs temperature compensation of an oscillation signal of the oscillation circuit, and the like are integrally formed. A pad electrode 52 is disposed on the active surface (lower surface) of the integrated circuit 50. The pad electrode 52 includes connection terminals (X1, X2) electrically connected to the piezoelectric vibrating piece 38, a power supply terminal (Vdd) that receives power from the outside, a ground terminal (GND), and an output signal output terminal (OUT). Is placed. Further, as the pad electrode 52, an adjustment voltage input terminal (Vc) for inputting an adjustment voltage for adjusting the oscillation frequency of the output signal of the oscillation circuit built in the integrated circuit 50 is disposed. The integrated circuit 50 includes a thermistor, and temperature information is generated based on the thermistor. In order to output this, the integrated circuit 50 is provided with a temperature information output terminal (T) as one of the pad electrodes 52.

ベース基板12は、圧電振動片38や集積回路50が搭載される搭載面14と、その裏面となる実装面16を有している。
図5に示すように、ベース基板12の搭載面14の引出電極46A、46Bに対向する位置にはマウント電極24A,24Bが配置されている。また搭載面14のパッド電極52に対向する位置には接続電極20(X1,X2,Vdd,GND,OUT,Vc,T)が配置されている。一方、図4、図5に示すように、ベース基板12の実装面16の下面の周縁には実装電極18A(Vdd),18B(GND),18C(OUT),18D(Vc),18E(T)が配置されている。
The base substrate 12 has a mounting surface 14 on which the piezoelectric vibrating piece 38 and the integrated circuit 50 are mounted, and a mounting surface 16 as the back surface thereof.
As shown in FIG. 5, mount electrodes 24 </ b> A and 24 </ b> B are arranged at positions facing the extraction electrodes 46 </ b> A and 46 </ b> B on the mounting surface 14 of the base substrate 12. Further, connection electrodes 20 (X1, X2, Vdd, GND, OUT, Vc, T) are arranged at positions facing the pad electrodes 52 on the mounting surface. On the other hand, as shown in FIGS. 4 and 5, mounting electrodes 18A (Vdd), 18B (GND), 18C (OUT), 18D (Vc), 18E (T) are provided on the periphery of the lower surface of the mounting surface 16 of the base substrate 12. ) Is arranged.

図5に示すように、マウント電極24A(X1)と、接続電極20(X1)とが、引き回し電極22Aにより電気的に互いに接続され、マウント電極24B(X2)と接続電極20(X2)も、引き回し電極22Bにより電気的に互いに接続されている。   As shown in FIG. 5, the mount electrode 24A (X1) and the connection electrode 20 (X1) are electrically connected to each other by the routing electrode 22A, and the mount electrode 24B (X2) and the connection electrode 20 (X2) are also The lead electrodes 22B are electrically connected to each other.

接続電極20(Vdd)からは、引き回し電極22Cが延出している。引き回し電極22Cは、実装電極18Aの真上となる位置に延出しており、ベース基板12を貫通する貫通電極26を介して実装電極18Aと電気的に接続される。これにより接続電極20(Vdd)は、実装電極18Aに電気的に接続される。   A lead electrode 22C extends from the connection electrode 20 (Vdd). The routing electrode 22 </ b> C extends to a position directly above the mounting electrode 18 </ b> A, and is electrically connected to the mounting electrode 18 </ b> A via a through electrode 26 that penetrates the base substrate 12. Thereby, the connection electrode 20 (Vdd) is electrically connected to the mounting electrode 18A.

接続電極20(GND)は、実装電極18Bの真上となる位置に配置され、貫通電極26を介して実装電極18Bと電気的に接続されている。
接続電極20(OUT)は、実装電極18Cの真上となる位置に配置され、貫通電極26を介して実装電極18Cと電気的に接続されている。
The connection electrode 20 (GND) is disposed at a position directly above the mounting electrode 18B, and is electrically connected to the mounting electrode 18B through the through electrode 26.
The connection electrode 20 (OUT) is disposed at a position directly above the mounting electrode 18C, and is electrically connected to the mounting electrode 18C through the through electrode 26.

接続電極20(Vc)からは、引き回し電極22Dが延出している。引き回し電極22Dは、実装電極18Dの真上となる位置に延出しており、貫通電極26を介して実装電極18Dと電気的に接続される。これにより接続電極20(Vc)は、実装電極18Dに電気的に接続される。   A lead electrode 22D extends from the connection electrode 20 (Vc). The routing electrode 22D extends to a position directly above the mounting electrode 18D, and is electrically connected to the mounting electrode 18D through the through electrode 26. Thereby, the connection electrode 20 (Vc) is electrically connected to the mounting electrode 18D.

接続電極20(T)は、実装電極18Eの真上となる位置に配置され、貫通電極26を介して実装電極18Eと電気的に接続されている。
ベース基板12の搭載面14の圧電振動片38及び集積回路50を囲む位置には枠形状のメタライズ28が配置されている。メタライズ28は接続電極20(GND)と接続されている。よって、メタライズ28は、実装電極18Bと電気的に接続される。このメタライズ28を接合面として金属製のキャップ32(図3)がベース基板12に接合される。よって、キャップ32は、圧電振動片38及び集積回路50を気密封止するとともに、キャップ32内の収容空間を外部から静電遮蔽し、圧電振動片38及び集積回路50に対する電気的な外乱を低減することができる。
The connection electrode 20 (T) is disposed at a position directly above the mounting electrode 18E, and is electrically connected to the mounting electrode 18E through the through electrode 26.
A frame-shaped metallization 28 is disposed at a position surrounding the piezoelectric vibrating piece 38 and the integrated circuit 50 on the mounting surface 14 of the base substrate 12. The metallized 28 is connected to the connection electrode 20 (GND). Therefore, the metallized 28 is electrically connected to the mounting electrode 18B. A metal cap 32 (FIG. 3) is bonded to the base substrate 12 with the metallized 28 as a bonding surface. Therefore, the cap 32 hermetically seals the piezoelectric vibrating piece 38 and the integrated circuit 50, and electrostatically shields the accommodation space in the cap 32 from the outside, thereby reducing electrical disturbance to the piezoelectric vibrating piece 38 and the integrated circuit 50. can do.

図3、図5に示すように、引出電極46Aとマウント電極24Aとを導電性接着剤48Aにより接合し、且つ引出電極46Bとマウント電極24Bとを導電性接着剤48Bにより接合する態様で圧電振動片38をベース基板12上に接合する。これにより、圧電振動片38は、マウント部42(図6)を固定端として片持ち支持状態でベース基板12に支持されるとともにマウント電極24A,24Bに電気的に接続する。   As shown in FIGS. 3 and 5, piezoelectric vibration is performed in such a manner that the lead electrode 46A and the mount electrode 24A are joined by the conductive adhesive 48A, and the lead electrode 46B and the mount electrode 24B are joined by the conductive adhesive 48B. The piece 38 is bonded onto the base substrate 12. Accordingly, the piezoelectric vibrating piece 38 is supported by the base substrate 12 in a cantilevered state with the mount portion 42 (FIG. 6) as a fixed end and is electrically connected to the mount electrodes 24A and 24B.

また、集積回路50のパッド電極52(X1,X2,Vdd,GND,OUT,Vc,T)を接続電極20(X1,X2,Vdd,GND,OUT、Vc,T)に接合することにより、集積回路50は、接続電極20、マウント電極24A,24B、実装電極18A〜18Eに電気的に接続する。よって、集積回路50は、実装電極18B(GND)が接地され、実装電極18A(Vdd)から給電を受けることにより駆動する。そして、集積回路50が、パッド電極52(X1,X2)を介して圧電振動片38に交流電圧を印加することにより、圧電振動片38が所定に共振周波数により振動し、その発振信号を実装電極18C(OUT)から出力することができる。また集積回路50への調整電圧の印加は実装電極18C(Vc)を介して行ない、サーミスタに基づいた温度情報は実装電極18Eから出力することができる。   Further, the pad electrode 52 (X1, X2, Vdd, GND, OUT, Vc, T) of the integrated circuit 50 is joined to the connection electrode 20 (X1, X2, Vdd, GND, OUT, Vc, T) to integrate the integrated circuit 50. The circuit 50 is electrically connected to the connection electrode 20, the mount electrodes 24A and 24B, and the mounting electrodes 18A to 18E. Accordingly, the integrated circuit 50 is driven by receiving power from the mounting electrode 18A (Vdd) with the mounting electrode 18B (GND) grounded. The integrated circuit 50 applies an AC voltage to the piezoelectric vibrating piece 38 via the pad electrodes 52 (X1, X2), so that the piezoelectric vibrating piece 38 vibrates at a predetermined resonance frequency, and the oscillation signal is transmitted to the mounting electrode. It can be output from 18C (OUT). The adjustment voltage is applied to the integrated circuit 50 through the mounting electrode 18C (Vc), and temperature information based on the thermistor can be output from the mounting electrode 18E.

図2、図4に示すように、第1の配線60A,60B,60Cは、シート基板54の実装面16において基板領域56の配列の列方向に伸びて配置され、同一行内の実装電極18Aを並列に接続するものである。   As shown in FIGS. 2 and 4, the first wirings 60A, 60B, 60C are arranged to extend in the column direction of the arrangement of the substrate regions 56 on the mounting surface 16 of the sheet substrate 54, and the mounting electrodes 18A in the same row are connected. They are connected in parallel.

第1の配線60Aは、1番、2番、3番の基板領域56の配列に沿って配置され、引き回し電極76を介して、1番、2番、3番の基板領域56の実装電極18Aに接続されている。   The first wiring 60 </ b> A is arranged along the arrangement of the first, second, and third substrate regions 56, and the mounting electrode 18 </ b> A of the first, second, and third substrate regions 56 through the routing electrode 76. It is connected to the.

第1の配線60Bは、1番、2番、3番の基板領域56の配列と、4番、5番、6番の基板領域56の配列と、の間に配置され、引き回し電極76を介して、4番、5番、6番の基板領域56の実装電極18Aに接続されている。   The first wiring 60B is disposed between the array of the first, second, and third substrate regions 56 and the array of the fourth, fifth, and sixth substrate regions 56, and is arranged via the routing electrode 76. The fourth, fifth, and sixth substrate regions 56 are connected to the mounting electrodes 18A.

第1の配線60Cは、4番、5番、6番の基板領域56の配列と、7番、8番、9番の基板領域56の配列と、の間に配置され、引き回し電極76を介して、7番、8番、9番の基板領域56の実装電極18Aに接続されている。   The first wiring 60 </ b> C is disposed between the array of the fourth, fifth, and sixth substrate regions 56 and the array of the seventh, eighth, and ninth substrate regions 56, and is arranged via the routing electrode 76. And connected to the mounting electrodes 18A of the substrate regions 56 of No. 7, No. 8, and No. 9.

また第1の端子62A,62B,62Cは、シート基板54の上面の端子領域58に配置され、貫通電極26を介して第1の配線60A,60B,60Cと電気的に接続されている。   The first terminals 62A, 62B, and 62C are disposed in the terminal region 58 on the upper surface of the sheet substrate 54, and are electrically connected to the first wirings 60A, 60B, and 60C through the through electrode 26.

図2、図4に示すように、第2の配線64A,64B,64Cは、シート基板54の搭載面14において、同一列内のメタライズ28を直列に接続するように配置されている(図5参照)。これにより、第2の配線64Aは、1番、4番、7番の基板領域56の実装電極18Bを並列に接続し、第2の配線64Bは、2番、5番、8番の基板領域56の実装電極18Bを並列に接続し、第2の配線64Cは、3番、6番、9番の基板領域56の実装電極18Bを並列に接続する。   As shown in FIGS. 2 and 4, the second wirings 64A, 64B and 64C are arranged on the mounting surface 14 of the sheet substrate 54 so as to connect the metallizations 28 in the same row in series (FIG. 5). reference). Accordingly, the second wiring 64A connects the mounting electrodes 18B of the first, fourth, and seventh substrate regions 56 in parallel, and the second wiring 64B is connected to the second, fifth, and eighth substrate regions. The 56 mounting electrodes 18B are connected in parallel, and the second wiring 64C connects the mounting electrodes 18B in the third, sixth, and ninth substrate regions 56 in parallel.

図4、図5に示すように、実装電極18Eは、引き回し電極78を介して左隣の基板領域56の実装電極18Bに電気的に接続されている。よって、第2の配線64Aは、2番、5番、8番の基板領域56の実装電極18Eを電気的に並列に接続し、第2の配線64Bは、3番、6番、9番の基板領域56の実装電極18Eを電気的に並列に接続する。また第2の配線64A,64B,64Cは端子領域58に延出し、それぞれ第2の端子66A,66B,66Cに接続されている。   As shown in FIGS. 4 and 5, the mounting electrode 18 </ b> E is electrically connected to the mounting electrode 18 </ b> B in the substrate region 56 on the left side via the routing electrode 78. Therefore, the second wiring 64A electrically connects the mounting electrodes 18E of the second, fifth, and eighth substrate regions 56 in parallel, and the second wiring 64B includes the third, sixth, and ninth wirings. The mounting electrodes 18E in the substrate region 56 are electrically connected in parallel. The second wirings 64A, 64B, 64C extend to the terminal region 58 and are connected to the second terminals 66A, 66B, 66C, respectively.

図2に示すように、第3の配線68Aは、シート基板54の搭載面14において、1番、4番、7番の基板領域56の配列と2番、5番、8番の基板領域56の配列の間で行方向に伸びるように配置されている。   As shown in FIG. 2, the third wiring 68 </ b> A has an array of the first, fourth, and seventh substrate regions 56 and the second, fifth, and eighth substrate regions 56 on the mounting surface 14 of the sheet substrate 54. Are arranged so as to extend in the row direction between the arrays.

図4に示すように、第3の配線68Aは、1番、4番、7番の基板領域56の実装電極18Cと、及び2番、5番、8番の基板領域56の実装電極18Dと、を引き回し電極80及び貫通電極26を介して電気的に並列に接続している。   As shown in FIG. 4, the third wiring 68 </ b> A includes the mounting electrode 18 </ b> C in the first, fourth, and seventh substrate regions 56 and the mounting electrode 18 </ b> D in the second, fifth, and eighth substrate regions 56. Are electrically connected in parallel via the electrode 80 and the through electrode 26.

図2に示すように、第3の配線68Bは、シート基板54の搭載面14において、2番、5番、8番の基板領域56の配列と3番、6番、9番の基板領域56の配列の間で行方向に伸びるように配置されている。   As shown in FIG. 2, the third wiring 68 </ b> B is arranged on the mounting surface 14 of the sheet substrate 54 with an array of the second, fifth, and eighth substrate regions 56 and the third, sixth, and ninth substrate regions 56. Are arranged so as to extend in the row direction between the arrays.

図4に示すように、第3の配線68Bは、2番、5番、8番の基板領域56の実装電極18Cと、3番、6番、9番の基板領域56の実装電極18Dと、を引き回し配線80及び貫通電極26を介して電気的に並列に接続している。
第3の配線68A,68Bは端子領域58まで延出し、それぞれ第3の端子70A,70Bに接続されている。
As shown in FIG. 4, the third wiring 68B includes a mounting electrode 18C in the second, fifth, and eighth substrate regions 56, and a mounting electrode 18D in the third, sixth, and ninth substrate regions 56; Are electrically connected in parallel via the wiring 80 and the through electrode 26.
The third wirings 68A and 68B extend to the terminal region 58 and are connected to the third terminals 70A and 70B, respectively.

図2に示すように、補助配線72Aは、シート基板54の搭載面14において、1番、4番、7番の基板領域56の配列に沿って行方向に伸びるように配置されている。
図4に示すように、補助配線72Aは、1番、4番、7番の基板領域56の実装電極18Eを、引き回し電極82及び貫通電極26を介して電気的に並列に接続している。
As shown in FIG. 2, the auxiliary wiring 72 </ b> A is arranged on the mounting surface 14 of the sheet substrate 54 so as to extend in the row direction along the array of the first, fourth, and seventh substrate regions 56.
As shown in FIG. 4, the auxiliary wiring 72 </ b> A electrically connects the mounting electrodes 18 </ b> E of the first, fourth, and seventh substrate regions 56 in parallel via the routing electrode 82 and the through electrode 26.

図2に示すように、補助配線72Bは、補助配線72Aと、1番、4番、7番の基板領域56の配列と、の間で行方向に伸びるように配置されている。
図4に示すように、補助配線72Bは、1番、4番、7番の基板領域56の実装電極18Dを、引き回し電極82及び貫通電極26を介して電気的に並列に接続している。
As shown in FIG. 2, the auxiliary wiring 72 </ b> B is arranged to extend in the row direction between the auxiliary wiring 72 </ b> A and the array of the first, fourth, and seventh substrate regions 56.
As shown in FIG. 4, the auxiliary wiring 72 </ b> B electrically connects the mounting electrodes 18 </ b> D of the first, fourth, and seventh substrate regions 56 in parallel via the routing electrode 82 and the through electrode 26.

図2に示すように、補助配線72Cは、シート基板54の搭載面14において、3番、6番、9番の基板領域56の配列に沿って行方向に伸びるように配置されている。
図4に示すように、補助配線72Cは、3番、6番、9番の基板領域56の実装電極18Cを、引き回し電極82及び貫通電極26を介して電気的に並列に接続している。補助配線72A,72B,72Cは端子領域58に延出して、それぞれ補助端子74A,74B,74Cに接続されている。
As shown in FIG. 2, the auxiliary wiring 72 </ b> C is arranged on the mounting surface 14 of the sheet substrate 54 so as to extend in the row direction along the arrangement of the third, sixth, and ninth substrate regions 56.
As shown in FIG. 4, the auxiliary wiring 72 </ b> C electrically connects the mounting electrodes 18 </ b> C of the third, sixth, and ninth substrate regions 56 in parallel via the routing electrode 82 and the through electrode 26. The auxiliary wirings 72A, 72B, 72C extend to the terminal region 58 and are connected to the auxiliary terminals 74A, 74B, 74C, respectively.

図3において、左側(4番)の基板領域56(電子部品10)は、集積回路50のパッド電極52(Vc)が、接続電極20(Vc)、引き回し電極22D、貫通電極26、実装電極18D、引き回し電極82、貫通電極26を介して補助配線72B(補助端子74B)に電気的に接続された状態を表している。また、左側(4番)の基板領域56は、集積回路50のパッド電極52(T)が、接続電極20(T)、貫通電極26、実装電極18E、引き回し電極82、貫通電極26を介して補助配線72A(補助端子74A)に電気的に接続された状態を表している。   In FIG. 3, the left side (4th) substrate region 56 (electronic component 10) includes a pad electrode 52 (Vc) of the integrated circuit 50, a connection electrode 20 (Vc), a lead-out electrode 22D, a through electrode 26, and a mounting electrode 18D. The state is shown in which it is electrically connected to the auxiliary wiring 72B (auxiliary terminal 74B) via the lead-out electrode 82 and the through electrode 26. In the left (No. 4) substrate region 56, the pad electrode 52 (T) of the integrated circuit 50 is connected via the connection electrode 20 (T), the through electrode 26, the mounting electrode 18E, the routing electrode 82, and the through electrode 26. The state where it is electrically connected to the auxiliary wiring 72A (auxiliary terminal 74A) is shown.

図3の中央(5番)の基板領域56(電子部品10)は、集積回路50のパッド電極52(T)が、接続電極20(T)、貫通電極26、実装電極18E、引き回し電極78、4番の基板領域56の実装電極18B、貫通電極26、接続電極20(GND)を介してメタライズ28(第2の配線64A、第2の端子66A)に電気的に接続された状態を表している。また中央(5番)の基板領域56は、集積回路50のパッド電極52(OUT)が、接続電極20(OUT)、貫通電極26、実装電極18C、引き回し電極80、貫通電極26を介して第3の配線68B(第3の端子70B)に電気的に接続された状態を表していている。   In the center (number 5) substrate region 56 (electronic component 10) of FIG. 3, the pad electrode 52 (T) of the integrated circuit 50 is connected to the connection electrode 20 (T), the through electrode 26, the mounting electrode 18E, the lead electrode 78, The state where it electrically connected to metallization 28 (2nd wiring 64A, 2nd terminal 66A) via mounting electrode 18B of 4th substrate field 56, penetration electrode 26, and connection electrode 20 (GND) is expressed. Yes. Further, in the central (No. 5) substrate region 56, the pad electrode 52 (OUT) of the integrated circuit 50 is formed through the connection electrode 20 (OUT), the through electrode 26, the mounting electrode 18C, the routing electrode 80, and the through electrode 26. 3 shows a state of being electrically connected to the third wiring 68B (third terminal 70B).

図3の右側は、3番と6番の基板領域56の間であって第2の配線64Cを切断する切断面による図となっているが、第1の端子62Bが、貫通電極26、第1の配線60B、引き回し電極76を介して実装電極18A(図3では不図示)に電気的に接続された状態を表している。   The right side of FIG. 3 is a view of a cut surface between the third and sixth substrate regions 56 and cutting the second wiring 64C, but the first terminal 62B is connected to the through electrode 26 and the second electrode 64C. 1 shows a state in which it is electrically connected to the mounting electrode 18A (not shown in FIG. 3) via one wiring 60B and the routing electrode 76.

本実施形態のシート基板54は、複数の基板領域56と端子領域58を有する焼結前のセラミック基板に貫通電極26を形成するための貫通孔を形成したのちに焼成し、貫通孔に貫通電極26を埋め込むとともに各種配線・電極を、スパッタ等を用いて形成すればよい。   The sheet substrate 54 of the present embodiment is fired after forming a through hole for forming the through electrode 26 in the ceramic substrate before sintering having a plurality of substrate regions 56 and terminal regions 58, and the through electrode is formed in the through hole. 26 and various wirings and electrodes may be formed using sputtering or the like.

本実施形態の電子部品10の製造工程は、シート基板54の各基板領域56に圧電振動片38、集積回路50、キャップ32を実装する。次に、端子領域58に配置された第1の端子62A,62B,62C、第2の端子66A,66B,66Cを任意に選択して各基板領域56(電子部品10)に配置された集積回路50を一つずつ起動させる。起動した集積回路50から出力される発振信号及び温度情報の検査を行なうとともに、その集積回路50に対して調整電圧を印加して各種調整を行う。もちろん集積回路50またはこれに接続した圧電振動片38に不良があった場合には、その基板領域56にかかる電子部品10は除去する。そして、シート基板54を、基板領域56の境界に沿って分割することにより電子部品10を個片化することができる。   In the manufacturing process of the electronic component 10 of the present embodiment, the piezoelectric vibrating piece 38, the integrated circuit 50, and the cap 32 are mounted on each substrate region 56 of the sheet substrate 54. Next, the first terminals 62A, 62B, and 62C and the second terminals 66A, 66B, and 66C arranged in the terminal area 58 are arbitrarily selected, and the integrated circuit arranged in each board area 56 (electronic component 10). Activate 50 one by one. The oscillation signal and temperature information output from the activated integrated circuit 50 are inspected, and various adjustments are made by applying an adjustment voltage to the integrated circuit 50. Of course, when there is a defect in the integrated circuit 50 or the piezoelectric vibrating piece 38 connected thereto, the electronic component 10 over the substrate region 56 is removed. The electronic component 10 can be separated into pieces by dividing the sheet substrate 54 along the boundary of the substrate region 56.

図7に、第2実施形態のシート基板の回路図を示す。なお、以降の説明において前述の実施形態と共通の構成要素には同一の番号を付し、必要な場合を除いてその説明を省略する。   FIG. 7 shows a circuit diagram of the sheet substrate according to the second embodiment. In the following description, the same reference numerals are given to the same components as those in the above-described embodiment, and the description thereof is omitted unless necessary.

第2実施形態のシート基板54Aは、第1実施形態とは異なり第3の配線の向きが異なっている。すなわち、第3の配線68A,68Bは、電子部品10(基板領域56)のうち、互いに隣接する行同士として一方向にそれぞれ配列された電子部品10同士であって、一方の配列に含まれる電子部品10に配置された実装電極18Cと、他方の配列に含まれる電子部品10に配置された実装電極18Dと、をそれぞれ並列に接続している。よって、第3の配線68Aは、1番、2番、3番の電子部品10の実装電極18Dと、4番、5番、6番の電子部品10の実装電極18Cと、をそれぞれ並列に接続している。第3の配線68Bは、4番、5番、6番の電子部品10の実装電極18Dと、7番、8番、9番の電子部品10の実装電極18Cと、をそれぞれ並列に接続している。   Unlike the first embodiment, the sheet substrate 54A of the second embodiment differs in the direction of the third wiring. That is, the third wirings 68A and 68B are electronic components 10 arranged in one direction as rows adjacent to each other among the electronic components 10 (substrate region 56), and are included in one arrangement. A mounting electrode 18C disposed on the component 10 and a mounting electrode 18D disposed on the electronic component 10 included in the other array are connected in parallel. Therefore, the third wiring 68A connects the mounting electrodes 18D of the first, second, and third electronic components 10 and the mounting electrodes 18C of the fourth, fifth, and sixth electronic components 10 in parallel. doing. The third wiring 68B connects the mounting electrodes 18D of the electronic components 10 of Nos. 4, 5, and 6 and the mounting electrodes 18C of the electronic components 10 of Nos. 7, 8, and 9 in parallel. Yes.

また、補助配線72Bが7番、8番、9番の電子部品10の実装電極18Dを並列に接続し、補助配線72Cが、1番、2番、3番の電子部品10の実装電極18Cを並列に接続している。   The auxiliary wiring 72B connects the mounting electrodes 18D of the electronic components 10 of No. 7, 8, and 9 in parallel, and the auxiliary wiring 72C connects the mounting electrodes 18C of the electronic components 10 of No. 1, No. 2, No. 3, and No. 3. Connected in parallel.

図2に対応させると、第3の配線68A,68B、補助配線72B,72Cは、それぞれシート基板54A(シート基板54)の搭載面14に配置すればよい。第3の配線68Aは、1番、2番、3番の基板領域56の配列と、4番、5番、6番の基板領域56の配列の間に配置し、第3の配線68Bは、4番、5番、6番の基板領域56の配列と、7番、8番、9番の基板領域56の配列の間に配置すればよい。また補助配線72Bは、7番、8番、9番の基板領域56の配列に沿って配置し、補助配線72Cは、1番、2番、3番の基板領域56の配列に沿って配置すればよい。第2実施形態のシート基板54Aに配置された電子部品10の検査方法は、第1実施形態と同様なので説明を省略する。   In correspondence with FIG. 2, the third wirings 68A and 68B and the auxiliary wirings 72B and 72C may be arranged on the mounting surface 14 of the sheet substrate 54A (sheet substrate 54), respectively. The third wiring 68A is arranged between the array of the first, second, and third substrate regions 56 and the array of the fourth, fifth, and sixth substrate regions 56, and the third wiring 68B is What is necessary is just to arrange | position between the arrangement | sequence of the 4th, 5th, 6th board | substrate area | region 56, and the arrangement | sequence of the 7th, 8th, 9th board | substrate area | region 56. The auxiliary wiring 72B is arranged along the arrangement of the seventh, eighth, and ninth substrate regions 56, and the auxiliary wiring 72C is arranged along the arrangement of the first, second, and third substrate regions 56. That's fine. The method for inspecting the electronic component 10 arranged on the sheet substrate 54A of the second embodiment is the same as that of the first embodiment, and the description thereof is omitted.

図8に、第3実施形態のシート基板の回路図を示し、図9に、第3実施形態のシート基板の平面図を示す。第3実施形態のシート基板54Bでは、第3の配線68A,68Bを、それぞれ第3の配線68Aa、第3の配線68Ab、第3の配線68Ba、第3の配線68Bbに分割している。   FIG. 8 shows a circuit diagram of the sheet substrate of the third embodiment, and FIG. 9 shows a plan view of the sheet substrate of the third embodiment. In the sheet substrate 54B of the third embodiment, the third wirings 68A and 68B are divided into a third wiring 68Aa, a third wiring 68Ab, a third wiring 68Ba, and a third wiring 68Bb, respectively.

第3の配線68Aaは、1番、4番、7番の電子部品10(基板領域56)の実装電極18Cを並列に接続するとともに、その端部が第3の端子70Aaに接続されている。
第3の配線68Abは、2番、5番、8番の電子部品10の実装電極18Dを並列に接続するとともに、その端部が第3の端子70Abに接続されている。
The third wiring 68Aa connects the mounting electrodes 18C of the first, fourth, and seventh electronic components 10 (substrate region 56) in parallel, and the end thereof is connected to the third terminal 70Aa.
The third wiring 68Ab connects the mounting electrodes 18D of the second, fifth, and eighth electronic components 10 in parallel, and the end thereof is connected to the third terminal 70Ab.

第3の配線68Baは、2番、5番、8番の電子部品10の実装電極18Cを並列に接続するとともに、その端部が第3の端子70Baに接続されている。
第3の配線68Bbは、3番、6番、9番の電子部品10の実装電極18Dを並列に接続するとともに、その端部が第3の端子70Bbに接続されている。
The third wiring 68Ba connects the mounting electrodes 18C of the second, fifth, and eighth electronic components 10 in parallel, and the end thereof is connected to the third terminal 70Ba.
The third wiring 68Bb connects the mounting electrodes 18D of the third, sixth, and ninth electronic components 10 in parallel, and the end thereof is connected to the third terminal 70Bb.

上記構成において、5番の電子部品10を起動するためには、第1の端子62Bと第2の端子66Bをオン状態とする。そして、5番の電子部品10の温度情報は第2の端子66Aから取り込み、5番の電子部品10に対する調整電圧の印加は第3の端子70Abから行い、5番の電子部品10の出力は第3の端子70Baから取り出すことができる。   In the above configuration, in order to activate the fifth electronic component 10, the first terminal 62B and the second terminal 66B are turned on. The temperature information of the fifth electronic component 10 is taken in from the second terminal 66A, and the adjustment voltage is applied to the fifth electronic component 10 from the third terminal 70Ab, and the output of the fifth electronic component 10 is output from the second terminal 66A. 3 terminal 70Ba.

図9に示すように、第3の配線68Aa,68Ab,68Ba,68Bbは、それぞれシート基板54Bの搭載面14に配置すればよい。第3の配線68Aa,68Abは、1番、4番、7番の基板領域56の配列と、2番、5番、8番の基板領域56の配列の間で互いに平行となるように配置すればよい。第3の配線68Ba,68Bbは、2番、5番、8番の基板領域56の配列と、3番、6番、9番の基板領域56の配列の間で互いに平行となるように配置すればよい。   As shown in FIG. 9, the third wirings 68Aa, 68Ab, 68Ba, and 68Bb may be arranged on the mounting surface 14 of the sheet substrate 54B. The third wires 68Aa and 68Ab are arranged so as to be parallel to each other between the arrangement of the first, fourth, and seventh substrate regions 56 and the arrangement of the second, fifth, and eighth substrate regions 56. That's fine. The third wires 68Ba and 68Bb are arranged so as to be parallel to each other between the arrangement of the second, fifth, and eighth substrate regions 56 and the arrangement of the third, sixth, and ninth substrate regions 56. That's fine.

第1実施形態、第2実施形態において、第3の端子70A,70Bは、電子部品10の出力を取り出す目的と、電子部品10に調整電圧を印加する目的で用いられる。よって、起動した電子部品10に調整電圧を印加すると、その電子部品10と同じ第3の端子に接続された電子部品10の実装電極18Cにも調整電圧が印加され、この調整電圧が集積回路50に悪影響を与える場合がある。そこで、本実施形態では、電子部品10の出力を取り出す配線と、電子部品10に調整電圧を印加する配線を分けている。   In the first embodiment and the second embodiment, the third terminals 70 </ b> A and 70 </ b> B are used for the purpose of taking out the output of the electronic component 10 and for applying an adjustment voltage to the electronic component 10. Therefore, when the adjustment voltage is applied to the activated electronic component 10, the adjustment voltage is also applied to the mounting electrode 18 </ b> C of the electronic component 10 connected to the same third terminal as the electronic component 10, and this adjustment voltage is applied to the integrated circuit 50. May be adversely affected. Therefore, in the present embodiment, wiring for extracting the output of the electronic component 10 and wiring for applying an adjustment voltage to the electronic component 10 are separated.

図10に、本実施形態の電子部品を搭載した電子機器(携帯端末)の模式図を示す。図10において、携帯端末88(PHSを含む)は、複数の操作ボタン90、受話口92及び送話口94を備え、操作ボタン90と受話口92との間には表示部96が配置されている。最近では、このような携帯端末88においてもGPS機能を備えている。そこで、携帯端末88には、GPS回路のクロック源として本実施形態の電子部品10(圧電デバイス)が内蔵されている。   In FIG. 10, the schematic diagram of the electronic device (mobile terminal) which mounts the electronic component of this embodiment is shown. In FIG. 10, the portable terminal 88 (including PHS) includes a plurality of operation buttons 90, an earpiece 92 and a mouthpiece 94, and a display unit 96 is disposed between the operation buttons 90 and the earpiece 92. Yes. Recently, the portable terminal 88 has a GPS function. Therefore, the portable terminal 88 incorporates the electronic component 10 (piezoelectric device) of the present embodiment as a clock source for the GPS circuit.

なお、本実施形態の電子部品10を備える電子機器は、上述の携帯端末88のほかに、高機能携帯、デジタルスチルカメラ、パーソナルコンピュータ、ラップトップ型パーソナルコンピュータ、テレビ、ビデオカメラ、ビデオテープレコーダ、カーナビゲーション装置、ページャ、インクジェット式吐出装置、電子手帳、電卓、電子ゲーム機器、ワードプロセッサ、ワークステーション、テレビ電話、防犯用テレビモニタ、電子双眼鏡、POS端末、医療機器(例えば、電子体温計、血圧計、血糖計、心電図計測装置、超音波診断装置、電子内視鏡)、魚群探知機、各種測定機器、計器類(例えば、車両、航空機、船舶の計器類)、フライトシミュレータ等に適用することができる。   In addition, the electronic device including the electronic component 10 according to the present embodiment includes, in addition to the portable terminal 88 described above, a high-functionality portable, a digital still camera, a personal computer, a laptop personal computer, a television, a video camera, a video tape recorder, Car navigation device, pager, inkjet discharge device, electronic notebook, calculator, electronic game device, word processor, workstation, video phone, TV monitor for crime prevention, electronic binoculars, POS terminal, medical device (for example, electronic thermometer, blood pressure monitor, It can be applied to blood glucose meters, electrocardiogram measuring devices, ultrasound diagnostic devices, electronic endoscopes), fish detectors, various measuring instruments, instruments (eg, vehicles, aircraft, ship instruments), flight simulators, etc. .

10………電子部品、12………ベース基板、14………搭載面、16………実装面、18A〜18E………実装電極、20………接続電極、22A〜22D………引き回し電極、24A,24B………マウント電極、26………貫通電極、28………メタライズ、32………キャップ、38………圧電振動片、40………振動部、42………マウント部、44A,44B………励振電極、46A,46B………引出電極、48A,48B………導電性接着剤、50………集積回路、52………パッド電極、54,54A,54B………シート基板、56………基板領域、58………端子領域、60A〜60C………第1の配線、62A〜62C………第1の端子、64A〜64C………第2の配線、66A〜66C………第2の端子、68A,68Aa,68Aa,68B,68ba,68Bb………第3の配線、70A,70Aa,70Ab,70B,70Ba,70Bb………第3の端子、72A〜72C………補助配線、74A〜74C………補助端子、76………引き回し電極、78………引き回し電極、80………引き回し電極、82………引き回し電極、88………携帯端末、90………操作ボタン、92………受話口、94………送話口、96………表示部。 DESCRIPTION OF SYMBOLS 10 ......... Electronic component, 12 ......... Base substrate, 14 ......... Mounting surface, 16 ......... Mounting surface, 18A-18E ......... Mounting electrode, 20 ...... Connection electrode, 22A-22D ......... Lead electrode, 24A, 24B ......... Mount electrode, 26 ......... Penetration electrode, 28 ......... Metalized, 32 ......... Cap, 38 ......... Piezoelectric vibrating piece, 40 ...... Vibrating part, 42 ......... Mount part, 44A, 44B ... Excitation electrode, 46A, 46B ... Extraction electrode, 48A, 48B ... Conductive adhesive, 50 ... Integrated circuit, 52 ... Pad electrode, 54, 54A, 54B ......... Sheet substrate, 56 ......... Board area, 58 ......... Terminal area, 60A-60C ......... First wiring, 62A-62C ......... First terminal, 64A-64C ......... No. 2 wirings, 66A to 66C..., Second terminal, 68 , 68Aa, 68Aa, 68B, 68ba, 68Bb ......... Third wiring, 70A, 70Aa, 70Ab, 70B, 70Ba, 70Bb ......... Third terminal, 72A-72C ......... Auxiliary wiring, 74A-74C ... ...... Auxiliary terminal, 76 ..... Leading electrode, 78 ..... Leading electrode, 80 ..... Leading electrode, 82 ....... Leading electrode, 88 ..... Portable terminal, 90 ..... Operation buttons, 92 .... ... earpiece, 94 ..... mouthpiece, 96 ..... display part.

Claims (7)

マトリックス状に複数配列された基板領域を有するとともに、各基板領域に電子素子が配置され、前記電子素子と電気的に接続する第1の実装電極及び第2の実装電極が各基板領域に配置されるシート基板であって、
前記第1の実装電極を、前記基板領域の行ごとに並列に接続する第1の端子と、
前記第2の実装電極を、前記基板領域の列ごとに並列に接続する第2の端子と、を有し、
前記電子素子のうち、選択された前記第1の端子及び前記第2の端子により特定される任意の前記電子素子を起動可能としたことを特徴とするシート基板。
A plurality of substrate regions are arranged in a matrix, electronic elements are disposed in each substrate region, and first and second mounting electrodes that are electrically connected to the electronic elements are disposed in each substrate region. A sheet substrate,
A first terminal for connecting the first mounting electrode in parallel for each row of the substrate region;
A second terminal for connecting the second mounting electrode in parallel for each column of the substrate region;
A sheet substrate characterized in that, among the electronic elements, any of the electronic elements specified by the selected first terminal and second terminal can be activated.
各基板領域に配置され、前記電子素子と電気的に接続する第3の実装電極及び第4の実装電極と、
前記基板領域のうち、互いに隣接する行同士または列同士として一方向にそれぞれ配列された前記基板領域同士であって、一方の配列に含まれる前記基板領域に配置された前記第3の実装電極と、他方の配列に含まれる前記基板領域に配置された前記第4の実装電極と、をそれぞれ並列に接続する第3の端子と、を有することを特徴とする請求項1に記載のシート基板。
A third mounting electrode and a fourth mounting electrode disposed in each substrate region and electrically connected to the electronic element;
Among the substrate regions, the substrate regions arranged in one direction as rows or columns adjacent to each other, and the third mounting electrodes arranged in the substrate region included in one of the arrays The sheet substrate according to claim 1, further comprising a third terminal that connects the fourth mounting electrodes disposed in the substrate region included in the other array in parallel.
各基板領域には、前記電子素子に接合する第5の実装電極が配置され、
前記第2の端子は、
前記基板領域のうち、互いに隣接する列同士として一方向にそれぞれ配列された前記基板領域同士であって、一方の配列に含まれる前記基板領域に配置された前記第2の実装電極と、他方の配列に含まれる前記基板領域に配置された前記第5の実装電極と、をそれぞれ並列に接続していることを特徴とする請求項1または2に記載のシート基板。
A fifth mounting electrode that is bonded to the electronic element is disposed in each substrate region,
The second terminal is
Among the substrate regions, the substrate regions arranged in one direction as rows adjacent to each other, the second mounting electrodes arranged in the substrate region included in one array, and the other The sheet substrate according to claim 1, wherein the fifth mounting electrodes arranged in the substrate region included in the array are connected in parallel.
請求項1乃至3のいずれか1項に記載のシート基板の各基板領域に前記電子素子を配置し、前記シート基板を前記基板領域の境界に沿って分割して個片化されたことを特徴とする電子部品。   The electronic device is arranged in each substrate region of the sheet substrate according to claim 1, and the sheet substrate is divided into individual pieces along a boundary of the substrate region. And electronic parts. 請求項4に記載の電子部品を搭載したことを特徴とする電子機器。   An electronic device comprising the electronic component according to claim 4. マトリックス状に複数配列された基板領域を有するシート基板に対し、各基板領域に電子素子を配置し、前記電子素子と電気的に接続する第1の実装電極及び第2の実装電極を各基板領域に配置することにより、前記シート基板において基板領域ごとに構成された電子部品の検査方法であって、
前記第1の実装電極を、前記基板領域の行ごとに第1の端子に接続し、
前記第2の実装電極を、前記基板領域の列ごとに第2の端子に接続し、
前記電子素子のうち、選択された前記第1の端子及び前記第2の端子により特定される任意の前記電子素子を起動することを特徴とする電子部品の検査方法。
With respect to a sheet substrate having a plurality of substrate regions arranged in a matrix, an electronic element is disposed in each substrate region, and a first mounting electrode and a second mounting electrode that are electrically connected to the electronic element are connected to each substrate region. An electronic component inspection method configured for each substrate region in the sheet substrate,
Connecting the first mounting electrode to a first terminal for each row of the substrate region;
Connecting the second mounting electrode to a second terminal for each column of the substrate region;
A method of inspecting an electronic component, comprising: activating any of the electronic elements specified by the selected first terminal and the second terminal.
マトリックス状に複数配列された基板領域を有するシート基板に対し、各基板領域に電子素子を配置し、前記電子素子と電気的に接続する第1の実装電極及び第2の実装電極を各基板領域に配置することにより、前記シート基板において基板領域ごとに構成された電子部品の製造方法であって、
前記第1の実装電極を、前記基板領域の行ごとに並列に接続する第1の端子と、前記第2の実装電極を、前記基板領域の列ごとに並列に接続する第2の端子と、を配置する第1工程と、
前記電子素子のうち、選択された前記第1の端子及び前記第2の端子により特定される任意の前記電子素子を起動する第2工程と、
前記シート基板を前記基板領域の境界に沿って分割する第3工程と、
を有することを特徴とする電子部品の製造方法。
With respect to a sheet substrate having a plurality of substrate regions arranged in a matrix, an electronic element is disposed in each substrate region, and a first mounting electrode and a second mounting electrode that are electrically connected to the electronic element are connected to each substrate region. A method of manufacturing an electronic component configured for each substrate region in the sheet substrate,
A first terminal for connecting the first mounting electrode in parallel for each row of the substrate region; a second terminal for connecting the second mounting electrode in parallel for each column of the substrate region; A first step of arranging
A second step of activating any of the electronic elements identified by the selected first terminal and the second terminal;
A third step of dividing the sheet substrate along a boundary of the substrate region;
A method for manufacturing an electronic component, comprising:
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