JP2013206920A - Module including circuit element - Google Patents

Module including circuit element Download PDF

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JP2013206920A
JP2013206920A JP2012071048A JP2012071048A JP2013206920A JP 2013206920 A JP2013206920 A JP 2013206920A JP 2012071048 A JP2012071048 A JP 2012071048A JP 2012071048 A JP2012071048 A JP 2012071048A JP 2013206920 A JP2013206920 A JP 2013206920A
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alloy
copper plate
circuit element
tin
electrode
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JP5723314B2 (en
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Masanori Usui
正則 臼井
Toshiichi Sato
敏一 佐藤
Masaki Aoshima
正貴 青島
Toru Tanaka
徹 田中
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Toyota Central R&D Labs Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

PROBLEM TO BE SOLVED: To realize a module which achieves stable joint strength between an electrode of a circuit element and a copper plate.SOLUTION: A module 100 includes: a copper plate 10; a circuit element 30; and an alloy layer 20 that joins the copper plate 10 to an electrode 32 of the circuit element 30. The alloy layer 20 includes a first portion 22, a second portion 26, and a third portion 24. The first portion 22 is positioned on the copper plate 10 side and is made of a first type alloy composed of tin and copper. The second portion 26 is positioned on the electrode 32 side of the circuit element 30 and is made of a second type alloy including at least one kind of metal, which is selected from gold, nickel, and silver, and tin. The third portion 24 is positioned between the first portion 22 and the second portion 26, and the first type alloy and the second type alloy are mixed therein.

Description

本明細書は、銅板と回路素子の電極が接合されたモジュールに関する技術を開示する。   This specification discloses the technique regarding the module with which the electrode of the copper plate and the circuit element was joined.

基板と回路素子の電極が接合されたモジュールでは、すずを材料とするはんだ(以下、すずはんだと称する)を用いて基板と回路素子の電極を接合することがあり、その一例が特許文献1に開示されている。特許文献1には、半導体装置の裏面電極と銅製の回路パターン(以下、銅板と称する)を、すずはんだで接合する技術が開示されている。特許文献1では、裏面電極の金属とすずが合金化し、銅とすずが合金化することにより、銅板と半導体装置の裏面電極が接合される。   In a module in which a substrate and circuit element electrodes are joined, solder made of tin (hereinafter referred to as tin solder) may be used to join the substrate and circuit element electrodes. It is disclosed. Patent Document 1 discloses a technique for joining a back electrode of a semiconductor device and a copper circuit pattern (hereinafter referred to as a copper plate) with tin solder. In Patent Document 1, the metal of the back electrode and tin are alloyed, and the copper and tin are alloyed, whereby the copper plate and the back electrode of the semiconductor device are joined.

特開2011−187782号公報JP 2011-187882 A

回路素子は駆動中に発熱する。回路素子の電極と銅板の間に合金化していないすずはんだが残存していると、回路素子の使用中にすずはんだが軟化し、回路素子と銅板の接合強度が低下する。すなわち、回路素子と銅板の接合強度が安定しない。特許文献1の技術では、スクリーン印刷技術を利用して銅板上にすずはんだを形成しているので、すずはんだが厚く形成される。このため、回路素子の電極と銅板の間に、合金化していないすずはんだが残存する。本明細書では、回路素子の電極と銅板の接合強度が安定したモジュールを提供する。   The circuit element generates heat during driving. If tin solder that is not alloyed remains between the electrode of the circuit element and the copper plate, the tin solder is softened during use of the circuit element, and the bonding strength between the circuit element and the copper plate is reduced. That is, the bonding strength between the circuit element and the copper plate is not stable. In the technique of Patent Document 1, tin solder is formed on a copper plate using a screen printing technique, so that tin solder is formed thick. For this reason, unalloyed tin solder remains between the electrode of the circuit element and the copper plate. The present specification provides a module in which the bonding strength between an electrode of a circuit element and a copper plate is stable.

本明細書で開示する技術は、回路素子の電極と銅板との間に、合金層だけが介在していることを特徴とする。換言すると、回路素子の電極と銅板の間に、合金化していないすずはんだが残存していない。本明細書で開示する技術では、すずはんだを薄く形成することで、回路素子の電極と銅板との間に合金層だけが介在するモジュールを実現する。従来は、すずはんだを厚く形成することで、回路素子の電極と銅板を確実に接合しようとしてした。しかしながら、本明細書で開示する技術は、従来の技術常識に反して、すずはんだを薄く形成して回路素子の電極と銅板を確実に接合する技術である。   The technique disclosed in this specification is characterized in that only an alloy layer is interposed between an electrode of a circuit element and a copper plate. In other words, unalloyed tin solder does not remain between the electrode of the circuit element and the copper plate. In the technique disclosed in the present specification, a module in which only an alloy layer is interposed between an electrode of a circuit element and a copper plate is realized by forming tin solder thinly. Conventionally, an attempt has been made to reliably join the electrode of the circuit element and the copper plate by forming a thick tin solder. However, the technique disclosed in the present specification is a technique for securely joining the electrode of the circuit element and the copper plate by forming a thin tin solder, contrary to conventional common sense.

本明細書で開示するモジュールは、銅板と、回路素子と、銅板と回路素子の電極を接合する合金層を備えている。合金層は、第1部分と第2部分と第3部分を有している。第1部分は、銅板側に位置しており、すずと銅からなる第1種類の合金である。第2部分は、回路素子の電極側に位置しており、金、ニッケル、銀の少なくとも1種の金属とすずを含む第2種類の合金である。第3部分は、第1部分と第2部分の間に位置しており、第1種類の合金と第2種類の合金が混在している。この態様のモジュールでは、合金化していないすずが残存していないので、第1部分と第2部分の間に、第1種類の合金と第2種類の合金が混在した第3部分が形成される。第3部分では、第1種類の合金と第2種類の合金が絡み合うように存在している。より詳細には、第3部分では、第2部分から樹枝状に突出した第2種類の合金が、第1種類の合金に囲まれている。よって、第1部分と第2部分が強固に接合される。このような特徴を有することにより、本明細書で開示するモジュールは、回路素子の電極と銅板の接合強度が安定している。   The module disclosed in this specification includes a copper plate, a circuit element, and an alloy layer that joins the copper plate and the electrode of the circuit element. The alloy layer has a first portion, a second portion, and a third portion. The first portion is located on the copper plate side and is a first type alloy made of tin and copper. The second portion is located on the electrode side of the circuit element, and is a second type alloy containing at least one metal of gold, nickel, and silver and tin. The third part is located between the first part and the second part, and the first type alloy and the second type alloy are mixed. In the module according to this aspect, since no unalloyed tin remains, a third portion in which the first type alloy and the second type alloy are mixed is formed between the first portion and the second portion. . In the third part, the first type alloy and the second type alloy exist so as to be intertwined. More specifically, in the third portion, the second type alloy protruding in a dendritic shape from the second portion is surrounded by the first type alloy. Therefore, the first part and the second part are firmly joined. With such a feature, the module disclosed in this specification has a stable bonding strength between the electrode of the circuit element and the copper plate.

本明細書で開示される技術によると、回路素子の電極と銅板の接合強度が安定したモジュールを提供することができる。   According to the technique disclosed in this specification, a module in which the bonding strength between the electrode of the circuit element and the copper plate is stable can be provided.

半導体モジュールの要部断面図を示す。The principal part sectional view of a semiconductor module is shown. 半導体素子と銅板の拡大断面図を示す。The expanded sectional view of a semiconductor element and a copper plate is shown. 合金層の拡大断面図を示す。The expanded sectional view of an alloy layer is shown. 半導体モジュールの製造工程を示す(1)。The manufacturing process of a semiconductor module is shown (1). 半導体モジュールの製造工程を示す(2)。The manufacturing process of a semiconductor module is shown (2).

以下、本明細書で開示する実施例の技術的特徴の幾つかを記す。なお、以下に記す事項は、各々単独で技術的な有用性を有している。   Hereinafter, some technical features of the embodiments disclosed in this specification will be described. The items described below have technical usefulness independently.

(特徴1)モジュールは、銅板と、回路素子と、銅板と回路素子の電極を接合する合金層を備えている。合金層は、銅板側に位置しており、すずと銅からなる第1種類の合金である第1部分を備えていてもよい。第1種類の合金は、すずと銅のみの合金であり、他の金属を含んでいなくてもよい。また、合金層は、回路素子の電極側に位置しており、金、ニッケル、銀の少なくとも1種の金属とすずを含む第2種類の合金である第2部分を備えていてもよい。さらに、合金層は、第1部分と第2部分の間に位置しており、第1種類の合金と第2種類の合金が混在している第3部分を有していてもよい。第3部分では、少なくとも第1種類の合金と第2種類の合金が混在しており、他の種類の合金が含まれていてもよい。ここで、「種類」とは、広義に解釈されるものである。例えば、含有する金属原子が同一であり、それらの組成比が異なる場合も、同一の「種類」と解釈されるものである。
(特徴2)銅板は、絶縁基板に含まれる回路パターンであってもよい。絶縁基板は、回路素子と冷却器の間に配置され、回路素子と冷却器を電気的に絶縁するために用いられる。
(特徴3)回路素子は、縦型の半導体素子であってもよい。また、縦型の半導体素子の一例には、IGBT,MOSFET,ダイオード,サイリスタが挙げられる。
(特徴4)合金層は、銅板と回路素子の電極を結ぶ方向で観測したときに、複数種類の合金のみで構成されており、単一の金属層が含まれていなく。
(特徴5)第2種類の合金は、ニッケルを含んでいてもよい。ニッケルを含む合金は、第1部分に向けて突出しやすい。そのため、第1種類の合金と第2種類の合金が混在した第3部分が形成されやすい。
(特徴6)第2種類の合金は、CuNi3−xSn(0≦x≦2)で表される合金であってもよい。第2種類の合金に含まれる銅(Cu)は、銅板に由来する。第2種類の合金が上記式で表されることは、銅板を構成していた銅原子が、すずを越えて、電極を構成していたニッケル(Ni)と合金化したことを示している。銅板と回路素子の電極との間に介在していたすずが、確実に合金化したことを示している。CuNi3−xSn(0≦x≦2)で表される合金は、[Cu(Ni)]Sn,CuNiSnであってもよい。
(特徴7)第2部分には、電極を構成していた金(Au)が含まれている部分が存在してもよい。
(特徴8)第1部分の合金は、CuSnで表される合金であってもよい。
(Feature 1) The module includes a copper plate, a circuit element, and an alloy layer that joins the copper plate and the electrode of the circuit element. The alloy layer is located on the copper plate side and may include a first portion which is a first type alloy made of tin and copper. The first type of alloy is an alloy of only tin and copper, and may not contain other metals. The alloy layer is located on the electrode side of the circuit element, and may include a second portion that is a second type alloy including at least one metal of gold, nickel, and silver and tin. Furthermore, the alloy layer may be located between the first portion and the second portion, and may have a third portion in which the first type alloy and the second type alloy are mixed. In the third portion, at least the first type alloy and the second type alloy are mixed, and other types of alloys may be included. Here, the “type” is interpreted in a broad sense. For example, even when the contained metal atoms are the same and the composition ratios thereof are different, they are interpreted as the same “kind”.
(Feature 2) The copper plate may be a circuit pattern included in the insulating substrate. The insulating substrate is disposed between the circuit element and the cooler, and is used for electrically insulating the circuit element and the cooler.
(Feature 3) The circuit element may be a vertical semiconductor element. Examples of vertical semiconductor elements include IGBTs, MOSFETs, diodes, and thyristors.
(Feature 4) The alloy layer is composed of only a plurality of types of alloys when observed in the direction connecting the copper plate and the electrode of the circuit element, and does not include a single metal layer.
(Feature 5) The second type of alloy may contain nickel. The alloy containing nickel tends to protrude toward the first portion. Therefore, the third portion in which the first type alloy and the second type alloy are mixed is easily formed.
(Feature 6) The second type of alloy may be an alloy represented by Cu x Ni 3-x Sn (0 ≦ x ≦ 2). Copper (Cu) contained in the second type alloy is derived from the copper plate. The fact that the second type alloy is represented by the above formula indicates that the copper atoms constituting the copper plate have been alloyed with nickel (Ni) constituting the electrode beyond tin. This shows that the tin intervening between the copper plate and the electrode of the circuit element is surely alloyed. The alloy represented by Cu 2 Ni 3-x Sn (0 ≦ x ≦ 2) may be [Cu (Ni)] 3 Sn, CuNi 2 Sn.
(Characteristic 7) The second portion may include a portion containing gold (Au) constituting the electrode.
(Feature 8) The alloy of the first portion may be an alloy represented by Cu 3 Sn.

図1〜図3に示すように、半導体モジュール100は、冷却器2と、放熱板4と、絶縁基板12と、合金層20と、半導体素子30を備える。半導体素子30は、半導体層34と裏面電極32を有している。なお、半導体素子30は、表面電極及びゲート電極等の他の要素も有しているが、説明の便宜のために省略する。冷却器2は、複数の水路2aを備えている。放熱板4は、冷却器2と絶縁基板12に接合されており、半導体素子30で発生した熱を冷却器2に伝熱する。絶縁基板12は、銅板6と絶縁体8と銅板10が積層されたDBC(Direct Bonding Copper)基板である。絶縁体8の材料として、窒化珪素(Si),窒化アルミニウム(AlN),酸化アルミニウム(Al)等を用いることができる。絶縁基板12は、半導体素子30の裏面電極32と放熱板4を絶縁しながら、半導体素子30で発生した熱を放熱板4に伝熱する。 As shown in FIGS. 1 to 3, the semiconductor module 100 includes a cooler 2, a radiator plate 4, an insulating substrate 12, an alloy layer 20, and a semiconductor element 30. The semiconductor element 30 has a semiconductor layer 34 and a back electrode 32. The semiconductor element 30 also has other elements such as a surface electrode and a gate electrode, which are omitted for convenience of explanation. The cooler 2 includes a plurality of water channels 2a. The heat radiating plate 4 is bonded to the cooler 2 and the insulating substrate 12, and transfers heat generated in the semiconductor element 30 to the cooler 2. The insulating substrate 12 is a DBC (Direct Bonding Copper) substrate in which a copper plate 6, an insulator 8, and a copper plate 10 are laminated. As a material of the insulator 8, silicon nitride (Si 3 N 4 ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), or the like can be used. The insulating substrate 12 transfers the heat generated in the semiconductor element 30 to the heat radiating plate 4 while insulating the back surface electrode 32 of the semiconductor element 30 and the heat radiating plate 4.

合金層20は、銅板10と半導体素子30の裏面電極32との間に介在している。合金層20の厚みT20は、5〜20μmに調整されている。合金層20は、合金に含まれている金属の種類により、第1部分22と第2部分26と第3部分24に区別することができる。第1部分22は、銅板10側に位置しており、すず(Sn)と銅(Cu)からなる合金である。第1部分22は、銅板10上に形成されたすずと銅板10とが合金化したものである。第1部分22の合金は、CuSnである。すずと銅からなる合金は、第1種類の合金の一例である。 The alloy layer 20 is interposed between the copper plate 10 and the back electrode 32 of the semiconductor element 30. The thickness T20 of the alloy layer 20 is adjusted to 5 to 20 μm. The alloy layer 20 can be distinguished into a first portion 22, a second portion 26, and a third portion 24 depending on the type of metal contained in the alloy. The first portion 22 is located on the copper plate 10 side and is an alloy made of tin (Sn) and copper (Cu). The first portion 22 is an alloy of tin formed on the copper plate 10 and the copper plate 10. The alloy of the first portion 22 is Cu 3 Sn. An alloy composed of tin and copper is an example of the first type of alloy.

第2部分26は、裏面電極32側に位置しており、銅とニッケル(Ni)とすずを主体とする合金である。第2部分26は、裏面電極32を構成している金属(ニッケル)と、銅板10上に形成されたすずと、銅板10から拡散された銅とが合金化したものである。第2部分26の合金は、CuNi3−xSn(0≦x≦2)で表すことができる。第2部分26の合金は、[Cu(Ni)]Snである。銅とニッケルとすずを主体とする合金は、第2種類の合金の一例である。 The second portion 26 is located on the back electrode 32 side and is an alloy mainly composed of copper, nickel (Ni), and tin. The second portion 26 is an alloy of metal (nickel) constituting the back electrode 32, tin formed on the copper plate 10, and copper diffused from the copper plate 10. The alloy of the second portion 26 can be represented by Cu x Ni 3-x Sn (0 ≦ x ≦ 2). The alloy of the second portion 26 is [Cu (Ni)] 3 Sn. An alloy mainly composed of copper, nickel, and tin is an example of the second type of alloy.

第3部分24は、第1部分22と第2部分26の間に位置している。第3部分24では、第2部分26の合金26aが、第1部分22の合金22a内に樹枝状に突出している。合金26aは、合金22aに囲まれている。その結果、第3部分24では、第1種類の合金と第2種類の合金が混在している。第3部分24によって、第1部分22と第2部分26が強固に接合される。   The third portion 24 is located between the first portion 22 and the second portion 26. In the third portion 24, the alloy 26 a of the second portion 26 protrudes in a dendritic manner within the alloy 22 a of the first portion 22. The alloy 26a is surrounded by the alloy 22a. As a result, in the third portion 24, the first type alloy and the second type alloy are mixed. The first portion 22 and the second portion 26 are firmly joined by the third portion 24.

上記したように、半導体モジュール100では、銅板10と裏面電極32の間に合金層20だけが存在する。合金層20の融点が高いので、半導体素子30が発熱しても、合金層20の軟化が抑制される。その結果、半導体素子30の裏面電極32と銅板10との接合が維持される。また、半導体素子30が発熱しても、合金化していないすずの合金化が進行することがない。半導体モジュール100の使用中に合金化が進行すると、銅板10と裏面電極32の間にボイドが発生することがある。銅板10と裏面電極32の間に合金層20だけが存在することにより、信頼性の高い半導体モジュール100を実現することができる。   As described above, in the semiconductor module 100, only the alloy layer 20 exists between the copper plate 10 and the back electrode 32. Since the melting point of the alloy layer 20 is high, softening of the alloy layer 20 is suppressed even if the semiconductor element 30 generates heat. As a result, the bonding between the back electrode 32 of the semiconductor element 30 and the copper plate 10 is maintained. Further, even if the semiconductor element 30 generates heat, the alloying of unalloyed tin does not proceed. When alloying proceeds during use of the semiconductor module 100, voids may be generated between the copper plate 10 and the back electrode 32. Since only the alloy layer 20 exists between the copper plate 10 and the back electrode 32, the highly reliable semiconductor module 100 can be realized.

半導体モジュール100の製造方法を説明する。ここでは、銅板10と半導体素子30の裏面電極32の接合方法のみを説明する。なお、絶縁基板12の製造方法、冷却器2と放熱板4の接合方法、放熱板4と絶縁基板12の接合方法は、公知の方法を用いることができる。   A method for manufacturing the semiconductor module 100 will be described. Here, only the bonding method of the copper plate 10 and the back electrode 32 of the semiconductor element 30 will be described. In addition, the manufacturing method of the insulated substrate 12, the joining method of the cooler 2 and the heat sink 4, and the joining method of the heat sink 4 and the insulated substrate 12 can use a well-known method.

まず、図4に示すように、銅板10上にすず膜40を蒸着する。すず膜40は、スパッタ法、めっき法、EB(Electron Beam)法、抵抗加熱法等を用いて蒸着することができる。蒸着によって銅板10上にすず膜40を形成するので、薄膜のすず膜40を形成することができる。すず膜40の厚みT40は、5〜10μmに調整する。   First, as shown in FIG. 4, a tin film 40 is deposited on the copper plate 10. The tin film 40 can be deposited using a sputtering method, a plating method, an EB (Electron Beam) method, a resistance heating method, or the like. Since the tin film 40 is formed on the copper plate 10 by vapor deposition, a thin tin film 40 can be formed. The thickness T40 of the tin film 40 is adjusted to 5 to 10 μm.

ここで、銅板10に接合される前の半導体素子30について説明する。半導体素子30は、半導体層34と裏面電極32を備えている。裏面電極32は、アルミニウム(Al)とチタン(Ti)とニッケルと金がこの順に積層された積層電極である。アルミニウムが、半導体層34に接触している。アルミニウムとチタンがオーミック接触部36を形成し、ニッケルと金が接合部38を形成している。銅板10と裏面電極32を接合するときは、接合部38をすず膜40に接触させる。   Here, the semiconductor element 30 before being bonded to the copper plate 10 will be described. The semiconductor element 30 includes a semiconductor layer 34 and a back electrode 32. The back electrode 32 is a laminated electrode in which aluminum (Al), titanium (Ti), nickel, and gold are laminated in this order. Aluminum is in contact with the semiconductor layer 34. Aluminum and titanium form an ohmic contact 36, and nickel and gold form a joint 38. When the copper plate 10 and the back electrode 32 are bonded, the bonding portion 38 is brought into contact with the tin film 40.

次に、図5に示すように、接合部38をすず膜40に接触させた状態で、半導体素子30と銅板10を250〜450℃で熱処理する。熱処理を行うことにより、矢印50に示すように、すず膜40と接合部38の金属が相互に拡散する。また、矢印52,54に示すように、すず膜40と銅板10の金属も相互に拡散する。なお、銅は拡散しやすい金属なので、矢印54に示すように、すず膜40を超えて、接合部38にまで拡散する。その結果、図3に示すように、第1部分22が銅板10側に形成され、第2部分26が裏面電極32側に形成される。その後、第2部分26の合金26aが、第1部分22に向けて樹枝状に突出して、第1部分22の合金22aに囲まれる。その結果、第1部分22の合金(第1種類の合金)と第2部分26の合金(第2種類の合金)が混在した第3部分が形成される。   Next, as shown in FIG. 5, the semiconductor element 30 and the copper plate 10 are heat-treated at 250 to 450 ° C. in a state where the bonding portion 38 is in contact with the tin film 40. By performing the heat treatment, as shown by the arrow 50, the tin film 40 and the metal of the bonding portion 38 diffuse to each other. Further, as indicated by arrows 52 and 54, the tin film 40 and the metal of the copper plate 10 also diffuse to each other. Note that since copper is a metal that is easily diffused, it diffuses beyond the tin film 40 and into the junction 38 as indicated by an arrow 54. As a result, as shown in FIG. 3, the first portion 22 is formed on the copper plate 10 side, and the second portion 26 is formed on the back electrode 32 side. Thereafter, the alloy 26 a of the second portion 26 protrudes in a dendritic shape toward the first portion 22 and is surrounded by the alloy 22 a of the first portion 22. As a result, a third portion in which the alloy of the first portion 22 (first type alloy) and the alloy of the second portion 26 (second type alloy) are mixed is formed.

以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時の請求項に記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数の目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。   Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10:銅板
20:合金層
22:第2部分
24:第3部分
26:第1部分
30:回路素子
100:モジュール
10: Copper plate 20: Alloy layer 22: Second part 24: Third part 26: First part 30: Circuit element 100: Module

Claims (3)

銅板と、
回路素子と、
前記銅板と前記回路素子の電極を接合する合金層と、を備えており、
前記合金層は、
前記銅板側に位置しており、すずと銅からなる第1種類の合金である第1部分と、
前記回路素子の前記電極側に位置しており、金、ニッケル、銀の少なくとも1種の金属とすずを含む第2種類の合金である第2部分と、
前記第1部分と前記第2部分の間に位置しており、前記第1種類の合金と前記第2種類の合金が混在している第3部分と、を有するモジュール。
A copper plate,
Circuit elements;
An alloy layer that joins the copper plate and the electrode of the circuit element, and
The alloy layer is
A first portion which is located on the copper plate side and is a first type alloy made of tin and copper;
A second portion that is located on the electrode side of the circuit element and is a second type alloy containing at least one metal of gold, nickel, silver and tin;
A module located between the first part and the second part and having a third part in which the first type alloy and the second type alloy are mixed.
前記第2種類の合金は、ニッケルを含む請求項1に記載のモジュール。   The module according to claim 1, wherein the second type alloy includes nickel. 前記第2種類の合金は、CuNi3−xSn(0≦x≦2)で表される請求項2に記載のモジュール。 The module according to claim 2, wherein the second type alloy is represented by Cu x Ni 3-x Sn (0 ≦ x ≦ 2).
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