JP2008085190A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a sheet resistance value in a cathode region of a Schottky barrier diode is difficult to be reduced in a conventional semiconductor device. <P>SOLUTION: In this semiconductor device, an N-type epitaxial layer 3 is formed on an N-type single crystal silicon substrate 2. In the epitaxial layer 3, trenches 6, 7 are formed so as to reach the substrate 2, and the trenches 6, 7 are filled with conductive metals 15, 16. The conductive metals 15, 16 in the trenches 6, 7 are used as current paths in the cathode region. With this configuration, the sheet resistance value in the cathode region in the Schottky barrier diode 1 is reduced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device that realizes a diode having a cathode region with reduced resistance.

As one example of a conventional semiconductor device, the following variable capacitance diode is known. An epitaxial layer into which the N-type impurity is introduced is formed on the semiconductor substrate into which the N-type impurity is introduced. Then, an N-type diffusion layer used as a cathode region is diffused in the first region of the epitaxial layer until it reaches the semiconductor substrate. The N type diffusion layer is a diffusion layer having a higher impurity concentration than the N type epitaxial layer. On the other hand, an N type diffusion layer and a P type diffusion layer are formed in the second region of the epitaxial layer, and a PN junction is formed by the N type diffusion layer and the P type diffusion layer. An anode electrode is formed on the P-type diffusion layer in the second region of the epitaxial layer, and a bump is formed on the anode electrode. A pair of cathode electrodes is formed on the N-type diffusion layer in the first region of the epitaxial layer, and bumps are formed on the cathode electrodes. (For example, refer to Patent Document 1).
JP 2004-311675 A (pages 7-8, FIG. 10)

  As described above, in the conventional semiconductor device, the variable capacitance diode is formed through the PN junction formed in the second region of the epitaxial layer. In the variable capacitance diode, the semiconductor substrate is used as a current path by diffusing the N-type diffusion layer formed in the first region of the epitaxial layer to the semiconductor substrate. The N-type semiconductor substrate is formed with a higher impurity concentration than the N-type epitaxial layer, but has a problem that the sheet resistance value is high and it is difficult to reduce the sheet resistance value in the cathode region.

  The present invention has been made in view of the above circumstances, and in the semiconductor device of the present invention, a semiconductor layer used as a cathode region, a cathode electrode formed on one main surface side of the semiconductor layer, and the semiconductor layer A Schottky barrier metal layer that is Schottky-bonded to one main surface side, and an anode electrode that is connected to the Schottky barrier metal layer, a trench is formed in the semiconductor layer from the one main surface side, The trench is embedded with a conductive metal, and the conductive metal is connected to the cathode electrode. Therefore, in the present invention, the conductive metal burying the trench becomes a current path in the cathode region, and the sheet resistance value in the cathode region is greatly reduced.

  In the present invention, the semiconductor layer is formed by depositing a one-conductive type epitaxial layer on a one-conductivity type substrate, and the epitaxial layer has one conductive around the Schottky junction. A diffusion layer of a mold is formed, the trench reaches the substrate, is disposed in a formation region of the diffusion layer of one conductivity type, and the trench is buried with the conductive metal. Therefore, in the present invention, it is possible to prevent a short circuit between the cathode electrode and the anode electrode due to the diffusion layer of one conductivity type.

  In the present invention, an insulating layer is formed on the epitaxial layer, and the Schottky barrier metal layer is in Schottky junction with the epitaxial layer through the opening formed in the insulating layer, and the inside of the opening is formed. A reverse conductivity type diffusion layer is formed in the epitaxial layer located below the periphery of the Schottky barrier metal layer. Therefore, in the present invention, the change in curvature of the depletion layer below the periphery of the Schottky barrier metal layer is reduced, electric field concentration is prevented, and the breakdown voltage characteristics of the semiconductor device are prevented from deteriorating.

  In the present invention, a resin sealing body is formed on one main surface of the epitaxial layer so as to cover the cathode electrode and the anode electrode. Therefore, in the present invention, underfill is not required in the mounting structure on the mounting substrate, and reworkability is improved.

  In the present invention, a bump connected to the cathode electrode and the anode electrode is formed through a contact hole formed in the resin sealing body. Accordingly, in the present invention, the cathode electrode and the anode electrode are formed on the one main surface side of the semiconductor layer, thereby enabling flip chip mounting.

  In the present invention, a semiconductor layer used as a cathode region, a diffusion layer used as an anode region formed in the semiconductor layer, and a cathode electrode and an anode electrode formed on one main surface side of the semiconductor layer are provided. And a trench is formed in the semiconductor layer from the one main surface side, the trench is buried with a conductive metal, and the conductive metal is connected to the cathode electrode. Therefore, in the present invention, the conductive metal burying the trench becomes a current path in the cathode region, and the sheet resistance value in the cathode region is greatly reduced.

  In the present invention, the semiconductor layer is formed by depositing a one-conductive type epitaxial layer on a one-conductive type substrate, and the epitaxial layer has a one-conductive type diffusion around the diffusion layer as the anode region. A layer is formed, the trench reaches the substrate, is disposed in a region where the diffusion layer of one conductivity type is formed, and the trench is buried with the conductive metal. Therefore, in the present invention, it is possible to prevent a short circuit between the cathode electrode and the anode electrode due to the diffusion layer of one conductivity type.

  Further, in the present invention, a semiconductor layer used as a cathode region, a cathode electrode formed on one main surface side of the semiconductor layer, and a Schottky barrier metal layer that forms a Schottky junction on one main surface side of the semiconductor layer And an anode electrode connected to the Schottky barrier metal layer, and a metal layer used as a cathode region is formed on the other main surface side of the semiconductor layer facing the one main surface, A trench is formed in the semiconductor layer from the one main surface side, the trench is buried with a conductive metal, and the conductive metal is connected to the cathode electrode. Therefore, in the present invention, the metal layer and the conductive metal serve as a current path, and the sheet resistance value in the cathode region is greatly reduced.

  In the present invention, the semiconductor layer is formed by depositing a one-conductive type epitaxial layer on a one-conductive type substrate, and a one-conductive type diffusion layer is formed around the Schottky junction in the epitaxial layer. The trench reaches the substrate, is disposed in a region where the diffusion layer of one conductivity type is formed, and the trench is buried with the conductive metal. Therefore, in the present invention, it is possible to prevent a short circuit between the cathode electrode and the anode electrode due to the diffusion layer of one conductivity type.

  In the present invention, a semiconductor layer used as a cathode region, a diffusion layer used as an anode region formed in the semiconductor layer, and a cathode electrode and an anode electrode formed on one main surface side of the semiconductor layer are provided. A metal layer used as a cathode region is formed on the other main surface side of the semiconductor layer facing the one main surface, and a trench is formed in the semiconductor layer from the one main surface side, The trench is embedded with a conductive metal, and the conductive metal is connected to the cathode electrode. Therefore, in the present invention, the metal layer and the conductive metal serve as a current path, and the sheet resistance value in the cathode region is greatly reduced.

  In the present invention, the semiconductor layer is formed by depositing a one-conductive type epitaxial layer on a one-conductive type substrate, and the epitaxial layer has a one-conductive type diffusion around the diffusion layer as the anode region. A layer is formed, the trench reaches the substrate, is disposed in a region where the diffusion layer of one conductivity type is formed, and the trench is buried with the conductive metal. Therefore, in the present invention, it is possible to prevent a short circuit between the cathode electrode and the anode electrode due to the diffusion layer of one conductivity type.

  Further, in the present invention, a semiconductor layer used as a cathode region, a cathode electrode formed on one main surface side of the semiconductor layer, and a Schottky barrier metal layer that forms a Schottky junction on one main surface side of the semiconductor layer And an anode electrode connected to the Schottky barrier metal layer, and a metal layer used as a cathode region is formed on the other main surface side of the semiconductor layer facing the one main surface, The semiconductor layer is characterized in that a trench penetrating the semiconductor layer is formed, the trench is buried with a conductive metal, and the conductive metal is connected to the cathode electrode and the metal layer. Therefore, in the present invention, the metal layer and the conductive metal are connected, the metal layer and the conductive metal serve as a current path, and the sheet resistance value in the cathode region is greatly reduced.

  In the present invention, the semiconductor layer is formed by depositing a one-conductive type epitaxial layer on a one-conductive type substrate, and a one-conductive type diffusion layer is formed around the Schottky junction in the epitaxial layer. The trench penetrates the substrate and the epitaxial layer and is disposed in a formation region of the diffusion layer of one conductivity type, and the trench is buried with the conductive metal. Therefore, in the present invention, it is possible to prevent a short circuit between the cathode electrode and the anode electrode due to the diffusion layer of one conductivity type.

  In the present invention, a semiconductor layer used as a cathode region, a diffusion layer used as an anode region formed in the semiconductor layer, and a cathode electrode and an anode electrode formed on one main surface side of the semiconductor layer are provided. A metal layer used as a cathode region is formed on the other main surface side of the semiconductor layer facing the one main surface, and a trench penetrating the semiconductor layer is formed in the semiconductor layer, The trench is embedded with a conductive metal, and the conductive metal is connected to the cathode electrode and the metal layer. Therefore, in the present invention, the metal layer and the conductive metal are connected, the metal layer and the conductive metal serve as a current path, and the sheet resistance value in the cathode region is greatly reduced.

  In the present invention, the semiconductor layer is formed by depositing a one-conductive type epitaxial layer on a one-conductive type substrate, and the epitaxial layer has a one-conductive type diffusion around the diffusion layer as the anode region. A layer is formed, the trench penetrates the substrate and the epitaxial layer, and is disposed in a formation region of the diffusion layer of one conductivity type, and the trench is buried with the conductive metal. To do. Therefore, in the present invention, it is possible to prevent a short circuit between the cathode electrode and the anode electrode due to the diffusion layer of one conductivity type.

  In the present invention, a cathode electrode and an anode electrode are formed on one main surface side of the semiconductor substrate. A trench is formed from one main surface side of the semiconductor substrate, and the trench is buried with a conductive metal. With this structure, the conductive metal is used as a current path in the cathode region, and the sheet resistance value in the cathode region is greatly reduced.

  In the present invention, a metal layer is formed on the other main surface side of the semiconductor substrate. With this structure, the metal layer is used as a current path in the cathode region, and the sheet resistance value in the cathode region is greatly reduced.

  Moreover, in this invention, the electroconductive metal which embeds a trench is connected with the metal layer of the other main surface side of a semiconductor substrate. With this structure, the conductive metal and the metal layer are used as a current path in the cathode region, and the sheet resistance value in the cathode region is greatly reduced.

  In the present invention, a P-type diffusion layer is formed below the periphery of the Schottky barrier metal layer that is in Schottky junction with the epitaxial layer. With this structure, in the vicinity of the peripheral portion of the Schottky barrier metal layer, the curvature change in the termination region of the depletion layer is reduced, and the breakdown voltage characteristics of the diode are improved.

  In the present invention, the cathode electrode and the anode electrode are formed on one main surface side of the semiconductor substrate. With this structure, flip chip mounting is possible, and the semiconductor device can be made smaller and thinner than the wire bonding method.

  In the present invention, a metal layer is formed on the other main surface side of the semiconductor substrate. With this structure, the metal layer is used as a heat spreader, and the heat dissipation of the semiconductor device is improved.

  Moreover, in this invention, the resin sealing body is formed in the one main surface side of a semiconductor substrate, and the bump is formed through the contact hole formed in the resin sealing body. With this structure, the melting point of the material (solder) used can be lowered and the thermal stress during mounting can be reduced as compared with the wire bonding method.

  Moreover, in this invention, the resin sealing body and bump are formed in the one main surface side of the semiconductor substrate. This structure eliminates the need for underfill in the mounting structure on the mounting substrate, and improves reworkability.

  The semiconductor device according to the first embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 is a cross-sectional view for explaining the Schottky barrier diode according to the present embodiment. FIG. 2A is a cross-sectional view for describing the Schottky barrier diode according to this embodiment. FIG. 2B is a cross-sectional view illustrating a structure in which the Schottky barrier diode illustrated in FIG.

  First, as shown in FIG. 1, a Schottky barrier diode 1 mainly includes an N-type single crystal silicon substrate 2, an N-type epitaxial layer 3, and N-type diffusion layers 4 and 5 used as an annular ring. , Trenches 6 and 7 used as a cathode region, P-type diffusion layers 8 and 9, an insulating layer 10, a Schottky barrier metal layer 11, an anode electrode 12, and cathode electrodes 13 and 14. ing.

  An N type epitaxial layer 3 is deposited on the upper surface of the N type single crystal silicon substrate 2. And the thickness of the board | substrate 2 is 50-200 (micrometer), for example, 400 (micrometer) board | substrates 2 are grind | polished by BG (Back Grinding) method, and the film thickness is adjusted. Moreover, the film thickness of the epitaxial layer 3 is 1.5-10 (micrometer), for example. In this embodiment, the case where one epitaxial layer 3 is formed on the substrate 2 is shown, but the present invention is not limited to this case. For example, a plurality of epitaxial layers may be stacked on the upper surface of the substrate.

  N-type diffusion layers 4 and 5 are formed in the epitaxial layer 3. The N type diffusion layers 4 and 5 are used as an annular ring of the Schottky barrier diode 1. The N type diffusion layers 4 and 5 are formed to have a higher impurity concentration than the epitaxial layer 3 and are diffused so as to be connected to the substrate 2. The N type diffusion layers 4 and 5 are formed in a ring around the substrate 2 and the epitaxial layer 3, for example.

  The trenches 6 and 7 are formed in the epitaxial layer 3 so as to reach the substrate 2. The trenches 6 and 7 are formed in the formation region of the N type diffusion layers 4 and 5, and reach the substrate 2 through the N type diffusion layers 4 and 5. The trenches 6 and 7 are formed by, for example, dry etching, and the trenches 6 and 7 are embedded with conductive metals 15 and 16 such as copper (Cu) and aluminum (Al). With this structure, in the Schottky barrier diode 1, a cathode region using the trenches 6 and 7 is realized. Since the trenches 6 and 7 are buried with the conductive metals 15 and 16, the sheet resistance value in the cathode region is greatly reduced. The trenches 6 and 7 are disposed in the formation region of the N-type diffusion layers 4 and 5 and are formed in a ring shape around the substrate 2 and the epitaxial layer 3 around the Schottky barrier metal layer 11, for example. The N-type diffusion layers 4 and 5 have a high impurity concentration, and the surface thereof is difficult to reverse, so that a short circuit between the anode electrode and the cathode electrode can be prevented.

  P-type diffusion layers 8 and 9 are formed in the epitaxial layer 3. The P-type diffusion layers 8 and 9 are formed below the end portions 17 and 18 of the Schottky barrier metal layer 11 serving as an anode electrode. The P-type diffusion layers 8 and 9 have a diffusion depth of 1 to 2 (μm), for example. With this structure, electric field concentration at the end portions 17 and 18 of the Schottky barrier metal layer 11 is alleviated, and the breakdown voltage characteristics of the Schottky barrier diode 1 are improved.

An insulating layer 10 is formed on the epitaxial layer 3. The insulating layer 10 is formed of a PSG (Phospho Silicate Glass) film or the like. Then, contact holes 19, 20, and 21 are formed in the insulating layer 10 by dry etching using, for example, a CHF ₃ or CF ₄ gas using a known photolithography technique.

A Schottky barrier metal layer 11 is formed on the upper surface of the epitaxial layer 3. The Schottky barrier metal layer 11 is, for example, a titanium (Ti) layer. The Schottky barrier metal layer 11 is located between the P-type diffusion layer 8 and the P-type diffusion layer 9 and is formed so as to bury the contact hole 20 formed in the insulating layer 10. On the surface where the Schottky barrier metal layer 11 and the epitaxial layer 3 are in contact with each other, a silicide layer 22 of a titanium silicide (TiSi ₂ ) layer is formed. The silicide layer 22 of the Schottky barrier metal layer 11 and the epitaxial layer 3 constitute a Schottky barrier diode. In place of the titanium (Ti) layer, a metal such as tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), or platinum (Pt) may be used. In this case, as the silicide layer 22, a tungsten silicide (WSi ₂ ) layer, a molybdenum silicide (MoSi ₂ ) layer, a cobalt silicide (CoSi ₂ ) layer, a nickel silicide (NiSi ₂ ) layer, a platinum silicide (PtSi ₂ ) layer, etc. Is formed.

  An anode electrode 12 is formed so as to be connected to the Schottky barrier metal layer 11. The anode electrode 12 has a structure in which, for example, an aluminum (Al) layer or an aluminum silicon (AlSi) layer is laminated on a barrier metal layer.

  Cathode electrodes 13 and 14 are formed on epitaxial layer 3 so as to bury contact holes 19 and 21 formed in insulating layer 10. The cathode electrodes 13 and 14 have a structure in which, for example, a titanium (Ti) and an aluminum (Al) layer or an aluminum silicon (AlSi) layer is laminated. The cathode electrodes 13 and 14 are connected to the conductive metals 15 and 16 through the contact holes 19 and 21.

  With this structure, in the region where the N type diffusion layers 4 and 5 are formed, the conductive metals 15 and 16 in the trenches 6 and 7 have a small sheet resistance value and become a current path. As indicated by arrows (dashed lines), in the cathode region, free carriers (electrons) are the conductive metals 15 and 16 in the trenches 6 and 7, the N-type single crystal silicon substrate 2 that is the cathode region, The N-type epitaxial layer 3 passes in the order. In addition, the direction of the arrow (dashed line) indicates the direction of current passage.

  Next, as shown in FIG. 2A, the Schottky barrier diode 31 has a structure in which bumps are formed by sealing the Schottky barrier diode 1 described above with reference to FIG. Therefore, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and the description in FIG. 1 is referred to, and the description is omitted here.

  As shown in FIG. 2A, the Schottky barrier diode 31 mainly includes an N-type single crystal silicon substrate 2, an N-type epitaxial layer 3, an N-type diffusion layer 4 used as an annular ring, 5, trenches 6 and 7 used as a cathode region, P-type diffusion layers 8 and 9, an insulating layer 10, a Schottky barrier metal layer 11, an anode electrode 12, cathode electrodes 13 and 14, A resin sealing body 32 and bumps 33, 34, and 35 are included.

  A resin sealing body 32 is formed on the epitaxial layer 3 so as to cover the anode electrode 12 and the cathode electrodes 13 and 14. The resin sealing body 32 is formed so as to cover at least the side surface on which the anode electrode 12 and the cathode electrodes 13 and 14 are formed. Then, contact holes 36, 37, and 38 are formed in the resin sealing body 32 so that parts of the anode electrode 12 and the cathode electrodes 13 and 14 are exposed.

  Bumps 33, 34, and 35 are formed so as to bury contact holes 36, 37, and 38 formed in the resin sealing body 32. The bumps 33, 34, and 35 are made of, for example, solder, gold, or the like. Here, UBM (Under Bump Metal) layers 39, 40 and 41 are formed on the anode electrode 12 and the cathode electrodes 13 and 14 exposed through the contact holes 36, 37 and 38. The UBM layers 39, 40, and 41 are made of, for example, titanium (Ti), nickel (Ni), or gold (Au), and are formed by a sputter deposition method, a plating method, or the like. The bumps 33, 34, and 35 are connected to the anode electrode 12 and the cathode electrodes 13 and 14 through the UBM layers 39, 40, and 41, respectively.

  As shown in FIG. 2B, the Schottky barrier diode 31 is mounted on the conductive patterns 43, 44, 45 of the mounting substrate 42. On the conductive patterns 43, 44, 45, for example, solder (not shown) is applied by screen printing. Then, the solder on the conductive patterns 43, 44, 45 is melted, and a part of the bumps 33, 34, 35 is melted and alloyed to fix the Schottky barrier diode 31 on the mounting substrate 42. . The mounting board 42 is a printed board, a ceramic board, a flexible sheet board, a metal board, or the like. The conductive patterns 43, 44, 45 are copper (Cu) wiring, gold (Au) wiring, nickel (Ni) wiring, or the like.

  With this structure, the Schottky barrier diode 31 is flip-chip mounted on the mounting substrate 42, and can be reduced in size and thickness as compared with the wire bonding method. Furthermore, solder bonding on the mounting substrate 42 results in a low melting point bonding as compared with the wire bonding method, and thermal stress during mounting is reduced. Further, in the Schottky barrier diode 31, a resin sealing body 32 is formed and is mounted via the bumps 33, 34, and 35, so that underfill is not necessary. For example, when the Schottky barrier diode 31 on the mounting substrate 42 becomes defective, only the Schottky barrier diode 31 needs to be replaced, and reworkability is improved.

  In this embodiment, the case where the conductive metals 15 and 16 such as copper (Cu) and aluminum (Al) are used as the material for burying the trenches 6 and 7 has been described. However, the present invention is not limited to this case. Absent. For example, the trenches 6 and 7 may be buried with polysilicon in which a large amount of impurities are introduced and resistance is lowered. In this embodiment, the case where the bumps 33, 34, and 35 are formed on the Schottky barrier diode 31 has been described. However, the present invention is not limited to this case. For example, bumps may be formed on the conductive patterns 43, 44, and 45 of the mounting substrate 42, and the Schottky barrier diode 31 may be fixed on the bumps. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a semiconductor device according to a second embodiment of the present invention will be described in detail with reference to FIGS. FIG. 3 is a cross-sectional view for explaining the PN junction diode according to the present embodiment. FIG. 4A is a cross-sectional view for explaining the PN junction diode according to this embodiment. FIG. 4B is a cross-sectional view for explaining a structure in which the PN junction diode shown in FIG.

  As shown in FIG. 3, the PN junction diode 51 mainly includes an N-type single crystal silicon substrate 52, an N-type epitaxial layer 53, N-type diffusion layers 54 and 55 used as an annular ring, and a cathode region. Are formed of a trench 56, 57 used as an anode region, a P-type diffusion layer 58 used as an anode region, an insulating layer 59, an anode electrode 60, and cathode electrodes 61, 62.

  An N type epitaxial layer 53 is deposited on the upper surface of the N type single crystal silicon substrate 52. The thickness of the substrate 52 is, for example, 50 to 200 (μm). The 400 (μm) substrate 52 is polished by, for example, a BG (Back Grinding) method, and the film thickness is adjusted. The film thickness of the epitaxial layer 53 is, for example, 1.5 to 10 (μm). In the present embodiment, a case where one epitaxial layer 53 is formed on the substrate 52 is shown, but the present invention is not limited to this case. For example, a plurality of epitaxial layers may be stacked on the upper surface of the substrate.

  N-type diffusion layers 54 and 55 are formed in the epitaxial layer 53. The N type diffusion layers 54 and 55 are used as an annular ring of the PN junction diode 51. The N type diffusion layers 54 and 55 are formed to have a higher impurity concentration than the epitaxial layer 53 and are diffused so as to be connected to the substrate 52. The N type diffusion layers 54 and 55 are formed in a ring around the substrate 52 and the epitaxial layer 53, for example.

  Trenches 56 and 57 are formed in the epitaxial layer 53 so as to reach the substrate 52. The trenches 56 and 57 are formed in the formation region of the N type diffusion layers 54 and 55, and reach the substrate 52 through the N type diffusion layers 54 and 55. The trenches 56 and 57 are formed by dry etching, for example, and the trenches 56 and 57 are embedded with conductive metals 63 and 64 such as copper (Cu) and aluminum (Al). With this structure, in the PN junction diode 51, a cathode region using the trenches 56 and 57 is realized. Since the trenches 56 and 57 are buried with the conductive metals 63 and 64, the sheet resistance value in the cathode region is greatly reduced. Note that the trenches 56 and 57 are disposed in the formation region of the N type diffusion layers 54 and 55, and are formed in a ring on the substrate 52 and the epitaxial layer 53 around the P type diffusion layer 58, for example. The N-type diffusion layers 54 and 55 have a high impurity concentration, and the surface thereof is difficult to reverse, so that a short circuit between the anode electrode and the cathode electrode can be prevented.

  A P type diffusion layer 58 is formed in the epitaxial layer 53. The P type diffusion layer 58 is used as an anode region of the PN junction diode 51.

An insulating layer 59 is formed on the epitaxial layer 53. The insulating layer 59 is formed of a PSG (Phospho Silicate Glass) film or the like. Then, contact holes 65, 66, and 67 are formed in the insulating layer 59 by a known photolithography technique, for example, by dry etching using a CHF ₃ or CF ₄ gas.

  An anode electrode 60 is formed on the epitaxial layer 53 so as to bury the contact hole 66 formed in the insulating layer 59. The anode electrode 60 has a structure in which, for example, a titanium (Ti) and an aluminum (Al) layer or an aluminum silicon (AlSi) layer is laminated.

  Cathode electrodes 61 and 62 are formed on epitaxial layer 53 so as to bury contact holes 65 and 67 formed in insulating layer 59. The cathode electrodes 61 and 62 have, for example, a structure in which a titanium (Ti) and aluminum (Al) layer or an aluminum silicon (AlSi) layer is laminated.

  With this structure, in the formation region of the N type diffusion layers 54 and 55, the conductive metals 63 and 64 in the trenches 56 and 57 have a small sheet resistance value and become a current path. As indicated by the arrows (dashed lines), in the cathode region, free carriers (electrons) are the conductive metals 63 and 64 in the trenches 56 and 57, the N-type single crystal silicon substrate 52 that is the cathode region, The N-type epitaxial layer 53 is passed through in the order. In addition, the direction of the arrow (dashed line) indicates the direction of current passage.

  Next, as shown in FIG. 4A, the PN junction diode 71 has a structure in which the PN junction diode 51 described above with reference to FIG. Therefore, the same components as those shown in FIG. 3 are denoted by the same reference numerals, and the description in FIG. 3 is referred to, and the description is omitted here.

  As shown in FIG. 4A, the PN junction diode 71 mainly includes an N-type single crystal silicon substrate 52, an N-type epitaxial layer 53, and N-type diffusion layers 54 and 55 used as an annular ring. Trenches 56 and 57 used as a cathode region, P-type diffusion layer 58, insulating layer 59, anode electrode 60, cathode electrodes 61 and 62, resin sealing body 72, bumps 73 and 74, 75.

  A resin sealing body 72 is formed on the epitaxial layer 53 so as to cover the anode electrode 60 and the cathode electrodes 61 and 62. The resin sealing body 72 is formed so as to cover at least the side surface on which the anode electrode 60 and the cathode electrodes 61 and 62 are formed. Then, contact holes 76, 77, 78 are formed in the resin sealing body 72 so that parts of the anode electrode 60 and the cathode electrodes 61, 62 are exposed.

  Bumps 73, 74, and 75 are formed so as to bury contact holes 76, 77, and 78 formed in the resin sealing body 72. The bumps 73, 74, and 75 are made of, for example, solder, gold, or the like. Here, UBM (Under Bump Metal) layers 79, 80, 81 are formed on the anode electrode 60 and the cathode electrodes 61, 62 exposed through the contact holes 76, 77, 78. The UBM layers 79, 80, 81 are made of, for example, titanium (Ti), nickel (Ni), or gold (Au), and are formed by a sputter deposition method, a plating method, or the like. The bumps 73, 74, and 75 are connected to the anode electrode 60 and the cathode electrodes 61 and 62 through the UBM layers 79, 80, and 81, respectively.

  As shown in FIG. 4B, the PN junction diode 71 is mounted on the conductive patterns 83, 84, 85 of the mounting substrate 82. On the conductive patterns 83, 84, 85, for example, solder (not shown) is applied by screen printing. Then, the solder on the conductive patterns 83, 84, 85 is melted, and a part of the bumps 73, 74, 75 is melted and alloyed to fix the PN junction diode 71 on the mounting substrate 82. The mounting board 82 is a printed board, a ceramic board, a flexible sheet board, a metal board, or the like. The conductive patterns 83, 84, 85 are copper (Cu) wiring, gold (Au) wiring, nickel (Ni) wiring, or the like.

  With this structure, the PN junction diode 71 is flip-chip mounted on the mounting substrate 82, and can be reduced in size and thickness as compared with the wire bonding method. Furthermore, soldering on the mounting substrate 82 results in a low melting point bonding as compared to the wire bonding method, and thermal stress during mounting is reduced. Further, in the PN junction diode 71, a resin sealing body 72 is formed and mounted via the bumps 73, 74, and 75, and an underfill is unnecessary. For example, when the PN junction diode 71 on the mounting substrate 82 becomes defective, only the PN junction diode 71 needs to be replaced, and the reworkability is improved.

  In the present embodiment, the case where the conductive metals 63 and 64 such as copper (Cu) and aluminum (Al) are used as the material for burying the trenches 56 and 57 has been described. However, the present invention is not limited to this case. Absent. For example, the trenches 56 and 57 may be buried by polysilicon in which a large amount of impurities are introduced and resistance is reduced. In the present embodiment, the case where the bumps 73, 74, and 75 are formed on the PN junction diode 71 has been described. However, the present invention is not limited to this case. For example, bumps may be formed on the conductive patterns 83, 84, 85 of the mounting substrate 82, and the PN junction diode 71 may be fixed on the bumps. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a semiconductor device according to a third embodiment of the present invention will be described in detail with reference to FIGS. FIG. 5 is a cross-sectional view for explaining the Schottky barrier diode according to the present embodiment. FIG. 6A is a cross-sectional view for describing the Schottky barrier diode according to this embodiment. FIG. 6B is a cross-sectional view for explaining the structure in which the Schottky barrier diode shown in FIG.

  First, as shown in FIG. 5, the Schottky barrier diode 91 mainly includes an N-type single crystal silicon substrate 92, an N-type epitaxial layer 93, and N-type diffusion layers 94 and 95 used as an annular ring. Trench 96, 97 used as a cathode region, P type diffusion layers 98, 99, insulating layer 100, Schottky barrier metal layer 101, anode electrode 102, cathode electrodes 103, 104, and metal layer 105.

  An N type epitaxial layer 93 is deposited on the upper surface of the N type single crystal silicon substrate 92. The thickness of the substrate 92 is, for example, 50 to 200 (μm). The 400 (μm) substrate 92 is polished by a BG (Back Grinding) method, and the film thickness is adjusted. The film thickness of the epitaxial layer 93 is, for example, 1.5 to 10 (μm). In the present embodiment, a case where one epitaxial layer 93 is formed on the substrate 92 is shown, but the present invention is not limited to this case. For example, a plurality of epitaxial layers may be stacked on the upper surface of the substrate.

  N-type diffusion layers 94 and 95 are formed in the epitaxial layer 93. The N type diffusion layers 94 and 95 are used as an annular ring for the Schottky barrier diode 91. The N type diffusion layers 94 and 95 are formed to have a higher impurity concentration than the epitaxial layer 93 and are diffused so as to be connected to the substrate 92. The N type diffusion layers 94 and 95 are formed in a ring around the substrate 92 and the epitaxial layer 93, for example.

  Trenches 96 and 97 are formed in the epitaxial layer 93 so as to reach the substrate 92. The trenches 96 and 97 are formed in the formation region of the N type diffusion layers 94 and 95, and reach the substrate 92 through the N type diffusion layers 94 and 95. The trenches 96 and 97 are formed by dry etching, for example, and the trenches 96 and 97 are embedded with conductive metals 106 and 107 such as copper (Cu) and aluminum (Al). With this structure, in the Schottky barrier diode 91, a cathode region using the trenches 96 and 97 is realized. Since the trenches 96 and 97 are buried with the conductive metals 106 and 107, the sheet resistance value in the cathode region is greatly reduced. As a result, in the formation region of the N-type diffusion layers 94 and 95, the conductive metals 106 and 107 in the trenches 96 and 97 have a small sheet resistance value and become a current path. The trenches 96 and 97 are disposed in the formation region of the N-type diffusion layers 94 and 95, and are formed in a ring on the substrate 92 and the epitaxial layer 93 around the Schottky barrier metal layer 101, for example. The N-type diffusion layers 94 and 95 have a high impurity concentration, the surface thereof is difficult to reverse, and a short circuit between the anode electrode and the cathode electrode can be prevented.

  P type diffusion layers 98 and 99 are formed in the epitaxial layer 93. The P-type diffusion layers 98 and 99 are formed below the end portions 108 and 109 of the Schottky barrier metal layer 101 serving as an anode electrode. The P-type diffusion layers 98 and 99 have a diffusion depth of 1 to 2 (μm), for example. With this structure, electric field concentration at the end portions 108 and 109 of the Schottky barrier metal layer 101 is alleviated, and the breakdown voltage characteristics of the Schottky barrier diode 91 are improved.

An insulating layer 100 is formed on the epitaxial layer 93. The insulating layer 100 is formed of a PSG (Phospho Silicate Glass) film or the like. Then, contact holes 110, 111, and 112 are formed in the insulating layer 100 by dry etching using, for example, a CHF ₃ or CF ₄ gas using a known photolithography technique.

A Schottky barrier metal layer 101 is formed on the upper surface of the epitaxial layer 93. The Schottky barrier metal layer 101 is, for example, a titanium (Ti) layer. The Schottky barrier metal layer 101 is located between the P-type diffusion layer 98 and the P-type diffusion layer 99 and is formed so as to bury the contact hole 111 formed in the insulating layer 100. A silicide layer 113 of a titanium silicide (TiSi ₂ ) layer is formed on the surface where the Schottky barrier metal layer 101 and the epitaxial layer 93 are in contact with each other. The silicide layer 113 and the epitaxial layer 93 of the Schottky barrier metal layer 101 constitute a Schottky barrier diode. In place of the titanium (Ti) layer, a metal such as tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), or platinum (Pt) may be used. In this case, as the silicide layer 113, a tungsten silicide (WSi ₂ ) layer, a molybdenum silicide (MoSi ₂ ) layer, a cobalt silicide (CoSi ₂ ) layer, a nickel silicide (NiSi ₂ ) layer, a platinum silicide (PtSi ₂ ) layer, etc. Is formed.

  An anode electrode 102 is formed so as to be connected to the Schottky barrier metal layer 101. The anode electrode 102 has, for example, a structure in which an aluminum (Al) layer or an aluminum silicon (AlSi) layer is stacked on a barrier metal layer.

  Cathode electrodes 103 and 104 are formed on the epitaxial layer 93 so as to bury the contact holes 110 and 112 formed in the insulating layer 100. The cathode electrodes 103 and 104 have a structure in which, for example, a titanium (Ti) and an aluminum (Al) layer or an aluminum silicon (AlSi) layer is laminated. The cathode electrodes 103 and 104 are connected to the conductive metals 106 and 107 through the contact holes 110 and 112.

  A metal layer 105 is formed on the back surface 114 side of the substrate 92. The metal layer 105 is made of, for example, titanium (Ti) and aluminum (Al) film, and is used as a cathode region of the Schottky barrier diode 91. As shown by the arrows (dashed lines), in the cathode region, free carriers (electrons) are generated from the conductive metals 106 and 107 in the trenches 96 and 97, the N-type single crystal silicon substrate 92, the metal layer 105, The N-type single crystal silicon substrate 92 and the N-type epitaxial layer 93 are passed through in this order. In addition, the direction of the arrow (dashed line) indicates the direction of current passage.

  Next, as shown in FIG. 6A, the Schottky barrier diode 121 has a structure in which the Schottky barrier diode 91 described above with reference to FIG. Therefore, the same components as those shown in FIG. 5 are denoted by the same reference numerals, and the description in FIG. 5 is referred to, and the description is omitted here.

  As shown in FIG. 6A, the Schottky barrier diode 121 mainly includes an N-type single crystal silicon substrate 92, an N-type epitaxial layer 93, an N-type diffusion layer 94 used as an annular ring, 95, trenches 96 and 97 used as a cathode region, P-type diffusion layers 98 and 99, an insulating layer 100, a Schottky barrier metal layer 101, an anode electrode 102, cathode electrodes 103 and 104, The metal layer 105, the resin sealing body 122, and the bumps 123, 124, and 125 are configured.

  A resin sealing body 122 is formed on the epitaxial layer 93 so as to cover the anode electrode 102 and the cathode electrodes 103 and 104. The resin sealing body 122 is formed so as to cover at least the side surface on which the anode electrode 102 and the cathode electrodes 103 and 104 are formed. In the resin sealing body 122, contact holes 126, 127, and 128 are formed so that parts of the anode electrode 102 and the cathode electrodes 103 and 104 are exposed.

  Bumps 123, 124, and 125 are formed so as to bury contact holes 126, 127, and 128 formed in the resin sealing body 122. The bumps 123, 124, and 125 are made of, for example, solder, gold, or the like. Here, UBM (Under Bump Metal) layers 129, 130 and 131 are formed on the anode electrode 102 and the cathode electrodes 103 and 104 exposed through the contact holes 126, 127 and 128. The UBM layers 129, 130, and 131 are made of, for example, titanium (Ti), nickel (Ni), or gold (Au), and are formed by a sputter deposition method, a plating method, or the like. The bumps 123, 124, and 125 are connected to the anode electrode 102 and the cathode electrodes 103 and 104 through the UBM layers 129, 130, and 131, respectively.

  As shown in FIG. 6B, the Schottky barrier diode 121 is mounted on the conductive patterns 133, 134, and 135 of the mounting substrate 132. On the conductive patterns 133, 134, and 135, solder (not shown) is applied by screen printing, for example. Then, the solder on the conductive patterns 133, 134, 135 is melted, and a part of the bumps 123, 124, 125 is melted and alloyed to fix the Schottky barrier diode 121 on the mounting substrate 132. . The mounting board 132 is a printed board, a ceramic board, a flexible sheet board, a metal board, or the like. The conductive patterns 133, 134, and 135 are copper (Cu) wiring, gold (Au) wiring, nickel (Ni) wiring, and the like.

  With this structure, the Schottky barrier diode 121 is flip-chip mounted on the mounting substrate 132, and can be reduced in size and thickness as compared with the wire bonding method. Furthermore, solder bonding onto the mounting substrate 132 results in a low melting point bonding as compared with the wire bonding method, and thermal stress during mounting is reduced. Further, since the metal layer 105 on the back surface 104 side of the substrate 92 is disposed on the upper side with respect to the mounting substrate 132, the metal layer 105 plays a role as a heat spreader and heat dissipation is improved. Further, in the Schottky barrier diode 121, the resin sealing body 122 is formed, and the structure is mounted via the bumps 123, 124, and 125, and the underfill is unnecessary. For example, when the Schottky barrier diode 121 on the mounting substrate 132 becomes defective, only the Schottky barrier diode 121 needs to be replaced, and reworkability is improved.

  In this embodiment, the case where the metal layer 105 is exposed on the back surface 104 side of the substrate 92 has been described. However, the present invention is not limited to this case. For example, a silicon oxide film may be formed on the back surface 104 side of the substrate 92 by a CVD (Chemical Vapor Deposition) method, and insulation of the back surface 104 of the substrate 92 may be realized. Further, although the case where the metal layer 105 is formed of an aluminum (Al) film has been described in this embodiment, the present invention is not limited to this case. For example, as the metal layer 105, an aluminum-silicon (Al-Si) film, an aluminum-silicon-copper (Al-Si-Cu) film, an aluminum-copper (Al-Cu) film, or titanium-titanium nitride-aluminum (Ti) Even when a -TiN-Al) film is used, the same effect can be obtained. Further, the thickness of the metal layer 105 can be arbitrarily changed according to the purpose of use. In this embodiment, the case where the conductive metals 106 and 107 such as copper (Cu) and aluminum (Al) are used as the material for burying the trenches 96 and 97 has been described. However, the present invention is not limited to this case. Absent. For example, the trenches 96 and 97 may be buried with polysilicon in which a large amount of impurities are introduced and resistance is reduced. In this embodiment, the case where the bumps 123, 124, and 125 are formed on the Schottky barrier diode 121 has been described. However, the present invention is not limited to this case. For example, bumps may be formed on the conductive patterns 133, 134, and 135 of the mounting substrate 132, and the Schottky barrier diode 121 may be fixed on the bumps. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a semiconductor device according to a fourth embodiment of the present invention will be described in detail with reference to FIGS. FIG. 7 is a cross-sectional view for explaining the PN junction diode according to the present embodiment. FIG. 8A is a cross-sectional view for explaining a PN junction diode according to this embodiment. FIG. 8B is a cross-sectional view for explaining a structure in which the PN junction diode shown in FIG.

  As shown in FIG. 7, the PN junction diode 141 mainly includes an N-type single crystal silicon substrate 142, an N-type epitaxial layer 143, N-type diffusion layers 144 and 145 used as an annular ring, and a cathode region. Are formed of a trench 146, 147 used as an anode region, a P-type diffusion layer 148 used as an anode region, an insulating layer 149, an anode electrode 150, cathode electrodes 151, 152, and a metal layer 153.

  An N type epitaxial layer 143 is deposited on the upper surface of the N type single crystal silicon substrate 142. The thickness of the substrate 142 is, for example, 50 to 200 (μm). The 400 (μm) substrate 142 is polished by, for example, a BG (Back Grinding) method, and the film thickness is adjusted. The film thickness of the epitaxial layer 143 is, for example, 1.5 to 10 (μm). Note that although a case where one epitaxial layer 143 is formed over the substrate 142 is described in this embodiment mode, the present invention is not limited to this case. For example, a plurality of epitaxial layers may be stacked on the upper surface of the substrate.

  N-type diffusion layers 144 and 145 are formed in the epitaxial layer 143. The N type diffusion layers 144 and 145 are used as an annular ring of the PN junction diode 141. The N type diffusion layers 144 and 145 are formed to have a higher impurity concentration than the epitaxial layer 143 and are diffused so as to be connected to the substrate 142. The N type diffusion layers 144 and 145 are formed in a ring around the substrate 142 and the epitaxial layer 143, for example.

  Trenches 146 and 147 are formed in the epitaxial layer 143 so as to reach the substrate 142. The trenches 146 and 147 are formed in regions where the N type diffusion layers 144 and 145 are formed, and reach the substrate 142 through the N type diffusion layers 144 and 145. The trenches 146 and 147 are formed by dry etching, for example, and the trenches 146 and 147 are embedded with conductive metals 154 and 155 such as copper (Cu) and aluminum (Al). With this structure, a cathode region using the trenches 146 and 147 is realized in the PN junction diode 141. And since the trenches 146 and 147 are embedded with the conductive metals 154 and 155, the sheet resistance value in the cathode region is greatly reduced. The trenches 146 and 147 are arranged in the formation region of the N type diffusion layers 144 and 145, and are formed in a ring shape around the substrate 142 and the epitaxial layer 143 around the P type diffusion layer 148, for example. The N-type diffusion layers 144 and 145 have a high impurity concentration, and the surface thereof is difficult to reverse, so that a short circuit between the anode electrode and the cathode electrode can be prevented.

  A P type diffusion layer 148 is formed in the epitaxial layer 143. The P type diffusion layer 148 is used as an anode region of the PN junction diode 141.

An insulating layer 149 is formed on the epitaxial layer 143. The insulating layer 149 is formed of a PSG (Phospho Silicate Glass) film or the like. Then, contact holes 156, 157, and 158 are formed in the insulating layer 149 by a known photolithography technique, for example, by dry etching using a CHF ₃ or CF ₄ gas.

  An anode electrode 150 is formed on the epitaxial layer 143 so as to bury the contact hole 157 formed in the insulating layer 149. The anode electrode 150 has, for example, a structure in which a titanium (Ti) and an aluminum (Al) layer or an aluminum silicon (AlSi) layer is laminated.

  Cathode electrodes 151 and 152 are formed on the epitaxial layer 143 so as to bury the contact holes 156 and 158 formed in the insulating layer 149. The cathode electrodes 151 and 152 have a structure in which, for example, a titanium (Ti) and aluminum (Al) layer or an aluminum silicon (AlSi) layer is laminated.

  A metal layer 153 is formed on the back surface 159 side of the substrate 142. The metal layer 153 is made of, for example, titanium (Ti) and aluminum (Al) film, and is used as a cathode region of the PN junction diode 141. Then, as shown by arrows (dashed lines), in the cathode region, free carriers (electrons) are generated from the conductive metals 154 and 155 in the trenches 146 and 147, the N-type single crystal silicon substrate 142, the metal layer 153, The N-type single crystal silicon substrate 142 and the N-type epitaxial layer 143 are passed through in this order. In addition, the direction of the arrow (dashed line) indicates the direction of current passage.

  Next, as shown in FIG. 8A, the PN junction diode 161 has a structure in which the PN junction diode 141 described above with reference to FIG. 7 is resin-sealed to form bumps. Therefore, the same components as those shown in FIG. 7 are denoted by the same reference numerals, and the description in FIG. 7 is referred to, and the description is omitted here.

  As shown in FIG. 8A, the PN junction diode 161 mainly includes an N-type single crystal silicon substrate 142, an N-type epitaxial layer 143, and N-type diffusion layers 144 and 145 used as an annular ring. Trenches 146 and 147 used as a cathode region, a P-type diffusion layer 148, an insulating layer 149, an anode electrode 150, cathode electrodes 151 and 152, a metal layer 153, a resin sealing body 162, The bumps 163, 164, and 165 are configured.

  A resin sealing body 162 is formed on the epitaxial layer 143 so as to cover the anode electrode 150 and the cathode electrodes 151 and 152. The resin sealing body 162 is formed so as to cover at least the side surface on which the anode electrode 150 and the cathode electrodes 151 and 152 are formed. Then, contact holes 166, 167, and 168 are formed in the resin sealing body 162 so that parts of the anode electrode 150 and the cathode electrodes 151 and 152 are exposed.

  Bumps 163, 164, 165 are formed so as to bury contact holes 166, 167, 168 formed in the resin sealing body 162. The bumps 163, 164, 165 are made of, for example, solder, gold, or the like. Here, UBM (Under Bump Metal) layers 169, 170, and 171 are formed on the anode electrode 150 and the cathode electrodes 151 and 152 exposed through the contact holes 166, 167, and 168, respectively. The UBM layers 169, 170, and 171 are made of, for example, titanium (Ti), nickel (Ni), or gold (Au), and are formed by a sputter deposition method, a plating method, or the like. The bumps 163, 164, and 165 are connected to the anode electrode 150 and the cathode electrodes 151 and 152 through the UBM layers 169, 170, and 171 respectively.

  As shown in FIG. 8B, the PN junction diode 161 is mounted on the conductive patterns 173, 174, and 175 of the mounting substrate 172. On the conductive patterns 173, 174, and 175, solder (not shown) is applied by screen printing, for example. Then, the solder on the conductive patterns 173, 174, and 175 is melted, and a part of the bumps 163, 164, and 165 is melted and alloyed to fix the PN junction diode 161 on the mounting substrate 172. The mounting board 172 is a printed board, a ceramic board, a flexible sheet board, a metal board, or the like. The conductive patterns 173, 174, and 175 are copper (Cu) wiring, gold (Au) wiring, nickel (Ni) wiring, and the like.

  With this structure, the PN junction diode 161 is flip-chip mounted on the mounting substrate 172, and can be reduced in size and thickness as compared with the wire bonding method. Furthermore, soldering on the mounting substrate 172 results in a low melting point bonding as compared with the wire bonding method, and thermal stress during mounting is reduced. Further, in the PN junction diode 161, the resin sealing body 162 is formed and is mounted via the bumps 163, 164, 165, and the underfill is unnecessary. For example, when the PN junction diode 161 on the mounting substrate 172 becomes defective, only the PN junction diode 161 needs to be replaced, and the reworkability is improved.

  Note that although the case where the metal layer 153 is exposed on the back surface 159 side of the substrate 142 has been described in this embodiment mode, the present invention is not limited to this case. For example, a silicon oxide film may be formed on the back surface 159 side of the substrate 142 by a CVD (Chemical Vapor Deposition) method, and insulation of the back surface 159 of the substrate 142 may be realized. In this embodiment, the case where the metal layer 153 is formed from an aluminum (Al) film has been described. However, the present invention is not limited to this case. For example, as the metal layer 153, an aluminum-silicon (Al-Si) film, an aluminum-silicon-copper (Al-Si-Cu) film, an aluminum-copper (Al-Cu) film, or a titanium-titanium nitride-aluminum (Ti) Even when a -TiN-Al) film is used, the same effect can be obtained. The film thickness of the metal layer 153 can be arbitrarily changed according to the purpose of use. In this embodiment, the case where conductive metals 154 and 155 such as copper (Cu) and aluminum (Al) are used as the material for burying the trenches 146 and 147 has been described. However, the present invention is not limited to this case. Absent. For example, the trenches 146 and 147 may be buried with polysilicon in which a large amount of impurities are introduced to reduce resistance. In this embodiment, the case where the bumps 163, 164, and 165 are formed on the PN junction diode 161 has been described. However, the present invention is not limited to this case. For example, bumps may be formed on the conductive patterns 173, 174, and 175 of the mounting substrate 172, and the PN junction diode 161 may be fixed on the bumps. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a semiconductor device according to a fifth embodiment of the present invention will be described in detail with reference to FIGS. FIG. 9 is a cross-sectional view for explaining the Schottky barrier diode according to the present embodiment. FIG. 10A is a cross-sectional view for describing the Schottky barrier diode according to this embodiment. FIG. 10B is a cross-sectional view illustrating a structure in which the Schottky barrier diode illustrated in FIG.

  First, as shown in FIG. 9, the Schottky barrier diode 181 mainly includes an N-type single crystal silicon substrate 182, an N-type epitaxial layer 183, and N-type diffusion layers 184 and 185 used as an annular ring. , Trenches 186 and 187 used as a cathode region, P-type diffusion layers 188 and 189, an insulating layer 190, a Schottky barrier metal layer 191, an anode electrode 192, cathode electrodes 193 and 194, and a metal layer 195.

  An N type epitaxial layer 183 is deposited on the upper surface of the N type single crystal silicon substrate 182. The thickness of the substrate 182 is, for example, 50 to 200 (μm), and the 400 (μm) substrate 182 is polished by a BG (Back Grinding) method, and the film thickness is adjusted. The film thickness of the epitaxial layer 183 is, for example, 1.5 to 10 (μm). In this embodiment mode, a case where one epitaxial layer 183 is formed over the substrate 182 is shown; however, the present invention is not limited to this case. For example, a plurality of epitaxial layers may be stacked on the upper surface of the substrate.

  N-type diffusion layers 184 and 185 are formed in the epitaxial layer 183. The N type diffusion layers 184 and 185 are used as an annular ring for the Schottky barrier diode 181. The N type diffusion layers 184 and 185 are formed to have a higher impurity concentration than the epitaxial layer 183 and are diffused so as to be connected to the substrate 182. The N-type diffusion layers 184 and 185 are formed in a ring around the substrate 182 and the epitaxial layer 183, for example.

  Trenches 186 and 187 are formed so as to penetrate the substrate 182 and the epitaxial layer 183. The trenches 186 and 187 are formed by dry etching, for example, and the trenches 186 and 187 are embedded with conductive metals 196 and 197 such as copper (Cu) and aluminum (Al). With this structure, in the Schottky barrier diode 181, a cathode region using the trenches 186 and 187 is realized. The trenches 186 and 187 are buried with the conductive metals 196 and 197, so that the sheet resistance value in the cathode region is greatly reduced. As a result, in the formation region of the substrate 182 and the N-type diffusion layers 184 and 185, the conductive metals 196 and 197 in the trenches 186 and 187 have a small sheet resistance value and become a current path. The trenches 186 and 187 are disposed in the formation region of the N-type diffusion layers 184 and 185, and are formed in a ring on the substrate 182 and the epitaxial layer 183 around the Schottky barrier metal layer 191, for example. The N-type diffusion layers 184 and 185 have a high impurity concentration, and the surface thereof is difficult to reverse, so that a short circuit between the anode electrode and the cathode electrode can be prevented.

  P-type diffusion layers 188 and 189 are formed in the epitaxial layer 183. The P-type diffusion layers 188 and 189 are formed below the ends 198 and 199 of the Schottky barrier metal layer 191 to be the anode electrode. The P-type diffusion layers 188 and 189 have a diffusion depth of 1 to 2 (μm), for example. With this structure, electric field concentration at the end portions 198 and 199 of the Schottky barrier metal layer 191 is alleviated, and the breakdown voltage characteristics of the Schottky barrier diode 181 are improved.

An insulating layer 190 is formed on the epitaxial layer 183. The insulating layer 190 is formed of a PSG (Phospho Silicate Glass) film or the like. Then, contact holes 200, 201, and 202 are formed in the insulating layer 190 by dry etching using, for example, a CHF ₃ or CF ₄ gas using a known photolithography technique.

A Schottky barrier metal layer 191 is formed on the upper surface of the epitaxial layer 183. The Schottky barrier metal layer 191 is, for example, a titanium (Ti) layer. The Schottky barrier metal layer 191 is located between the P-type diffusion layer 188 and the P-type diffusion layer 189 and is formed so as to bury the contact hole 201 formed in the insulating layer 190. A silicide layer 203 of a titanium silicide (TiSi ₂ ) layer is formed on the surface where the Schottky barrier metal layer 191 and the epitaxial layer 183 are in contact with each other. The silicide layer 203 and the epitaxial layer 183 of the Schottky barrier metal layer 191 constitute a Schottky barrier diode. In place of the titanium (Ti) layer, a metal such as tungsten (W), molybdenum (Mo), tantalum (Ta), cobalt (Co), nickel (Ni), or platinum (Pt) may be used. In this case, as the silicide layer 203, a tungsten silicide (WSi ₂ ) layer, a molybdenum silicide (MoSi ₂ ) layer, a cobalt silicide (CoSi ₂ ) layer, a nickel silicide (NiSi ₂ ) layer, a platinum silicide (PtSi ₂ ) layer, etc. Is formed.

  An anode electrode 192 is formed so as to be connected to the Schottky barrier metal layer 191. The anode electrode 192 has, for example, a structure in which an aluminum (Al) layer or an aluminum silicon (AlSi) layer is stacked on a barrier metal layer.

  Cathode electrodes 193 and 194 are formed on the epitaxial layer 183 so as to bury the contact holes 200 and 202 formed in the insulating layer 190. The cathode electrodes 193 and 194 have a structure in which, for example, a titanium (Ti) and aluminum (Al) layer or an aluminum silicon (AlSi) layer is laminated. The cathode electrodes 193 and 194 are connected to the conductive metals 196 and 197 through the contact holes 200 and 202, respectively.

  A metal layer 195 is formed on the back surface 204 side of the substrate 182. The metal layer 195 is made of, for example, titanium (Ti) and aluminum (Al) film, and is used as a cathode region of the Schottky barrier diode 181. Then, as shown by arrows (dashed lines), in the cathode region, free carriers (electrons) are the conductive metals 196 and 197 in the trenches 186 and 187, the metal layer 195, the N-type single crystal silicon substrate 182, The N-type epitaxial layer 183 passes in the order. In addition, the direction of the arrow (dashed line) indicates the direction of current passage.

  Next, as shown in FIG. 10A, the Schottky barrier diode 211 has a structure in which the Schottky barrier diode 181 described above with reference to FIG. 9 is resin-sealed to form bumps. Therefore, the same components as those shown in FIG. 9 are denoted by the same reference numerals, and the description in FIG. 9 is referred to, and the description is omitted here.

  As shown in FIG. 10A, the Schottky barrier diode 211 mainly includes an N-type single crystal silicon substrate 182, an N-type epitaxial layer 183, an N-type diffusion layer 184 used as an annular ring, 185, trenches 186 and 187 used as a cathode region, P-type diffusion layers 188 and 189, an insulating layer 190, a Schottky barrier metal layer 191, an anode electrode 192, cathode electrodes 193 and 194, A metal layer 195, a resin sealing body 212, and bumps 213, 214, and 215 are included.

  A resin sealing body 212 is formed on the epitaxial layer 183 so as to cover the anode electrode 192 and the cathode electrodes 193 and 194. The resin sealing body 212 is formed so as to cover at least the side surface on which the anode electrode 192 and the cathode electrodes 193 and 194 are formed. In the resin sealing body 212, contact holes 216, 217, and 218 are formed so that parts of the anode electrode 192 and the cathode electrodes 193 and 194 are exposed.

  Bumps 213, 214, and 215 are formed so as to bury contact holes 216, 217, and 218 formed in the resin sealing body 212. The bumps 213, 214, and 215 are formed from, for example, solder, gold, or the like. Here, UBM (Under Bump Metal) layers 219, 220, and 221 are formed on the anode electrode 192 and the cathode electrodes 193 and 194 exposed through the contact holes 216, 217, and 218, respectively. The UBM layers 219, 220, and 221 are made of, for example, titanium (Ti), nickel (Ni), or gold (Au), and are formed by a sputter deposition method, a plating method, or the like. The bumps 213, 214, and 215 are connected to the anode electrode 192 and the cathode electrodes 193 and 194 through the UBM layers 219, 220, and 221 respectively.

  As illustrated in FIG. 10B, the Schottky barrier diode 211 is mounted on the conductive patterns 223, 224, and 225 of the mounting substrate 222. On the conductive patterns 223, 224, and 225, solder (not shown) is applied by screen printing, for example. Then, the solder on the conductive patterns 223, 224, and 225 is melted, and a part of the bumps 213, 214, and 215 is melted and alloyed to fix the Schottky barrier diode 211 on the mounting substrate 222. . The mounting board 222 is a printed board, a ceramic board, a flexible sheet board, a metal board, or the like. The conductive patterns 223, 224, and 225 are copper (Cu) wiring, gold (Au) wiring, nickel (Ni) wiring, or the like.

  With this structure, the Schottky barrier diode 211 is flip-chip mounted on the mounting substrate 222, and can be reduced in size and thickness as compared with the wire bonding method. Furthermore, solder bonding onto the mounting substrate 222 results in a low melting point bonding compared to the wire bonding method, and thermal stress during mounting is reduced. In addition, since the metal layer 195 on the back surface 204 side of the substrate 182 is disposed on the upper side with respect to the mounting substrate 222, the metal layer 195 plays a role as a heat spreader and heat dissipation is improved. Further, in the Schottky barrier diode 211, a resin sealing body 212 is formed and mounted via the bumps 213, 214, and 215, and an underfill is not necessary. For example, when the Schottky barrier diode 211 on the mounting substrate 222 becomes defective, only the Schottky barrier diode 211 needs to be replaced, and reworkability is improved.

  Note that although the case where the metal layer 195 is exposed on the back surface 204 side of the substrate 182 has been described in this embodiment mode, the present invention is not limited to this case. For example, a silicon oxide film may be formed on the back surface 204 side of the substrate 182 by a CVD (Chemical Vapor Deposition) method, and insulation of the back surface 204 of the substrate 182 may be realized. In the present embodiment, the case where the metal layer 195 is formed of an aluminum (Al) film has been described. However, the present invention is not limited to this case. For example, as the metal layer 195, an aluminum-silicon (Al-Si) film, an aluminum-silicon-copper (Al-Si-Cu) film, an aluminum-copper (Al-Cu) film, or a titanium-titanium nitride-aluminum (Ti) Even when a -TiN-Al) film is used, the same effect can be obtained. Further, the thickness of the metal layer 195 can be arbitrarily changed according to the purpose of use. In this embodiment, the case where conductive metals 196 and 197 such as copper (Cu) and aluminum (Al) are used as the material for burying the trenches 186 and 187 has been described. However, the present invention is not limited to this case. Absent. For example, the trenches 186 and 187 may be buried with polysilicon in which a large amount of impurities are introduced to reduce resistance. In this embodiment, the case where the bumps 213, 214, and 215 are formed on the Schottky barrier diode 211 has been described. However, the present invention is not limited to this case. For example, bumps may be formed on the conductive patterns 223, 224, and 225 of the mounting substrate 222, and the Schottky barrier diode 211 may be fixed on the bumps. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a semiconductor device according to a sixth embodiment of the present invention will be described in detail with reference to FIGS. FIG. 11 is a cross-sectional view for explaining the PN junction diode according to the present embodiment. FIG. 12A is a cross-sectional view for explaining a PN junction diode according to this embodiment. FIG. 12B is a cross-sectional view for explaining the structure in which the PN junction diode shown in FIG.

  As shown in FIG. 11, the PN junction diode 231 mainly includes an N-type single crystal silicon substrate 232, an N-type epitaxial layer 233, N-type diffusion layers 234 and 235 used as an annular ring, and a cathode region. The trench 236 is used as the anode region, the P-type diffusion layer 238 is used as the anode region, the insulating layer 239, the anode electrode 240, the cathode electrodes 241, 242, and the metal layer 243.

  An N type epitaxial layer 233 is deposited on the upper surface of the N type single crystal silicon substrate 232. The thickness of the substrate 232 is, for example, 50 to 200 (μm). The 400 (μm) substrate 232 is polished by, for example, a BG (Back Grinding) method, and the film thickness is adjusted. The film thickness of the epitaxial layer 233 is, for example, 1.5 to 10 (μm). Note that although a case where one epitaxial layer 233 is formed over the substrate 232 is described in this embodiment mode, the present invention is not limited to this case. For example, a plurality of epitaxial layers may be stacked on the upper surface of the substrate.

  N-type diffusion layers 234 and 235 are formed in the epitaxial layer 233. The N type diffusion layers 234 and 235 are used as an annular ring of the PN junction diode 231. The N type diffusion layers 234 and 235 are formed to have a higher impurity concentration than the epitaxial layer 233 and are diffused so as to be connected to the substrate 232. The N-type diffusion layers 234 and 235 are formed in a ring around the substrate 232 and the epitaxial layer 233, for example.

  Trenches 236 and 237 are formed so as to penetrate the substrate 232 and the epitaxial layer 233. The trenches 236 and 237 are formed by dry etching, for example, and the trenches 236 and 237 are embedded with conductive metals 244 and 245 such as copper (Cu) and aluminum (Al). With this structure, in the PN junction diode 231, a cathode region using the trenches 236 and 237 is realized. And since the trenches 236 and 237 are buried with the conductive metals 244 and 245, the sheet resistance value in the cathode region is greatly reduced. As a result, in the formation region of the substrate 232 and the N-type diffusion layers 234 and 235, the conductive metals 244 and 245 in the trenches 236 and 237 have a small sheet resistance value and become a current path. The trenches 236 and 237 are arranged in the formation region of the N type diffusion layers 234 and 235, and are formed in a ring shape on the substrate 232 and the epitaxial layer 233 around the P type diffusion layer 238, for example. The N-type diffusion layers 234 and 235 have a high impurity concentration, and the surface thereof is difficult to reverse, so that a short circuit between the anode electrode and the cathode electrode can be prevented.

  A P type diffusion layer 238 is formed in the epitaxial layer 233. The P type diffusion layer 238 is used as an anode region of the PN junction diode 231.

An insulating layer 239 is formed on the epitaxial layer 233. The insulating layer 239 is formed of a PSG (Phospho Silicate Glass) film or the like. Then, contact holes 246, 247, and 248 are formed in the insulating layer 239 by a known photolithography technique, for example, by dry etching using a CHF ₃ or CF ₄ gas.

  An anode electrode 240 is formed on the epitaxial layer 233 so as to bury the contact hole 247 formed in the insulating layer 239. The anode electrode 240 has a structure in which, for example, a titanium (Ti) and an aluminum (Al) layer or an aluminum silicon (AlSi) layer is laminated.

  Cathode electrodes 241 and 242 are formed on the epitaxial layer 233 so as to bury the contact holes 246 and 248 formed in the insulating layer 239. The cathode electrodes 241 and 242 have a structure in which, for example, a titanium (Ti) and aluminum (Al) layer or an aluminum silicon (AlSi) layer is laminated.

  A metal layer 243 is formed on the back surface 249 side of the substrate 232. The metal layer 243 is made of, for example, titanium (Ti) and aluminum (Al) film, and is used as a cathode region of the PN junction diode 231. Then, as illustrated by arrows (dashed lines), in the cathode region, free carriers (electrons) are generated from the conductive metals 244 and 245, the metal layer 243 in the trenches 236 and 237, the N-type single crystal silicon substrate 232, The N-type epitaxial layer 233 passes in the order. In addition, the direction of the arrow (dashed line) indicates the direction of current passage.

  Next, as shown in FIG. 12A, the PN junction diode 251 has a structure in which the PN junction diode 251 described above with reference to FIG. 11 is resin-sealed to form bumps. Therefore, the same components as those shown in FIG. 11 are denoted by the same reference numerals, and the description in FIG. 11 is referred to, and the description is omitted here.

  As shown in FIG. 12A, the PN junction diode 251 mainly includes an N-type single crystal silicon substrate 232, an N-type epitaxial layer 233, and N-type diffusion layers 234 and 235 used as an annular ring. Trenches 236 and 237 used as a cathode region, a P-type diffusion layer 238, an insulating layer 239, an anode electrode 240, cathode electrodes 241 and 242, a metal layer 243, a resin sealing body 252, It consists of bumps 253, 254, and 255.

  A resin sealing body 252 is formed on the epitaxial layer 233 so as to cover the anode electrode 240 and the cathode electrodes 241 and 242. The resin sealing body 252 is formed so as to cover at least the side surface on which the anode electrode 240 and the cathode electrodes 241 and 242 are formed. Then, contact holes 256, 257, and 258 are formed in the resin sealing body 252 so that parts of the anode electrode 240 and the cathode electrodes 241 and 242 are exposed.

  Bumps 253, 254, and 255 are formed so as to bury contact holes 256, 257, and 258 formed in resin sealing body 252. Formed on one side surface. The bumps 253, 254, and 255 are made of, for example, solder, gold, or the like. Here, UBM (Under Bump Metal) layers 259, 260, and 261 are formed on the anode electrode 240 and the cathode electrodes 241 and 242 that are exposed through the contact holes 256, 257, and 258, respectively. The UBM layers 259, 260, and 261 are made of, for example, titanium (Ti), nickel (Ni), or gold (Au), and are formed by a sputter deposition method, a plating method, or the like. The bumps 253, 254, and 255 are connected to the anode electrode 240 and the cathode electrodes 241 and 242 through the UBM layers 259, 260, and 261, respectively.

  As shown in FIG. 12B, the PN junction diode 251 is mounted on the conductive patterns 263, 264, and 265 of the mounting substrate 262. On the conductive patterns 263, 264, 265, for example, solder (not shown) is applied by screen printing. The solder on the conductive patterns 263, 264, and 265 is melted, and a part of the bumps 253, 254, and 255 is melted and alloyed to fix the PN junction diode 251 on the mounting substrate 262. The mounting board 262 is a printed board, a ceramic board, a flexible sheet board, a metal board, or the like. The conductive patterns 263, 264, and 265 are copper (Cu) wiring, gold (Au) wiring, nickel (Ni) wiring, or the like.

  With this structure, the PN junction diode 251 is flip-chip mounted on the mounting substrate 262, and can be reduced in size and thickness as compared with the wire bonding method. Furthermore, soldering on the mounting substrate 262 results in a low melting point bonding as compared to the wire bonding method, and thermal stress during mounting is reduced. In the PN junction diode 251, a resin sealing body 252 is formed and mounted via the bumps 253, 254, and 255, so that an underfill is unnecessary. For example, when the PN junction diode 251 on the mounting substrate 262 becomes defective, only the PN junction diode 251 needs to be replaced, and reworkability is improved.

  Note that although the case where the metal layer 243 is exposed on the back surface 249 side of the substrate 232 has been described in this embodiment mode, the present invention is not limited to this case. For example, a silicon oxide film may be formed on the back surface 249 side of the substrate 232 by a CVD (Chemical Vapor Deposition) method, and insulation of the back surface 249 of the substrate 232 may be realized. In this embodiment, the case where the metal layer 243 is formed using an aluminum (Al) film has been described. However, the present invention is not limited to this case. For example, as the metal layer 243, an aluminum-silicon (Al-Si) film, an aluminum-silicon-copper (Al-Si-Cu) film, an aluminum-copper (Al-Cu) film, or titanium-titanium nitride-aluminum (Ti) Even when a -TiN-Al) film is used, the same effect can be obtained. In addition, the thickness of the metal layer 243 can be arbitrarily changed according to the purpose of use. In this embodiment, the case where conductive metals 244 and 245 such as copper (Cu) and aluminum (Al) are used as the material for burying the trenches 236 and 237 has been described. However, the present invention is not limited to this case. Absent. For example, the trenches 236 and 237 may be buried by polysilicon in which a large amount of impurities are introduced and resistance is reduced. In this embodiment, the case where the bumps 253, 254, and 255 are formed on the PN junction diode 251 has been described. However, the present invention is not limited to this case. For example, bumps may be formed on the conductive patterns 263, 264, and 265 of the mounting substrate 262, and the PN junction diode 251 may be fixed on the bumps. In addition, various modifications can be made without departing from the scope of the present invention.

It is sectional drawing for demonstrating the Schottky barrier diode in embodiment of this invention. (A) It is sectional drawing for demonstrating the Schottky barrier diode in embodiment of this invention, (B) It is sectional drawing for demonstrating the structure in which the Schottky barrier diode was mounted. It is sectional drawing for demonstrating the PN junction diode in embodiment of this invention. It is sectional drawing for demonstrating the (A) PN junction diode in embodiment of this invention, (B) It is sectional drawing for demonstrating the structure in which the PN junction diode was mounted. It is sectional drawing for demonstrating the Schottky barrier diode in embodiment of this invention. (A) It is sectional drawing for demonstrating the Schottky barrier diode in embodiment of this invention, (B) It is sectional drawing for demonstrating the structure in which the Schottky barrier diode was mounted. It is sectional drawing for demonstrating the PN junction diode in embodiment of this invention. It is sectional drawing for demonstrating the (A) PN junction diode in embodiment of this invention, (B) It is sectional drawing for demonstrating the structure in which the PN junction diode was mounted. It is sectional drawing for demonstrating the Schottky barrier diode in embodiment of this invention. (A) It is sectional drawing for demonstrating the Schottky barrier diode in embodiment of this invention, (B) It is sectional drawing for demonstrating the structure in which the Schottky barrier diode was mounted. It is sectional drawing for demonstrating the PN junction diode in embodiment of this invention. It is sectional drawing for demonstrating the (A) PN junction diode in embodiment of this invention, (B) It is sectional drawing for demonstrating the structure in which the PN junction diode was mounted.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Schottky barrier diode 2 N type single crystal silicon substrate 3 N type epitaxial layer 4 N type diffusion layer 5 N type diffusion layer 6 Trench 7 Trench 8 P type diffusion layer 9 P type diffusion layer 10 Insulating layer 11 Schottky barrier metal layer 12 Anode electrode 13 Cathode electrode 14 Cathode electrode 15 Conductive metal 16 Conductive metal 20 Contact hole 32 Resin sealing body 33 Bump 34 Bump 35 Bump 36 Contact hole 37 Contact hole 38 Contact hole 51 PN junction Diode 52 N-type single crystal silicon substrate 53 N-type epitaxial layer 54 N-type diffusion layer 55 N-type diffusion layer 56 Trench 57 Trench 58 P-type diffusion layer 60 Anode electrode 61 Cathode electrode 62 Cathode electrode 63 Conductive metal 64 Conductive gold Metal 72 Resin encapsulant 73 Bump 74 Bump 75 Bump 76 Contact hole 77 Contact hole 78 Contact hole 91 Schottky barrier diode 92 N type single crystal silicon substrate 93 N type epitaxial layer 94 N type diffusion layer 95 N type diffusion layer Diffusion layer 96 Trench 97 Trench 98 P-type diffusion layer 99 P-type diffusion layer 100 Insulating layer 101 Schottky barrier metal layer 102 Anode electrode 103 Cathode electrode 104 Cathode electrode 105 Metal layer 106 Conductive metal 107 Conductive metal 111 Contact Hole 122 Resin encapsulant 123 Bump 124 Bump 125 Bump 126 Contact hole 127 Contact hole 128 Contact hole 141 PN junction diode 142 N-type single crystal silicon substrate 14 N type epitaxial layer 144 N type diffusion layer 145 N type diffusion layer 146 Trench 147 Trench 148 P type diffusion layer 150 Anode electrode 151 Cathode electrode 152 Cathode electrode 153 Metal layer 154 Conductive metal 155 Conductive metal 162 Resin sealing Stopping body 163 Bump 164 Bump 165 Bump 166 Contact hole 167 Contact hole 168 Contact hole 181 Schottky barrier diode 182 N-type single crystal silicon substrate 183 N-type epitaxial layer 184 N-type diffusion layer 185 N-type diffusion layer 186 trench 187 Trench 188 P type diffusion layer 189 P type diffusion layer 190 Insulating layer 191 Schottky barrier metal layer 192 Anode electrode 193 Cathode electrode 194 Cathode electrode 195 Metal 196 Conductive metal 197 Conductive metal 201 Contact hole 212 Resin sealing body 213 Bump 214 Bump 215 Bump 216 Contact hole 217 Contact hole 218 Contact hole 231 PN junction diode 232 N-type single crystal silicon substrate 233 N-type epitaxial layer 234 N-type diffusion layer 235 N-type diffusion layer 236 Trench 237 Trench 238 P-type diffusion layer 240 Anode electrode 241 Cathode electrode 242 Cathode electrode 243 Metal layer 244 Conductive metal 245 Conductive metal 252 Resin sealing body 253 Bump 254 Bump 255 Bump 256 Contact hole 257 Contact hole 258 Contact hole

Claims (27)

A semiconductor layer used as a cathode region;
A cathode electrode formed on one main surface side of the semiconductor layer;
A Schottky barrier metal layer for Schottky junction to one main surface side of the semiconductor layer;
An anode electrode connected to the metal layer for Schottky barrier,
The semiconductor device is characterized in that a trench is formed in the semiconductor layer from the one main surface side, the trench is buried with a conductive metal, and the conductive metal is connected to the cathode electrode. The semiconductor layer is formed by depositing an epitaxial layer of one conductivity type on a substrate of one conductivity type,
A diffusion layer of one conductivity type is formed around the Schottky junction in the epitaxial layer,
The trench reaches the substrate and is disposed in a region where the diffusion layer of one conductivity type is formed,
The semiconductor device according to claim 1, wherein the trench is embedded with the conductive metal. An insulating layer is formed on the epitaxial layer, and the Schottky barrier metal layer is in Schottky junction with the epitaxial layer through an opening formed in the insulating layer.
3. The semiconductor device according to claim 2, wherein a reverse conductivity type diffusion layer is formed in the epitaxial layer located below the periphery of the Schottky barrier metal layer in the opening. The semiconductor device according to claim 2, wherein a resin sealing body is formed on one principal surface of the epitaxial layer so as to cover the cathode electrode and the anode electrode. The semiconductor device according to claim 4, wherein bumps connected to the cathode electrode and the anode electrode are formed through contact holes formed in the resin sealing body. A semiconductor layer used as a cathode region;
A diffusion layer used as an anode region formed in the semiconductor layer;
A cathode electrode and an anode electrode formed on one main surface side of the semiconductor layer;
2. A semiconductor device according to claim 1, wherein a trench is formed in the semiconductor layer from the one main surface side, the trench is buried with a conductive metal, and the conductive metal is connected to the cathode electrode. The semiconductor layer is formed by depositing an epitaxial layer of one conductivity type on a substrate of one conductivity type,
A diffusion layer of one conductivity type is formed around the diffusion layer as the anode region in the epitaxial layer,
The trench reaches the substrate and is disposed in a region where the diffusion layer of one conductivity type is formed,
The semiconductor device according to claim 6, wherein the trench is embedded with the conductive metal. 8. The semiconductor device according to claim 7, wherein a resin sealing body is formed on one main surface of the epitaxial layer so as to cover the cathode electrode and the anode electrode. 9. The semiconductor device according to claim 8, wherein bumps connected to the cathode electrode and the anode electrode are formed through contact holes formed in the resin sealing body. A semiconductor layer used as a cathode region;
A cathode electrode formed on one main surface side of the semiconductor layer;
A Schottky barrier metal layer for Schottky junction to one main surface side of the semiconductor layer;
An anode electrode connected to the metal layer for Schottky barrier,
On the other main surface side of the semiconductor layer facing the one main surface, a metal layer used as a cathode region is formed,
The semiconductor device is characterized in that a trench is formed in the semiconductor layer from the one main surface side, the trench is buried with a conductive metal, and the conductive metal is connected to the cathode electrode. The semiconductor layer is formed by depositing an epitaxial layer of one conductivity type on a substrate of one conductivity type,
A diffusion layer of one conductivity type is formed around the Schottky junction in the epitaxial layer,
The trench reaches the substrate and is disposed in a region where the diffusion layer of one conductivity type is formed,
The semiconductor device according to claim 10, wherein the trench is embedded with the conductive metal. An insulating layer is formed on the epitaxial layer, and the Schottky barrier metal layer is in Schottky junction with the epitaxial layer through an opening formed in the insulating layer.
The semiconductor device according to claim 11, wherein a diffusion layer of a reverse conductivity type is formed in the epitaxial layer located below the periphery of the Schottky barrier metal layer in the opening. The semiconductor device according to claim 11, wherein a resin sealing body is formed on one main surface of the epitaxial layer so as to cover the cathode electrode and the anode electrode. 14. The semiconductor device according to claim 13, wherein bumps connected to the cathode electrode and the anode electrode are formed through contact holes formed in the resin sealing body. A semiconductor layer used as a cathode region;
A diffusion layer used as an anode region formed in the semiconductor layer;
A cathode electrode and an anode electrode formed on one main surface side of the semiconductor layer;
On the other main surface side of the semiconductor layer facing the one main surface, a metal layer used as a cathode region is formed,
The semiconductor device is characterized in that a trench is formed in the semiconductor layer from the one main surface side, the trench is buried with a conductive metal, and the conductive metal is connected to the cathode electrode. The semiconductor layer is formed by depositing an epitaxial layer of one conductivity type on a substrate of one conductivity type,
A diffusion layer of one conductivity type is formed around the diffusion layer as the anode region in the epitaxial layer,
The trench reaches the substrate and is disposed in a region where the diffusion layer of one conductivity type is formed,
The semiconductor device according to claim 15, wherein the trench is embedded with the conductive metal. The semiconductor device according to claim 16, wherein a resin sealing body is formed on one principal surface of the epitaxial layer so as to cover the cathode electrode and the anode electrode. 18. The semiconductor device according to claim 17, wherein bumps connected to the cathode electrode and the anode electrode are formed through contact holes formed in the resin sealing body. A semiconductor layer used as a cathode region;
A cathode electrode formed on one main surface side of the semiconductor layer;
A Schottky barrier metal layer for Schottky junction to one main surface side of the semiconductor layer;
An anode electrode connected to the metal layer for Schottky barrier,
On the other main surface side of the semiconductor layer facing the one main surface, a metal layer used as a cathode region is formed,
The semiconductor layer includes a trench penetrating the semiconductor layer, the trench is buried with a conductive metal, and the conductive metal is connected to the cathode electrode and the metal layer. . The semiconductor layer is formed by depositing an epitaxial layer of one conductivity type on a substrate of one conductivity type,
A diffusion layer of one conductivity type is formed around the Schottky junction in the epitaxial layer,
The trench penetrates the substrate and the epitaxial layer, and is disposed in a region where the diffusion layer of one conductivity type is formed,
The semiconductor device according to claim 19, wherein the trench is embedded with the conductive metal. An insulating layer is formed on the epitaxial layer, and the Schottky barrier metal layer is in Schottky junction with the epitaxial layer through an opening formed in the insulating layer.
21. The semiconductor device according to claim 20, wherein a reverse conductivity type diffusion layer is formed in the epitaxial layer located below the periphery of the Schottky barrier metal layer in the opening. 21. The semiconductor device according to claim 20, wherein a resin sealing body is formed on one principal surface of the epitaxial layer so as to cover the cathode electrode and the anode electrode. 23. The semiconductor device according to claim 22, wherein a bump connected to the cathode electrode and the anode electrode is formed through a contact hole formed in the resin sealing body. A semiconductor layer used as a cathode region;
A diffusion layer used as an anode region formed in the semiconductor layer;
A cathode electrode and an anode electrode formed on one main surface side of the semiconductor layer;
On the other main surface side of the semiconductor layer facing the one main surface, a metal layer used as a cathode region is formed,
The semiconductor layer includes a trench penetrating the semiconductor layer, the trench is buried with a conductive metal, and the conductive metal is connected to the cathode electrode and the metal layer. . The semiconductor layer is formed by depositing an epitaxial layer of one conductivity type on a substrate of one conductivity type,
A diffusion layer of one conductivity type is formed around the diffusion layer as the anode region in the epitaxial layer,
The trench penetrates the substrate and the epitaxial layer, and is disposed in a region where the diffusion layer of one conductivity type is formed,
25. The semiconductor device according to claim 24, wherein the trench is embedded with the conductive metal. 26. The semiconductor device according to claim 25, wherein a resin sealing body is formed on one main surface of the epitaxial layer so as to cover the cathode electrode and the anode electrode. 27. The semiconductor device according to claim 26, wherein bumps connected to the cathode electrode and the anode electrode are formed through contact holes formed in the resin sealing body.