JP2013162067A - パワー半導体装置 - Google Patents
パワー半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 168
- 238000007789 sealing Methods 0.000 claims description 85
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000005538 encapsulation Methods 0.000 abstract 2
- 239000000463 material Substances 0.000 description 15
- 238000000034 method Methods 0.000 description 9
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】本発明に係るパワー半導体装置は、パワー半導体素子1と、パワー半導体素子1を制御する制御素子2と、パワー半導体素子1と制御素子2とをそれぞれ保持する、第1のフレーム3および第2のフレーム4と、パワー半導体素子1と第1のフレーム3とを電気的に接続する導電部材5と、パワー半導体素子1と、制御素子2と、第1のフレーム3および第2のフレーム4の少なくとも一部と、導電部材5とを覆う封止体6とを備え、導電部材5は、パワー半導体素子1表面と平行に延びるように配置される。
【選択図】図1
Description
以下、本発明の実施の形態1について説明する。まず、図1を参照して、実施の形態1に係るパワー半導体装置の構成を説明する。パワー半導体装置は、パワー半導体素子1と、パワー半導体素子1を制御する制御素子2と、パワー半導体素子1と制御素子2とをそれぞれ保持しながら外部との電気的接続を担う第1のフレーム3および第2のフレーム4と、パワー半導体素子1と第1のフレーム3とを電気的に接続する導電部材5と、封止体6とを備える。
以下、本発明の実施の形態2について説明する。まず、図4を参照して、本実施の形態に係るパワー半導体装置の構成を説明する。パワー半導体装置は、パワー半導体素子1と、パワー半導体素子1を制御する制御素子2と、パワー半導体素子1と制御素子2とをそれぞれ保持しながら外部との電気的接続を担う第1のフレーム3および第2のフレーム4と、パワー半導体素子1と第1のフレーム3とを電気的に接続する導電部材5と、封止体6とを備える。本実施の形態に係るパワー半導体装置は、基本的には図1に示した実施の形態1に係るパワー半導体装置と同じ構成部材から成るが、第2のフレーム4が第2の凹部7を含み、かつ導電部材5がワイヤボンディング法で形成される点で異なる。第1のフレーム3に設けた第1の凹部8の内部で、パワー半導体素子1が保持されており、導電部材5はこれらのパワー半導体素子1と第1のフレーム3とを電気的に接続している。第1の凹部8の深さは、パワー半導体素子1の厚みより十分深くなっている。このように、パワー半導体素子1を第1のフレーム3に形成された第1の凹部8の内部に配置することで、図1〜図3に示したパワー半導体装置と同様の効果を得ることができる。
以下、本発明の実施の形態3について説明する。まず、図6を参照して、本実施の形態に係るパワー半導体装置を説明する。パワー半導体装置は、パワー半導体素子1と、パワー半導体素子1を制御する制御素子2と、パワー半導体素子1と制御素子2とをそれぞれ保持しながら外部との電気的接続を担う第1のフレーム3および第2のフレーム4と、パワー半導体素子1と第1のフレーム3とを電気的に接続する導電部材5と、封止体6とを備える。本実施の形態に係るパワー半導体装置は、基本的には図4に示した実施の形態2に係るパワー半導体装置と同じ構成部材から成るが、制御素子2が第2のフレーム4の裏面側に保持されている点が図4に示したパワー半導体装置と異なる。
Claims (6)
- パワー半導体素子と、
前記パワー半導体素子を制御する制御素子と、
前記パワー半導体素子と前記制御素子とをそれぞれ保持する、第1および第2のフレームと、
前記パワー半導体素子と前記第1のフレームとを電気的に接続する導電部材と、
前記パワー半導体素子と、前記制御素子と、前記第1および第2のフレームの少なくとも一部と、前記導電部材とを覆う封止体とを備え、
前記導電部材は、前記パワー半導体素子表面と平行に延びるように配置される、パワー半導体装置。 - 前記第2のフレームは凹部を含み、
前記凹部に前記制御素子を保持する、請求項1に記載のパワー半導体装置。 - 前記第1のフレームにおいて前記パワー半導体素子が保持された側と反対側に位置する面である、前記第2のフレームの裏面に、前記制御素子が保持されている、請求項1に記載のパワー半導体装置。
- パワー半導体素子と、
前記パワー半導体素子を制御する制御素子と、
前記パワー半導体素子と前記制御素子とをそれぞれ保持する、第1および第2のフレームと、
前記パワー半導体素子と、前記制御素子と、前記第1および第2のフレームとを覆う封止体とを備え、
前記第2のフレームは凹部を含み、
前記凹部に前記制御素子を保持する、パワー半導体装置。 - パワー半導体素子と、
前記パワー半導体素子を制御する制御素子と、
前記パワー半導体素子と前記制御素子とをそれぞれ保持する、第1および第2のフレームと、
前記パワー半導体素子と、前記制御素子と、前記第1および第2のフレームとを覆う封止体とを備え、
前記第1のフレームにおいて前記パワー半導体素子が保持された側と反対側に位置する面である、前記第2のフレームの裏面に、前記制御素子が保持されている、パワー半導体装置。 - 前記パワー半導体素子と前記第1のフレームとを電気的に接続する導電部材を備え、
前記第1のフレームは凹部を含み、
前記パワー半導体素子は前記第1のフレームの前記凹部に保持され、
前記導電部材は、前記第1のフレームの前記凹部の内部において前記第1のフレームと電気的に接続する、請求項4または請求項5に記載のパワー半導体装置。
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Cited By (1)
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JP2018081947A (ja) * | 2016-11-14 | 2018-05-24 | 三菱電機株式会社 | パワーモジュールおよびその製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000091499A (ja) * | 1998-09-11 | 2000-03-31 | Hitachi Ltd | パワー半導体モジュール並びにそれを用いた電動機駆動システム |
JP2001250911A (ja) * | 2000-03-07 | 2001-09-14 | Mitsubishi Electric Corp | 樹脂封止形電力用半導体装置 |
JP2001339041A (ja) * | 2000-05-29 | 2001-12-07 | Toshiba Digital Media Engineering Corp | 半導体装置及び半導体装置の製造方法 |
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JP2000091499A (ja) * | 1998-09-11 | 2000-03-31 | Hitachi Ltd | パワー半導体モジュール並びにそれを用いた電動機駆動システム |
JP2001250911A (ja) * | 2000-03-07 | 2001-09-14 | Mitsubishi Electric Corp | 樹脂封止形電力用半導体装置 |
JP2001339041A (ja) * | 2000-05-29 | 2001-12-07 | Toshiba Digital Media Engineering Corp | 半導体装置及び半導体装置の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2018081947A (ja) * | 2016-11-14 | 2018-05-24 | 三菱電機株式会社 | パワーモジュールおよびその製造方法 |
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