JP2013145852A - Semiconductor package and manufacturing method of the same - Google Patents
Semiconductor package and manufacturing method of the same Download PDFInfo
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- JP2013145852A JP2013145852A JP2012006552A JP2012006552A JP2013145852A JP 2013145852 A JP2013145852 A JP 2013145852A JP 2012006552 A JP2012006552 A JP 2012006552A JP 2012006552 A JP2012006552 A JP 2012006552A JP 2013145852 A JP2013145852 A JP 2013145852A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000011347 resin Substances 0.000 claims abstract description 68
- 229920005989 resin Polymers 0.000 claims abstract description 68
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 238000007639 printing Methods 0.000 claims abstract description 13
- 238000007599 discharging Methods 0.000 claims abstract description 8
- 239000007787 solid Substances 0.000 claims description 7
- 239000012530 fluid Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 27
- 238000009413 insulation Methods 0.000 abstract 3
- 238000001354 calcination Methods 0.000 abstract 1
- 238000010304 firing Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/24247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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Abstract
Description
本発明は、搭載部材上に搭載した半導体素子の電極部と該搭載部材側の電極部との間を接続する配線及びその下地層の構造を改良した半導体パッケージ及びその製造方法に関する発明である。 The present invention relates to a semiconductor package having an improved structure of wiring and an underlying layer for connecting between an electrode portion of a semiconductor element mounted on a mounting member and an electrode portion on the mounting member side, and a manufacturing method thereof.
従来より、半導体素子の実装工程では、半導体素子を搭載部材(回路基板、リードフレーム等)にダイボンドした後に、該半導体素子側の電極部と搭載部材側の電極部との間をワイヤボンディングで配線するのが一般的である。 Conventionally, in the mounting process of a semiconductor element, after the semiconductor element is die-bonded to a mounting member (circuit board, lead frame, etc.), wiring is performed between the electrode part on the semiconductor element side and the electrode part on the mounting member side by wire bonding. It is common to do.
しかし、特許文献1(特許第3992038号公報)に記載されているように、ワイヤボンディングを行うときの機械的なストレスによって不良が発生する可能性があるため、ワイヤボンディングに代わる接続信頼性の高い実装構造を低コストで実現することを目的として、配線基板上に搭載した半導体素子の周囲に流動性の樹脂材料をディスペンサで吐出して硬化させて、半導体素子の上面と配線基板の表面との間を傾斜面でつなぐ樹脂スロープを形成した後、半導体素子上面の電極部と配線基板の電極部との間を接続する配線パターンを、インクジェット等の液滴吐出法により樹脂スロープ上に形成する配線技術が提案されている。 However, as described in Patent Document 1 (Japanese Patent No. 3992038), there is a possibility that defects may occur due to mechanical stress when wire bonding is performed. Therefore, connection reliability that replaces wire bonding is high. For the purpose of realizing the mounting structure at a low cost, a fluid resin material is discharged around a semiconductor element mounted on the wiring board with a dispenser and cured, so that the upper surface of the semiconductor element and the surface of the wiring board are After forming a resin slope that connects the surfaces with an inclined surface, a wiring pattern that connects the electrode part on the upper surface of the semiconductor element and the electrode part of the wiring board is formed on the resin slope by a droplet discharge method such as inkjet. Technology has been proposed.
ところで、液滴吐出法や印刷法で形成する配線は、配線パターン描画後に所定の焼成温度(例えば230℃)で焼成する必要がある。このため、配線焼成時に、配線の下地樹脂層も加熱されて、下地樹脂層の内部で分解したガスが発生し、この分解ガスがいわゆるアウトガスとして下地樹脂層の表面側に漏れ出してくる。このため、配線焼成時に、下地樹脂層と配線との接合面にもアウトガスが漏れ出して配線内部に侵入してしまい、このアウトガスによってインク塗膜に含まれる有機成分の分解と飛散が十分に行われないため、配線の緻密度が低下して配線の抵抗値が高くなるという問題があった。 Incidentally, the wiring formed by the droplet discharge method or the printing method needs to be fired at a predetermined firing temperature (for example, 230 ° C.) after the wiring pattern is drawn. For this reason, when the wiring is baked, the underlying resin layer of the wiring is also heated to generate decomposed gas inside the underlying resin layer, and this decomposed gas leaks out to the surface side of the underlying resin layer as so-called outgas. For this reason, when the wiring is baked, outgas leaks out to the joint surface between the base resin layer and the wiring and enters the wiring, and this outgas sufficiently decomposes and scatters the organic components contained in the ink coating film. Therefore, there is a problem that the wiring density decreases and the wiring resistance value increases.
例えば、LEDパッケージで、配線の抵抗値が高くなると、LED点灯時にLED素子に流れる電流が減少して輝度が低下するだけでなく、配線の発熱量が増加して素子温度が上昇し、耐久性が低下するおそれもある。 For example, in a LED package, when the wiring resistance value increases, not only does the current flowing through the LED element decrease when the LED is lit, but the brightness decreases, the heating value of the wiring increases, the element temperature increases, and the durability May decrease.
そこで、本発明が解決しようとする課題は、半導体素子側の電極部と搭載部材側の電極部との間を接続する配線を液滴吐出法又は印刷法で描画して焼成する際の下地樹脂層からのアウトガスによる配線の高抵抗値化を防止することができる半導体パッケージ及びその製造方法を提供することである。 Therefore, the problem to be solved by the present invention is to provide a base resin when a wiring connecting between the electrode part on the semiconductor element side and the electrode part on the mounting member side is drawn and fired by a droplet discharge method or a printing method It is an object to provide a semiconductor package and a method for manufacturing the same that can prevent a wiring from having a high resistance value due to outgas from the layer.
上記課題を解決するために、請求項1に係る発明は、搭載部材上に半導体素子を搭載し、該半導体素子側の電極部と該搭載部材側の電極部との間を配線で接続した半導体パッケージにおいて、前記搭載部材上の前記半導体素子の周囲に絶縁性樹脂を設けて該搭載部材上の該半導体素子側の電極部と該搭載部材側の電極部との間の配線経路の下地樹脂層を形成し、前記配線経路の下地樹脂層上にガスバリア性(ガス不透過性)を有する中間絶縁層を形成し、導電性のインクを前記中間絶縁層上に吐出又は印刷し又は固体状の導電部材を実装して前記配線のパターンを形成して焼成した構成としたものである。 In order to solve the above-mentioned problem, the invention according to claim 1 is a semiconductor in which a semiconductor element is mounted on a mounting member, and the electrode part on the semiconductor element side and the electrode part on the mounting member side are connected by wiring. In the package, an insulating resin is provided around the semiconductor element on the mounting member, and a base resin layer of a wiring path between the electrode part on the semiconductor element side and the electrode part on the mounting member side on the mounting member An intermediate insulating layer having a gas barrier property (gas impermeability) is formed on the base resin layer of the wiring path, and conductive ink is ejected or printed on the intermediate insulating layer, or a solid conductive layer is formed. The member is mounted and the wiring pattern is formed and fired.
この構成では、下地樹脂層とその上に形成する配線との間にガスバリア性(ガス不透過性)を有する中間絶縁層が介在されているため、配線焼成時に下地樹脂層で発生したアウトガスが配線内部に侵入することを中間絶縁層によって防止でき、配線の高抵抗値化を防止できる。 In this configuration, since an intermediate insulating layer having a gas barrier property (gas impermeability) is interposed between the base resin layer and the wiring formed thereon, outgas generated in the base resin layer during wiring firing is connected to the wiring. Intrusion into the inside can be prevented by the intermediate insulating layer, and an increase in the resistance value of the wiring can be prevented.
この場合、請求項2のように、下地樹脂層は、搭載部材上の半導体素子の周囲に流動性の絶縁性樹脂を吐出して硬化させて形成しても良いし、固体状の絶縁部材を実装して形成しても良い。 In this case, as described in claim 2, the base resin layer may be formed by discharging and curing a fluid insulating resin around the semiconductor element on the mounting member, or a solid insulating member. It may be formed by mounting.
本発明は、液滴吐出法又は印刷法で配線を形成可能な構造であれば、様々な構造の半導体パッケージに適用可能であり、例えば、LED等の発光素子パッケージに適用しても良い。 The present invention can be applied to semiconductor packages having various structures as long as the wiring can be formed by a droplet discharge method or a printing method. For example, the present invention may be applied to a light emitting element package such as an LED.
本発明をLED等の発光素子パッケージに適用する場合は、請求項3のように、発光素子の周囲に、透明な絶縁性樹脂を吐出して硬化させて透明な下地樹脂層を形成し、ガスバリア性を有する絶縁性インクを下地樹脂層上に吐出又は印刷して中間絶縁層を線状又は帯状に形成するようにすると良い。本発明を発光素子パッケージに適用すれば、発光時に発光素子に流れる電流が増加して輝度が増大するだけでなく、配線の発熱量が減少して素子温度の上昇を少なくすることができ、耐久性を向上させることができる。しかも、配線の下地となる中間絶縁層は、発光素子の周囲から透明な下地樹脂層に照射される光の放出を減少させる要因となるため、中間絶縁層を線状又は帯状に形成すれば、発光素子の周囲から透明な下地樹脂層を通して放出される光が中間絶縁層で減少される割合を少なくできて、外部に放出される光の取り出し効率を高めることができる。 When the present invention is applied to a light emitting device package such as an LED, a transparent base resin layer is formed by discharging a transparent insulating resin around the light emitting device to form a gas barrier. The intermediate insulating layer may be formed in a linear shape or a strip shape by discharging or printing an insulating ink having a property on the base resin layer. When the present invention is applied to a light emitting device package, not only the current flowing through the light emitting device during light emission increases and the brightness increases, but also the amount of heat generated in the wiring decreases and the increase in device temperature can be reduced, and durability is improved. Can be improved. Moreover, since the intermediate insulating layer serving as the base of the wiring is a factor that reduces the emission of light irradiated from the periphery of the light emitting element to the transparent base resin layer, if the intermediate insulating layer is formed in a linear or belt shape, The rate at which light emitted from the periphery of the light emitting element through the transparent base resin layer is reduced by the intermediate insulating layer can be reduced, and the extraction efficiency of light emitted to the outside can be increased.
具体的には、請求項4のように、中間絶縁層を、配線が該中間絶縁層からはみ出さないように該配線の線幅よりも製造ばらつき相当値以上太い線幅に形成すれば良い。中間絶縁層の線幅を配線の線幅よりも製造ばらつき相当値以上太い線幅に形成すれば、製造時に中間絶縁層の位置ずれや配線の位置ずれが生じても、配線の下面全体を中間絶縁層で確実に覆うことができ、配線焼成時に下地樹脂層で発生したアウトガスが配線内部に侵入することを中間絶縁層によって確実に防止できる。 Specifically, as in claim 4, the intermediate insulating layer may be formed to have a line width that is thicker than the line width of the wiring by a value equal to or greater than the manufacturing variation so that the wiring does not protrude from the intermediate insulating layer. If the line width of the intermediate insulating layer is formed to be thicker than the line width of the wiring by an amount equivalent to or more than the manufacturing variation, even if the intermediate insulating layer or the wiring is misaligned during manufacturing, It can be reliably covered with the insulating layer, and the intermediate insulating layer can reliably prevent outgas generated in the base resin layer during wiring firing from entering the wiring.
この場合、請求項5のように、中間絶縁層を中間絶縁層の上面全体に形成しても良いことは言うまでもない。 In this case, it goes without saying that the intermediate insulating layer may be formed on the entire upper surface of the intermediate insulating layer as in claim 5.
尚、請求項6に係る発明は、請求項1に係る「半導体パッケージ」の発明と実質的に同一の技術思想を、カテゴリーの異なる「半導体パッケージの製造方法」の発明として記載したものである。 The invention according to claim 6 describes the technical idea substantially the same as the invention of “semiconductor package” according to claim 1 as an invention of “method of manufacturing a semiconductor package” of a different category.
以下、本発明を実施するための形態をLEDパッケージに適用して具体化した2つの実施例1,2を説明する。 Hereinafter, two Examples 1 and 2 which embodied the form for implementing this invention to an LED package are demonstrated.
本発明の実施例1を図1乃至図3に基づいて説明する。
搭載部材10は、リードフレーム11に素子搭載凹部12を有するパッケージ本体13を樹脂で成形して構成されている。この搭載部材10の素子搭載凹部12の底面中央部には、半導体素子であるLED素子14(発光素子)がダイボンディング(接合)されている。素子搭載凹部12の深さ寸法(高さ寸法)は、LED素子14の高さ寸法とほぼ同一に設定され、素子搭載凹部12内に搭載したLED素子14上面の電極部15が搭載部材10上面のリードフレーム11の電極部11aとほぼ同じ高さとなっている。
A first embodiment of the present invention will be described with reference to FIGS.
The
搭載部材10の素子搭載凹部12内のうちのLED素子14の周囲に、透明な絶縁性樹脂をインクジェット、ディスペンサ等の液滴吐出法により充填して透明な下地樹脂層16が形成されている。これにより、LED素子14上面の電極部15と搭載部材10上面の電極部11aとの間をつなぐ配線経路は、LED素子14の周囲に充填された下地樹脂層16で平坦化され、該下地樹脂層16の上面に、後述する配線17の下地となる中間絶縁層18がLED素子14上面の電極部15と搭載部材10上面の電極部11aとに跨がって線状又は帯状に形成されている。中間絶縁層18の形成方法は、インクジェット、ディスペンサ等の液滴吐出法又は印刷法により、ガスバリア性(ガス不透過性)を有する絶縁性材料のインクを下地樹脂層16上に吐出して、中間絶縁層18のパターンを下地樹脂層16上に線状又は帯状に描画して乾燥・硬化させ、ガスバリア性を有する中間絶縁層18を形成する。
A transparent
ここで、ガスバリア性を有する中間絶縁層18の材料としては、例えば、エポキシ樹脂系、ポリイミド樹脂系、ガラス(SiO2 )系等の絶縁性材料があり、これらの絶縁性材料の中から、ガスバリア性とその他の特性(例えば光透過性、耐湿性、下地樹脂層16及び配線17に対する密着性等)を考慮して選択すれば良い。
Here, as the material of the intermediate insulating
そして、中間絶縁層18の乾燥・硬化後に、インクジェット、ディスペンサ等の液滴吐出法により導電性のインク(Ag等の導体粒子を含むインク)を中間絶縁層18上に吐出して、配線17のパターンをLED素子14上面の電極部15と搭載部材10上面の電極部11aとに跨がって中間絶縁層18上に描画し、これを乾燥して焼成して、LED素子14上面の電極部15と搭載部材10上面の電極部11aとの間を配線17で接続する。この際、配線17の焼成温度は、200℃以上(例えば230℃)で、焼成時間は30分〜60分程度である。
Then, after the intermediate insulating
この場合、中間絶縁層18は、配線17が該中間絶縁層18からはみ出さないように該配線17の線幅よりも製造ばらつき相当値以上太い線幅に形成されている。具体的には、中間絶縁層18の線幅は、例えば、配線17の線幅の1.2〜2.5倍、より好ましくは、1.5〜2.0倍の範囲で設定すると良い。尚、搭載部材10の素子搭載凹部12内に搭載したLED素子14及び配線17等は、透明な封止材料(図示せず)によって封止されている。
In this case, the
以上説明した本実施例1によれば、LED素子14の周囲に充填した下地樹脂層16とその上に形成する配線17との間にガスバリア性を有する中間絶縁層18が介在されているため、配線17の焼成時に下地樹脂層16で発生したアウトガスが配線17の内部に侵入することを中間絶縁層18によって防止でき、配線17の高抵抗値化を防止することができる。本発明者らの実験結果によれば、中間絶縁層18を形成することで、配線17の体積抵抗率が1/2程度になることが確認されている。これにより、LED素子14の発光時にLED素子14に流れる電流が増加して輝度が増大するだけでなく、配線17の発熱量が減少してLED素子14の温度上昇を少なくすることができ、耐久性を向上させることができる。
According to the first embodiment described above, since the intermediate insulating
しかも、配線17の下地となる中間絶縁層18は、光の放出を減少させる要因となるため、本実施例1のように、中間絶縁層18を線状又は帯状に形成することで、LED素子14の周囲から透明な下地樹脂層16を通して放出される光が中間絶縁層18で減少される割合を少なくできて、外部に放出される光の取り出し効率を高めることができる。
In addition, since the intermediate insulating
また、本実施例1では、中間絶縁層18を、配線17が該中間絶縁層18からはみ出さないように該配線17の線幅よりも製造ばらつき相当値以上太い線幅に形成するようにしたので、製造時に中間絶縁層18の位置ずれや配線17の位置ずれが生じても、配線17の下面全体を中間絶縁層18で確実に覆うことができ、配線17の焼成時に下地樹脂層16で発生したアウトガスが配線17の内部に侵入することを中間絶縁層18によって確実に防止できる。
In the first embodiment, the intermediate insulating
次に、本発明の実施例2を図4に基づいて説明する。
搭載部材21は、リードフレーム22に素子搭載凹部23を有するパッケージ本体24を樹脂で成形して構成され、該素子搭載凹部23の側面が傾斜状に形成されている。素子搭載凹部23の底面には、リードフレーム22の素子搭載部22a(ダイパッド)が露出し、該素子搭載部22a上に半導体素子であるLED素子25(発光素子)がダイボンド(接合)されている。
Next, a second embodiment of the present invention will be described with reference to FIG.
The mounting
素子搭載凹部23の傾斜状の側面には、LED素子25上面の2つの電極部26と接続する2つの電極部27が形成されている。各電極部27は、それぞれリードフレーム22に一体に形成されている。この場合、素子搭載凹部23の側面に形成する電極部26の高さ方向の幅が広くなるほど、搭載可能なLED素子25の高さ寸法の範囲が広がることを考慮して、本実施例2では、素子搭載凹部23に側面に形成する電極部27は、該素子搭載凹部23の側面の上部から下部まで延びるように形成され、且つ、該電極部27がLED素子25の光を反射する反射板(リフレクター)としても機能するように構成されている。
Two
搭載部材21の素子搭載凹部23内に搭載可能なLED素子25は、高さ寸法が該素子搭載凹部23の側面(電極部27)の高さ寸法以下で且つリードフレーム22の素子搭載部22a上に搭載可能なサイズのLED素子である。これにより、高さ寸法の異なる複数種のLED素子25を同一仕様・寸法の搭載部材21の素子搭載凹部23内に搭載できるようになっている。
The
素子搭載凹部23内のうちのLED素子25の周囲に、透明な絶縁性樹脂をインクジェット、ディスペンサ等の液滴吐出法により充填して透明な下地樹脂層28が形成され、該下地樹脂層28の上面の高さ位置がLED素子25の電極部26上面の高さ位置と一致することで、LED素子25上面の電極部26と素子搭載凹部23側面の電極部27との間の配線経路が下地樹脂層28で平坦化されている。
A transparent
この下地樹脂層28の上面に、後述する配線29の下地となる中間絶縁層30がLED素子25上面の電極部26と素子搭載凹部23側面の電極部27とに跨がって線状又は帯状に形成されている。中間絶縁層30の形成方法は、インクジェット、ディスペンサ等の液滴吐出法又は印刷法により、前記実施例1と同様のガスバリア性を有する絶縁性材料のインクを下地樹脂層28上に吐出して中間絶縁層30のパターンを線状又は帯状に描画して乾燥・硬化させ、ガスバリア性を有する中間絶縁層30を形成する。
On the upper surface of the
中間絶縁層30の乾燥・硬化後に、インクジェット、ディスペンサ等の液滴吐出法により導電性のインク(Ag等の導体粒子を含むインク)を中間絶縁層30上に吐出して、該中間絶縁層30上に、配線29のパターンをLED素子25上面の電極部26と素子搭載凹部23側面の電極部27とに跨がって描画し、これを乾燥して焼成して、LED素子25上面の電極部26と素子搭載凹部23側面の電極部27との間を該配線29で接続する。この際、配線29の焼成温度は、200℃以上(例えば230℃)で、焼成時間は30分程度である。
After the intermediate insulating
前記実施例1と同様に、中間絶縁層30は、配線29が該中間絶縁層30からはみ出さないように該配線29の線幅よりも製造ばらつき相当値以上太い線幅に形成されている。尚、素子搭載凹部23内に搭載したLED素子25及び配線29等は、透明な封止材料(図示せず)によって封止されている。
As in the first embodiment, the intermediate insulating
以上説明した本実施例2でも、LED素子25の周囲に充填した下地樹脂層28とその上に形成する配線29との間にガスバリア性を有する中間絶縁層30が介在されているため、前記実施例1と同様の効果を得ることができる。
Also in the second embodiment described above, since the intermediate insulating
尚、上記実施例1,2では、搭載部材の素子搭載凹部内にLED素子を搭載して、該素子搭載凹部内のうちのLED素子の周囲に、透明な絶縁性樹脂を充填して下地樹脂層を形成するようにしたが、搭載部材(回路基板、リードフレーム等)の平坦面上に搭載したLED素子等の半導体素子の周囲に、流動性の樹脂材料をディスペンサで吐出して、半導体素子の上面と搭載部材の表面との間を傾斜面でつなぐスロープ状の下地樹脂層を形成した後、このスロープ状の下地樹脂層上にガスバリア性を有する中間絶縁層を形成し、導電性のインクを前記中間絶縁層上に吐出又は印刷して配線のパターンを形成して焼成した構成としても良い。 In Examples 1 and 2, the LED element is mounted in the element mounting recess of the mounting member, and the base resin is filled with a transparent insulating resin around the LED element in the element mounting recess. Although a layer is formed, a fluid resin material is discharged by a dispenser around a semiconductor element such as an LED element mounted on a flat surface of a mounting member (circuit board, lead frame, etc.), and the semiconductor element After forming a slope-shaped base resin layer connecting the upper surface of the substrate and the surface of the mounting member with an inclined surface, an intermediate insulating layer having a gas barrier property is formed on the slope-shaped base resin layer, and conductive ink is formed. It is good also as a structure which discharged or printed on the said intermediate | middle insulating layer, formed the pattern of the wiring, and baked.
また、上記実施例1,2では、中間絶縁層を配線の線幅よりも製造ばらつき相当値以上太い線幅の線状に形成したが、中間絶縁層を中間絶縁層の上面全体に形成しても良いことは言うまでもない。 In Examples 1 and 2, the intermediate insulating layer is formed in a line shape having a line width thicker than the line width of the wiring by a value corresponding to the manufacturing variation, but the intermediate insulating layer is formed on the entire upper surface of the intermediate insulating layer. It goes without saying that it is also good.
また、配線を形成する方法は、液滴吐出法に限定されず、スクリーン印刷等の印刷法で形成しても良いし、或は、固体状の導体を中間絶縁層上に実装しても良い。 Further, the method of forming the wiring is not limited to the droplet discharge method, and may be formed by a printing method such as screen printing, or a solid conductor may be mounted on the intermediate insulating layer. .
また、中間絶縁層を形成する方法は、液滴吐出法又は印刷法に限定されず、固体状の絶縁物を下地樹脂層上に装着しても良く、ガスバリア性フィルムを下地樹脂層上に接合して形成しても良い。 The method for forming the intermediate insulating layer is not limited to the droplet discharge method or the printing method, and a solid insulating material may be mounted on the base resin layer, and a gas barrier film is bonded on the base resin layer. May be formed.
その他、本発明は、LED素子以外の半導体素子を搭載部材に搭載した半導体パッケージにも適用して実施できる等、要旨を逸脱しない範囲内で種々変更して実施できることは言うまでもない。 In addition, it goes without saying that the present invention can be implemented with various modifications without departing from the gist, such as being applicable to a semiconductor package in which a semiconductor element other than an LED element is mounted on a mounting member.
10…搭載部材、11…リードフレーム、11a…電極部、12…素子搭載凹部、13…パッケージ本体、14…LED素子(発光素子,半導体素子)、15…電極部、16…下地樹脂層、17…配線、18…中間絶縁層、21…搭載部材、22…リードフレーム、23…素子搭載凹部、24…パッケージ本体、25…LED素子(発光素子,半導体素子)、26,27…電極部、28…下地樹脂層、29…配線、30…中間絶縁層
DESCRIPTION OF
Claims (6)
前記搭載部材上の前記半導体素子の周囲に絶縁性樹脂を設けて該搭載部材上の該半導体素子側の電極部と該搭載部材側の電極部との間の配線経路の下地樹脂層を形成し、
前記配線経路の下地樹脂層上にガスバリア性を有する中間絶縁層を形成し、
導電性のインクを前記中間絶縁層上に吐出又は印刷し又は固体状の導電部材を実装して前記配線のパターンを形成して焼成したことを特徴とする半導体パッケージ。 In a semiconductor package in which a semiconductor element is mounted on a mounting member and the electrode part on the semiconductor element side and the electrode part on the mounting member side are connected by wiring,
An insulating resin is provided around the semiconductor element on the mounting member to form a base resin layer of a wiring path between the electrode part on the mounting element side and the electrode part on the mounting member side on the mounting member. ,
Forming an intermediate insulating layer having gas barrier properties on the underlying resin layer of the wiring path;
A semiconductor package, wherein conductive ink is ejected or printed on the intermediate insulating layer, or a solid conductive member is mounted to form a pattern of the wiring and fired.
前記絶縁性樹脂は、透明な絶縁性樹脂であり、
前記中間絶縁層は、ガスバリア性を有する絶縁性インクを前記配線経路の下地樹脂層上に吐出又は印刷して線状又は帯状に形成されていることを特徴とする請求項1又は2に記載の半導体パッケージ。 The semiconductor element is a light emitting element,
The insulating resin is a transparent insulating resin,
3. The intermediate insulating layer according to claim 1, wherein the intermediate insulating layer is formed in a linear shape or a strip shape by discharging or printing an insulating ink having a gas barrier property on a base resin layer of the wiring path. Semiconductor package.
前記搭載部材上に前記半導体素子を搭載する工程と、
前記搭載部材上の前記半導体素子の周囲に絶縁性樹脂を設けて該半導体素子側の電極部と該搭載部材側の電極部との間の配線経路の下地樹脂層を形成する工程と、
前記配線経路の下地樹脂層上にガスバリア性を有する中間絶縁層を形成する工程と、
導電性のインクを前記中間絶縁層上に吐出又は印刷し又は固体状の導電部材を実装して前記配線のパターンを形成して焼成する工程と
を含むことを特徴とする半導体パッケージの製造方法。 In a manufacturing method of a semiconductor package in which a semiconductor element is mounted on a mounting member and the electrode part on the semiconductor element side and the electrode part on the mounting member side are connected by wiring.
Mounting the semiconductor element on the mounting member;
Providing an insulating resin around the semiconductor element on the mounting member to form a base resin layer of a wiring path between the electrode part on the semiconductor element side and the electrode part on the mounting member side;
Forming an intermediate insulating layer having a gas barrier property on a base resin layer of the wiring path;
And a step of ejecting or printing conductive ink on the intermediate insulating layer or mounting a solid conductive member to form a pattern of the wiring and baking the semiconductor package.
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