JP2013145852A - Semiconductor package and manufacturing method of the same - Google Patents

Semiconductor package and manufacturing method of the same Download PDF

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JP2013145852A
JP2013145852A JP2012006552A JP2012006552A JP2013145852A JP 2013145852 A JP2013145852 A JP 2013145852A JP 2012006552 A JP2012006552 A JP 2012006552A JP 2012006552 A JP2012006552 A JP 2012006552A JP 2013145852 A JP2013145852 A JP 2013145852A
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wiring
insulating layer
intermediate insulating
base resin
mounting member
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JP5905267B2 (en
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Kazuhiro Sugiyama
和裕 杉山
Kenji Tsukada
謙磁 塚田
Masato Suzuki
雅登 鈴木
Masatoshi Fujita
政利 藤田
Akihiro Kawajiri
明宏 川尻
Yoshitaka Hashimoto
良崇 橋本
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Fuji Corp
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Fuji Machine Manufacturing Co Ltd
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Priority to CN201280057767.7A priority patent/CN103959450B/en
Priority to PCT/JP2012/077870 priority patent/WO2013077144A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/24247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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Abstract

PROBLEM TO BE SOLVED: To prevent a high resistance value of wiring caused by an out gas from a base resin layer when wiring is formed on the base resin layer by a droplet discharge method or a printing method and calcined.SOLUTION: A semiconductor package manufacturing method comprises: mounting an LED element 14 on the center of a bottom surface of an element mounting recess 12 of a mounting component 10; forming a base resin layer 16 by filling a fluent insulating resin in the element mounting recess 12 around the LED element 14 and hardening the insulating resin; planarizing a wiring path between an electrode part 15 on a top face of the LED element 14 and an electrode part 11a on a top face of the mounting component 10 by the base resin layer 16; subsequently, drawing an intermediate insulation layer 18 having a gas barrier property linearly or in a belt-shape on the base resin layer 16 by a droplet discharge method or a printing method; and discharging or printing a conductive ink on the intermediate insulation layer 18 to draw and calcine a pattern. At the time of calcination, an out gas generated at the base resin layer 16 is prevented by the intermediate insulation layer 18 from entering the wiring 17 to the inside.

Description

本発明は、搭載部材上に搭載した半導体素子の電極部と該搭載部材側の電極部との間を接続する配線及びその下地層の構造を改良した半導体パッケージ及びその製造方法に関する発明である。   The present invention relates to a semiconductor package having an improved structure of wiring and an underlying layer for connecting between an electrode portion of a semiconductor element mounted on a mounting member and an electrode portion on the mounting member side, and a manufacturing method thereof.

従来より、半導体素子の実装工程では、半導体素子を搭載部材（回路基板、リードフレーム等）にダイボンドした後に、該半導体素子側の電極部と搭載部材側の電極部との間をワイヤボンディングで配線するのが一般的である。   Conventionally, in the mounting process of a semiconductor element, after the semiconductor element is die-bonded to a mounting member (circuit board, lead frame, etc.), wiring is performed between the electrode part on the semiconductor element side and the electrode part on the mounting member side by wire bonding. It is common to do.

しかし、特許文献１（特許第３９９２０３８号公報）に記載されているように、ワイヤボンディングを行うときの機械的なストレスによって不良が発生する可能性があるため、ワイヤボンディングに代わる接続信頼性の高い実装構造を低コストで実現することを目的として、配線基板上に搭載した半導体素子の周囲に流動性の樹脂材料をディスペンサで吐出して硬化させて、半導体素子の上面と配線基板の表面との間を傾斜面でつなぐ樹脂スロープを形成した後、半導体素子上面の電極部と配線基板の電極部との間を接続する配線パターンを、インクジェット等の液滴吐出法により樹脂スロープ上に形成する配線技術が提案されている。   However, as described in Patent Document 1 (Japanese Patent No. 3992038), there is a possibility that defects may occur due to mechanical stress when wire bonding is performed. Therefore, connection reliability that replaces wire bonding is high. For the purpose of realizing the mounting structure at a low cost, a fluid resin material is discharged around a semiconductor element mounted on the wiring board with a dispenser and cured, so that the upper surface of the semiconductor element and the surface of the wiring board are After forming a resin slope that connects the surfaces with an inclined surface, a wiring pattern that connects the electrode part on the upper surface of the semiconductor element and the electrode part of the wiring board is formed on the resin slope by a droplet discharge method such as inkjet. Technology has been proposed.

特許第３９９２０３８号公報Japanese Patent No. 3992038

ところで、液滴吐出法や印刷法で形成する配線は、配線パターン描画後に所定の焼成温度（例えば２３０℃）で焼成する必要がある。このため、配線焼成時に、配線の下地樹脂層も加熱されて、下地樹脂層の内部で分解したガスが発生し、この分解ガスがいわゆるアウトガスとして下地樹脂層の表面側に漏れ出してくる。このため、配線焼成時に、下地樹脂層と配線との接合面にもアウトガスが漏れ出して配線内部に侵入してしまい、このアウトガスによってインク塗膜に含まれる有機成分の分解と飛散が十分に行われないため、配線の緻密度が低下して配線の抵抗値が高くなるという問題があった。   Incidentally, the wiring formed by the droplet discharge method or the printing method needs to be fired at a predetermined firing temperature (for example, 230 ° C.) after the wiring pattern is drawn. For this reason, when the wiring is baked, the underlying resin layer of the wiring is also heated to generate decomposed gas inside the underlying resin layer, and this decomposed gas leaks out to the surface side of the underlying resin layer as so-called outgas. For this reason, when the wiring is baked, outgas leaks out to the joint surface between the base resin layer and the wiring and enters the wiring, and this outgas sufficiently decomposes and scatters the organic components contained in the ink coating film. Therefore, there is a problem that the wiring density decreases and the wiring resistance value increases.

例えば、ＬＥＤパッケージで、配線の抵抗値が高くなると、ＬＥＤ点灯時にＬＥＤ素子に流れる電流が減少して輝度が低下するだけでなく、配線の発熱量が増加して素子温度が上昇し、耐久性が低下するおそれもある。   For example, in a LED package, when the wiring resistance value increases, not only does the current flowing through the LED element decrease when the LED is lit, but the brightness decreases, the heating value of the wiring increases, the element temperature increases, and the durability May decrease.

そこで、本発明が解決しようとする課題は、半導体素子側の電極部と搭載部材側の電極部との間を接続する配線を液滴吐出法又は印刷法で描画して焼成する際の下地樹脂層からのアウトガスによる配線の高抵抗値化を防止することができる半導体パッケージ及びその製造方法を提供することである。   Therefore, the problem to be solved by the present invention is to provide a base resin when a wiring connecting between the electrode part on the semiconductor element side and the electrode part on the mounting member side is drawn and fired by a droplet discharge method or a printing method It is an object to provide a semiconductor package and a method for manufacturing the same that can prevent a wiring from having a high resistance value due to outgas from the layer.

上記課題を解決するために、請求項１に係る発明は、搭載部材上に半導体素子を搭載し、該半導体素子側の電極部と該搭載部材側の電極部との間を配線で接続した半導体パッケージにおいて、前記搭載部材上の前記半導体素子の周囲に絶縁性樹脂を設けて該搭載部材上の該半導体素子側の電極部と該搭載部材側の電極部との間の配線経路の下地樹脂層を形成し、前記配線経路の下地樹脂層上にガスバリア性（ガス不透過性）を有する中間絶縁層を形成し、導電性のインクを前記中間絶縁層上に吐出又は印刷し又は固体状の導電部材を実装して前記配線のパターンを形成して焼成した構成としたものである。   In order to solve the above-mentioned problem, the invention according to claim 1 is a semiconductor in which a semiconductor element is mounted on a mounting member, and the electrode part on the semiconductor element side and the electrode part on the mounting member side are connected by wiring. In the package, an insulating resin is provided around the semiconductor element on the mounting member, and a base resin layer of a wiring path between the electrode part on the semiconductor element side and the electrode part on the mounting member side on the mounting member An intermediate insulating layer having a gas barrier property (gas impermeability) is formed on the base resin layer of the wiring path, and conductive ink is ejected or printed on the intermediate insulating layer, or a solid conductive layer is formed. The member is mounted and the wiring pattern is formed and fired.

この構成では、下地樹脂層とその上に形成する配線との間にガスバリア性（ガス不透過性）を有する中間絶縁層が介在されているため、配線焼成時に下地樹脂層で発生したアウトガスが配線内部に侵入することを中間絶縁層によって防止でき、配線の高抵抗値化を防止できる。   In this configuration, since an intermediate insulating layer having a gas barrier property (gas impermeability) is interposed between the base resin layer and the wiring formed thereon, outgas generated in the base resin layer during wiring firing is connected to the wiring. Intrusion into the inside can be prevented by the intermediate insulating layer, and an increase in the resistance value of the wiring can be prevented.

この場合、請求項２のように、下地樹脂層は、搭載部材上の半導体素子の周囲に流動性の絶縁性樹脂を吐出して硬化させて形成しても良いし、固体状の絶縁部材を実装して形成しても良い。   In this case, as described in claim 2, the base resin layer may be formed by discharging and curing a fluid insulating resin around the semiconductor element on the mounting member, or a solid insulating member. It may be formed by mounting.

本発明は、液滴吐出法又は印刷法で配線を形成可能な構造であれば、様々な構造の半導体パッケージに適用可能であり、例えば、ＬＥＤ等の発光素子パッケージに適用しても良い。   The present invention can be applied to semiconductor packages having various structures as long as the wiring can be formed by a droplet discharge method or a printing method. For example, the present invention may be applied to a light emitting element package such as an LED.

本発明をＬＥＤ等の発光素子パッケージに適用する場合は、請求項３のように、発光素子の周囲に、透明な絶縁性樹脂を吐出して硬化させて透明な下地樹脂層を形成し、ガスバリア性を有する絶縁性インクを下地樹脂層上に吐出又は印刷して中間絶縁層を線状又は帯状に形成するようにすると良い。本発明を発光素子パッケージに適用すれば、発光時に発光素子に流れる電流が増加して輝度が増大するだけでなく、配線の発熱量が減少して素子温度の上昇を少なくすることができ、耐久性を向上させることができる。しかも、配線の下地となる中間絶縁層は、発光素子の周囲から透明な下地樹脂層に照射される光の放出を減少させる要因となるため、中間絶縁層を線状又は帯状に形成すれば、発光素子の周囲から透明な下地樹脂層を通して放出される光が中間絶縁層で減少される割合を少なくできて、外部に放出される光の取り出し効率を高めることができる。   When the present invention is applied to a light emitting device package such as an LED, a transparent base resin layer is formed by discharging a transparent insulating resin around the light emitting device to form a gas barrier. The intermediate insulating layer may be formed in a linear shape or a strip shape by discharging or printing an insulating ink having a property on the base resin layer. When the present invention is applied to a light emitting device package, not only the current flowing through the light emitting device during light emission increases and the brightness increases, but also the amount of heat generated in the wiring decreases and the increase in device temperature can be reduced, and durability is improved. Can be improved. Moreover, since the intermediate insulating layer serving as the base of the wiring is a factor that reduces the emission of light irradiated from the periphery of the light emitting element to the transparent base resin layer, if the intermediate insulating layer is formed in a linear or belt shape, The rate at which light emitted from the periphery of the light emitting element through the transparent base resin layer is reduced by the intermediate insulating layer can be reduced, and the extraction efficiency of light emitted to the outside can be increased.

具体的には、請求項４のように、中間絶縁層を、配線が該中間絶縁層からはみ出さないように該配線の線幅よりも製造ばらつき相当値以上太い線幅に形成すれば良い。中間絶縁層の線幅を配線の線幅よりも製造ばらつき相当値以上太い線幅に形成すれば、製造時に中間絶縁層の位置ずれや配線の位置ずれが生じても、配線の下面全体を中間絶縁層で確実に覆うことができ、配線焼成時に下地樹脂層で発生したアウトガスが配線内部に侵入することを中間絶縁層によって確実に防止できる。   Specifically, as in claim 4, the intermediate insulating layer may be formed to have a line width that is thicker than the line width of the wiring by a value equal to or greater than the manufacturing variation so that the wiring does not protrude from the intermediate insulating layer. If the line width of the intermediate insulating layer is formed to be thicker than the line width of the wiring by an amount equivalent to or more than the manufacturing variation, even if the intermediate insulating layer or the wiring is misaligned during manufacturing, It can be reliably covered with the insulating layer, and the intermediate insulating layer can reliably prevent outgas generated in the base resin layer during wiring firing from entering the wiring.

この場合、請求項５のように、中間絶縁層を中間絶縁層の上面全体に形成しても良いことは言うまでもない。   In this case, it goes without saying that the intermediate insulating layer may be formed on the entire upper surface of the intermediate insulating layer as in claim 5.

尚、請求項６に係る発明は、請求項１に係る「半導体パッケージ」の発明と実質的に同一の技術思想を、カテゴリーの異なる「半導体パッケージの製造方法」の発明として記載したものである。   The invention according to claim 6 describes the technical idea substantially the same as the invention of “semiconductor package” according to claim 1 as an invention of “method of manufacturing a semiconductor package” of a different category.

図１は本発明の実施例１のＬＥＤパッケージの構造を図３のＡ−Ａ線に沿って示す断面図である。1 is a cross-sectional view showing the structure of the LED package of Example 1 of the present invention along the line AA in FIG. 図２は図３のＢ−Ｂ線に沿って示す断面図である。2 is a cross-sectional view taken along line BB in FIG. 図３はＬＥＤパッケージの平面図である。FIG. 3 is a plan view of the LED package. 図４は本発明の実施例２のＬＥＤパッケージの構造を示す断面図である。FIG. 4 is a cross-sectional view showing the structure of the LED package of Example 2 of the present invention.

以下、本発明を実施するための形態をＬＥＤパッケージに適用して具体化した２つの実施例１，２を説明する。   Hereinafter, two Examples 1 and 2 which embodied the form for implementing this invention to an LED package are demonstrated.

本発明の実施例１を図１乃至図３に基づいて説明する。
搭載部材１０は、リードフレーム１１に素子搭載凹部１２を有するパッケージ本体１３を樹脂で成形して構成されている。この搭載部材１０の素子搭載凹部１２の底面中央部には、半導体素子であるＬＥＤ素子１４（発光素子）がダイボンディング（接合）されている。素子搭載凹部１２の深さ寸法（高さ寸法）は、ＬＥＤ素子１４の高さ寸法とほぼ同一に設定され、素子搭載凹部１２内に搭載したＬＥＤ素子１４上面の電極部１５が搭載部材１０上面のリードフレーム１１の電極部１１ａとほぼ同じ高さとなっている。 A first embodiment of the present invention will be described with reference to FIGS.
The mounting member 10 is configured by molding a package body 13 having an element mounting recess 12 in a lead frame 11 with a resin. An LED element 14 (light emitting element), which is a semiconductor element, is die-bonded (joined) to the center of the bottom surface of the element mounting recess 12 of the mounting member 10. The depth dimension (height dimension) of the element mounting recess 12 is set to be substantially the same as the height dimension of the LED element 14, and the electrode portion 15 on the upper surface of the LED element 14 mounted in the element mounting recess 12 is the upper surface of the mounting member 10. The lead frame 11 has almost the same height as the electrode portion 11a.

搭載部材１０の素子搭載凹部１２内のうちのＬＥＤ素子１４の周囲に、透明な絶縁性樹脂をインクジェット、ディスペンサ等の液滴吐出法により充填して透明な下地樹脂層１６が形成されている。これにより、ＬＥＤ素子１４上面の電極部１５と搭載部材１０上面の電極部１１ａとの間をつなぐ配線経路は、ＬＥＤ素子１４の周囲に充填された下地樹脂層１６で平坦化され、該下地樹脂層１６の上面に、後述する配線１７の下地となる中間絶縁層１８がＬＥＤ素子１４上面の電極部１５と搭載部材１０上面の電極部１１ａとに跨がって線状又は帯状に形成されている。中間絶縁層１８の形成方法は、インクジェット、ディスペンサ等の液滴吐出法又は印刷法により、ガスバリア性（ガス不透過性）を有する絶縁性材料のインクを下地樹脂層１６上に吐出して、中間絶縁層１８のパターンを下地樹脂層１６上に線状又は帯状に描画して乾燥・硬化させ、ガスバリア性を有する中間絶縁層１８を形成する。   A transparent base resin layer 16 is formed by filling a transparent insulating resin around the LED element 14 in the element mounting recess 12 of the mounting member 10 by a droplet discharge method such as inkjet or dispenser. As a result, the wiring path connecting the electrode portion 15 on the upper surface of the LED element 14 and the electrode portion 11a on the upper surface of the mounting member 10 is flattened by the base resin layer 16 filled around the LED element 14, and the base resin On the upper surface of the layer 16, an intermediate insulating layer 18 serving as a base of the wiring 17 to be described later is formed in a linear shape or a strip shape across the electrode portion 15 on the upper surface of the LED element 14 and the electrode portion 11 a on the upper surface of the mounting member 10. Yes. The intermediate insulating layer 18 is formed by discharging an ink of an insulating material having a gas barrier property (gas impermeability) onto the base resin layer 16 by a droplet discharge method such as ink jet or dispenser or a printing method. The pattern of the insulating layer 18 is drawn in a linear or strip shape on the base resin layer 16 and dried and cured to form the intermediate insulating layer 18 having gas barrier properties.

ここで、ガスバリア性を有する中間絶縁層１８の材料としては、例えば、エポキシ樹脂系、ポリイミド樹脂系、ガラス（ＳｉＯ2 ）系等の絶縁性材料があり、これらの絶縁性材料の中から、ガスバリア性とその他の特性（例えば光透過性、耐湿性、下地樹脂層１６及び配線１７に対する密着性等）を考慮して選択すれば良い。 Here, as the material of the intermediate insulating layer 18 having gas barrier properties, there are, for example, insulating materials such as epoxy resin-based, polyimide resin-based, glass (SiO 2 ) -based, and the gas barrier is selected from these insulating materials. And other characteristics (for example, light transmittance, moisture resistance, adhesion to the base resin layer 16 and the wiring 17 and the like) may be selected.

そして、中間絶縁層１８の乾燥・硬化後に、インクジェット、ディスペンサ等の液滴吐出法により導電性のインク（Ａｇ等の導体粒子を含むインク）を中間絶縁層１８上に吐出して、配線１７のパターンをＬＥＤ素子１４上面の電極部１５と搭載部材１０上面の電極部１１ａとに跨がって中間絶縁層１８上に描画し、これを乾燥して焼成して、ＬＥＤ素子１４上面の電極部１５と搭載部材１０上面の電極部１１ａとの間を配線１７で接続する。この際、配線１７の焼成温度は、２００℃以上（例えば２３０℃）で、焼成時間は３０分〜６０分程度である。   Then, after the intermediate insulating layer 18 is dried and cured, conductive ink (ink containing conductive particles such as Ag) is discharged onto the intermediate insulating layer 18 by a droplet discharge method such as ink jet or dispenser. A pattern is drawn on the intermediate insulating layer 18 across the electrode portion 15 on the upper surface of the LED element 14 and the electrode portion 11a on the upper surface of the mounting member 10, and this is dried and baked to form an electrode portion on the upper surface of the LED element 14. 15 and the electrode part 11 a on the upper surface of the mounting member 10 are connected by a wiring 17. At this time, the firing temperature of the wiring 17 is 200 ° C. or higher (for example, 230 ° C.), and the firing time is about 30 to 60 minutes.

この場合、中間絶縁層１８は、配線１７が該中間絶縁層１８からはみ出さないように該配線１７の線幅よりも製造ばらつき相当値以上太い線幅に形成されている。具体的には、中間絶縁層１８の線幅は、例えば、配線１７の線幅の１．２〜２．５倍、より好ましくは、１．５〜２．０倍の範囲で設定すると良い。尚、搭載部材１０の素子搭載凹部１２内に搭載したＬＥＤ素子１４及び配線１７等は、透明な封止材料（図示せず）によって封止されている。   In this case, the intermediate insulating layer 18 is formed to have a line width that is larger than the line width of the wiring 17 by a value corresponding to a manufacturing variation or more so that the wiring 17 does not protrude from the intermediate insulating layer 18. Specifically, the line width of the intermediate insulating layer 18 may be set in the range of 1.2 to 2.5 times, more preferably 1.5 to 2.0 times the line width of the wiring 17, for example. The LED element 14 and the wiring 17 mounted in the element mounting recess 12 of the mounting member 10 are sealed with a transparent sealing material (not shown).

以上説明した本実施例１によれば、ＬＥＤ素子１４の周囲に充填した下地樹脂層１６とその上に形成する配線１７との間にガスバリア性を有する中間絶縁層１８が介在されているため、配線１７の焼成時に下地樹脂層１６で発生したアウトガスが配線１７の内部に侵入することを中間絶縁層１８によって防止でき、配線１７の高抵抗値化を防止することができる。本発明者らの実験結果によれば、中間絶縁層１８を形成することで、配線１７の体積抵抗率が１／２程度になることが確認されている。これにより、ＬＥＤ素子１４の発光時にＬＥＤ素子１４に流れる電流が増加して輝度が増大するだけでなく、配線１７の発熱量が減少してＬＥＤ素子１４の温度上昇を少なくすることができ、耐久性を向上させることができる。   According to the first embodiment described above, since the intermediate insulating layer 18 having gas barrier properties is interposed between the base resin layer 16 filled around the LED element 14 and the wiring 17 formed thereon, The intermediate insulating layer 18 can prevent the outgas generated in the base resin layer 16 from entering the wiring 17 when the wiring 17 is baked, and the resistance of the wiring 17 can be prevented from being increased. According to the experimental results of the present inventors, it has been confirmed that the volume resistivity of the wiring 17 becomes about ½ by forming the intermediate insulating layer 18. As a result, not only does the current flowing through the LED element 14 increase when the LED element 14 emits light, the brightness increases, but also the amount of heat generated in the wiring 17 decreases and the temperature rise of the LED element 14 can be reduced. Can be improved.

しかも、配線１７の下地となる中間絶縁層１８は、光の放出を減少させる要因となるため、本実施例１のように、中間絶縁層１８を線状又は帯状に形成することで、ＬＥＤ素子１４の周囲から透明な下地樹脂層１６を通して放出される光が中間絶縁層１８で減少される割合を少なくできて、外部に放出される光の取り出し効率を高めることができる。   In addition, since the intermediate insulating layer 18 which is the base of the wiring 17 becomes a factor of reducing light emission, the LED element can be formed by forming the intermediate insulating layer 18 in a linear shape or a belt shape as in the first embodiment. The rate at which the light emitted from the periphery of 14 through the transparent base resin layer 16 is reduced by the intermediate insulating layer 18 can be reduced, and the extraction efficiency of the light emitted to the outside can be increased.

また、本実施例１では、中間絶縁層１８を、配線１７が該中間絶縁層１８からはみ出さないように該配線１７の線幅よりも製造ばらつき相当値以上太い線幅に形成するようにしたので、製造時に中間絶縁層１８の位置ずれや配線１７の位置ずれが生じても、配線１７の下面全体を中間絶縁層１８で確実に覆うことができ、配線１７の焼成時に下地樹脂層１６で発生したアウトガスが配線１７の内部に侵入することを中間絶縁層１８によって確実に防止できる。   In the first embodiment, the intermediate insulating layer 18 is formed to have a line width that is thicker than the line width of the wiring 17 by a value corresponding to the manufacturing variation or more so that the wiring 17 does not protrude from the intermediate insulating layer 18. Therefore, even if the displacement of the intermediate insulating layer 18 or the displacement of the wiring 17 occurs during manufacturing, the entire lower surface of the wiring 17 can be reliably covered with the intermediate insulating layer 18, and the underlying resin layer 16 can be used when the wiring 17 is baked. The intermediate insulating layer 18 can reliably prevent the generated outgas from entering the wiring 17.

次に、本発明の実施例２を図４に基づいて説明する。
搭載部材２１は、リードフレーム２２に素子搭載凹部２３を有するパッケージ本体２４を樹脂で成形して構成され、該素子搭載凹部２３の側面が傾斜状に形成されている。素子搭載凹部２３の底面には、リードフレーム２２の素子搭載部２２ａ（ダイパッド）が露出し、該素子搭載部２２ａ上に半導体素子であるＬＥＤ素子２５（発光素子）がダイボンド（接合）されている。 Next, a second embodiment of the present invention will be described with reference to FIG.
The mounting member 21 is formed by molding a package body 24 having an element mounting recess 23 on a lead frame 22 with resin, and the side surface of the element mounting recess 23 is formed in an inclined shape. The element mounting portion 22a (die pad) of the lead frame 22 is exposed on the bottom surface of the element mounting recess 23, and the LED element 25 (light emitting element), which is a semiconductor element, is die-bonded (joined) on the element mounting portion 22a. .

素子搭載凹部２３の傾斜状の側面には、ＬＥＤ素子２５上面の２つの電極部２６と接続する２つの電極部２７が形成されている。各電極部２７は、それぞれリードフレーム２２に一体に形成されている。この場合、素子搭載凹部２３の側面に形成する電極部２６の高さ方向の幅が広くなるほど、搭載可能なＬＥＤ素子２５の高さ寸法の範囲が広がることを考慮して、本実施例２では、素子搭載凹部２３に側面に形成する電極部２７は、該素子搭載凹部２３の側面の上部から下部まで延びるように形成され、且つ、該電極部２７がＬＥＤ素子２５の光を反射する反射板（リフレクター）としても機能するように構成されている。   Two electrode portions 27 connected to the two electrode portions 26 on the upper surface of the LED element 25 are formed on the inclined side surface of the element mounting recess 23. Each electrode portion 27 is formed integrally with the lead frame 22. In this case, in consideration of the fact that the range of the height dimension of the LED element 25 that can be mounted increases as the width in the height direction of the electrode part 26 formed on the side surface of the element mounting recess 23 increases, The electrode portion 27 formed on the side surface of the element mounting recess 23 is formed so as to extend from the upper side to the lower side of the side surface of the element mounting recess 23, and the electrode portion 27 reflects the light of the LED element 25. It is also configured to function as a (reflector).

搭載部材２１の素子搭載凹部２３内に搭載可能なＬＥＤ素子２５は、高さ寸法が該素子搭載凹部２３の側面（電極部２７）の高さ寸法以下で且つリードフレーム２２の素子搭載部２２ａ上に搭載可能なサイズのＬＥＤ素子である。これにより、高さ寸法の異なる複数種のＬＥＤ素子２５を同一仕様・寸法の搭載部材２１の素子搭載凹部２３内に搭載できるようになっている。   The LED element 25 that can be mounted in the element mounting recess 23 of the mounting member 21 has a height dimension equal to or less than the height dimension of the side surface (electrode part 27) of the element mounting recess 23 and on the element mounting part 22 a of the lead frame 22. LED element of a size that can be mounted on Accordingly, a plurality of types of LED elements 25 having different height dimensions can be mounted in the element mounting recess 23 of the mounting member 21 having the same specifications and dimensions.

素子搭載凹部２３内のうちのＬＥＤ素子２５の周囲に、透明な絶縁性樹脂をインクジェット、ディスペンサ等の液滴吐出法により充填して透明な下地樹脂層２８が形成され、該下地樹脂層２８の上面の高さ位置がＬＥＤ素子２５の電極部２６上面の高さ位置と一致することで、ＬＥＤ素子２５上面の電極部２６と素子搭載凹部２３側面の電極部２７との間の配線経路が下地樹脂層２８で平坦化されている。   A transparent base resin layer 28 is formed by filling a transparent insulating resin around the LED element 25 in the element mounting recess 23 by a droplet discharge method such as ink jet or dispenser. Since the height position of the upper surface coincides with the height position of the upper surface of the electrode part 26 of the LED element 25, the wiring path between the electrode part 26 on the upper surface of the LED element 25 and the electrode part 27 on the side surface of the element mounting recess 23 becomes a base. The resin layer 28 is flattened.

この下地樹脂層２８の上面に、後述する配線２９の下地となる中間絶縁層３０がＬＥＤ素子２５上面の電極部２６と素子搭載凹部２３側面の電極部２７とに跨がって線状又は帯状に形成されている。中間絶縁層３０の形成方法は、インクジェット、ディスペンサ等の液滴吐出法又は印刷法により、前記実施例１と同様のガスバリア性を有する絶縁性材料のインクを下地樹脂層２８上に吐出して中間絶縁層３０のパターンを線状又は帯状に描画して乾燥・硬化させ、ガスバリア性を有する中間絶縁層３０を形成する。   On the upper surface of the base resin layer 28, an intermediate insulating layer 30 serving as a base of a wiring 29 described later extends over the electrode portion 26 on the upper surface of the LED element 25 and the electrode portion 27 on the side surface of the element mounting recess 23, and forms a line or a band. Is formed. The intermediate insulating layer 30 is formed by discharging an ink of an insulating material having a gas barrier property similar to that of the first embodiment onto the base resin layer 28 by a droplet discharge method such as inkjet or dispenser or a printing method. The pattern of the insulating layer 30 is drawn in a linear shape or a belt shape, and dried and cured to form the intermediate insulating layer 30 having gas barrier properties.

中間絶縁層３０の乾燥・硬化後に、インクジェット、ディスペンサ等の液滴吐出法により導電性のインク（Ａｇ等の導体粒子を含むインク）を中間絶縁層３０上に吐出して、該中間絶縁層３０上に、配線２９のパターンをＬＥＤ素子２５上面の電極部２６と素子搭載凹部２３側面の電極部２７とに跨がって描画し、これを乾燥して焼成して、ＬＥＤ素子２５上面の電極部２６と素子搭載凹部２３側面の電極部２７との間を該配線２９で接続する。この際、配線２９の焼成温度は、２００℃以上（例えば２３０℃）で、焼成時間は３０分程度である。   After the intermediate insulating layer 30 is dried and cured, conductive ink (ink containing conductive particles such as Ag) is discharged onto the intermediate insulating layer 30 by a droplet discharge method such as ink jet or dispenser. On top of this, a pattern of the wiring 29 is drawn across the electrode part 26 on the upper surface of the LED element 25 and the electrode part 27 on the side surface of the element mounting recess 23, and this is dried and fired to form an electrode on the upper surface of the LED element 25. The wiring 26 is connected between the portion 26 and the electrode portion 27 on the side surface of the element mounting recess 23. At this time, the firing temperature of the wiring 29 is 200 ° C. or higher (for example, 230 ° C.), and the firing time is about 30 minutes.

前記実施例１と同様に、中間絶縁層３０は、配線２９が該中間絶縁層３０からはみ出さないように該配線２９の線幅よりも製造ばらつき相当値以上太い線幅に形成されている。尚、素子搭載凹部２３内に搭載したＬＥＤ素子２５及び配線２９等は、透明な封止材料（図示せず）によって封止されている。   As in the first embodiment, the intermediate insulating layer 30 is formed to have a line width that is thicker than the line width of the wiring 29 by a value corresponding to the manufacturing variation or more, so that the wiring 29 does not protrude from the intermediate insulating layer 30. The LED element 25 and the wiring 29 mounted in the element mounting recess 23 are sealed with a transparent sealing material (not shown).

以上説明した本実施例２でも、ＬＥＤ素子２５の周囲に充填した下地樹脂層２８とその上に形成する配線２９との間にガスバリア性を有する中間絶縁層３０が介在されているため、前記実施例１と同様の効果を得ることができる。   Also in the second embodiment described above, since the intermediate insulating layer 30 having gas barrier properties is interposed between the base resin layer 28 filled around the LED element 25 and the wiring 29 formed thereon, The same effect as in Example 1 can be obtained.

尚、上記実施例１，２では、搭載部材の素子搭載凹部内にＬＥＤ素子を搭載して、該素子搭載凹部内のうちのＬＥＤ素子の周囲に、透明な絶縁性樹脂を充填して下地樹脂層を形成するようにしたが、搭載部材（回路基板、リードフレーム等）の平坦面上に搭載したＬＥＤ素子等の半導体素子の周囲に、流動性の樹脂材料をディスペンサで吐出して、半導体素子の上面と搭載部材の表面との間を傾斜面でつなぐスロープ状の下地樹脂層を形成した後、このスロープ状の下地樹脂層上にガスバリア性を有する中間絶縁層を形成し、導電性のインクを前記中間絶縁層上に吐出又は印刷して配線のパターンを形成して焼成した構成としても良い。   In Examples 1 and 2, the LED element is mounted in the element mounting recess of the mounting member, and the base resin is filled with a transparent insulating resin around the LED element in the element mounting recess. Although a layer is formed, a fluid resin material is discharged by a dispenser around a semiconductor element such as an LED element mounted on a flat surface of a mounting member (circuit board, lead frame, etc.), and the semiconductor element After forming a slope-shaped base resin layer connecting the upper surface of the substrate and the surface of the mounting member with an inclined surface, an intermediate insulating layer having a gas barrier property is formed on the slope-shaped base resin layer, and conductive ink is formed. It is good also as a structure which discharged or printed on the said intermediate | middle insulating layer, formed the pattern of the wiring, and baked.

また、上記実施例１，２では、中間絶縁層を配線の線幅よりも製造ばらつき相当値以上太い線幅の線状に形成したが、中間絶縁層を中間絶縁層の上面全体に形成しても良いことは言うまでもない。   In Examples 1 and 2, the intermediate insulating layer is formed in a line shape having a line width thicker than the line width of the wiring by a value corresponding to the manufacturing variation, but the intermediate insulating layer is formed on the entire upper surface of the intermediate insulating layer. It goes without saying that it is also good.

また、配線を形成する方法は、液滴吐出法に限定されず、スクリーン印刷等の印刷法で形成しても良いし、或は、固体状の導体を中間絶縁層上に実装しても良い。   Further, the method of forming the wiring is not limited to the droplet discharge method, and may be formed by a printing method such as screen printing, or a solid conductor may be mounted on the intermediate insulating layer. .

また、中間絶縁層を形成する方法は、液滴吐出法又は印刷法に限定されず、固体状の絶縁物を下地樹脂層上に装着しても良く、ガスバリア性フィルムを下地樹脂層上に接合して形成しても良い。   The method for forming the intermediate insulating layer is not limited to the droplet discharge method or the printing method, and a solid insulating material may be mounted on the base resin layer, and a gas barrier film is bonded on the base resin layer. May be formed.

その他、本発明は、ＬＥＤ素子以外の半導体素子を搭載部材に搭載した半導体パッケージにも適用して実施できる等、要旨を逸脱しない範囲内で種々変更して実施できることは言うまでもない。   In addition, it goes without saying that the present invention can be implemented with various modifications without departing from the gist, such as being applicable to a semiconductor package in which a semiconductor element other than an LED element is mounted on a mounting member.

１０…搭載部材、１１…リードフレーム、１１ａ…電極部、１２…素子搭載凹部、１３…パッケージ本体、１４…ＬＥＤ素子（発光素子，半導体素子）、１５…電極部、１６…下地樹脂層、１７…配線、１８…中間絶縁層、２１…搭載部材、２２…リードフレーム、２３…素子搭載凹部、２４…パッケージ本体、２５…ＬＥＤ素子（発光素子，半導体素子）、２６，２７…電極部、２８…下地樹脂層、２９…配線、３０…中間絶縁層   DESCRIPTION OF SYMBOLS 10 ... Mounting member, 11 ... Lead frame, 11a ... Electrode part, 12 ... Element mounting recessed part, 13 ... Package main body, 14 ... LED element (light emitting element, semiconductor element), 15 ... Electrode part, 16 ... Base resin layer, 17 DESCRIPTION OF SYMBOLS ... Wiring, 18 ... Intermediate insulating layer, 21 ... Mounting member, 22 ... Lead frame, 23 ... Element mounting recessed part, 24 ... Package main body, 25 ... LED element (light emitting element, semiconductor element), 26, 27 ... Electrode part, 28 ... base resin layer, 29 ... wiring, 30 ... intermediate insulating layer

Claims (6)

搭載部材上に半導体素子を搭載し、該半導体素子側の電極部と該搭載部材側の電極部との間を配線で接続した半導体パッケージにおいて、
前記搭載部材上の前記半導体素子の周囲に絶縁性樹脂を設けて該搭載部材上の該半導体素子側の電極部と該搭載部材側の電極部との間の配線経路の下地樹脂層を形成し、
前記配線経路の下地樹脂層上にガスバリア性を有する中間絶縁層を形成し、
導電性のインクを前記中間絶縁層上に吐出又は印刷し又は固体状の導電部材を実装して前記配線のパターンを形成して焼成したことを特徴とする半導体パッケージ。 In a semiconductor package in which a semiconductor element is mounted on a mounting member and the electrode part on the semiconductor element side and the electrode part on the mounting member side are connected by wiring,
An insulating resin is provided around the semiconductor element on the mounting member to form a base resin layer of a wiring path between the electrode part on the mounting element side and the electrode part on the mounting member side on the mounting member. ,
Forming an intermediate insulating layer having gas barrier properties on the underlying resin layer of the wiring path;
A semiconductor package, wherein conductive ink is ejected or printed on the intermediate insulating layer, or a solid conductive member is mounted to form a pattern of the wiring and fired. 前記下地樹脂層は、前記搭載部材上の前記半導体素子の周囲に流動性の絶縁性樹脂を吐出して硬化させて形成され、又は固体状の絶縁部材を実装して形成されていることを特徴とする請求項１に記載の半導体パッケージ。   The base resin layer is formed by discharging and curing a fluid insulating resin around the semiconductor element on the mounting member, or formed by mounting a solid insulating member. The semiconductor package according to claim 1. 前記半導体素子は、発光素子であり、
前記絶縁性樹脂は、透明な絶縁性樹脂であり、
前記中間絶縁層は、ガスバリア性を有する絶縁性インクを前記配線経路の下地樹脂層上に吐出又は印刷して線状又は帯状に形成されていることを特徴とする請求項１又は２に記載の半導体パッケージ。 The semiconductor element is a light emitting element,
The insulating resin is a transparent insulating resin,
3. The intermediate insulating layer according to claim 1, wherein the intermediate insulating layer is formed in a linear shape or a strip shape by discharging or printing an insulating ink having a gas barrier property on a base resin layer of the wiring path. Semiconductor package. 前記中間絶縁層は、前記配線が該中間絶縁層からはみ出さないように該配線の線幅よりも製造ばらつき相当値以上太い線幅に形成されていることを特徴とする請求項１乃至３のいずれかに記載の半導体パッケージ。   4. The intermediate insulating layer according to claim 1, wherein the intermediate insulating layer is formed to have a line width that is thicker than a value corresponding to manufacturing variation than a line width of the wiring so that the wiring does not protrude from the intermediate insulating layer. The semiconductor package in any one. 前記中間絶縁層は、前記中間絶縁層の上面全体に形成されていることを特徴とする請求項１乃至３のいずれかに記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the intermediate insulating layer is formed on the entire top surface of the intermediate insulating layer. 搭載部材上に半導体素子を搭載し、該半導体素子側の電極部と該搭載部材側の電極部との間を配線で接続した半導体パッケージの製造方法において、
前記搭載部材上に前記半導体素子を搭載する工程と、
前記搭載部材上の前記半導体素子の周囲に絶縁性樹脂を設けて該半導体素子側の電極部と該搭載部材側の電極部との間の配線経路の下地樹脂層を形成する工程と、
前記配線経路の下地樹脂層上にガスバリア性を有する中間絶縁層を形成する工程と、
導電性のインクを前記中間絶縁層上に吐出又は印刷し又は固体状の導電部材を実装して前記配線のパターンを形成して焼成する工程と
を含むことを特徴とする半導体パッケージの製造方法。 In a manufacturing method of a semiconductor package in which a semiconductor element is mounted on a mounting member and the electrode part on the semiconductor element side and the electrode part on the mounting member side are connected by wiring.
Mounting the semiconductor element on the mounting member;
Providing an insulating resin around the semiconductor element on the mounting member to form a base resin layer of a wiring path between the electrode part on the semiconductor element side and the electrode part on the mounting member side;
Forming an intermediate insulating layer having a gas barrier property on a base resin layer of the wiring path;
And a step of ejecting or printing conductive ink on the intermediate insulating layer or mounting a solid conductive member to form a pattern of the wiring and baking the semiconductor package.
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