JP2014003177A - Semiconductor package and manufacturing method of the same - Google Patents

Semiconductor package and manufacturing method of the same Download PDF

Info

Publication number
JP2014003177A
JP2014003177A JP2012137903A JP2012137903A JP2014003177A JP 2014003177 A JP2014003177 A JP 2014003177A JP 2012137903 A JP2012137903 A JP 2012137903A JP 2012137903 A JP2012137903 A JP 2012137903A JP 2014003177 A JP2014003177 A JP 2014003177A
Authority
JP
Japan
Prior art keywords
wiring
repellent film
liquid
liquid repellent
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012137903A
Other languages
Japanese (ja)
Other versions
JP6037545B2 (en
Inventor
Kazuhiro Sugiyama
和裕 杉山
Masatoshi Fujita
政利 藤田
Kenji Tsukada
謙磁 塚田
Masato Suzuki
雅登 鈴木
Akihiro Kawajiri
明宏 川尻
Yoshitaka Hashimoto
良崇 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Corp
Original Assignee
Fuji Machine Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Machine Manufacturing Co Ltd filed Critical Fuji Machine Manufacturing Co Ltd
Priority to JP2012137903A priority Critical patent/JP6037545B2/en
Publication of JP2014003177A publication Critical patent/JP2014003177A/en
Application granted granted Critical
Publication of JP6037545B2 publication Critical patent/JP6037545B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
    • H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/24998—Reinforcing structures, e.g. ramp-like support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/76—Apparatus for connecting with build-up interconnects
    • H01L2224/7615—Means for depositing
    • H01L2224/76151—Means for direct writing
    • H01L2224/76155—Jetting means, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve connection reliability of wiring in an LED package.SOLUTION: A semiconductor package manufacturing method comprises: forming a thin liquid repellent film 17 having a liquid-repellent property against a liquid of an insulation resin 16 on a surface of en electrode part 15 on a top face of an LED element 14 and on a surface of an electrode part 11a on a top face of a package body 13; and subsequently filling a gap around the LED element 14 among element mounting recesses 12 of the package body 13 with the transparent insulation resin 16 to form an embedded layer of the transparent insulation resin 16. At this time, even when the liquid of the insulation resin 16 overflowed from the element mounting recess 12 wet spreads to edges of the electrode parts 15, 11a, the liquid of the insulation resin 16 which has wet spread to the edges of the electrode parts 15, 11a is repelled by the liquid-repellent film 17 and the liquid of the insulation resin 16 is prevented from wet spreading over the liquid-repellent film 17 because surfaces of the electrode parts 15, 11a are covered with the liquid-repellent films 17. The semiconductor package manufacturing method further comprises: subsequently forming wiring 18 on a wiring path between both electrode parts 15, 11a and electrically connecting the wiring 18 to the electrode parts 15, 11a through the liquid-repellent film 17.

Description

本発明は、搭載部材上に搭載した半導体素子側の電極部と該搭載部材側の電極部との間を接続する配線の接続信頼性を向上させた半導体パッケージ及びその製造方法に関する発明である。   The present invention relates to a semiconductor package in which the connection reliability of wiring connecting between an electrode portion on a semiconductor element mounted on a mounting member and an electrode portion on the mounting member is improved, and a manufacturing method thereof.

従来より、半導体素子の実装工程では、半導体素子を搭載部材（回路基板、リードフレーム等）にダイボンドした後に、該半導体素子側の電極部と搭載部材側の電極部との間をワイヤボンディングで配線するのが一般的である。   Conventionally, in the mounting process of a semiconductor element, after the semiconductor element is die-bonded to a mounting member (circuit board, lead frame, etc.), wiring is performed between the electrode part on the semiconductor element side and the electrode part on the mounting member side by wire bonding. It is common to do.

しかし、特許文献１（特許第３９９２０３８号公報）に記載されているように、ワイヤボンディングを行うときの機械的なストレスによって不良が発生する可能性があるため、ワイヤボンディングに代わる接続信頼性の高い実装構造を低コストで実現することを目的として、配線基板上に搭載した半導体素子の周囲に樹脂材料の液をディスペンサで吐出して硬化させて、半導体素子の上面と配線基板の表面との間を傾斜面でつなぐ樹脂スロープを形成した後、半導体素子上面の電極部と配線基板の電極部との間を接続する配線の経路に沿ってインクジェット等の液滴吐出法で導電性インクを吐出して配線を形成することが提案されている。   However, as described in Patent Document 1 (Japanese Patent No. 3992038), there is a possibility that defects may occur due to mechanical stress when wire bonding is performed. Therefore, connection reliability that replaces wire bonding is high. For the purpose of realizing the mounting structure at low cost, the resin material liquid is discharged by a dispenser around the semiconductor element mounted on the wiring board and cured, so that the space between the upper surface of the semiconductor element and the surface of the wiring board is obtained. After forming a resin slope that connects the inclined surfaces, conductive ink is ejected by a droplet ejection method such as ink jet along the wiring path connecting the electrode portion on the upper surface of the semiconductor element and the electrode portion of the wiring board. It has been proposed to form wiring.

特許第３９９２０３８号公報Japanese Patent No. 3992038

上記特許文献１の構造では、配線基板上に搭載した半導体素子の周囲に樹脂材料の液をディスペンサで吐出して樹脂スロープを形成する際に、吐出した樹脂材料の液が半導体素子上面の電極部上や配線基板の電極部上に濡れ広がって、該電極部の一部又は全部が樹脂材料で覆われてしまうことがあり、該電極部と配線との導通性を十分に確保できない場合がある。   In the structure of Patent Document 1, when a resin slope is formed by discharging a resin material liquid around a semiconductor element mounted on a wiring board with a dispenser, the discharged resin material liquid is applied to the electrode portion on the upper surface of the semiconductor element. The electrode part of the wiring board may get wet and spread over the top or on the wiring board, and part or all of the electrode part may be covered with a resin material. .

この対策として、樹脂材料の吐出量を少なめにして電極部上への樹脂材料の濡れ広がりを防止する必要があり、その結果、半導体素子の電極部と配線基板の電極部との間を接続する配線経路の段差を樹脂スロープで十分に小さくすることができず、該配線経路上に形成した配線が段差の角部で熱応力等により断線する可能性がある。   As a countermeasure, it is necessary to reduce the discharge amount of the resin material to prevent the resin material from spreading on the electrode part. As a result, the electrode part of the semiconductor element and the electrode part of the wiring board are connected. The step of the wiring path cannot be sufficiently reduced by the resin slope, and the wiring formed on the wiring path may be disconnected at the corner of the step due to thermal stress or the like.

そこで、本発明が解決しようとする課題は、搭載部材上に搭載した半導体素子側の電極部と該搭載部材側の電極部との間を接続する配線の接続信頼性を向上できる半導体パッケージ及びその製造方法を提供することである。   Therefore, the problem to be solved by the present invention is to provide a semiconductor package capable of improving the connection reliability of the wiring connecting the electrode part on the semiconductor element side mounted on the mounting member and the electrode part on the mounting member side, and the semiconductor package It is to provide a manufacturing method.

上記課題を解決するために、本発明は、搭載部材上に半導体素子を搭載し、該半導体素子側の電極部と該搭載部材側の電極部との間の配線経路の凹部及び／又は段差を絶縁性樹脂で埋めると共に、該半導体素子側の電極部と該搭載部材側の電極部との間を接続する配線を該配線経路上に形成した半導体パッケージ及びその製造方法において、前記配線経路の凹部及び／又は段差を前記絶縁性樹脂で埋める前に前記半導体素子側の電極部の表面及び／又は前記搭載部材側の電極部の表面に、前記絶縁性樹脂の液に対して撥液性のある撥液膜を厚さ所定値以下に薄く形成し、若しくは予め電極部の表面に前記撥液膜が形成された半導体素子及び／又は予め電極部の表面に前記撥液膜が形成された搭載部材を使用し、前記配線経路の凹部及び／又は段差を前記絶縁性樹脂で埋めた後に前記配線を該配線経路上と前記撥液膜上とに跨がって形成することで該配線を該撥液膜を介して前記電極部に導通させたことを特徴とするものである。   In order to solve the above-described problems, the present invention mounts a semiconductor element on a mounting member, and forms a recess and / or a step in a wiring path between the electrode part on the semiconductor element side and the electrode part on the mounting member side. In a semiconductor package filled with an insulating resin and connected on the wiring path to connect between the electrode part on the semiconductor element side and the electrode part on the mounting member side, and a manufacturing method therefor, a recess in the wiring path And / or the surface of the electrode part on the semiconductor element side and / or the surface of the electrode part on the mounting member side is liquid repellent to the liquid of the insulating resin before the step is filled with the insulating resin. A semiconductor element in which the liquid repellent film is formed thinly below a predetermined value, or the liquid repellent film is previously formed on the surface of the electrode part, and / or the mounting member in which the liquid repellent film is previously formed on the surface of the electrode part And / or a recess in the wiring path and / or After filling the difference with the insulating resin, the wiring is formed across the wiring path and the liquid-repellent film, thereby connecting the wiring to the electrode portion through the liquid-repellent film. It is characterized by this.

本発明では、電極部の表面に、絶縁性樹脂の液に対して撥液性のある撥液膜を形成するため、配線経路の凹部及び／又は段差を絶縁性樹脂で埋める際に、絶縁性樹脂の吐出量を適度に増やしても、絶縁性樹脂の液が電極部上に濡れ広がることを撥液膜によって防止できる。これにより、配線の断線の原因となる配線経路の凹部や段差を十分に絶縁性樹脂で埋めて配線経路を十分になだらかにすることができ、配線経路の段差による配線の断線を防止できると共に、配線と電極部との間の撥液膜を薄くすることで配線と電極部との導通性を確保することができ、配線の接続信頼性を向上できる。   In the present invention, since a liquid repellent film having a liquid repellency with respect to the liquid of the insulating resin is formed on the surface of the electrode part, the insulating property is reduced when the recesses and / or steps of the wiring path are filled with the insulating resin. Even if the discharge amount of the resin is increased moderately, the liquid-repellent film can prevent the liquid of the insulating resin from spreading on the electrode portion. As a result, it is possible to sufficiently fill the recesses and steps of the wiring path that cause the disconnection of the wiring with insulating resin to sufficiently smooth the wiring path, and to prevent the disconnection of the wiring due to the step of the wiring path. By reducing the thickness of the liquid repellent film between the wiring and the electrode portion, the continuity between the wiring and the electrode portion can be ensured, and the connection reliability of the wiring can be improved.

この場合、配線経路の凹部及び／又は段差を絶縁性樹脂で埋めた後に、該配線経路上にプライマ樹脂層を形成して該プライマ樹脂層上に配線を形成するようにしても良い。このようにすれば、プライマ樹脂層によって配線経路をより一層なだらかにすることができるため、厚膜法（液滴吐出法や印刷法等）で配線をプライマ樹脂層上に形成しやすくなると共に、配線との密着性等を向上させることができる。   In this case, after the recess and / or step of the wiring path is filled with an insulating resin, a primer resin layer may be formed on the wiring path to form a wiring on the primer resin layer. In this way, since the wiring path can be further smoothed by the primer resin layer, it becomes easier to form the wiring on the primer resin layer by a thick film method (droplet discharge method, printing method, etc.) Adhesion with the wiring can be improved.

また、本発明は、撥液膜を形成する前に半導体素子側の電極部の表面及び／又は搭載部材側の電極部の表面に導電性材料を塗布又は印刷して導電性材料膜を形成した後、該導電性材料膜上に撥液膜を形成するようにしても良い。このようにすれば、電極部の表面に導電性材料膜を介して撥液膜を形成した構造となるため、導電性材料膜中の導電粒子が撥液膜中に浸透して該撥液膜の電気抵抗値が低下するようになり、電極部と配線との間の導通性を向上させることができる。   Further, according to the present invention, a conductive material film is formed by applying or printing a conductive material on the surface of the electrode part on the semiconductor element side and / or on the surface of the electrode part on the mounting member side before forming the liquid repellent film. Thereafter, a liquid repellent film may be formed on the conductive material film. In this case, since the liquid repellent film is formed on the surface of the electrode portion via the conductive material film, the conductive particles in the conductive material film permeate into the liquid repellent film and the liquid repellent film is formed. As a result, the electrical resistance value decreases, and the electrical conductivity between the electrode portion and the wiring can be improved.

また、配線経路の凹部及び／又は段差を絶縁性樹脂で埋めた後に、配線を形成する前に撥液膜を焼成又は光照射することで該撥液膜の組成成分を分解・蒸発させて該撥液膜の膜厚を薄くするようにしても良い。このようにしても、電極部と配線との間の撥液膜の電気抵抗値を低下させて電極部と配線との間の導通性を向上させることができる。   Further, after filling the recesses and / or steps of the wiring path with an insulating resin, before forming the wiring, the liquid repellent film is baked or irradiated with light to decompose and evaporate the composition components of the liquid repellent film. The film thickness of the liquid repellent film may be reduced. Even in this case, the electrical resistance value of the liquid repellent film between the electrode portion and the wiring can be reduced, and the electrical conductivity between the electrode portion and the wiring can be improved.

また、本発明は、配線経路の凹部及び／又は段差を絶縁性樹脂で埋めた後に撥液膜を焼成又は光照射することで該撥液膜の組成成分をほぼ全て分解・蒸発させて該撥液膜を除去した後に、配線を配線経路上に形成して該配線を電極部に接続するようにしても良い。このようにすれば、配線経路の凹部及び／又は段差を絶縁性樹脂で埋める際に、絶縁性樹脂の液が電極部上に濡れ広がることを撥液膜によって防止しながら、配線を形成する前に該撥液膜を除去してから配線を形成することで、電極部と配線との間の導通性を向上させることができる。   In addition, the present invention provides that the liquid repellent film is baked or irradiated with light after the recesses and / or steps of the wiring path are filled with an insulating resin to decompose and evaporate almost all the composition components of the liquid repellent film. After removing the liquid film, a wiring may be formed on the wiring path and connected to the electrode portion. In this way, when the recesses and / or steps of the wiring path are filled with the insulating resin, the liquid of the insulating resin is prevented from spreading on the electrode portion by the liquid repellent film, and before the wiring is formed. In addition, by forming the wiring after removing the liquid repellent film, the electrical conductivity between the electrode portion and the wiring can be improved.

尚、配線は、薄膜法で形成しても良いし、厚膜法で形成して焼成しても良い。厚膜法で形成した配線を焼成すれば、配線中の有機成分等を分解・蒸発させて配線の電気抵抗値を低下させることができると共に、配線焼成時の熱により撥液膜の組成成分を分解・蒸発させて該撥液膜の膜厚を薄くすることができ、電極部と配線との間の導通性も向上させることができる。   The wiring may be formed by a thin film method, or may be formed by a thick film method and fired. If the wiring formed by the thick film method is baked, the organic components in the wiring can be decomposed and evaporated to lower the electrical resistance value of the wiring, and the composition component of the liquid repellent film can be reduced by the heat during wiring baking. The liquid repellent film can be thinned by being decomposed and evaporated, and the electrical conductivity between the electrode portion and the wiring can be improved.

図１は本発明の実施例１の素子搭載工程を示す縦断面図である。FIG. 1 is a longitudinal sectional view showing an element mounting process of Example 1 of the present invention. 図２は実施例１の撥液膜形成工程を示す縦断面図である。FIG. 2 is a longitudinal sectional view showing a liquid repellent film forming process of the first embodiment. 図３は実施例１の絶縁性樹脂埋込み工程を示す縦断面図である。FIG. 3 is a longitudinal sectional view showing the insulating resin embedding process of the first embodiment. 図４は実施例１の配線形成工程を示す縦断面図である。FIG. 4 is a longitudinal sectional view showing a wiring formation process of the first embodiment. 図５は実施例２のＬＥＤパッケージの構造を示す縦断面図である。FIG. 5 is a longitudinal sectional view showing the structure of the LED package of the second embodiment. 図６は実施例３のＬＥＤパッケージの構造を示す縦断面図である。FIG. 6 is a longitudinal sectional view showing the structure of the LED package of Example 3. 図７は実施例４のＬＥＤパッケージの構造を示す縦断面図である。FIG. 7 is a longitudinal sectional view showing the structure of the LED package of Example 4. 図８は実施例４のＬＥＤパッケージの製造工程を示す工程フローチャートである。FIG. 8 is a process flowchart showing the manufacturing process of the LED package of Example 4. 図９は実施例５のＬＥＤパッケージの構造を示す縦断面図である。FIG. 9 is a longitudinal sectional view showing the structure of the LED package of Example 5.

以下、本発明を実施するための形態をＬＥＤパッケージに適用して具体化した５つの実施例１〜５を説明する。   Hereinafter, five Examples 1 to 5 in which the embodiment for implementing the present invention is applied to an LED package and embodied will be described.

本発明の実施例１を図１乃至図４に基づいて説明する。
まず、図４を参照してＬＥＤパッケージの構造を説明する。 A first embodiment of the present invention will be described with reference to FIGS.
First, the structure of the LED package will be described with reference to FIG.

搭載部材１０は、リードフレーム１１に素子搭載凹部１２を有するパッケージ本体１３を絶縁性樹脂で成形して構成されている。このパッケージ本体１３の素子搭載凹部１２の底面中央部には、半導体素子であるＬＥＤ素子１４（発光素子）がダイボンディング（接合）されている。素子搭載凹部１２の深さ寸法（高さ寸法）は、ＬＥＤ素子１４の高さ寸法とほぼ同一に設定され、素子搭載凹部１２内に搭載したＬＥＤ素子１４上面の電極部１５がパッケージ本体１３上面のリードフレーム１１の電極部１１ａとほぼ同じ高さとなっている。   The mounting member 10 is configured by molding a package body 13 having an element mounting recess 12 in a lead frame 11 with an insulating resin. An LED element 14 (light emitting element), which is a semiconductor element, is die-bonded (bonded) to the center of the bottom surface of the element mounting recess 12 of the package body 13. The depth dimension (height dimension) of the element mounting recess 12 is set to be approximately the same as the height dimension of the LED element 14, and the electrode portion 15 on the upper surface of the LED element 14 mounted in the element mounting recess 12 is the upper surface of the package body 13. The lead frame 11 has almost the same height as the electrode portion 11a.

ＬＥＤ素子１４上面の電極部１５とパッケージ本体１３上面の電極部１１ａの表面には、それぞれ後述する絶縁性樹脂１６の液に対して撥液性のある撥液膜１７が厚さ所定値以下に薄く形成されている。この撥液膜１７の形成方法は、厚膜法（インクジェット、ディスペンサ等の液滴吐出法又は印刷法等）により、例えば、シラン化合物系、フッ素樹脂系等の撥液性材料の液を吐出又は印刷して、撥液膜１７のパターンを描画して乾燥・硬化させれば良い。撥液膜１７の膜厚は、後述する配線１８と電極部１５，１１ａとの間の導通性を確保できる所定値以下（例えば１００ｎｍ以下）に形成されている。撥液膜１７は、電極部１５，１１ａの表面のみに形成しても良いし、電極部１５，１１ａからその周辺部にはみ出すように形成しても良い。要は、少なくとも電極部１５，１１ａの表面に撥液膜１７を形成すれば良い。   On the surface of the electrode portion 15 on the upper surface of the LED element 14 and the surface of the electrode portion 11a on the upper surface of the package body 13, a liquid repellent film 17 having a liquid repellency with respect to the liquid of the insulating resin 16 described later has a thickness of a predetermined value or less. Thinly formed. The liquid repellent film 17 can be formed by, for example, discharging a liquid of a liquid repellent material such as a silane compound type or a fluororesin type by a thick film method (e.g., a droplet discharge method such as ink jet or dispenser or a printing method). What is necessary is just to print, to draw the pattern of the liquid repellent film 17, and to dry and harden. The film thickness of the liquid repellent film 17 is formed to be equal to or less than a predetermined value (for example, 100 nm or less) that can secure electrical conductivity between a wiring 18 (described later) and the electrode portions 15 and 11a. The liquid repellent film 17 may be formed only on the surfaces of the electrode portions 15 and 11a, or may be formed so as to protrude from the electrode portions 15 and 11a to the periphery thereof. In short, the liquid repellent film 17 may be formed on at least the surfaces of the electrode portions 15 and 11a.

パッケージ本体１３の素子搭載凹部１２内のうちのＬＥＤ素子１４の周囲の隙間（凹部）に、透明な絶縁性樹脂１６が充填されて透明な埋込み樹脂層が形成されている。これにより、ＬＥＤ素子１４上面の電極部１５とパッケージ本体１３上面の電極部１１ａとの間をつなぐ配線経路は、素子搭載凹部１２内のＬＥＤ素子１４の周囲の隙間に充填した絶縁性樹脂１６により段差（凹凸）が小さくなってなだらかになっている。   A transparent insulating resin 16 is filled in a gap (recess) around the LED element 14 in the element mounting recess 12 of the package body 13 to form a transparent embedded resin layer. As a result, the wiring path connecting the electrode portion 15 on the upper surface of the LED element 14 and the electrode portion 11a on the upper surface of the package body 13 is formed by the insulating resin 16 filled in the gap around the LED element 14 in the element mounting recess 12. The step (unevenness) becomes smaller and smoother.

ＬＥＤ素子１４上面の電極部１５とパッケージ本体１３上面の電極部１１ａとの間の配線経路には、配線１８が電極部１５，１１ａ上の撥液膜１７に重ねて形成され、該配線１８が該撥液膜１７を介して電極部１５，１１ａに導通した状態となっている。この配線１８の形成方法は、インクジェット、ディスペンサ等の液滴吐出法又は印刷法により導電性のインク（Ａｇ等の導体粒子を含むインク）を吐出又は印刷して配線１８のパターンを描画し、これを乾燥して焼成すれば良い。
尚、搭載部材１０の上側部分は、ＬＥＤ素子１４と配線１８を封止する透明な絶縁封止材でモールドされる。 In the wiring path between the electrode portion 15 on the upper surface of the LED element 14 and the electrode portion 11a on the upper surface of the package body 13, the wiring 18 is formed so as to overlap the liquid repellent film 17 on the electrode portions 15 and 11a. The electrode portions 15 and 11a are electrically connected through the liquid repellent film 17. The wiring 18 is formed by discharging or printing conductive ink (ink containing conductive particles such as Ag) by a droplet discharge method such as ink jet or dispenser or a printing method, thereby drawing a pattern of the wiring 18. Is dried and fired.
The upper portion of the mounting member 10 is molded with a transparent insulating sealing material that seals the LED element 14 and the wiring 18.

次に、上記構成のＬＥＤパッケージの製造方法を説明する。
搭載部材１０の形成後に、素子搭載工程に進み、図１に示すように、パッケージ本体１３の素子搭載凹部１２の底面中央部に、ＬＥＤ素子１４がダイボンディング（接合）する。 Next, a method for manufacturing the LED package having the above configuration will be described.
After the mounting member 10 is formed, the process proceeds to an element mounting process, and the LED element 14 is die-bonded (bonded) to the center of the bottom surface of the element mounting recess 12 of the package body 13 as shown in FIG.

この後、撥液膜形成工程に移行し、図２に示すように、ＬＥＤ素子１４上面の電極部１５の表面とパッケージ本体１３上面の電極部１１ａの表面に、厚膜法（インクジェット、ディスペンサ等の液滴吐出法又は印刷法）により撥液性材料の液を吐出又は印刷して、各電極部１５，１１ａの表面に撥液膜１７のパターンを描画して乾燥させる。   Thereafter, the process proceeds to a liquid repellent film forming step, and as shown in FIG. 2, a thick film method (inkjet, dispenser, etc.) is applied to the surface of the electrode portion 15 on the upper surface of the LED element 14 and the surface of the electrode portion 11a on the upper surface of the package body 13. The liquid repellent material is discharged or printed by the liquid droplet discharge method or printing method), and the pattern of the liquid repellent film 17 is drawn on the surfaces of the electrode portions 15 and 11a and dried.

尚、ＬＥＤ素子１４上面の電極部１５の表面に撥液膜１７を形成する工程は、ＬＥＤ素子１４をパッケージ本体１３の素子搭載凹部１２にダイボンディングする前に行っても良い。   The step of forming the liquid repellent film 17 on the surface of the electrode portion 15 on the upper surface of the LED element 14 may be performed before the LED element 14 is die-bonded to the element mounting recess 12 of the package body 13.

また、ＬＥＤ素子１４の製造工程や、搭載部材１０の製造工程で、電極部１５，１１ａの表面に撥液膜１７を形成しても良い。つまり、電極部１５，１１ａの表面に撥液膜１７を形成する工程は、ＬＥＤ素子１４の製造元や搭載部材１０の製造元で行っても良く、これらの製造元から撥液膜１７付きのＬＥＤ素子１４や搭載部材１０を入手して、以下の工程を実行するようにしても良い。   Further, the liquid repellent film 17 may be formed on the surfaces of the electrode portions 15 and 11 a in the manufacturing process of the LED element 14 and the mounting process of the mounting member 10. That is, the step of forming the liquid repellent film 17 on the surfaces of the electrode portions 15 and 11a may be performed by the manufacturer of the LED element 14 or the manufacturer of the mounting member 10, and the LED element 14 with the liquid repellent film 17 from these manufacturers. Or the mounting member 10 may be acquired and the following processes may be performed.

この後、撥液膜焼成工程に移行し、撥液膜１７を所定温度で焼成して、該撥液膜１７の組成成分を分解・蒸発させて該撥液膜１７の膜厚を薄くする。この際、撥液膜１７の焼成温度は、配線１８の焼成温度又はそれ以下の温度とすれば良い。尚、撥液膜１７の焼成に代えて、紫外線等の光を撥液膜１７に照射することで、該撥液膜１７の組成成分を分解・蒸発させて該撥液膜１７の膜厚を薄くするようにしても良い。
この撥液膜焼成工程についても、ＬＥＤ素子１４の製造元や搭載部材１０の製造元で行っても良い。 Thereafter, the process proceeds to a liquid repellent film baking step, where the liquid repellent film 17 is baked at a predetermined temperature, the composition components of the liquid repellent film 17 are decomposed and evaporated, and the film thickness of the liquid repellent film 17 is reduced. At this time, the firing temperature of the liquid repellent film 17 may be set to the firing temperature of the wiring 18 or lower. Instead of firing the liquid repellent film 17, the liquid repellent film 17 is irradiated with light such as ultraviolet rays to decompose and evaporate the composition components of the liquid repellent film 17, thereby increasing the film thickness of the liquid repellent film 17. You may make it thin.
This liquid repellent film baking process may also be performed by the manufacturer of the LED element 14 or the manufacturer of the mounting member 10.

この後、絶縁性樹脂埋込み工程に移行し、図３に示すように、パッケージ本体１３の素子搭載凹部１２内のうちのＬＥＤ素子１４の周囲の隙間（凹部）に、透明な絶縁性樹脂１６の液をインクジェット、ディスペンサ等の液滴吐出法により充填して乾燥・硬化させて透明な絶縁性樹脂１６の埋込み層を形成する。この際、素子搭載凹部１２内に充填した絶縁性樹脂１６の液の一部が素子搭載凹部１２から溢れて各電極部１５，１１ａの縁部にまで広がるように絶縁性樹脂１６の吐出量を設定することで、ＬＥＤ素子１４上面の電極部１５とパッケージ本体１３上面の電極部１１ａとの間の配線経路の段差をできるだけ小さくして該配線経路全体をなだらかにする。   Thereafter, the process proceeds to an insulating resin embedding process, and as shown in FIG. 3, the transparent insulating resin 16 is placed in the gap (recess) around the LED element 14 in the element mounting recess 12 of the package body 13. The liquid is filled by a droplet discharge method such as ink jet or dispenser, dried and cured to form an embedded layer of transparent insulating resin 16. At this time, the discharge amount of the insulating resin 16 is set so that a part of the liquid of the insulating resin 16 filled in the element mounting recess 12 overflows from the element mounting recess 12 and spreads to the edges of the electrode portions 15 and 11a. By setting, the step of the wiring path between the electrode part 15 on the upper surface of the LED element 14 and the electrode part 11a on the upper surface of the package body 13 is made as small as possible to make the entire wiring path gentle.

このとき、素子搭載凹部１２から溢れた絶縁性樹脂１６の液が各電極部１５，１１ａの縁部にまで濡れ広がっても、各電極部１５，１１ａの表面は撥液膜１７で覆われているため、電極部１５，１１ａの縁部まで濡れ広がった絶縁性樹脂１６の液が電極部１５，１１ａ上の撥液膜１７ではじかれて撥液膜１７上に濡れ広がることが阻止される。   At this time, even if the liquid of the insulating resin 16 overflowing from the element mounting recess 12 wets and spreads to the edges of the electrode portions 15 and 11a, the surfaces of the electrode portions 15 and 11a are covered with the liquid repellent film 17. Therefore, the liquid of the insulating resin 16 that has spread to the edges of the electrode portions 15 and 11a is prevented from being repelled by the liquid repellent film 17 on the electrode portions 15 and 11a and spreading onto the liquid repellent film 17. .

この後、配線形成工程に移行し、図４に示すように、ＬＥＤ素子１４上面の電極部１５とパッケージ本体１３上面の電極部１１ａとの間の配線経路（絶縁性樹脂１６の埋込み層上面）に、インクジェット、ディスペンサ等の液滴吐出法又は印刷法により導電性のインク（Ａｇ等の導体粒子を含むインク）を吐出又は印刷して配線１８のパターンを描画し、これを乾燥して焼成する。この際、配線１８の焼成温度は、２００℃程度（例えば１８０℃以上）で、焼成時間は３０分〜６０分程度とすれば良い。配線１８の焼成時の熱により撥液膜１７の組成成分を分解・蒸発させて該撥液膜１７の膜厚を薄くすることができ、電極部１５，１１ａと配線１８との間の導通性も向上させることができる。   Thereafter, the process proceeds to a wiring forming process, and as shown in FIG. 4, a wiring path between the electrode part 15 on the upper surface of the LED element 14 and the electrode part 11a on the upper surface of the package body 13 (upper surface of the embedded layer of the insulating resin 16). Then, conductive ink (ink containing conductive particles such as Ag) is ejected or printed by a droplet ejection method such as inkjet or dispenser or a printing method to draw a pattern of the wiring 18, which is dried and baked. . At this time, the firing temperature of the wiring 18 may be about 200 ° C. (for example, 180 ° C. or more), and the firing time may be about 30 minutes to 60 minutes. The composition of the liquid repellent film 17 can be decomposed and evaporated by heat during firing of the wiring 18 to reduce the film thickness of the liquid repellent film 17, and the conductivity between the electrode portions 15, 11 a and the wiring 18 can be reduced. Can also be improved.

この後、封止工程に移行し、搭載部材１０の上側部分を透明な絶縁封止材でモールドしてＬＥＤ素子１４と配線１８を透明な絶縁封止材で封止する。   Then, it transfers to a sealing process, the upper part of the mounting member 10 is molded with a transparent insulating sealing material, and the LED element 14 and the wiring 18 are sealed with a transparent insulating sealing material.

以上説明した本実施例１によれば、ＬＥＤ素子１４上面の電極部１５の表面とパッケージ本体１３上面の電極部１１ａの表面に、絶縁性樹脂１６の液に対して撥液性のある撥液膜１７を形成するようにしているため、両電極部１５，１１ａ間の配線経路の凹部や段差を絶縁性樹脂１６で埋める際に、絶縁性樹脂１６の吐出量を適度に増やしても、絶縁性樹脂１６の液が電極部１５，１１ａ上に濡れ広がることを撥液膜１７によって防止できる。これにより、配線１８の断線の原因となる配線経路の凹部や段差を十分に絶縁性樹脂１６で埋めて配線経路を十分になだらかにすることができ、配線経路の段差による配線１８の断線を防止できると共に、配線１８と電極部１５，１１ａとの間の撥液膜１７を薄くすることで配線１８と電極部１１ａとの導通性を確保することができ、配線１８の接続信頼性を向上できる。   According to the first embodiment described above, the liquid repellent liquid repellent to the liquid of the insulating resin 16 is provided on the surface of the electrode portion 15 on the upper surface of the LED element 14 and the surface of the electrode portion 11a on the upper surface of the package body 13. Since the film 17 is formed, even when the discharge amount of the insulating resin 16 is increased moderately when the recesses or steps in the wiring path between the electrode portions 15 and 11a are filled with the insulating resin 16, the insulating film 16 is insulated. The liquid repellent film 17 can prevent the liquid of the conductive resin 16 from spreading on the electrode portions 15 and 11a. As a result, the recesses and steps of the wiring path that cause the disconnection of the wiring 18 can be sufficiently filled with the insulating resin 16 to sufficiently smooth the wiring path, and the disconnection of the wiring 18 due to the step of the wiring path is prevented. In addition, by reducing the thickness of the liquid-repellent film 17 between the wiring 18 and the electrode parts 15 and 11a, electrical connection between the wiring 18 and the electrode part 11a can be secured, and the connection reliability of the wiring 18 can be improved. .

しかも、本実施例１では、配線１８を形成する前に、撥液膜１７を焼成（又は光照射）することで、該撥液膜１７の組成成分を分解・蒸発させて該撥液膜１７の膜厚を薄くするようにしたので、電極部１５，１１ａと配線１８との間の撥液膜１７の電気抵抗値を低下させて電極部１５，１１ａと配線１８との間の導通性を向上させることができる。   Moreover, in the first embodiment, before the wiring 18 is formed, the liquid repellent film 17 is baked (or irradiated with light), so that the composition components of the liquid repellent film 17 are decomposed and evaporated to cause the liquid repellent film 17 to be decomposed. Therefore, the electrical resistance value of the liquid-repellent film 17 between the electrode portions 15 and 11a and the wiring 18 is reduced to improve the electrical conductivity between the electrode portions 15 and 11a and the wiring 18. Can be improved.

次に、図５を用いて本発明の実施例２を説明する。但し、上記実施例１と実質的に同じ部分には同じ符号を付して説明を省略又は簡略化し、主として異なる部分について説明する。   Next, Embodiment 2 of the present invention will be described with reference to FIG. However, substantially the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted or simplified, and different parts are mainly described.

上記実施例１では、パッケージ本体１３の素子搭載凹部１２内に充填した絶縁性樹脂１６の埋込み層上に配線１８を直接形成するようにしたが、絶縁性樹脂１６の埋込み層のみでは、ＬＥＤ素子１４上面の電極部１５とパッケージ本体１３上面の電極部１１ａとの間の配線経路の段差を完全には埋めきれずに段差が少し残る場合がある。   In the first embodiment, the wiring 18 is directly formed on the embedded layer of the insulating resin 16 filled in the element mounting recess 12 of the package body 13, but the LED element is formed only by the embedded layer of the insulating resin 16. The step of the wiring path between the electrode portion 15 on the upper surface 14 and the electrode portion 11a on the upper surface of the package main body 13 may not be completely filled, and a step may remain slightly.

そこで、図５に示す本発明の実施例２では、絶縁性樹脂埋込み工程の終了後に、配線１８を形成する前に、絶縁性樹脂１６の埋込み層上にプライマ樹脂層２１を形成して、ＬＥＤ素子１４上面の電極部１５とパッケージ本体１３上面の電極部１１ａとの間の配線経路の段差をプライマ樹脂層２１で更に小さくして配線経路をより一層なだらかにした後、該プライマ樹脂層２１上に配線１８を形成する。   Therefore, in the second embodiment of the present invention shown in FIG. 5, after the insulating resin embedding process is completed, before the wiring 18 is formed, a primer resin layer 21 is formed on the embedding layer of the insulating resin 16, and the LED The step of the wiring path between the electrode part 15 on the upper surface of the element 14 and the electrode part 11a on the upper surface of the package body 13 is further reduced by the primer resin layer 21 to further smooth the wiring path, and then on the primer resin layer 21. A wiring 18 is formed on the substrate.

この際、プライマ樹脂層２１は、配線１８を形成する部分のみに線状又は帯状に形成しても良いし、絶縁性樹脂１６の埋込み層の上面全体に面状に形成しても良い。要は、少なくとも配線１８を形成する下地部分にプライマ樹脂層２１を形成すれば良い。プライマ樹脂層２１を広範囲に形成する場合は、プライマ樹脂層２１がＬＥＤ素子１４の光の放射を遮らないように、透明な材料でプライマ樹脂層２１を形成することが望ましい。   At this time, the primer resin layer 21 may be formed in a linear shape or a strip shape only in a portion where the wiring 18 is formed, or may be formed in a planar shape on the entire upper surface of the embedded layer of the insulating resin 16. In short, the primer resin layer 21 may be formed at least on the base portion where the wiring 18 is formed. When forming the primer resin layer 21 in a wide range, it is desirable to form the primer resin layer 21 with a transparent material so that the primer resin layer 21 does not block the light emission of the LED element 14.

このプライマ樹脂層２１の形成方法は、インクジェット、ディスペンサ等の液滴吐出法又は印刷法により、上記絶縁性材料のインクを配線経路上に吐出又は印刷して、プライマ樹脂層２１のパターンを配線経路上に線状又は帯状に描画して乾燥・硬化させてプライマ樹脂層２１を形成する。この際、プライマ樹脂層２１の液が各電極部１５，１１ａの縁部にまで濡れ広がっても、各電極部１５，１１ａの表面は撥液膜１７で覆われているため、電極部１５，１１ａの縁部まで濡れ広がったプライマ樹脂層２１の液が電極部１５，１１ａ上の撥液膜１７ではじかれて撥液膜１７上に濡れ広がることが阻止される。   The primer resin layer 21 is formed by discharging or printing the ink of the insulating material on the wiring path by a droplet discharge method such as ink jet or dispenser or a printing method, and thereby forming a pattern of the primer resin layer 21 on the wiring path. The primer resin layer 21 is formed by drawing in a linear or strip shape on the top and drying and curing. At this time, even if the liquid of the primer resin layer 21 wets and spreads to the edges of the electrode portions 15 and 11a, the surfaces of the electrode portions 15 and 11a are covered with the liquid repellent film 17, so The liquid of the primer resin layer 21 that has spread to the edge of 11a is repelled by the liquid repellent film 17 on the electrode portions 15 and 11a and is prevented from spreading on the liquid repellent film 17.

ここで、プライマ樹脂層２１の材料としては、例えば、エポキシ樹脂系、ポリイミド樹脂系、ガラス（ＳｉＯ2 ）系等の絶縁性材料があり、これらの絶縁性材料の中から、光透過性、耐湿性、絶縁性樹脂１６の埋込み層及び配線１８に対する密着性等を考慮して選択すれば良い。 Here, the material of the primer resin layer 21 includes, for example, an insulating material such as an epoxy resin type, a polyimide resin type, or a glass (SiO 2 ) type. The selection may be made in consideration of the property, the adhesion of the insulating resin 16 to the buried layer and the wiring 18, and the like.

そして、プライマ樹脂層２１の乾燥・硬化後に、インクジェット、ディスペンサ等の液滴吐出法又は印刷法により導電性のインク（Ａｇ等の導体粒子を含むインク）をプライマ樹脂層２１上に吐出又は印刷して、配線１８のパターンをＬＥＤ素子１４上面の電極部１５上の撥液膜１７とパッケージ本体１３上面の電極部１１ａ上の撥液膜１７とに跨がってプライマ樹脂層２１上に描画し、これを乾燥して焼成して、ＬＥＤ素子１４上面の電極部１５とパッケージ本体１３上面の電極部１１ａとの間を配線１８で接続する。   Then, after the primer resin layer 21 is dried and cured, conductive ink (ink containing conductor particles such as Ag) is discharged or printed on the primer resin layer 21 by a droplet discharge method such as inkjet or dispenser or a printing method. Then, the pattern of the wiring 18 is drawn on the primer resin layer 21 across the liquid repellent film 17 on the electrode portion 15 on the upper surface of the LED element 14 and the liquid repellent film 17 on the electrode portion 11a on the upper surface of the package body 13. Then, this is dried and baked to connect the electrode portion 15 on the upper surface of the LED element 14 and the electrode portion 11a on the upper surface of the package body 13 by wiring 18.

以上説明した本実施例２では、両電極部１５，１１ａ間の配線経路の凹部や段差を絶縁性樹脂１６で埋めた後に、該配線経路上にプライマ樹脂層２１を形成して該プライマ樹脂層２１上に配線１８を形成するようにしたので、プライマ樹脂層２１によって配線経路をより一層なだらかにすることができ、液滴吐出法や印刷法で配線１８をプライマ樹脂層２１上に形成しやすくなると共に、配線経路の段差による配線１８の断線をより確実に防止できる。その他、前記実施例１と同様の効果を得ることができる。   In the second embodiment described above, after the recesses or steps of the wiring path between the electrode portions 15 and 11a are filled with the insulating resin 16, the primer resin layer 21 is formed on the wiring path to thereby form the primer resin layer. Since the wiring 18 is formed on the primer 21, the wiring route can be made smoother by the primer resin layer 21, and the wiring 18 can be easily formed on the primer resin layer 21 by a droplet discharge method or a printing method. In addition, disconnection of the wiring 18 due to a step in the wiring path can be more reliably prevented. In addition, the same effects as those of the first embodiment can be obtained.

次に、図６を用いて本発明の実施例３を説明する。但し、前記実施例１と実質的に同じ部分には同じ符号を付して説明を省略又は簡略化し、主として異なる部分について説明する。   Next, Embodiment 3 of the present invention will be described with reference to FIG. However, substantially the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted or simplified, and different parts are mainly described.

上記実施例１，２では、各電極部１５，１１ａ上に撥液膜１７を直接形成するようにしたが、図６に示す本発明の実施例３では、撥液膜１７を形成する前に、インクジェット、ディスペンサ等の液滴吐出法又は印刷法により、各電極部１５，１１ａの表面に導電性材料を塗布又は印刷して導電性材料膜２２を形成する。この導電性材料膜２２を形成する材料は、配線１８を形成する材料と同じ導電性材料を用いれば良い。   In the first and second embodiments, the liquid repellent film 17 is formed directly on the electrode portions 15 and 11a. However, in the third embodiment of the present invention shown in FIG. The conductive material film 22 is formed by applying or printing a conductive material on the surfaces of the electrode portions 15 and 11a by a droplet discharge method such as inkjet or dispenser or a printing method. As a material for forming the conductive material film 22, the same conductive material as that for forming the wiring 18 may be used.

導電性材料膜２２の形成後に、該導電性材料膜２２上に、前記実施例１と同様の方法で、撥液膜１７を形成する。この後、パッケージ本体１３の素子搭載凹部１２内に透明な絶縁性樹脂１６の液を充填して透明な絶縁性樹脂１６の埋込み層を形成した後、該絶縁性樹脂１６の埋込み層上に配線１８を形成する。或は、前記実施例２と同様に、絶縁性樹脂１６の埋込み層上にプライマ樹脂層２１を形成して該プライマ樹脂層２１上に配線１８を形成するようにしても良い。   After the formation of the conductive material film 22, the liquid repellent film 17 is formed on the conductive material film 22 by the same method as in the first embodiment. Thereafter, the element mounting recess 12 of the package body 13 is filled with a transparent insulating resin 16 solution to form an embedded layer of the transparent insulating resin 16, and then a wiring is formed on the embedded layer of the insulating resin 16. 18 is formed. Alternatively, as in the second embodiment, the primer resin layer 21 may be formed on the buried layer of the insulating resin 16 and the wiring 18 may be formed on the primer resin layer 21.

以上説明した本実施例３では、撥液膜１７を形成する前に各電極部１５，１１ａの表面に導電性材料を塗布又は印刷して導電性材料膜２２を形成した後、該導電性材料膜２２上に撥液膜１７を形成するようにしたので、導電性材料膜２２中の導電粒子が撥液膜１７中に浸透して該撥液膜１７の電気抵抗値が低下するようになり、電極部１５，１１ａと配線１８との間の導通性を向上させることができる。   In the third embodiment described above, the conductive material film 22 is formed by applying or printing the conductive material on the surfaces of the electrode portions 15 and 11a before the liquid repellent film 17 is formed. Since the liquid repellent film 17 is formed on the film 22, the conductive particles in the conductive material film 22 penetrate into the liquid repellent film 17 and the electric resistance value of the liquid repellent film 17 is lowered. The electrical conductivity between the electrode portions 15 and 11a and the wiring 18 can be improved.

次に、図７及び図８を用いて本発明の実施例４を説明する。但し、前記実施例１と実質的に同じ部分には同じ符号を付して説明を省略又は簡略化し、主として異なる部分について説明する。   Next, Embodiment 4 of the present invention will be described with reference to FIGS. However, substantially the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted or simplified, and different parts are mainly described.

本実施例４では、前記実施例１と同様の方法で、素子搭載工程と撥液膜形成工程を実行して、各電極部１５，１１ａの表面に撥液膜１７を形成した後、絶縁性樹脂埋込み工程に移行し、パッケージ本体１３の素子搭載凹部１２内のうちのＬＥＤ素子１４の周囲の隙間（凹部）に、透明な絶縁性樹脂１６の液を充填して透明な絶縁性樹脂１６の埋込み層を形成する。この際、素子搭載凹部１２から溢れた絶縁性樹脂１６の液が各電極部１５，１１ａの縁部にまで濡れ広がっても、各電極部１５，１１ａの表面は撥液膜１７で覆われているため、電極部１５，１１ａの縁部まで濡れ広がった絶縁性樹脂１６の液が電極部１５，１１ａ上の撥液膜１７ではじかれて撥液膜１７上に濡れ広がることが阻止される。   In the fourth embodiment, the element mounting step and the liquid repellent film forming step are performed by the same method as in the first embodiment to form the liquid repellent film 17 on the surfaces of the electrode portions 15 and 11a. The process proceeds to the resin embedding step, and the gap around the LED element 14 in the element mounting recess 12 of the package body 13 is filled with the liquid of the transparent insulating resin 16 to form the transparent insulating resin 16. A buried layer is formed. At this time, even if the liquid of the insulating resin 16 overflowing from the element mounting recess 12 wets and spreads to the edges of the electrode portions 15 and 11 a, the surfaces of the electrode portions 15 and 11 a are covered with the liquid repellent film 17. Therefore, the liquid of the insulating resin 16 that has spread to the edges of the electrode portions 15 and 11a is prevented from being repelled by the liquid repellent film 17 on the electrode portions 15 and 11a and spreading onto the liquid repellent film 17. .

尚、絶縁性樹脂埋込み工程後に、前記実施例２のように、絶縁性樹脂１６の埋込み層上に透明なプライマ樹脂層２１を形成するようにしても良い。   Note that, after the insulating resin embedding step, the transparent primer resin layer 21 may be formed on the insulating resin 16 embedding layer as in the second embodiment.

この後、撥液膜除去工程に移行し、撥液膜１７を焼成又は光照射することで該撥液膜１７の組成成分をほぼ全て分解・蒸発させて該撥液膜１７を除去した後に、配線形成工程に移行し、両電極部１５，１１ａ間の配線経路上に配線１８を形成して該配線１８を両電極部１５，１１ａに直接接続する。この後、封止工程に移行し、搭載部材１０の上側部分を透明な絶縁封止材でモールドして封止する。   Thereafter, the process proceeds to a liquid repellent film removal step, and the liquid repellent film 17 is baked or irradiated with light to decompose and evaporate almost all the composition components of the liquid repellent film 17 to remove the liquid repellent film 17. The process proceeds to a wiring forming process, where a wiring 18 is formed on a wiring path between both electrode parts 15 and 11a, and the wiring 18 is directly connected to both electrode parts 15 and 11a. Then, it transfers to a sealing process and molds the upper part of the mounting member 10 with a transparent insulating sealing material and seals it.

以上説明した本実施例４では、両電極部１５，１１ａ間の配線経路の凹部や段差を絶縁性樹脂１６で埋める際に、絶縁性樹脂１６の液が電極部１５，１１ａ上に濡れ広がることを撥液膜１７によって防止しながら、配線１８を形成する前に該撥液膜１７を除去することができるため、電極部１５，１１ａと配線１８との間の導通性を向上させることができる。   In the fourth embodiment described above, the liquid of the insulating resin 16 wets and spreads on the electrode portions 15 and 11a when the recesses or steps in the wiring path between the electrode portions 15 and 11a are filled with the insulating resin 16. Since the liquid repellent film 17 can be removed before the wiring 18 is formed while the liquid repellent film 17 is prevented, the electrical conductivity between the electrode portions 15 and 11a and the wiring 18 can be improved. .

次に、図９を用いて本発明の実施例５を説明する。但し、前記実施例１と実質的に同じ部分には同じ符号を付して説明を省略又は簡略化し、主として異なる部分について説明する。   Next, Embodiment 5 of the present invention will be described with reference to FIG. However, substantially the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted or simplified, and different parts are mainly described.

本実施例５では、素子搭載工程で、搭載部材である配線基板３１上にＬＥＤ素子１４をダイボンディングする。この後、撥液膜形成工程に移行し、ＬＥＤ素子１４上面の電極部１５と配線基板３１上面の電極部３２の表面に、厚膜法（インクジェット、ディスペンサ等の液滴吐出法又は印刷法）により撥液性材料の液を吐出又は印刷して、各電極部１５，３２の表面に撥液膜１７のパターンを描画して乾燥させる。この後、撥液膜焼成工程に移行し、撥液膜１７を所定温度で焼成して、該撥液膜１７の組成成分を分解・蒸発させて該撥液膜１７の膜厚を薄くする。   In the fifth embodiment, the LED element 14 is die-bonded on the wiring substrate 31 as a mounting member in the element mounting step. Thereafter, the process proceeds to a liquid repellent film forming step, and a thick film method (a droplet discharge method such as an ink jet or a dispenser or a printing method) is applied to the surfaces of the electrode portion 15 on the upper surface of the LED element 14 and the electrode portion 32 on the upper surface of the wiring substrate 31. Thus, a liquid of a liquid repellent material is discharged or printed, and a pattern of the liquid repellent film 17 is drawn on the surfaces of the electrode portions 15 and 32 and dried. Thereafter, the process proceeds to a liquid repellent film baking step, where the liquid repellent film 17 is baked at a predetermined temperature, the composition components of the liquid repellent film 17 are decomposed and evaporated, and the film thickness of the liquid repellent film 17 is reduced.

この後、絶縁性樹脂スロープ形成工程に移行し、ＬＥＤ素子１４の周囲に、透明な絶縁性樹脂３３の液をディスペンサで吐出して、ＬＥＤ素子１４上面の電極部１５と配線基板３１上面の電極部３２との間の配線経路の段差を絶縁性樹脂３３で埋めて該配線経路を傾斜面でなだらかにつなぐ透明な絶縁性樹脂３３のスロープを形成する。この際、絶縁性樹脂３３の液が各電極部１５，３２の縁部にまで濡れ広がっても、各電極部１５，３２の表面は撥液膜１７で覆われているため、電極部１５，３２の縁部まで濡れ広がった絶縁性樹脂３３の液が電極部１５，３２上の撥液膜１７ではじかれて撥液膜１７上に濡れ広がることが阻止される。尚、絶縁性樹脂３３のスロープ形成後に、該絶縁性樹脂３３のスロープ上に透明なプライマ樹脂層を形成するようにしても良い。   Thereafter, the process proceeds to an insulating resin slope forming step, and a liquid of transparent insulating resin 33 is discharged around the LED element 14 with a dispenser, so that the electrode portion 15 on the upper surface of the LED element 14 and the electrode on the upper surface of the wiring board 31 are discharged. The step of the wiring path to the portion 32 is filled with the insulating resin 33 to form a slope of the transparent insulating resin 33 that gently connects the wiring path with the inclined surface. At this time, even if the liquid of the insulating resin 33 spreads to the edges of the electrode portions 15 and 32, the surfaces of the electrode portions 15 and 32 are covered with the liquid repellent film 17. The liquid of the insulating resin 33 that has spread to the edge of 32 is repelled by the liquid repellent film 17 on the electrode portions 15 and 32 and is prevented from being wet spread on the liquid repellent film 17. A transparent primer resin layer may be formed on the slope of the insulating resin 33 after the slope of the insulating resin 33 is formed.

この後、配線形成工程に移行し、両電極部１５，３２間の配線経路上（絶縁性樹脂３３のスロープ上）に配線１８を形成して該配線１８を両電極部１５，３２に接続する。この後、封止工程に移行し、配線基板３１の上側部分を透明な絶縁封止材でモールドしてＬＥＤ素子１４と配線１８を透明な絶縁封止材で封止する。   Thereafter, the process proceeds to a wiring forming process, where the wiring 18 is formed on the wiring path between the electrode parts 15 and 32 (on the slope of the insulating resin 33), and the wiring 18 is connected to both the electrode parts 15 and 32. . Thereafter, the process proceeds to a sealing step, and the upper part of the wiring substrate 31 is molded with a transparent insulating sealing material, and the LED element 14 and the wiring 18 are sealed with a transparent insulating sealing material.

以上説明した本実施例５でも、前記実施例１と同様の効果を得ることができる。
尚、上記各実施例１〜５では、配線１７を厚膜法（液滴吐出法又は印刷法等）で形成したが、本発明は、これに限定されず、薄膜法又は導電性部材の貼付により形成しても良い。薄膜法は、例えば、ＩＴＯ等の透明な導電性材料を用いた物理蒸着「ＰＶＤ」（スパッタリング、真空蒸着、イオンプレーティング等）、化学蒸着「ＣＶＤ」（プラズマＣＶＤ、熱ＣＶＤ等）、溶射（プラズマ溶射、アーク溶射等）、めっき法のいずれかを用いて配線１８のパターンを形成しても良い。配線１８を透明な導電性材料で形成する場合は、線状や帯状に形成しても良いし、面状に形成しても良く、要は、他の導電物に接触してショートしない範囲内で、配線１８の位置ずれ等を考慮して配線１８の線幅を幅広に形成すれば良い。 In the fifth embodiment described above, the same effect as that of the first embodiment can be obtained.
In each of Examples 1 to 5, the wiring 17 is formed by a thick film method (droplet discharge method or printing method). However, the present invention is not limited to this, and a thin film method or a conductive member is attached. You may form by. Thin film methods include, for example, physical vapor deposition “PVD” (sputtering, vacuum vapor deposition, ion plating, etc.) using a transparent conductive material such as ITO, chemical vapor deposition “CVD” (plasma CVD, thermal CVD, etc.), thermal spraying ( The pattern of the wiring 18 may be formed using any one of plasma spraying, arc spraying, etc.) or plating. When the wiring 18 is formed of a transparent conductive material, it may be formed in a linear shape or a strip shape, or may be formed in a planar shape. Therefore, the line width of the wiring 18 may be formed wide in consideration of the positional deviation of the wiring 18 and the like.

また、上記各実施例１〜５では、ＬＥＤ素子１４上面の電極部１５とパッケージ本体１３（配線基板３１）の上面の電極部１１ａ（３２）の両方に撥液膜１７を形成したが、どちらか一方の電極部のみに絶縁性樹脂１６（３３）の液が濡れ広がりやすい構造のものでは、絶縁性樹脂１６の液が濡れ広がりやすい方の電極部のみに撥液膜１７を形成するようにしても良い。例えば、実施例５（図９）の構造では、配線基板３１上面の電極部３２がＬＥＤ素子１４上面の電極部１５よりも低い位置に存在するため、高い方のＬＥＤ素子１４上面の電極部１５と比べて、低い方の配線基板３１上面の電極部３２に向かって絶縁性樹脂３３の液が濡れ広がりやすい。この点を考慮して、配線基板３１上面の電極部３２のみに撥液膜１７を形成するようにしても良い。   In each of the above Examples 1 to 5, the liquid repellent film 17 is formed on both the electrode portion 15 on the upper surface of the LED element 14 and the electrode portion 11a (32) on the upper surface of the package body 13 (wiring substrate 31). In the structure in which the liquid of the insulating resin 16 (33) is easily wetted and spread only on one of the electrode parts, the liquid repellent film 17 is formed only on the electrode part on which the liquid of the insulating resin 16 is easily wetted and spread. May be. For example, in the structure of Example 5 (FIG. 9), since the electrode part 32 on the upper surface of the wiring board 31 is located at a position lower than the electrode part 15 on the upper surface of the LED element 14, the electrode part 15 on the upper surface of the higher LED element 14 is used. As compared with the above, the liquid of the insulating resin 33 tends to wet and spread toward the electrode portion 32 on the upper surface of the lower wiring substrate 31. Considering this point, the liquid repellent film 17 may be formed only on the electrode portion 32 on the upper surface of the wiring substrate 31.

その他、本発明は、ＬＥＤパッケージに限定されず、ＬＥＤ素子以外の半導体素子を搭載部材に搭載した様々な構造の半導体パッケージに適用して実施できる等、要旨を逸脱しない範囲内で種々変更して実施できることは言うまでもない。   In addition, the present invention is not limited to the LED package, and various modifications can be made without departing from the gist, such as being applicable to semiconductor packages having various structures in which semiconductor elements other than LED elements are mounted on a mounting member. Needless to say, it can be implemented.

１０…搭載部材、１１…リードフレーム、１１ａ…電極部、１２…素子搭載凹部、１３…パッケージ本体、１４…ＬＥＤ素子（半導体素子）、１５…電極部、１６…絶縁性樹脂、１７…撥液膜、１８…配線、２１…プライマ樹脂層、２２…導電性材料膜、３１…配線基板（搭載部材）   DESCRIPTION OF SYMBOLS 10 ... Mounting member, 11 ... Lead frame, 11a ... Electrode part, 12 ... Element mounting recessed part, 13 ... Package main body, 14 ... LED element (semiconductor element), 15 ... Electrode part, 16 ... Insulating resin, 17 ... Liquid repellent Membrane, 18 ... wiring, 21 ... primer resin layer, 22 ... conductive material film, 31 ... wiring substrate (mounting member)

Claims (10)

搭載部材上に半導体素子を搭載し、該半導体素子側の電極部と該搭載部材側の電極部との間の配線経路の凹部及び／又は段差を絶縁性樹脂で埋めると共に、該半導体素子側の電極部と該搭載部材側の電極部との間を接続する配線を該絶縁性樹脂上に形成した半導体パッケージにおいて、
前記配線経路の凹部及び／又は段差を前記絶縁性樹脂で埋める前に前記半導体素子側の電極部の表面及び／又は前記搭載部材側の電極部の表面に、前記絶縁性樹脂の液に対して撥液性のある撥液膜を厚さ所定値以下に薄く形成し、若しくは予め電極部の表面に前記撥液膜が形成された半導体素子及び／又は予め電極部の表面に前記撥液膜が形成された搭載部材を使用し、
前記配線経路の凹部及び／又は段差を前記絶縁性樹脂で埋めて該配線経路をなだらかにした後に前記配線を該配線経路上と前記撥液膜上とに跨がって形成することで該配線を該撥液膜を介して前記電極部に導通させたことを特徴とする半導体パッケージ。 A semiconductor element is mounted on the mounting member, and a recess and / or a step in the wiring path between the electrode part on the semiconductor element side and the electrode part on the mounting member side is filled with an insulating resin, and the semiconductor element side In the semiconductor package in which the wiring connecting the electrode part and the electrode part on the mounting member side is formed on the insulating resin,
Before the recesses and / or steps of the wiring path are filled with the insulating resin, the surface of the electrode part on the semiconductor element side and / or the surface of the electrode part on the mounting member side is exposed to the liquid of the insulating resin. A liquid repellent film having a liquid repellent thickness is formed thinly to a predetermined value or less, or a semiconductor element in which the liquid repellent film is previously formed on the surface of the electrode portion and / or the liquid repellent film is previously formed on the surface of the electrode portion. Using the formed mounting member,
The wiring path is formed by straddling the wiring path and the liquid-repellent film after filling the recess and / or step of the wiring path with the insulating resin to smooth the wiring path. A semiconductor package, wherein the electrode portion is electrically connected through the liquid repellent film. 前記配線経路の凹部及び／又は段差を前記絶縁性樹脂で埋めた後に、該配線経路上にプライマ樹脂層を形成して該プライマ樹脂層上に前記配線を形成したことを特徴とする請求項１に記載の半導体パッケージ。   2. The recesses and / or steps of the wiring path are filled with the insulating resin, a primer resin layer is formed on the wiring path, and the wiring is formed on the primer resin layer. The semiconductor package described in 1. 前記撥液膜を形成する前に前記半導体素子側の電極部の表面及び／又は前記搭載部材側の電極部の表面に導電性材料を塗布又は印刷して導電性材料膜を形成した後、該導電性材料膜上に前記撥液膜を形成したことを特徴とする請求項１又は２に記載の半導体パッケージ。   Before forming the liquid repellent film, a conductive material is applied or printed on the surface of the electrode part on the semiconductor element side and / or the surface of the electrode part on the mounting member side to form a conductive material film. 3. The semiconductor package according to claim 1, wherein the liquid repellent film is formed on a conductive material film. 搭載部材上に半導体素子を搭載し、該半導体素子側の電極部と該搭載部材側の電極部との間の配線経路の凹部及び／又は段差を絶縁性樹脂で埋めると共に、該半導体素子側の電極部と該搭載部材側の電極部との間を接続する配線を該配線経路上に形成する半導体パッケージの製造方法において、
前記半導体素子側の電極部の表面及び／又は前記搭載部材側の電極部の表面に、前記絶縁性樹脂の液に対して撥液性のある撥液膜を膜さ所定値以下に薄く形成する工程と、
前記撥液膜の形成後に前記配線経路の凹部及び／又は前記段差を前記絶縁性樹脂で埋めて該配線経路をなだらかにする工程と、
前記配線経路の凹部及び／又は段差を前記絶縁性樹脂で埋めた後に前記配線を該配線経路上と前記撥液膜上とに跨がって形成することで該配線を該撥液膜を介して前記電極部に導通させる工程と
を含むことを特徴とする半導体パッケージの製造方法。 A semiconductor element is mounted on the mounting member, and a recess and / or a step in the wiring path between the electrode part on the semiconductor element side and the electrode part on the mounting member side is filled with an insulating resin, and the semiconductor element side In the manufacturing method of the semiconductor package, the wiring connecting the electrode portion and the electrode portion on the mounting member side is formed on the wiring path.
A liquid repellent film having a liquid repellency with respect to the liquid of the insulating resin is formed thin on the surface of the electrode part on the semiconductor element side and / or on the surface of the electrode part on the mounting member side to a predetermined value or less. Process,
Filling the recesses and / or the steps of the wiring path with the insulating resin after the formation of the liquid repellent film, and smoothing the wiring path;
After the recess and / or step of the wiring path is filled with the insulating resin, the wiring is formed across the wiring path and the liquid repellent film so that the wiring passes through the liquid repellent film. And a step of conducting to the electrode part. 搭載部材上に半導体素子を搭載し、該半導体素子側の電極部と該搭載部材側の電極部との間の配線経路の凹部及び／又は段差を絶縁性樹脂で埋めると共に、該半導体素子側の電極部と該搭載部材側の電極部との間を接続する配線を該配線経路上に形成する半導体パッケージの製造方法において、
予め前記絶縁性樹脂の液に対して撥液性のある撥液膜が厚さ所定値以下に薄く形成された半導体素子及び／又は予め電極部の表面に前記絶縁性樹脂の液に対して撥液性のある撥液膜が厚さ所定値以下に薄く形成された搭載部材を使用し、
前記配線経路の凹部及び／又は前記段差を前記絶縁性樹脂で埋めて該配線経路をなだらかにする工程と、
前記配線経路の凹部及び／又は段差を前記絶縁性樹脂で埋めた後に前記配線を該配線経路上と前記撥液膜上とに跨がって形成することで該配線を該撥液膜を介して前記電極部に導通させる工程と
を含むことを特徴とする半導体パッケージの製造方法。 A semiconductor element is mounted on the mounting member, and a recess and / or a step in the wiring path between the electrode part on the semiconductor element side and the electrode part on the mounting member side is filled with an insulating resin, and the semiconductor element side In the manufacturing method of the semiconductor package, the wiring connecting the electrode portion and the electrode portion on the mounting member side is formed on the wiring path.
A semiconductor element in which a liquid repellent film having a liquid repellency with respect to the liquid of the insulating resin is formed thinly below a predetermined value and / or a surface of the electrode portion in advance with respect to the liquid of the insulating resin. Using a mounting member in which a liquid repellent film with a thin thickness is formed below a predetermined value,
Filling the recesses and / or the steps of the wiring path with the insulating resin to smooth the wiring path;
After the recess and / or step of the wiring path is filled with the insulating resin, the wiring is formed across the wiring path and the liquid repellent film so that the wiring passes through the liquid repellent film. And a step of conducting to the electrode part. 前記配線経路の凹部及び／又は段差を前記絶縁性樹脂で埋めた後に、前記配線を形成する前に前記撥液膜を焼成又は光照射することで該撥液膜の組成成分を分解・蒸発させて該撥液膜の膜厚を薄くすることを特徴とする請求項４又は５に記載の半導体パッケージの製造方法。   After the recesses and / or steps of the wiring path are filled with the insulating resin, the liquid repellent film is baked or irradiated with light before the wiring is formed to decompose and evaporate the composition of the liquid repellent film. 6. The method of manufacturing a semiconductor package according to claim 4, wherein the liquid repellent film is thinned. 前記配線経路の凹部及び／又は段差を前記絶縁性樹脂で埋めた後に、該配線経路上にプライマ樹脂層を形成した後、該プライマ樹脂層上に前記配線を形成することを特徴とする請求項４乃至６のいずれかに記載の半導体パッケージの製造方法。   The recesses and / or steps of the wiring path are filled with the insulating resin, a primer resin layer is formed on the wiring path, and then the wiring is formed on the primer resin layer. A method for manufacturing a semiconductor package according to any one of 4 to 6. 前記撥液膜を形成する前に前記半導体素子側の電極部の表面及び／又は前記搭載部材側の電極部の表面に導電性材料を塗布又は印刷して導電性材料膜を形成した後、該導電性材料膜上に前記撥液膜を形成することを特徴とする請求項４乃至７のいずれかに記載の半導体パッケージの製造方法。   Before forming the liquid repellent film, a conductive material is applied or printed on the surface of the electrode part on the semiconductor element side and / or the surface of the electrode part on the mounting member side to form a conductive material film. The method of manufacturing a semiconductor package according to claim 4, wherein the liquid repellent film is formed on a conductive material film. 搭載部材上に半導体素子を搭載し、該半導体素子側の電極部と該搭載部材側の電極部との間の配線経路の凹部及び／又は段差を絶縁性樹脂で埋めると共に、該半導体素子側の電極部と該搭載部材側の電極部との間を接続する配線を該配線経路上に形成する半導体パッケージの製造方法において、
前記半導体素子側の電極部の表面及び／又は前記搭載部材側の電極部の表面に、前記絶縁性樹脂の液に対して撥液性のある撥液膜を形成する工程と、
前記撥液膜の形成後に前記配線経路の凹部及び／又は前記段差を前記絶縁性樹脂で埋めて該配線経路をなだらかにする工程と、
前記配線経路の凹部及び／又は段差を前記絶縁性樹脂で埋めた後に前記撥液膜を焼成又は光照射することで該撥液膜の組成成分をほぼ全て分解・蒸発させて該撥液膜を除去する工程と、
前記撥液膜を除去した後に前記配線を前記配線経路上に形成して該配線を前記電極部に接続する工程と
を含むことを特徴とする半導体パッケージの製造方法。 A semiconductor element is mounted on the mounting member, and a recess and / or a step in the wiring path between the electrode part on the semiconductor element side and the electrode part on the mounting member side is filled with an insulating resin, and the semiconductor element side In the manufacturing method of the semiconductor package, the wiring connecting the electrode portion and the electrode portion on the mounting member side is formed on the wiring path.
Forming a liquid repellent film having liquid repellency to the liquid of the insulating resin on the surface of the electrode part on the semiconductor element side and / or on the surface of the electrode part on the mounting member side;
Filling the recesses and / or the steps of the wiring path with the insulating resin after the formation of the liquid repellent film, and smoothing the wiring path;
After filling the recesses and / or steps of the wiring path with the insulating resin, the liquid repellent film is baked or irradiated with light to decompose and evaporate almost all the composition components of the liquid repellent film, Removing, and
Forming the wiring on the wiring path after removing the liquid-repellent film, and connecting the wiring to the electrode portion. 前記配線を厚膜法で形成して焼成することを特徴とする請求項４乃至９のいずれかに記載の半導体パッケージの製造方法。   10. The method of manufacturing a semiconductor package according to claim 4, wherein the wiring is formed by a thick film method and fired.
JP2012137903A 2012-06-19 2012-06-19 LED package and manufacturing method thereof Active JP6037545B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012137903A JP6037545B2 (en) 2012-06-19 2012-06-19 LED package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012137903A JP6037545B2 (en) 2012-06-19 2012-06-19 LED package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2014003177A true JP2014003177A (en) 2014-01-09
JP6037545B2 JP6037545B2 (en) 2016-12-07

Family

ID=50036075

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012137903A Active JP6037545B2 (en) 2012-06-19 2012-06-19 LED package and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP6037545B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013115070A (en) * 2011-11-25 2013-06-10 Fuji Mach Mfg Co Ltd Semiconductor package and manufacturing method therefor
JP2021531652A (en) * 2018-07-16 2021-11-18 ナノ−ディメンション テクノロジーズ，リミテッド Methods and systems to improve connectivity of embedded components embedded in host structures

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61214444A (en) * 1985-03-18 1986-09-24 Fujitsu Ltd Semiconductor device
JP2005050911A (en) * 2003-07-30 2005-02-24 Seiko Epson Corp Semiconductor device
JP2007311596A (en) * 2006-05-19 2007-11-29 Murata Mfg Co Ltd Manufacturing method of circuit board having protruding electrode, and same circuit board having protruding electrode
JP2008021843A (en) * 2006-07-13 2008-01-31 Seiko Epson Corp Method of manufacturing wiring circuit and multilayer wiring circuit board
JP2010141293A (en) * 2008-11-14 2010-06-24 Seiko Epson Corp Semiconductor device and method for manufacturing the same
JP2012256769A (en) * 2011-06-10 2012-12-27 Fuji Mach Mfg Co Ltd Semiconductor device and manufacturing the same
JP2013115070A (en) * 2011-11-25 2013-06-10 Fuji Mach Mfg Co Ltd Semiconductor package and manufacturing method therefor
JP2013145852A (en) * 2012-01-16 2013-07-25 Fuji Mach Mfg Co Ltd Semiconductor package and manufacturing method of the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61214444A (en) * 1985-03-18 1986-09-24 Fujitsu Ltd Semiconductor device
JP2005050911A (en) * 2003-07-30 2005-02-24 Seiko Epson Corp Semiconductor device
JP2007311596A (en) * 2006-05-19 2007-11-29 Murata Mfg Co Ltd Manufacturing method of circuit board having protruding electrode, and same circuit board having protruding electrode
JP2008021843A (en) * 2006-07-13 2008-01-31 Seiko Epson Corp Method of manufacturing wiring circuit and multilayer wiring circuit board
JP2010141293A (en) * 2008-11-14 2010-06-24 Seiko Epson Corp Semiconductor device and method for manufacturing the same
JP2012256769A (en) * 2011-06-10 2012-12-27 Fuji Mach Mfg Co Ltd Semiconductor device and manufacturing the same
JP2013115070A (en) * 2011-11-25 2013-06-10 Fuji Mach Mfg Co Ltd Semiconductor package and manufacturing method therefor
JP2013145852A (en) * 2012-01-16 2013-07-25 Fuji Mach Mfg Co Ltd Semiconductor package and manufacturing method of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013115070A (en) * 2011-11-25 2013-06-10 Fuji Mach Mfg Co Ltd Semiconductor package and manufacturing method therefor
JP2021531652A (en) * 2018-07-16 2021-11-18 ナノ−ディメンション テクノロジーズ，リミテッド Methods and systems to improve connectivity of embedded components embedded in host structures
JP7374172B2 (en) 2018-07-16 2023-11-06 ナノ ディメンション テクノロジーズ，リミテッド Methods and systems for improving connectivity of embedded components embedded in host structures

Also Published As

Publication number Publication date
JP6037545B2 (en) 2016-12-07

Similar Documents

Publication Publication Date Title
US20170148966A1 (en) Surface-Mountable Semiconductor Component and Method for Producing Same
JP5639720B2 (en) Organic electroluminescent lighting device and manufacturing method thereof
JP6037544B2 (en) LED package and its manufacturing method
JP6122423B2 (en) LED package and manufacturing method thereof
JP2012256769A (en) Semiconductor device and manufacturing the same
JP4723479B2 (en) Insulated power semiconductor module in which partial discharge behavior is suppressed to a low level and manufacturing method thereof
WO2015018107A1 (en) Oled encapsulation structure and encapsulation method
WO2013077144A1 (en) Semiconductor package and method for manufacturing same
KR101426434B1 (en) Manufacturing method of semiconductor light emitting device
JP6029821B2 (en) Light emitting device package and manufacturing method thereof
JP5328827B2 (en) Power module structure, power module having the structure, and method of manufacturing the structure
CN106328633A (en) Electronic device module and method of manufacturing the same
JP6037545B2 (en) LED package and manufacturing method thereof
JP4549171B2 (en) Hybrid integrated circuit device
JP6081087B2 (en) Light emitting device package and manufacturing method thereof
JP5905267B2 (en) Light emitting device package and manufacturing method thereof
JP6032823B2 (en) Semiconductor device and manufacturing method thereof
KR102617348B1 (en) Chip on film semiconductor packages and display apparatus including the same
CN106299077B (en) The production method of LED encapsulation structure
CN109686857B (en) Display device and packaging method thereof
JP6053053B2 (en) Semiconductor package and manufacturing method thereof
US11715647B2 (en) Method for producing a substrate
JP2009302239A (en) Light source module
KR20120063434A (en) Method for producing a circuit arrangement
JP4036017B2 (en) Electronic component mounting structure

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150421

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20151218

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160112

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160307

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160822

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161013

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20161028

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20161031

R150 Certificate of patent or registration of utility model

Ref document number: 6037545

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250