JP2013115136A - Substrate with built-in electronic components and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit warp of a substrate with built-in electronic components; and manufacture a substrate with built-in electronic components having a high semiconductor chip occupancy.SOLUTION: A manufacturing method of a substrate with built-in electronic components comprises: preparing a first substrate including a resin insulation layer and component built-in parts in each of which an electronic component is arranged in a housing part formed in the resin insulation layer; preparing a second substrate having openings; cutting the first substrate into substrate pieces each including the component built-in part; and arranging and fixing the cut substrate pieces in the openings of the second substrate.

Description

  The present invention relates to an electronic component built-in substrate and a method for manufacturing the same.

  Patent Document 1 discloses an electronic component built-in substrate and a manufacturing method thereof.

JP 2008-131039 A

  In the method for manufacturing an electronic component built-in substrate described in Patent Document 1, after the electronic component is accommodated in the resin insulating layer, the entire substrate is heated and pressurized. In this case, the substrate is likely to warp due to the difference between the thermal expansion coefficient of the electronic component (for example, a semiconductor chip made of silicon) and the thermal expansion coefficient of the resin insulating layer.

  And if the curvature of a board | substrate becomes large, the mounting reliability in the case of surface-mounting components on a board | substrate will fall. For this reason, it becomes difficult to manufacture an electronic component built-in substrate having a high semiconductor chip occupation ratio.

  The present invention has been made in view of such circumstances, and an object thereof is to suppress warping of the electronic component built-in substrate. Another object of the present invention is to manufacture an electronic component built-in substrate having a high semiconductor chip occupation ratio.

The method for manufacturing an electronic component built-in substrate according to the present invention includes:
Preparing a first substrate having a resin insulation layer and a component built-in part in which an electronic component is arranged in a housing part formed in the resin insulation layer;
Providing a second substrate having an opening;
Cutting out a board piece including the component built-in part from the first board;
Arranging and fixing the cut out substrate piece in the opening of the second substrate;
including.

  The semiconductor chip occupancy ratio of the prepared first substrate is preferably lower than the semiconductor chip occupancy ratio of the electronic component built-in substrate in which the substrate pieces are arranged in all the openings of the second substrate.

  It is preferable that the semiconductor chip occupation ratio of the prepared first substrate is less than 10% in area ratio, and the semiconductor chip occupation ratio of the electronic component built-in substrate is 10% or more in area ratio.

  The prepared second substrate preferably does not have a semiconductor chip.

  In the preparation of the first substrate, it is preferable that the resin insulating layer is cured to a B stage or a C stage.

  In the preparation of the first substrate, it is preferable that the resin insulating layer is cured to the C stage.

  It is preferable that an alignment mark indicating a position of the component built-in portion is formed on the first substrate.

Preparing a second substrate having the opening,
Preparing a second substrate;
Forming an opening in the second substrate;
Cutting off the end of the second substrate to reduce warpage of the second substrate after forming the opening;
It is preferable that it contains.

  It is preferable that a conductor pattern is formed on an edge portion of the second substrate, and an end portion of the second substrate to be cut off includes the edge portion on which the conductor pattern is formed.

  The opening is preferably a hole penetrating the second substrate.

  The electronic component is preferably a semiconductor chip.

  The first substrate is preferably a rigid wiring board.

  The first substrate is preferably a build-up printed wiring board.

  It is preferable that the substrate piece disposed in the opening is fixed with an adhesive.

The first substrate has a plurality of the component built-in parts,
Prior to the placement of the board piece, including performing a pass / fail judgment for each of the component built-in parts,
In the arrangement of the board piece, only the board piece including the component built-in part determined to be non-defective by the quality determination is arranged in the opening.
It is preferable.

The electronic component built-in substrate according to the present invention is:
A substrate having a plurality of openings formed thereon;
A plurality of semiconductor chip built-in substrate pieces manufactured separately from the substrate and fixed to each of the plurality of openings,
Have

  The semiconductor chip occupancy ratio of the electronic component built-in substrate is preferably 10% or more by area ratio.

  According to the present invention, for example, it is possible to suppress warping of the electronic component built-in substrate. Further, according to the present invention, in addition to this effect or instead of this effect, there may be an effect that it is possible to manufacture an electronic component built-in substrate having a high semiconductor chip occupation ratio.

It is a flowchart which shows the manufacturing method of the electronic component built-in board | substrate which concerns on embodiment of this invention. It is a top view which shows the 1st board | substrate used in the manufacturing method of the electronic component built-in board | substrate which concerns on embodiment of this invention. It is sectional drawing of the component built-in part of the 1st board | substrate shown in FIG. FIG. 6 is a diagram for explaining a first step of manufacturing the first substrate shown in FIG. 2 in the method for manufacturing the electronic component built-in substrate according to the embodiment of the present invention. It is a figure for demonstrating the 2nd process after the process of FIG. 4A. It is a figure for demonstrating the 3rd process after the process of FIG. 4B. It is a figure for demonstrating the 4th process after the process of FIG. 4C. It is a figure for demonstrating the 5th process after the process of FIG. 4D. It is a figure for demonstrating the 6th process after the process of FIG. It is a figure for demonstrating the 7th process after the process of FIG. It is a figure for demonstrating the 8th process after the process of FIG. It is a figure for demonstrating the 9th process after the process of FIG. It is a figure for demonstrating the 10th process after the process of FIG. It is a figure for demonstrating the 11th process after the process of FIG. It is a figure for demonstrating the 12th process after the process of FIG. It is a figure for demonstrating the 13th process after the process of FIG. 12A. It is a figure for demonstrating the 14th process after the process of FIG. 12B. It is a top view which shows the alignment mark formed in a 1st board | substrate in the manufacturing method of the electronic component built-in board | substrate which concerns on embodiment of this invention. It is a top view which shows the 1st form of the alignment mark shown in FIG. It is a top view which shows the 2nd form of the alignment mark shown in FIG. It is sectional drawing which shows the 1st example of the alignment mark shown in FIG. It is sectional drawing which shows the 2nd example of the alignment mark shown in FIG. It is sectional drawing which shows the 3rd example of the alignment mark shown in FIG. It is sectional drawing which shows the 4th example of the alignment mark shown in FIG. It is a figure for demonstrating the process of test | inspecting a component built-in part in the manufacturing method of the electronic component built-in board which concerns on embodiment of this invention. It is a figure for demonstrating the process of cutting out a board | substrate piece from a 1st board | substrate in the manufacturing method of the electronic component built-in board | substrate which concerns on embodiment of this invention. It is a top view for demonstrating the 1st process of preparing the 2nd board | substrate which has an opening part in the manufacturing method of the electronic component built-in board | substrate which concerns on embodiment of this invention. It is sectional drawing of the 2nd board | substrate shown to FIG. 18A. It is a top view for demonstrating the 2nd process after the process of FIG. 18A. It is sectional drawing of the 2nd board | substrate shown to FIG. 19A. It is a top view for demonstrating the process of arrange | positioning a board piece in the opening part of a 2nd board | substrate in the manufacturing method of the electronic component built-in board | substrate which concerns on embodiment of this invention. It is sectional drawing, such as a board | substrate piece shown in FIG. 20A, a 2nd board | substrate. It is a figure which expands and shows the board piece arrange | positioned in the opening part of a 2nd board | substrate in the manufacturing method of the electronic component built-in board | substrate which concerns on embodiment of this invention. It is a top view for demonstrating the process of fixing the board | substrate piece arrange | positioned in an opening part with an adhesive agent in the manufacturing method of the electronic component built-in substrate which concerns on embodiment of this invention. It is sectional drawing, such as a board | substrate piece shown in FIG. 22A, a 2nd board | substrate. It is sectional drawing which shows the electronic component built-in board | substrate which concerns on embodiment of this invention. It is a graph which shows the relationship between the semiconductor chip occupation rate of the electronic component built-in board | substrate manufactured with one board | substrate, and the curvature amount, without performing the cutting-out of a board | substrate piece, and the transfer to another board | substrate. In other embodiment of this invention, it is a figure which shows the 1st example which forms an adhesive only in the predetermined part of the clearance gap between the 2nd board | substrate and board | substrate piece in an opening part. In other embodiment of this invention, it is a figure which shows the 2nd example which forms an adhesive agent only in the predetermined part of the clearance gap between the 2nd board | substrate and board | substrate piece in an opening part. The figure which shows the example which fixes a board | substrate piece in an opening part by the coupling | bonding of the nail | claw part (convex part) formed in the board | substrate piece and the nail | claw receiving part (concave part) formed in the opening part in other embodiment of this invention. It is. In other embodiment of this invention, it is a figure which shows the example in which several board | substrate pieces are accommodated in one opening part formed in the 2nd board | substrate. In other embodiment of this invention, it is a figure which shows the 1st example of the planar shape of the opening part, a board | substrate piece, and the through hole in the 1st board | substrate, the alignment mark, and the via hole of each layer. In other embodiment of this invention, it is a figure which shows the 2nd example of the planar shape of the through-hole in the opening part, a board | substrate piece, and a 1st board | substrate, an alignment mark, and the via hole of each layer. In other embodiment of this invention, it is a figure which shows the 3rd example of the planar shape of the opening part, a board | substrate piece, and the through hole in the 1st board | substrate, the alignment mark, and the via hole of each layer. In other embodiment of this invention, it is a figure which shows the 4th example of the planar shape of the opening part, a board | substrate piece, and the through-hole in the 1st board | substrate, the alignment mark, and the via hole of each layer. FIG. 4 is a view showing a first substrate having a structure different from the structure shown in FIG. 3 in another embodiment of the present invention. In other embodiment of this invention, it is a figure which shows the example by which the opening part formed in a 2nd board | substrate is comprised from the hole which does not penetrate a 2nd board | substrate. In other embodiment of this invention, it is a figure which shows the 1st example which consists of a surface where the wall surface of the opening part formed in a 2nd board | substrate is a taper. In other embodiment of this invention, it is a figure which shows the 2nd example which consists of a surface where the wall surface of the opening part formed in a 2nd board | substrate is a taper. It is a flowchart which shows the manufacturing method of the electronic component built-in board | substrate which concerns on other embodiment of this invention. FIG. 33 is a plan view for explaining a first step of preparing a second substrate having an opening in the method for manufacturing the electronic component built-in substrate shown in FIG. 32. It is sectional drawing of the 2nd board | substrate shown to FIG. 33A. It is a figure for demonstrating the 2nd process after the process of FIG. 33A. FIG. 33 is a view for explaining a step of cutting the end portion of the second substrate in the method of manufacturing the electronic component built-in substrate shown in FIG. 32.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the figure, arrows Z1 and Z2 indicate the stacking direction of the substrate (or the thickness direction of the substrate) corresponding to the normal direction of the main surface (front and back surfaces) of the substrate. On the other hand, arrows X1 and X2 and Y1 and Y2 respectively indicate directions orthogonal to the stacking direction (or sides of each layer). The main surface of the substrate is an XY plane. Further, the side surface of the substrate is an XZ plane or a YZ plane.

  In the present embodiment, the side closer to the core in the stacking direction is referred to as the lower layer, and the side farther from the core is referred to as the upper layer.

  The conductor layer is a layer composed of one or more conductor patterns. The conductor layer may include a conductor pattern that constitutes an electric circuit, for example, a wiring (including a ground), a pad, a land, or the like, or a planar conductor pattern that does not constitute an electric circuit.

  The openings include notches and cuts in addition to holes and grooves. The hole is not limited to a through hole, and includes a non-through hole.

  Preparation includes purchasing and using finished products in addition to purchasing materials and parts and making them themselves.

  The “arrangement in the opening” includes not only that the entire substrate piece is completely arranged in the opening, but also that only a part of the substrate piece is arranged in the opening. In short, it is sufficient that at least a part of the substrate piece is disposed in the opening.

  In addition to wet plating such as electrolytic plating, plating includes dry plating such as PVD (Physical Vapor Deposition) and CVD (Chemical Vapor Deposition).

  FIG. 1 shows a method for manufacturing an electronic component built-in substrate according to the present embodiment.

  In step S11, a first substrate 1000 is prepared as shown in FIG. The first substrate 1000 is a build-up printed wiring board. Specifically, the first substrate 1000 is, for example, a rigid wiring board.

  The shape of the first substrate 1000 is, for example, a substantially rectangular plate shape. However, the shape is not limited to this, and the shape of the first substrate 1000 is arbitrary.

  The first substrate 1000 has a plurality of component built-in parts 10 (for example, four). The interval d10 between the component built-in portions 10 is, for example, 22 mm. The smaller the interval d10 between the component built-in parts 10, the easier it is to increase the number of component built-in parts 10 obtained by one first substrate 1000.

  As shown in FIG. 3, the component built-in portion 10 has a housing portion R <b> 1 (cavity), and the electronic component 200 is built in the housing portion R <b> 1. The accommodating portion R1 of the present embodiment is configured from a hole that penetrates the insulating layer 100.

  As shown in FIG. 3, the component built-in portion 10 includes an insulating layer 100 (core substrate), insulating layers 101 and 102, conductor layers 301, 302, 110, and 120, via conductors 311b, 312b, and 322b, Hall conductor 300b. Hereinafter, one (Z1 side) of the front and back surfaces (two main surfaces) of the first substrate 1000 is referred to as a first surface F1, and the other (Z2 side) is referred to as a second surface F2. One (Z1 side) of the front and back surfaces (two main surfaces) of the insulating layer 100 is referred to as a third surface F3, and the other (Z2 side) is referred to as a fourth surface F4. Further, one (Z1 side) of the front and back surfaces (two main surfaces) of the electronic component 200 is referred to as a fifth surface F5, and the other (Z2 side) is referred to as a sixth surface F6.

  The electronic component 200 has electrodes 210 and 220. In the present embodiment, the electronic component 200 has electrodes only on one side (for example, the fifth side F5). The electronic component 200 is a semiconductor chip, for example. Specifically, the electronic component 200 is an IC (integrated circuit) chip made of, for example, silicon (Si). However, the present invention is not limited to this. For example, the electronic component 200 may be an IC composed of a semiconductor other than silicon, or may be an electronic component (such as a resistor, a capacitor, or a coil) other than an IC.

  The electronic component 200 is disposed in the accommodating portion R1 formed in the insulating layers 100, 101, and 102 (respective resin insulating layers). The fifth surface F5 of the electronic component 200 is in the same direction as the third surface F3 of the insulating layer 100. A gap between the electronic component 200 and the insulating layer 100 in the housing portion R1 is filled with an insulator 101a. The insulator 101a is made of, for example, a resin that flows out from surrounding insulating layers (for example, the insulating layers 100, 101, and 102).

  A conductor layer 301 is formed on the third surface F3 of the insulating layer 100. The insulating layer 101 and the conductor layer 301 are formed on the third surface F3 of the insulating layer 100, on the conductor layer 301, and on the fifth surface F5 of the electronic component 200. The conductor layer 110 is laminated in this order. Also, a conductor layer 302 is formed on the fourth surface F4 of the insulating layer 100, and a conductor layer is formed on the fourth surface F4 of the insulating layer 100, on the conductor layer 302, and on the sixth surface F6 of the electronic component 200. 302, the insulating layer 102, and the conductor layer 120 are laminated in this order. The conductor layers 110 and 120 are the outermost conductor layers on the first surface F1 side and the second surface F2 side, respectively.

  A through hole 300a that penetrates the insulating layer 100 is formed in the insulating layer 100, and a conductor (for example, copper plating) is filled in the through hole 300a, whereby the conductor in the through hole 300a becomes the through hole conductor 300b ( For example, a filled conductor). Via holes 311a and 312a are formed in the insulating layer 101, and each of the via holes 311a and 312a is filled with a conductor (for example, copper plating). For example, filled conductors). In addition, a via hole 322a is formed in the insulating layer 102, and a conductor (for example, copper plating) is filled in the via hole 322a, whereby the conductor in the via hole 322a becomes a via conductor 322b (for example, a filled conductor).

  The through-hole conductor 300b electrically connects the conductor layer 301 and the conductor layer 302 to each other, the via conductor 312b electrically connects the conductor layer 301 and the conductor layer 110 to each other, and the via conductor 322b 302 and the conductor layer 120 are electrically connected to each other. The via conductor 311b electrically connects the electrodes 210 and 220 of the electronic component 200 and the conductor layer 110. In this embodiment, each of the via conductors 312b and 322b is formed immediately above the through-hole conductor 300b (Z direction), and a stack conductor is formed by the via conductors 312b and 322b and the through-hole conductor 300b.

  The shape of the through-hole conductor 300b is, for example, an hourglass shape (a drum shape). That is, the through-hole conductor 300b has a constricted portion 300c, and the width of the through-hole conductor 300b gradually decreases from the third surface F3 of the insulating layer 100 toward the constricted portion 300c. As it gets closer to the constricted portion 300c from the surface F4, it gradually becomes smaller. However, the shape is not limited to this, and the shape of the through-hole conductor 300b is arbitrary, and may be, for example, a substantially cylindrical shape.

  Note that portions other than the component built-in portion 10 of the first substrate 1000 have substantially the same structure (see FIG. 3) as the component built-in portion 10 except that the electronic component 200 is not built.

  Hereinafter, the manufacture of the first substrate 1000 will be described with reference to a cross-sectional view corresponding to FIG. 3.

  First, as shown in FIG. 4A, a double-sided copper-clad laminate 3000 is prepared as a starting material. The double-sided copper-clad laminate 3000 includes an insulating layer 100 (core substrate), a copper foil 3001 formed on the third surface F3 of the insulating layer 100, and a copper foil formed on the fourth surface F4 of the insulating layer 100. 3002.

  The insulating layer 100 is made of, for example, a glass cloth (core material) impregnated with an epoxy resin (hereinafter referred to as glass epoxy). The core material is a material having a smaller coefficient of thermal expansion than the main material (in the present embodiment, epoxy resin). As a core material, it is thought that inorganic materials, such as glass fiber (for example, glass cloth or glass nonwoven fabric), an aramid fiber (for example, aramid nonwoven fabric), or a silica filler, are preferable, for example. However, the material of the insulating layer 100 is basically arbitrary. For example, instead of an epoxy resin, a polyester resin, a bismaleimide triazine resin (BT resin), an imide resin (polyimide), a phenol resin, an allylated phenylene ether resin (A-PPE resin), or the like may be used. Further, the insulating layer 100 may not include a core material. The insulating layer 100 may be composed of a plurality of layers made of different materials.

  In this embodiment, at this stage, the insulating layer 100 is made of a glass epoxy in a completely cured state (C stage).

Subsequently, as shown in FIG. 4B, a hole 3003 is formed by irradiating the double-sided copper-clad laminate 3000 with a laser from the third surface F3 side using, for example, a CO ₂ laser, and the laser is emitted from the fourth surface F4 side. Is formed on the double-sided copper-clad laminate 3000 to form a hole 3004. The hole 3003 and the hole 3004 are formed at substantially the same position in the XY plane and are finally connected to form a through hole 300a penetrating the double-sided copper-clad laminate 3000. The shape of the through hole 300a corresponds to the through hole conductor 300b and is, for example, an hourglass shape (a drum shape). The boundary between the hole 3003 and the hole 3004 corresponds to the constricted portion 300c. The laser irradiation on the third surface F3 and the laser irradiation on the fourth surface F4 may be performed simultaneously or may be performed one side at a time. After the through hole 300a is formed, it is preferable to perform desmearing on the through hole 300a. Undesirable conduction (short circuit) is suppressed by desmear. Further, in order to increase the absorption efficiency of laser light, the surfaces of the copper foils 3001 and 3002 may be blackened prior to laser irradiation. The through hole 300a may be formed by a method other than laser, such as drilling or etching. However, fine processing is easy with laser processing. In particular, when the thermal expansion coefficient of the insulating layer 100 is small, drilling becomes difficult, so laser processing is effective.

  Subsequently, as shown in FIG. 4C, for example, a copper plating 3005 is formed on the copper foils 3001 and 3002 and in the through holes 300a by, for example, a panel plating method. Specifically, electroless plating is first performed to form an electroless plating film, and then the electroless plating film is used as a seed layer to perform electroplating, thereby comprising an electroless plating film and electrolytic plating. A plating 3005 is formed. As a result, the through hole 300a is filled with the plating 3005, and the through hole conductor 300b is formed.

  Subsequently, the conductive layers formed on the third surface F3 and the fourth surface F4 of the insulating layer 100 are patterned using, for example, an etching resist and an etching solution. Specifically, each conductor layer is covered with an etching resist having a pattern corresponding to the conductor layers 301 and 302, and a portion of each conductor layer that is not covered with the etching resist (part exposed at the opening of the etching resist) Remove by etching. As a result, as shown in FIG. 4D, conductor layers 301 and 302 are formed on the third surface F3 and the fourth surface F4 of the insulating layer 100, respectively. Hereinafter, the substrate thus obtained is referred to as a substrate 3000a. Note that the etching is not limited to wet, and may be dry.

  Subsequently, as shown in FIG. 5, the accommodating portion R <b> 1 is formed on the substrate 3000 a (specifically, the insulating layer 100). In this embodiment, the housing part R1 (a hole penetrating the insulating layer 100) is formed by irradiating the insulating layer 100 with a laser. Specifically, for example, by irradiating a laser so as to draw a quadrangle in the XY plane, a region corresponding to the housing portion R1 in the insulating layer 100 is cut out from the surrounding portion.

  Subsequently, as shown in FIG. 6, a carrier 3006 made of, for example, PET (polyethylene terephthalate) is provided on one side (for example, the fourth surface F4 side) of the substrate 3000a. As a result, one opening of the housing portion R1 (hole) is closed by the carrier 3006. In the present embodiment, the carrier 3006 is made of an adhesive sheet (for example, a tape). The carrier 3006 has adhesiveness on one surface, and the substrate 3000a is placed on the adhesive surface (hereinafter referred to as an adhesive surface 3006a). The carrier 3006 is bonded to the substrate 3000a by lamination, for example.

  Subsequently, as shown in FIG. 7, the electronic component 200 is put into the housing portion R1 of the substrate 3000a from the side opposite to the opening where the housing portion R1 (hole) is blocked (Z1 side). The electronic component 200 is placed in the accommodating portion R1 by a component mounter, for example. As a result, as shown in FIG. 8, the electronic component 200 is placed on the adhesive surface 3006 a of the carrier 3006.

  Subsequently, as illustrated in FIG. 9, the insulating layer 101 is disposed on the third surface F <b> 3 of the insulating layer 100 and the fifth surface F <b> 5 of the electronic component 200.

  The insulating layer 101 is made of, for example, an epoxy resin and does not include a core material. As a material of the insulating layer 101, for example, ABF (Ajinomoto Build-up Film: manufactured by Ajinomoto Fine Techno Co., Ltd.) can be used. However, the material of the insulating layer 101 is basically arbitrary without being limited thereto. The insulating layer 101 may include a core material.

  Also, as shown in FIG. 9, by laminating the insulating layer 101 in an uncured or semi-cured state, the resin constituting the insulating layer 101 flows out and flows into the housing portion R1. Thereby, the insulator 101a (resin constituting the insulating layer 101) is filled in the gap R2 between the insulating layer 100 and the electronic component 200 in the housing portion R1.

  When the housing part R1 is filled with the insulator 101a, the filling resin (insulator 101a) and the electronic component 200 are temporarily welded. Specifically, the holding resin has such a degree that the electronic component 200 can be supported by the filling resin by heating. As a result, the electronic component 200 supported by the carrier 3006 is supported by the filling resin. Thereafter, the carrier 3006 is removed. Hereinafter, the substrate thus obtained is referred to as a substrate 3000b.

  At this stage, the insulator 101a (filling resin) and the insulating layer 101 are only semi-cured and are not completely cured. However, the invention is not limited to this. For example, the insulator 101a and the insulating layer 101 may be completely cured at this stage.

  Subsequently, as illustrated in FIG. 10, the insulating layer 102 is provided on the side opposite to the insulating layer 101 (the fourth surface F4 side or the sixth surface F6 side) of the substrate 3000b.

  The insulating layer 102 is made of, for example, an epoxy resin and does not include a core material. As a material of the insulating layer 102, for example, ABF can be used. However, the present invention is not limited to this, and the material of the insulating layer 102 is basically arbitrary. The insulating layer 102 may include a core material.

  Subsequently, the insulating layer 102 is bonded to the substrate 3000b in an uncured or semi-cured state by lamination, for example, and then heated to cure each of the insulating layers 101 and 102 to the C stage.

  In this embodiment, after removing the adhesive sheet (carrier 3006), the resin filled in the storage portion R1 is cured. For this reason, the insulating layers 101 and 102 can be simultaneously cured. Then, since the warping of the insulating layer 100 is suppressed by simultaneously curing the insulating layers 101 and 102 on both sides, the insulating layer 100 can be easily thinned.

  Subsequently, as shown in FIG. 11, via holes 311 a and 312 a are formed in the insulating layer 101, and a via hole 322 a is formed in the insulating layer 102 by, for example, a laser. Each of the via holes 311 a and 312 a penetrates the insulating layer 101, and the via hole 322 a penetrates the insulating layer 102. The via hole 311a reaches the electrode 210 or 220 of the electronic component 200, and each of the via holes 312a and 322a reaches directly above the through-hole conductor 300b. Then, desmear is performed as needed.

  Subsequently, as shown in FIG. 12A, for example, a copper electroless plating film 3007 or 3008 is formed in each of the via holes 311a, 312a, and 322a by, for example, chemical plating. Prior to electroless plating, for example, a catalyst made of palladium or the like may be adsorbed on the surfaces of the insulating layers 101 and 102.

  Subsequently, as shown in FIG. 12B, a plating resist 3009 having an opening 3009a is formed on the main surface (on the electroless plating film 3007) on the third surface F3 side by a lithography technique or printing, and the fourth surface. A plating resist 3010 having an opening 3010a is formed on the main surface on the F4 side (on the electroless plating film 3008). The openings 3009a and 3010a have patterns corresponding to the conductor layers 110 and 120 (FIG. 3), respectively.

  Subsequently, as shown in FIG. 12C, for example, copper electroplating 3011 and 3012 are formed in the openings 3009a and 3010a of the plating resists 3009 and 3010, for example, by pattern plating. Specifically, copper that is a material to be plated is connected to the anode, and electroless plating films 3007 and 3008 that are materials to be plated are connected to the cathode and immersed in a plating solution. Then, a direct current voltage is applied between the two electrodes to pass a current, and copper is deposited on the surfaces of the electroless plating films 3007 and 3008. As a result, the via holes 311a, 312a, and 322a are filled with the electrolytic plating 1011 or 1012, respectively, and via conductors 311b, 312b, and 322b made of, for example, copper plating are formed.

  Thereafter, the plating resists 3009 and 3010 are removed with, for example, a predetermined stripping solution, and then unnecessary electroless plating films 3007 and 3008 are removed, thereby forming the conductor layers 110 and 120 as shown in FIG. The

  In the present embodiment, as shown in FIG. 13, the conductor layer 110 includes an alignment mark M <b> 1 (for example, a conductor pattern) indicating the position of the component built-in portion 10. The alignment marks M1 are formed at the four corners of the component built-in part 10, for example. However, the present invention is not limited to this, and the arrangement and number of the alignment marks M1 are arbitrary.

  For example, as shown in FIG. 14A, the alignment mark M1 is made of a ring-shaped conductor. However, the present invention is not limited to this. For example, as shown in FIG. Further, the shape of the alignment mark M1 is not limited to the ring shape, and is arbitrary.

  The alignment mark M1 shown in FIG. 14A can be formed by a conductor pattern 110a included in the conductor layer 110, for example, as shown in FIG. 15A. However, the present invention is not limited to this. For example, as shown in FIG. 15B, a protrusion 110b may be selectively formed on the conductor pattern 110a of the conductor layer 110, and the protrusion 110b may be used as the alignment mark M1. The protrusion 110b is preferably made of metal, for example. Metal is easy to recognize optically. However, it is not limited to this, The material of the projection part 110b is arbitrary.

  The alignment mark M1 shown in FIG. 14B can be formed in the gap 110c of the conductor pattern 110a in the conductor layer 110, for example, as shown in FIG. 15C.

  In the present embodiment, the alignment mark M1 is formed on the outermost conductor layer 110. However, the present invention is not limited to this, and the alignment mark M1 may be formed on the inner conductor layer 301 as shown in FIG. 15D, for example. Further, the alignment mark M1 may be formed on each of the insulating layer 100 on the third surface F3 side and the fourth surface F4 side (for example, the conductor layers 110 and 120).

  The first substrate 1000 of this embodiment can be manufactured by the above manufacturing method, for example. The semiconductor chip occupation ratio (for example, Si occupation ratio) of the first substrate 1000 is less than 10% in the area ratio of the XY plane (the total area occupied by the semiconductor chips / the entire area of the first substrate 1000).

  In the manufacturing method of this embodiment, the insulating layers 101 and 102 are cured to the C stage by heat treatment.

  When each of the insulating layers 101 and 102 is made of ABF, it is preferable to heat the insulating layers 101 and 102 to a temperature of 180 ° C. or higher by a heat treatment for curing the insulating layers 101 and 102 to the C stage. When it consists of prepregs (copper foil with resin), it is preferable to heat to a temperature of 230 ° C. or higher by heat treatment for curing the insulating layers 101 and 102 to the C stage.

  Moreover, in the manufacturing method of this embodiment, since the alignment mark M1 which shows the position of the component built-in part 10 is formed in the 1st board | substrate 1000, it becomes possible to position the below-mentioned board piece 10a with high precision.

  Subsequently, in step S12 of FIG. 1, as shown in FIG. 16, each component built-in part 10 of the first substrate 1000 is inspected (good / bad judgment). Specifically, for example, a quality inspection is performed on electrical characteristics and the like. In FIG. 16, “◯” is written in the component built-in unit 10 determined as a non-defective product by the above-described quality determination, and “X” is written in the component built-in unit 10 determined as a defective product. As shown in FIG. 16, in the present embodiment, as an example, a case will be described in which two component built-in units 10 out of four component built-in units 10 are determined to be non-defective products.

  Subsequently, in step S13 of FIG. 1, as shown in FIG. 17, a substrate piece 10a (semiconductor chip built-in substrate piece) including the component built-in portion 10 is cut out from the first substrate 1000 by, for example, a UV (ultraviolet) laser.

  In the present embodiment, only the board piece 10a including the component built-in portion 10 that is determined to be a non-defective product by the above inspection (quality determination) is cut out. In addition, the method of cutting out the board | substrate piece 10a is not restricted to a laser, For example, a router etc. may be sufficient.

  In the manufacturing method of this embodiment, the board piece 10 a including the component built-in unit 10 is cut out from the first board 1000. By the cutting, the substrate piece 10a in which the thermal stress is released is obtained.

  While preparing the first substrate 1000, in step S21 of FIG. 1, the second substrate 2000 is prepared as shown in FIGS. 18A and 18B. In the present embodiment, the second substrate 2000 does not have a semiconductor chip. Further, the second substrate 2000 has no wiring. The second substrate 2000 is, for example, a frame dedicated substrate.

  The second substrate 2000 is composed of an insulating layer 400, for example. Hereinafter, one (Z1 side) of the front and back surfaces (two main surfaces) of the insulating layer 400 is referred to as a seventh surface F7, and the other (Z2 side) is referred to as an eighth surface F8.

  The shape of the insulating layer 400 is, for example, a substantially rectangular plate shape. However, the shape of the insulating layer 400 is not limited to this and is arbitrary.

  In the present embodiment, the insulating layer 400 is a rigid substrate.

  The insulating layer 400 is made of glass epoxy, for example. However, the present invention is not limited to this, and the material (core material and resin) of the insulating layer 400 is basically arbitrary. For example, instead of an epoxy resin, a polyester resin, a bismaleimide triazine resin (BT resin), an imide resin (polyimide), a phenol resin, an allylated phenylene ether resin (A-PPE resin), or the like may be used. The insulating layer 400 may not include a core material. The insulating layer 400 may not be a resin insulating layer. The insulating layer 400 may be composed of a plurality of layers made of different materials.

  Subsequently, in step S22 of FIG. 1, as shown in FIGS. 19A and 19B, the opening R10 is formed in the second substrate 2000 by, for example, a UV (ultraviolet) laser. Thereby, the second substrate 2000 having the opening R10 is obtained. The method for forming the opening R10 is not limited to the laser, and may be a router, for example.

  The second substrate 2000 has substantially the same thickness as the first substrate 1000, for example. Further, the opening R10 of the present embodiment is configured by a hole penetrating the second substrate 2000 (specifically, the insulating layer 400). The opening R10 has, for example, a shape (for example, a substantially rectangular parallelepiped) corresponding to the component built-in part 10 (strictly speaking, a board piece 10a described later).

  Subsequently, in step S31 of FIG. 1, as shown in FIG. 20A and FIG. 20B, the substrate piece 10a cut out by the process of step S13 of FIG. It arrange | positions in 2000 opening part R10. For example, as shown in FIG. 20B, a PET film 4001 is attached to one surface (for example, the eighth surface F8) of the second substrate 2000, and the other surface (for example, the seventh surface F7) is directed upward. It fixes on the metal plate which is not illustrated. Then, for example, using a chip mounter, the opening R10 and the substrate piece 10a are aligned with reference to the alignment mark M1 (FIG. 13) of the substrate piece 10a, for example, from the seventh surface F7 side, the second substrate. The substrate piece 10a is put into the 2000 opening R10. Since the substrate piece 10a is disposed in each of the openings R10 of the second substrate 2000, the ratio (semiconductor chip occupancy) of all the semiconductor chips (for example, the electronic component 200) in the electronic component built-in substrate is XY. The area ratio of the plane (the total area occupied by the semiconductor chips / the total area of the electronic component built-in substrate) is 10% or more.

  In the present embodiment, the semiconductor chip occupancy ratio (for example, Si occupancy ratio) of the first substrate 1000 prepared in step S <b> 11 of FIG. 1 has the substrate pieces 10 a disposed in all the openings R <b> 10 of the second substrate 2000. It is lower than the semiconductor chip occupation ratio (for example, Si occupation ratio) of the electronic component built-in substrate. When a necessary number of substrate pieces 10a cannot be prepared with one first substrate 1000, it is preferable to prepare a plurality of first substrates 1000 and cut out the substrate pieces 10a from each of them.

  In the manufacturing method of the present embodiment, the first substrate 1000 prepared in step S11 in FIG. 1 has a plurality of (for example, four) component built-in portions 10 and the arrangement of the substrate pieces 10a including the component built-in portions 10 (see FIG. Prior to step S31), a pass / fail judgment is made for each of the component built-in portions 10 (step S12 in FIG. 1). And in arrangement | positioning of the board | substrate piece 10a, only the board | substrate piece 10a containing the component built-in part 10 judged by the test | inspection of step S12 of FIG. 1 is arrange | positioned in opening R10. Thus, it is possible to increase the yield by inspecting the component built-in unit 10 in advance.

  In the present embodiment, the component built-in unit 10 is inspected prior to cutting out the board piece 10a (component built-in unit 10), and only the board piece 10a that is determined to be non-defective by the inspection is cut out. Not limited. For example, after all the board pieces 10a (component built-in part 10) included in the first board 1000 are cut out, each of the board pieces 10a is inspected, and only the board pieces 10a that are determined to be non-defective items are opened. You may make it arrange | position in part R10.

  In FIG. 21, the board | substrate piece 10a arrange | positioned in opening part R10 is expanded and shown. Hereinafter, a preferable example is shown about each dimension in FIG. The dimension d11 in the X direction of the gap between the second substrate 2000 and the substrate piece 10a in the opening R10 (the clearance in the X direction corresponds to twice the dimension d11) is 150 μm, and the second substrate in the opening R10. The dimension d12 in the Y direction of the gap between 2000 and the substrate piece 10a (the clearance in the Y direction corresponds to twice the dimension d12) is 150 μm.

  Subsequently, in step S32 of FIG. 1, as shown in FIGS. 22A and 22B, the substrate piece 10a disposed in the opening R10 is fixed to the second substrate 2000 by the adhesive 2000b. The adhesive 2000b is filled, for example, in the entire gap between the second substrate 2000 and the substrate piece 10a in the opening R10 (around the substrate piece 10a). However, the present invention is not limited to this, and the adhesive 2000b may be formed only in a part of the gap (see, for example, FIG. 25A or FIG. 25B).

  The adhesive 2000b may be a thermosetting adhesive or a non-thermosetting adhesive such as a photo-curing adhesive or a two-component curable adhesive. Further, for example, after bonding (temporarily fixing) with a non-thermosetting adhesive, the temporary fixing portion may be reinforced with, for example, a thermosetting adhesive.

  The adhesive 2000b has insulating properties, for example. However, the present invention is not limited to this, and the adhesive 2000b may have conductivity.

  A thermosetting adhesive usually has a stronger adhesive force than a photocurable adhesive. When the adhesive 2000b is a thermosetting adhesive, a high temperature treatment is required. However, in this embodiment, since the substrate piece 10a has been heat-treated in advance, a high temperature treatment is performed to cure the adhesive 2000b. However, the wiring board is not easily warped.

  By the manufacturing method described above (steps S11 to S32 in FIG. 1), the second substrate 2000, and the substrate piece 10a (component built-in portion 10) fixed with the adhesive 2000b in the opening R10 of the second substrate 2000, A wiring board 4000 (an electronic component built-in board) having the above is completed (see FIGS. 22A and 22B). The PET film 4001 is removed manually, for example, if necessary.

The manufacturing method of the electronic component built-in substrate according to the present embodiment is as follows.
Insulating layers 100, 101, and 102 (respectively resin insulating layers), and a component built-in portion 10 in which an electronic component 200 is disposed in a housing portion R1 formed in the resin insulating layers (specifically, the insulating layer 100), Preparing a first substrate 1000 having (step S11);
Preparing a second substrate 2000 having an opening R10 (steps S21 and S22);
Cutting out the board piece 10a including the component built-in portion 10 from the first board 1000 (step S13);
Placing and fixing the cut out substrate piece 10a in the opening R10 of the second substrate 2000 (steps S31 and S32);
including.

  The thermal stress is released by cutting the substrate piece 10a. Therefore, it is considered that stress is less likely to be generated in the wiring board 4000 (electronic component built-in substrate) to which the substrate piece 10a is fixed after cutting. As a result, it is considered that the warping of the wiring board 4000 is suppressed. Moreover, it is thought that the mounting reliability in the case of surface-mounting components on the wiring board 4000 is improved by making the wiring board 4000 difficult to warp.

  By heat-treating the first substrate 1000 in advance before cutting out the substrate piece 10a, stress is hardly generated in the wiring board 4000 (electronic component built-in substrate) due to heating after fixing the substrate piece 10a in the opening R10. It is considered to be. As a result, it is considered that the warping of the wiring board 4000 is suppressed. Moreover, it is thought that the mounting reliability in the case of surface-mounting components on the wiring board 4000 is improved by making the wiring board 4000 difficult to warp.

  In the method for manufacturing an electronic component built-in substrate according to the present embodiment, the second substrate 2000 does not have an electronic component. One reason for the warpage of the substrate is thought to be the large difference between the thermal expansion coefficient of the electronic component incorporated in the resin insulation layer and the thermal expansion coefficient of the resin insulation layer. If there are no parts, warping caused by electronic parts does not occur. Therefore, it is considered that the warpage of the second substrate 2000 and, consequently, the warpage of the wiring board 4000 (substrate with built-in electronic components) is suppressed because the second substrate 2000 has no electronic component.

  As shown in FIG. 23, the wiring board 4000 (substrate with built-in electronic components) of the present embodiment manufactured by the above manufacturing method includes the second substrate 2000 having a plurality of openings R10 and the second substrate 2000. A plurality of substrate pieces 10a (semiconductor chip built-in substrate pieces) manufactured separately and fixed to each of the openings R10.

  In this embodiment, the semiconductor chip occupation ratio of the wiring board 4000 (electronic component built-in substrate) is 10% or more in terms of area ratio.

  FIG. 24 shows the relationship between the semiconductor chip occupancy ratio and the warpage amount of an electronic component built-in substrate manufactured using one substrate without cutting out the substrate piece and transferring it to another substrate. In FIG. 24, data W1 indicates the amount of warpage of the electronic component built-in substrate with a semiconductor chip occupancy rate of 4.2%, data W2 indicates the amount of warpage of the electronic component built-in substrate with a semiconductor chip occupancy rate of 9.4%, Data W3 indicates the warpage amount of the electronic component built-in substrate having the semiconductor chip occupation ratio of 16.6%.

  As shown in FIG. 24, the warp amount of the electronic component built-in substrate increases as the semiconductor chip occupation ratio of the electronic component built-in substrate increases. In particular, when the semiconductor chip occupancy ratio of the electronic component built-in substrate is 10% or more in terms of area ratio, warpage increases and it becomes difficult to ensure sufficient mounting reliability. In this regard, in the manufacturing method of the present embodiment, after the component built-in portion 10 is formed on the first substrate 1000 whose semiconductor chip occupancy is less than 10% in area ratio, the substrate piece 10a including the component built-in portion 10 is cut out. Then, by placing and fixing the substrate piece 10a in the opening R10 of another substrate (second substrate 2000), the electronic component built-in substrate (wiring board) whose semiconductor chip occupancy is 10% or more by area ratio 4000). For this reason, it is possible to manufacture an electronic component built-in substrate having a high semiconductor chip occupancy rate and easily warped, with a high yield.

  The present invention is not limited to the above embodiment. For example, the present invention can be modified as follows.

  For example, as shown in FIG. 25A or FIG. 25B, the adhesive 2000b may be formed only in a predetermined portion of the gap between the second substrate 2000 and the substrate piece 10a in the opening R10. In the example of FIG. 25A, the adhesive 2000b is formed on the opposite sides of the substrate piece 10a, and in the example of FIG. 25B, the adhesive 2000b is formed at the four corners of the substrate piece 10a.

  The method of fixing the substrate piece 10a is not limited to the adhesive 2000b. For example, the clearance (for example, the dimensions d11 and d12 shown in FIG. 21) of the opening R10 may be set to approximately 0 μm, and the substrate piece 10a may be fixed by a frictional force. In particular, if each of the second substrate 2000 and the substrate piece 10a is a rigid substrate, it can be easily fixed by a frictional force.

  For example, as shown in FIG. 26, the substrate piece 10a has a claw portion 10b (convex portion), and the opening portion R10 of the second substrate 2000 can engage with the claw portion 10b (recess portion). You may have. In this case, the board | substrate piece 10a can be fixed in opening R10 by couple | bonding the nail | claw part 10b and the nail | claw receiving part 10c. The nail | claw part 10b and the nail | claw receiving part 10c may be combined with a frictional force, and may be combined with an adhesive agent. Further, if the claw portion 10b is partially thinned so that it can be easily cut with a weak force, the substrate piece 10a can be easily separated from the second substrate 2000.

  The number of the component built-in part 10, the opening R10, and the electronic component 200 is arbitrary. Further, one component built-in unit 10 may incorporate a plurality of (for example, two) electronic components. As shown in FIG. 27, a plurality of (for example, two) substrate pieces 10a may be accommodated in one opening R10 formed in the second substrate 2000.

  The planar shape (XY plane) of the opening R10, the substrate piece 10a, and the through hole 300a, the alignment mark M1, and the via hole of each layer in the first substrate 1000 is arbitrary. These planar shapes may be perfect circles as shown in FIG. 28A, for example, and may be regular squares as shown in FIG. 28B, for example. These planar shapes may be other regular polygons such as regular hexagons and regular octagons. In addition, the shape of the polygonal corner is arbitrary, and may be, for example, a right angle, an acute angle, an obtuse angle, or rounded. However, in order to prevent concentration of thermal stress, it is preferable that the corners are rounded.

  The planar shape may be an ellipse, a rectangle, a triangle, or the like. Furthermore, as shown in FIG. 28C or FIG. 28D, a shape that spreads radially from the center, such as a cross shape or a regular polygon star shape, may be the planar shape.

  The cross-sectional shapes (XZ plane, YZ plane) of the through holes and via holes in each layer in the first substrate 1000 are also arbitrary.

  The structure of the first substrate 1000 (particularly the component built-in portion 10) is not limited to that shown in FIG. For example, the component built-in portion may have a structure as shown in FIG. 29 (cross-sectional view corresponding to FIG. 3).

  In the example of FIG. 29, the insulating layer 100 (core substrate) is composed of a plurality of insulating layers (for example, insulating layers 100a and 100b). Each of the insulating layers 100a and 100b is made of, for example, a cured prepreg. Each of the conductor layers 110 and 120 is, for example, three layers in which a copper foil, a copper electroless plating (chemical copper), and a copper electrolytic plating (electrocopper) are laminated in this order from the lower layer to the upper layer. Consists of structure. Each of the conductor layers 110 and 120 can be formed by, for example, a subtractive method.

  In the example of FIG. 29, the through-hole conductor 300b is a conformal conductor. In the through hole 300a, for example, an insulator 300d is filled inside the through hole conductor 300b. The insulator 300d is made of resin that has flowed out of the insulating layers 101 and 102 by pressing, for example.

  In the example of FIG. 29, the opening R10 is filled with the adhesive 101b in addition to the insulator 101a. The insulator 101a is made of, for example, a resin that has flowed out of the insulating layers 100a and 100b by pressing. The adhesive 101b is used for fixing the electronic component 200 on the carrier, for example.

  In the example of FIG. 29, conductor patterns 302a and 302b are formed on the adhesive 101b. The conductor patterns 302a and 302b are, for example, the same layer as the conductor layer 302 (substantially the same Z coordinate). The conductor patterns 302a and 302b are electrically connected to the electrodes 210 and 220 of the electronic component 200 via the via conductors 301b formed in the adhesive 101b, and the via conductors 323b formed in the insulating layer 102 are respectively connected. And is electrically connected to the conductor layer 120.

  The opening R10 is not limited to a hole that penetrates the second substrate 2000, and may be a hole that does not penetrate the second substrate 2000, for example, as shown in FIG. Further, the opening R10 may be an opening such as a groove, a notch, or a cut.

  The wall surface of the opening R10 is not limited to one that is substantially orthogonal to the main surface, and may be a tapered surface, for example, as shown in FIG. 31A. In this case, it becomes easy to inject the adhesive 2000b from the side with the large opening area of the opening R10 (for example, the Z1 side). Further, for example, as shown in FIG. 31B, the side surface of the substrate piece 10a may be a tapered surface corresponding to the wall surface of the opening R10.

  It is not essential that the thickness of the first substrate 1000 (and thus the component built-in part 10) and the thickness of the second substrate 2000 are substantially the same. The first substrate 1000 may be thinner than the second substrate 2000, or the first substrate 1000 may be thicker than the second substrate 2000.

  With respect to other points as well, the configuration of the wiring board 4000 (FIGS. 22A and 22B), in particular, the type, performance, dimensions, material, shape, number of layers, or arrangement of the components do not depart from the spirit of the present invention. The range can be arbitrarily changed.

  The first substrate 1000 may have a solder resist. Further, the solder resist may be selectively formed only in the component built-in portion 10.

  The seed layer for electrolytic plating is not limited to the electroless plating film (chemical copper), but is optional. For example, instead of chemical copper, a sputtered film or the like may be used as the seed layer.

  The first substrate 1000 may be a metal core substrate. For example, a metal plate may be incorporated in the insulating layer 100 (core substrate) of the first substrate 1000 for the purpose of improving strength or heat dissipation.

  The number of build-up layers of the first substrate 1000 is arbitrary. Further, the number of buildup layers may be different between the front and back of the insulating layer 100 (core substrate) of the first substrate 1000. For example, the first substrate 1000 may be a single-sided wiring board having a conductor (conductor layer) on only one of the front and back surfaces of the core. However, in order to relieve stress, it is considered preferable to increase the symmetry of the front and back by making the number of buildup layers the same on the front and back of the core substrate.

  The structure of each conductor layer in the first substrate 1000 is arbitrary. For example, even in a three-layer structure of a metal foil, an electroless plating film, and an electrolytic plating film, the metal foil or the electroless plating film and the electrolytic plating film Even if it has a two-layer structure, a two-layer structure of a metal foil and an electroless plating film or an electrolytic plating film may be used. Moreover, the structure of each filled conductor is also arbitrary. For example, it may be a two-layer structure of a seed layer (for example, an electroless plating film) and electrolytic plating, or a structure consisting of only electroless plating.

  Each via conductor in the first substrate 1000 is not limited to a filled conductor, and may be a conformal conductor.

  The second substrate 2000 may be a build-up printed wiring board that does not incorporate electronic components. Further, the second substrate 2000 may incorporate electronic components. The second substrate 2000 may be a metal plate.

  The contents and order of the steps of the above embodiment can be arbitrarily changed without departing from the spirit of the present invention. Moreover, you may omit the process which is not required according to a use etc.

  As shown in FIG. 32, preparing a second substrate having an opening includes preparing a second substrate (step S21 in FIG. 32) and forming an opening in the second substrate (in FIG. 32). Step S22) and, after forming the opening, cutting off the end of the second substrate to reduce warpage of the second substrate (step S23 in FIG. 32) may be included.

  Specifically, in step S21 of FIG. 32, for example, as shown in FIGS. 33A and 33B, the second substrate 2000 including, for example, an insulating layer 400 and a conductor pattern 2000a formed on the insulating layer 400. Prepare.

  The conductor pattern 2000a is formed on the seventh surface F7 of the insulating layer 400, for example. The shape of the conductor pattern 2000a is, for example, a ring shape conforming to the outer shape of the insulating layer 400, and the conductor pattern 2000a is formed on the surface of the edge portion (for example, the entire circumference) of the insulating layer 400, for example. The conductor pattern 2000a may be formed on only one of the front and back surfaces, or may be formed on both the front and back surfaces. The conductor pattern 2000a is made of, for example, copper foil. However, the material is not limited to this, and the material of the conductor pattern 2000a is arbitrary.

  Subsequently, in step S22 of FIG. 32, as shown in FIG. 34, an opening R10 is formed in the second substrate 2000 by, for example, a UV (ultraviolet) laser. Thereby, the second substrate 2000 having the opening R10 is obtained.

  Subsequently, in step S23 of FIG. 32, in order to reduce warpage of the second substrate 2000, an end portion (specifically, a portion R11 in FIG. 34) of the second substrate 2000 is cut by, for example, an ultrasonic cutter. As a result, for example, as shown in FIG. 35, the edges (conductor pattern 2000 a) of the second substrate 2000 remain only at the four corners of the second substrate 2000.

  In addition, the cutting aspect of an edge part is arbitrary. For example, you may leave the edge part (conductor pattern 2000a) of the 2nd board | substrate 2000 in two opposing sides.

  In the manufacturing method of this embodiment, the conductor pattern 2000a is formed on the edge of the second substrate 2000 prepared in step S21 of FIG. 32, and after the formation of the opening R10 (step S22 of FIG. 32) The edge part (for example, part R11 shown by FIG. 34) of the 2nd board | substrate 2000 including an edge part is cut off. After the opening R10 is formed, the warp of the second substrate 2000 can be easily reduced by separating the edge conductor pattern 2000a from the second substrate 2000. If necessary, the second substrate 2000 may be flattened by pressing or the like after the opening R10 is formed.

  Also, a ring-shaped conductor pattern that conforms to the outer shape of the first substrate 1000 may be formed on the surface of the edge portion (for example, the entire circumference) of the first substrate 1000 prepared in step S11 of FIG. This conductor pattern may be formed on only one of the front and back surfaces, or may be formed on both the front and back surfaces.

  The edge conductor pattern (reinforcing pattern) may be formed on the outermost conductor layer or on the inner conductor layer.

  For example, if not necessary, the inspection (for example, step S12 in FIG. 1) or the like may be omitted.

  The heat treatment for curing the insulating layers 101 and 102 to the C stage may be performed, for example, after inspection (step S12 in FIG. 1) and before cutting out the substrate piece 10a (step S13 in FIG. 1).

  For example, in the manufacturing process of the first substrate 1000, the insulating layers 101 and 102 are only cured to the B stage by heat treatment, and after the substrate piece 10a is cut out, the insulating layers 101 and 102 are made to the C stage by heat treatment. It may be cured.

  The formation method of each conductor layer in the 1st board | substrate 1000 is arbitrary. For example, any one of a panel plating method, a pattern plating method, a full additive method, a semi-additive (SAP) method, a subtractive method, a transfer method, and a tenting method, or a combination of any two or more thereof. A conductor layer may be formed. Moreover, the formation method of each insulating layer (interlayer insulating layer) in the 1st board | substrate 1000 is also arbitrary.

  The processing method of the 1st board | substrate 1000 or the 2nd board | substrate 2000 is arbitrary. The processing method of each substrate may be laser, wet or dry etching. In the case of processing by etching, it is preferable to protect a portion that is not desired to be removed in advance with a resist or the like.

  The above embodiment and its modifications can be arbitrarily combined. In addition, the above-described methods shown as the method for manufacturing the first substrate 1000 may be applied to the manufacture of the second substrate 2000.

  The embodiment of the present invention has been described above. However, various modifications and combinations required for design reasons and other factors are not limited to the invention described in the “claims” or the “mode for carrying out the invention”. It should be understood that it is included in the scope of the invention corresponding to the specific examples described in the above.

DESCRIPTION OF SYMBOLS 10 Component built-in part 10a Substrate piece 10b Claw part 10c Claw receiving part 100 Insulating layer 100a Insulating layer 100b Insulating layer 101 Insulating layer 101a Insulator 101b Adhesive 102 Insulating layer 110, 120 Conductive layer 110a Conductive pattern 110b Protrusion part 110c Gap 200 Electron Component 210, 220 Electrode 300a Through hole 300b Through hole conductor 300c Constricted part 300d Insulator 301, 302 Conductor layer 301b Via conductor 302a, 302b Conductor pattern 311a, 312a, 322a Via hole 311b, 312b, 322b, 323b Via conductor 400 Insulating layer 1000 First board 2000 Second board 2000a Conductor pattern 2000b Adhesive 3000 Double-sided copper-clad laminate 4000 Wiring board 3001, 3002 Copper foil 3003, 3004 3005 Plating 3006 carriers 3007 and 3008 the electroless plating film 3009,3010 resist 3009a, 3010a openings 4000 wiring board (electronic component-embedded substrate)
4001 PET film M1 Alignment mark R1 Housing part R10 Opening part

Claims (17)

Preparing a first substrate having a resin insulation layer and a component built-in part in which an electronic component is arranged in a housing part formed in the resin insulation layer;
Providing a second substrate having an opening;
Cutting out a board piece including the component built-in part from the first board;
Arranging and fixing the cut out substrate piece in the opening of the second substrate;
including,
A method for manufacturing an electronic component-embedded substrate, comprising: The semiconductor chip occupancy of the prepared first substrate is lower than the semiconductor chip occupancy of the electronic component built-in substrate in which the substrate pieces are arranged in all the openings of the second substrate.
The manufacturing method of the electronic component built-in substrate according to claim 1. The semiconductor chip occupancy of the prepared first substrate is less than 10% in area ratio,
The semiconductor chip occupation ratio of the electronic component built-in substrate is 10% or more in terms of area ratio.
The method of manufacturing an electronic component built-in substrate according to claim 2. The prepared second substrate does not have a semiconductor chip,
The method for manufacturing a substrate with built-in electronic components according to claim 1, wherein In the preparation of the first substrate, the resin insulating layer is cured to a B stage or a C stage.
The manufacturing method of the electronic component built-in substrate according to any one of claims 1 to 4. In the preparation of the first substrate, the resin insulating layer is cured to the C stage.
The method for manufacturing an electronic component built-in substrate according to claim 5. Forming an alignment mark indicating a position of the component built-in part on the first substrate;
The method for manufacturing an electronic component built-in substrate according to any one of claims 1 to 6. Preparing a second substrate having the opening,
Preparing a second substrate;
Forming an opening in the second substrate;
Cutting off the end of the second substrate to reduce warpage of the second substrate after forming the opening;
including,
The method for manufacturing an electronic component built-in substrate according to any one of claims 1 to 7, A conductor pattern is formed on the edge of the second substrate,
The edge of the second substrate to be cut off includes the edge where the conductor pattern is formed,
The method for manufacturing a substrate with built-in electronic components according to claim 8. The opening is a hole penetrating the second substrate.
The method for manufacturing an electronic component built-in substrate according to any one of claims 1 to 9, The electronic component is a semiconductor chip.
The method for manufacturing an electronic component built-in substrate according to any one of claims 1 to 10, The first substrate is a rigid wiring board;
The method for manufacturing an electronic component built-in substrate according to any one of claims 1 to 11, The first substrate is a build-up printed wiring board;
The method for manufacturing an electronic component built-in substrate according to any one of claims 1 to 12, Fixing the substrate piece disposed in the opening with an adhesive;
The method for manufacturing an electronic component-embedded substrate according to any one of claims 1 to 13, The first substrate has a plurality of the component built-in parts,
Prior to the placement of the board piece, including performing a pass / fail judgment for each of the component built-in parts,
In the arrangement of the board piece, only the board piece including the component built-in part determined to be non-defective by the quality determination is arranged in the opening.
The method for manufacturing an electronic component built-in substrate according to any one of claims 1 to 14, A substrate having a plurality of openings formed thereon;
A plurality of semiconductor chip built-in substrate pieces manufactured separately from the substrate and fixed to each of the plurality of openings,
Having
An electronic component built-in board characterized by the above. The semiconductor chip occupation ratio of the electronic component built-in substrate is 10% or more by area ratio.
The electronic component built-in substrate according to claim 16.

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