JP2009224732A - Manufacturing method of multiple patterning circuit board, and intermediate product of multiple patterning circuit board - Google Patents

Manufacturing method of multiple patterning circuit board, and intermediate product of multiple patterning circuit board Download PDF

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JP2009224732A
JP2009224732A JP2008070490A JP2008070490A JP2009224732A JP 2009224732 A JP2009224732 A JP 2009224732A JP 2008070490 A JP2008070490 A JP 2008070490A JP 2008070490 A JP2008070490 A JP 2008070490A JP 2009224732 A JP2009224732 A JP 2009224732A
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wiring board
product
holes
region
wiring
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JP4975664B2 (en
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Motonobu Kurahashi
元信 倉橋
Takuya Hanto
琢也 半戸
Hajime Saiki
一 斉木
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a multiple patterning circuit board which can uniformly vacuum-suck a mask for solder ball alignment and can improve the yield of ball loading. <P>SOLUTION: The multiple patterning circuit board 100 is a board provided with a product region wherein a plurality of parts to be the product of a circuit board 10 are arrayed in a matrix along a plane direction and not provided with a waste selvage region around the product region. The multiple patterning circuit board 100 includes a buildup layer having a structure for which a resin insulating layer and a conductor layer are laminated and also having a plurality of terminal pads to which an IC chip can be connected. The multiple patterning circuit board 100 is provided with a plurality of through-holes 105 for vacuum-sucking the mask for solder ball alignment in the state of being dispersed to be a uniform density. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体素子が接続可能な複数の外部端子を有する配線基板を平面方向に沿って縦横に複数配列してなる多数個取り配線基板において、前記複数の外部端子上にはんだボールを搭載する多数個取り配線基板の製造方法、及び多数個取り配線基板の中間製品に関するものである。   According to the present invention, a solder ball is mounted on a plurality of external terminals in a multi-piece wiring board in which a plurality of wiring boards having a plurality of external terminals to which a semiconductor element can be connected are arranged vertically and horizontally along a plane direction. The present invention relates to a method of manufacturing a multi-cavity wiring board and an intermediate product of the multi-cavity wiring board.

コンピュータのマイクロプロセッサ等として使用される半導体集積回路素子(ICチップ)は、近年ますます高速化、高機能化しており、これに付随して端子数が増え、端子間ピッチも狭くなる傾向にある。一般的にICチップの底面には多数の端子が密集してアレイ状に配置されており、このような端子群はマザーボード側の端子群に対してフリップチップの形態で接続される。ただし、ICチップ側の端子群とマザーボード側の端子群とでは端子間ピッチに大きな差があることから、ICチップをマザーボード上に直接的に接続することは困難である。そのため、通常はICチップをICチップ搭載用配線基板上に搭載してなるパッケージを作製し、そのパッケージをマザーボード上に搭載するという手法が採用される。   In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard.

この種のパッケージを構成するICチップ搭載用配線基板においては、コア基板の表面及び裏面に、樹脂層間絶縁層と導体層とを交互に積層したビルドアップ層が形成される。そして、配線基板における一方のビルドアップ層にICチップを接続するための端子パッドがアレイ状に形成され、他方のビルドアップ層にはマザーボードに接続するための端子パッドがアレイ状に形成されている。   In an IC chip mounting wiring board that constitutes this type of package, build-up layers in which resin interlayer insulating layers and conductor layers are alternately laminated are formed on the front and back surfaces of a core substrate. Terminal pads for connecting the IC chip are formed in an array on one buildup layer of the wiring board, and terminal pads for connecting to the motherboard are formed in an array on the other buildup layer. .

ICチップ搭載用配線基板は、中間製品の段階では、複数個のものが縦横に一体化された大判(多数個取り配線基板)の状態で製造され、ビルドアップ層を形成するための導電層形成工程や各種めっき工程等は全ての中間製品について一括して行われる。図9に示されるように、多数個取り配線基板200には、配線基板の製品となるべき部分が縦横に複数配置された製品領域210と、製品領域210の周囲に設けられた捨て耳領域211(製品にならない領域)とが存在している。この多数個取り配線基板200を分割し、配線基板の個片を複数個同時に得ることにより、配線基板を効率よく製造している。   At the intermediate product stage, the IC chip mounting wiring board is manufactured in a large format (multiple wiring board) in which multiple products are integrated vertically and horizontally, and a conductive layer is formed to form a build-up layer. Processes and various plating processes are performed collectively for all intermediate products. As shown in FIG. 9, the multi-cavity wiring board 200 includes a product area 210 in which a plurality of parts to be products of the wiring board are arranged vertically and horizontally, and a waste ear area 211 provided around the product area 210. (Areas that do not become products). By dividing the multi-piece wiring board 200 and simultaneously obtaining a plurality of pieces of the wiring board, the wiring board is efficiently manufactured.

また一般に、ICチップ搭載用配線基板は、フリップチップ接続面にある各端子パッド上にはんだバンプが設けられた状態で出荷される。より詳しくは、多数個取り配線基板の状態でビルドアップ層を形成した後、その配線基板にボール搭載工程が実施される。このボール搭載工程では、はんだボール搭載装置を用いて、多数個取り配線基板の上面にはんだボール整列用マスクを配置し、その整列用マスクに設けられた各透孔にはんだボールを収納することにより、各端子パッド上にはんだボールが搭載される。その後、はんだボールを所定の温度に加熱してリフローすることにより、各端子パッド上にはんだバンプが形成される。   In general, the IC chip mounting wiring board is shipped with solder bumps provided on the terminal pads on the flip chip connection surface. More specifically, after a buildup layer is formed in the state of a multi-piece wiring board, a ball mounting process is performed on the wiring board. In this ball mounting process, by using a solder ball mounting device, a solder ball alignment mask is arranged on the upper surface of the multi-piece wiring substrate, and the solder balls are stored in the respective through holes provided in the alignment mask. A solder ball is mounted on each terminal pad. Thereafter, the solder balls are heated to a predetermined temperature and reflowed to form solder bumps on the terminal pads.

因みに、特許文献1には、BGA(ボール・グリッド・アレイ)タイプのチップの電極にはんだボールを搭載するためのはんだボール搭載装置が開示されている。
特開2001−358450号公報
Incidentally, Patent Document 1 discloses a solder ball mounting apparatus for mounting a solder ball on an electrode of a BGA (Ball Grid Array) type chip.
JP 2001-358450 A

ところで、図9に示すように、多数個取り配線基板200の捨て耳領域211には、ビルドアップ層の形成工程等で使用する貫通孔215(露光用の位置決め孔、基板固定用のガイド孔など)が形成されている。そして、はんだボール搭載装置において、はんだボール整列用マスクは、多数個取り配線基板200の捨て耳領域211に設けられた各貫通孔215を介して真空吸着されることにより、配線基板200の上面に固定される。なお、多数個取り配線基板200の捨て耳領域211には、ビルドアップ層の形成用の貫通孔215以外に、真空吸着専用の貫通孔が設けられる場合もある。   By the way, as shown in FIG. 9, through-holes 215 (positioning holes for exposure, guide holes for fixing the substrate, etc.) used in the build-up layer forming process etc. ) Is formed. In the solder ball mounting apparatus, the solder ball alignment mask is vacuum-sucked through the through-holes 215 provided in the throwing-off region 211 of the multi-piece wiring board 200, so that the solder ball alignment mask is placed on the upper surface of the wiring board 200. Fixed. It should be noted that in addition to the through hole 215 for forming the build-up layer, there may be a case where a through hole dedicated for vacuum suction is provided in the discard ear region 211 of the multi-cavity wiring board 200.

ところが、前記多数個取り配線基板200において、ビルドアップ層が形成される製品領域210と、その周囲の捨て耳領域211とでは厚さが異なり段差がある。また、捨て耳領域211に形成されている各貫通孔215は、異なる用途で使用される貫通孔であるため、それらサイズは均一でなく、形成される位置もバラバラで等間隔には形成されていない。このため、はんだボール整列用マスク全体を均等に真空吸着することができない。また、製品領域210には真空吸着のための貫通孔が形成されていないため、はんだボール整列用マスクが部分的に浮いてしまう。その結果、各端子パッド上にはんだボールを適切に搭載することがでず、ボール搭載の歩留まりが悪化する。   However, in the multi-cavity wiring board 200, the product area 210 where the build-up layer is formed and the surrounding edge area 211 around the product area 210 are different in thickness and have a level difference. Moreover, since each through-hole 215 formed in the disposal ear region 211 is a through-hole used for different applications, the sizes thereof are not uniform, and the positions to be formed are different and formed at equal intervals. Absent. For this reason, the entire solder ball alignment mask cannot be vacuum-sucked evenly. Further, since the through hole for vacuum suction is not formed in the product region 210, the solder ball alignment mask partially floats. As a result, the solder ball cannot be properly mounted on each terminal pad, and the yield of mounting the ball is deteriorated.

本発明は上記の課題に鑑みてなされたものであり、その目的は、基板上に配置されるはんだボール整列用マスクを均一に真空吸着することができ、ボール搭載の歩留まりを向上することができる多数個取り配線基板の製造方法、及び多数個取り配線基板の中間製品を提供することにある。   The present invention has been made in view of the above-described problems, and an object of the present invention is to uniformly vacuum-suck a solder ball alignment mask disposed on a substrate and to improve the yield of ball mounting. It is an object of the present invention to provide a manufacturing method of a multi-cavity wiring board and an intermediate product of the multi-cavity wiring board.

そして上記課題を解決するための手段(手段1)としては、製品領域とその製品領域の周囲に設けられる捨て耳領域とを備え、前記製品領域内に、配線基板が平面方向に沿って縦横に複数配列された多数個取り配線基板の製造方法において、前記捨て耳領域に設けられた位置決め用孔を利用して、層間絶縁層及び導体層を積層した構造を有しかつ半導体素子が接続可能な複数の外部端子を有する配線積層部を前記製品領域に形成する配線積層部形成工程と、前記製品領域内において均等な密度となるように複数の貫通孔を分散させた状態で設ける貫通孔配設工程と、前記捨て耳領域を切断除去して前記製品領域のみとする切断除去工程と、前記配線積層部形成工程、前記貫通孔配設工程及び前記切断除去工程の後、前記多数個取り配線基板をはんだボール搭載装置にセットし、この状態で前記複数の外部端子に対応した位置に複数の透孔を有するはんだボール整列用マスクを前記複数の貫通孔を介して真空吸着することにより、前記多数個取り配線基板上に前記マスクを固定し、前記複数の外部端子上にはんだボールを搭載するボール搭載工程とを含むことを特徴とする多数個取り配線基板の製造方法がある。   As means (means 1) for solving the above-mentioned problem, a product area and a throw-away area provided around the product area are provided, and the wiring board is vertically and horizontally along the plane direction in the product area. In a method for manufacturing a plurality of multi-cavity wiring boards arranged in plural, the semiconductor device has a structure in which an interlayer insulating layer and a conductor layer are laminated using a positioning hole provided in the abandoned lug region, and a semiconductor element can be connected A wiring laminated portion forming step for forming a wiring laminated portion having a plurality of external terminals in the product region, and a through hole arrangement in which a plurality of through holes are dispersed so as to have a uniform density in the product region After the step, the cutting and removing step of cutting and removing the abandoned ear region to make only the product region, the wiring stacking portion forming step, the through hole arranging step and the cutting and removing step, the multi-cavity wiring board The In this state, the solder ball alignment mask having a plurality of through-holes at positions corresponding to the plurality of external terminals is vacuum-sucked through the plurality of through-holes. There is a method for manufacturing a multi-piece wiring board, comprising: a ball mounting step of fixing the mask on a single-piece wiring board and mounting solder balls on the plurality of external terminals.

従って、手段1の多数個取り配線基板の製造方法によると、配線積層部形成工程において、多数個取り配線基板の製品領域に配線積層部が形成された後、貫通孔配設工程において、その製品領域内に均等な密度となるように複数の貫通孔が分散された状態で設けられる。その後、切断除去工程において、製品領域の周囲に設けられる捨て耳領域が切断除去されることにより、製品領域のみの配線基板とされる。この配線基板は、従来の配線基板のように製品領域と捨て耳領域との厚さに起因する段差がなく、ほぼ均一な厚さとなる。そして、ボール搭載工程では、製品領域のみの多数個取り配線基板がはんだボール搭載装置にセットされ、均等な密度となるように設けられた複数の貫通孔を介してはんだボール整列用マスクが真空吸着される。このようにすれば、はんだボール整列用マスク全体を均等に真空吸着して確実に固定することができ、その整列用マスクが部分的に浮いてしまうといった問題を回避することができる。その結果、複数の外部端子上にはんだボールを確実に整列させて搭載することができ、ボール搭載の歩留まりを向上させることができる。また、製品領域のみの配線基板がボール搭載装置にセットされているため、捨て耳領域がある従来の配線基板と比較して基板サイズが小さくなり、はんだボール搭載装置の小型化が可能となる。   Therefore, according to the manufacturing method of the multi-cavity wiring board of the means 1, in the wiring laminated portion forming step, after the wiring laminated portion is formed in the product area of the multi-cavity wiring substrate, the product A plurality of through-holes are provided in a dispersed state so as to have a uniform density in the region. Thereafter, in the cutting / removing step, the discarded lug area provided around the product area is cut and removed, so that the wiring board of only the product area is obtained. This wiring board does not have a step due to the thickness between the product area and the lapping area unlike the conventional wiring board, and has a substantially uniform thickness. In the ball mounting process, a multi-piece wiring board of only the product area is set in the solder ball mounting device, and the solder ball alignment mask is vacuum-sucked through a plurality of through holes provided to have a uniform density. Is done. In this way, the entire solder ball alignment mask can be uniformly vacuum-sucked and securely fixed, and the problem that the alignment mask partially floats can be avoided. As a result, the solder balls can be reliably aligned and mounted on the plurality of external terminals, and the yield of ball mounting can be improved. In addition, since the wiring board only for the product area is set in the ball mounting apparatus, the board size is reduced as compared with a conventional wiring board having a throw-away area, and the solder ball mounting apparatus can be downsized.

前記複数の貫通孔は、前記製品領域を切断して複数の配線基板にするときの切断予定線上に設けられることが好ましい。多数個取り配線基板の切断予定線は、製品領域における配線積層部の導体層が形成されていない位置であって等間隔に設定されている。このため、切断予定線上に貫通孔を形成することにより、配線基板の機能を損ねることなく、かつ、均等な密度となるように複数の貫通孔を分散させることができる。   The plurality of through holes are preferably provided on a planned cutting line when the product region is cut into a plurality of wiring boards. The cutting lines of the multi-cavity wiring board are set at equal intervals at positions where the conductor layer of the wiring laminated portion is not formed in the product region. For this reason, by forming the through holes on the planned cutting line, it is possible to disperse the plurality of through holes so as to obtain a uniform density without impairing the function of the wiring board.

前記複数の貫通孔は、前記製品領域の外形線上にも設けられることが好ましい。このようにすれば、製品領域を分割して個々の配線基板にしたとき、各配線基板を全て同一形状とすることができる。   It is preferable that the plurality of through holes are also provided on the outline of the product region. In this way, when the product area is divided into individual wiring boards, all the wiring boards can have the same shape.

前記複数の貫通孔は、前記製品領域を切断して複数の配線基板にするときの切断予定線同士が交差する点上に設けられていてもよい。このように、切断予定線同士の交差点に貫通孔を形成することにより、配線基板の機能を損ねることなく、かつ、均等な密度となるように複数の貫通孔を分散させることができる。   The plurality of through holes may be provided on points where the planned cutting lines intersect when the product region is cut into a plurality of wiring boards. Thus, by forming the through holes at the intersections between the planned cutting lines, it is possible to disperse the plurality of through holes so as to obtain a uniform density without impairing the function of the wiring board.

前記複数の貫通孔は、前期捨て耳領域の位置決め用孔よりも径が小さいことが好ましい。このように貫通孔の径を小さくすれば、製品領域においてより多くの貫通孔を分散して設けることが可能となり、はんだボール整列用マスクをより均等に真空吸着することができる。   The plurality of through-holes preferably have a smaller diameter than the positioning holes in the abandoned ear region. By reducing the diameter of the through holes in this way, it is possible to disperse and provide more through holes in the product region, and the solder ball alignment mask can be vacuum-sucked more evenly.

前記複数の貫通孔は、前記切断工程を経て半円状の凹部とすることにより、前記配線基板を位置決めするための部品位置決め用凹部として利用されることが好ましい。このようにすれば、配線基板において、部品位置決め用凹部を別途設ける必要がなくなり、配線基板の製造コストを抑えることができる。   It is preferable that the plurality of through holes are used as component positioning recesses for positioning the wiring board by forming a semicircular recess through the cutting step. In this way, it is not necessary to separately provide a component positioning recess in the wiring board, and the manufacturing cost of the wiring board can be reduced.

前記配線基板は、4つの辺を有する矩形状であり、対向する2つの辺に前記部品位置決め用凹部を有していることが好ましい。この場合、2つの部品位置決め用凹部を利用して配線基板の位置決めを確実に行うことができる。   The wiring board has a rectangular shape having four sides, and preferably has the component positioning recesses on two opposing sides. In this case, the wiring board can be reliably positioned using the two component positioning recesses.

また、上記課題を解決するための別の手段(手段2)としては、配線基板の製品となるべき部分が平面方向に沿って縦横に複数配列された製品領域を有する一方、その製品領域の周囲に捨て耳領域を有しない多数個取り配線基板の中間製品であって、層間絶縁層及び導体層を積層した構造を有しかつ半導体素子が接続可能な複数の外部端子を有する配線積層部を備え、はんだボール整列用マスクを真空吸着するための複数の貫通孔が、前記製品領域内において均等な密度となるように分散させた状態で設けられていることを特徴とする多数個取り配線基板の中間製品がある。   Further, as another means (means 2) for solving the above-described problem, a part of the wiring board to be a product has a product area in which a plurality of parts are arranged vertically and horizontally along the plane direction, while the periphery of the product area An intermediate product of a multi-cavity wiring board that does not have an abandoned ear region, and has a structure in which an interlayer insulating layer and a conductor layer are laminated, and a wiring laminated portion having a plurality of external terminals to which a semiconductor element can be connected A plurality of through-holes for vacuum-adsorbing the solder ball alignment mask are provided in a state of being distributed so as to have a uniform density in the product region. There are intermediate products.

従って、手段2の多数個取り配線基板の中間製品によると、製品領域の周囲に捨て耳領域を有していないので、従来の配線基板のように製品領域と捨て耳領域との厚さに起因する段差がなくなり、ほぼ均一な厚さとなる。また、製品領域内において均等な密度となるように分散させた状態で複数の貫通孔が設けられているので、各貫通孔を介してはんだボール整列用マスク全体を均等に真空吸着することができる。よって、多数個取り配線基板の中間製品を用いれば、その上面にはんだボール整列用マスクを確実に固定することができ、はんだボール整列用マスクが部分的に浮いてしまうといった問題を回避することができる。その結果、複数の外部端子上にはんだボールを確実に搭載することができ、ボール搭載の歩留まりを向上させることができる。   Therefore, according to the intermediate product of the multi-cavity wiring board of the means 2, since there is no discarded ear area around the product area, it is caused by the thickness of the product area and the discarded ear area as in the conventional wiring board. The level difference is eliminated and the thickness becomes almost uniform. In addition, since the plurality of through holes are provided in a state of being distributed so as to have a uniform density in the product region, the entire solder ball alignment mask can be vacuum-sucked uniformly through each through hole. . Therefore, if an intermediate product of a multi-piece wiring board is used, the solder ball alignment mask can be securely fixed on the upper surface, and the problem that the solder ball alignment mask partially floats can be avoided. it can. As a result, solder balls can be reliably mounted on the plurality of external terminals, and the yield of ball mounting can be improved.

前記配線基板としては、樹脂材料またはセラミック材料などを主体として構成されたコア基板上に前記配線積層部を形成した多層配線基板を挙げることができる。前記樹脂材料を主体として構成されたコア基板の具体例としては、EP樹脂(エポキシ樹脂)基板、PI樹脂(ポリイミド樹脂)基板、BT樹脂(ビスマレイミド・トリアジン樹脂)基板、PPE樹脂(ポリフェニレンエーテル樹脂)基板などがある。そのほか、これらの樹脂とガラス繊維(ガラス織布やガラス不織布)やポリアミド繊維等の有機繊維との複合材料からなる基板を使用してもよい。あるいは、連続多孔質PTFE等の三次元網目状フッ素系樹脂基材にエポキシ樹脂などの熱硬化性樹脂を含浸させた樹脂−樹脂複合材料からなる基板等を使用してもよい。また、セラミック材料を主体として構成されたコア基板の具体例としては、アルミナ、窒化アルミニウム、窒化ほう素、炭化珪素、窒化珪素などのセラミック材料からなる基板などがある。   Examples of the wiring board include a multilayer wiring board in which the wiring laminated portion is formed on a core substrate mainly composed of a resin material or a ceramic material. Specific examples of the core substrate composed mainly of the resin material include an EP resin (epoxy resin) substrate, a PI resin (polyimide resin) substrate, a BT resin (bismaleimide / triazine resin) substrate, and a PPE resin (polyphenylene ether resin). ) There is a substrate. In addition, a substrate made of a composite material of these resins and organic fibers such as glass fibers (glass woven fabric or glass nonwoven fabric) or polyamide fibers may be used. Alternatively, a substrate made of a resin-resin composite material obtained by impregnating a thermosetting resin such as an epoxy resin with a three-dimensional network fluorine-based resin base material such as continuous porous PTFE may be used. Specific examples of the core substrate mainly composed of a ceramic material include a substrate made of a ceramic material such as alumina, aluminum nitride, boron nitride, silicon carbide, or silicon nitride.

前記配線基板を構成する配線積層部は、高分子材料を主体とする層間絶縁層及び導体層を積層した構造を有している。なお、配線積層部は、前記コア基板のコア主面上及びコア裏面上のいずれか一方にのみ形成されていてもよいし、前記コア主面上及び前記コア裏面上の両方に形成されていてもよいが、前記コア主面上及び前記コア裏面上の両方に形成されることが好ましい。このように構成すれば、コア主面上に形成された配線積層部とコア裏面上に形成された配線積層部との両方に電気回路を形成できるため、配線基板のよりいっそうの高機能化を図ることができる。   The wiring laminated portion constituting the wiring board has a structure in which an interlayer insulating layer mainly composed of a polymer material and a conductor layer are laminated. The wiring laminated portion may be formed only on one of the core main surface and the core back surface of the core substrate, or may be formed on both the core main surface and the core back surface. However, it is preferably formed on both the core main surface and the core back surface. With this configuration, an electric circuit can be formed in both the wiring laminated portion formed on the core main surface and the wiring laminated portion formed on the back surface of the core, thereby further enhancing the functionality of the wiring board. Can be planned.

前記導体層は、サブトラクティブ法、セミアディティブ法、フルアディティブ法などといった公知の手法によって、コア基板上や層間絶縁層上にパターン形成される。導体層の形成に用いられる金属材料の例としては、銅、銅合金、ニッケル、ニッケル合金、スズ、スズ合金などが挙げられる。   The conductor layer is patterned on the core substrate or the interlayer insulating layer by a known method such as a subtractive method, a semi-additive method, or a full additive method. Examples of the metal material used for forming the conductor layer include copper, a copper alloy, nickel, a nickel alloy, tin, and a tin alloy.

層間絶縁層は、絶縁性、耐熱性、耐湿性等を考慮して適宜選択することができる。層間絶縁層を形成するための高分子材料の好適例としては、エポキシ樹脂、フェノール樹脂、ウレタン樹脂、シリコーン樹脂、ポリイミド樹脂などの熱硬化性樹脂、ポリカーボネート樹脂、アクリル樹脂、ポリアセタール樹脂、ポリプロピレン樹脂などの熱可塑性樹脂等が挙げられる。そのほか、これらの樹脂とガラス繊維(ガラス織布やガラス不織布)やポリアミド繊維等の有機繊維との複合材料、あるいは、連続多孔質PTFE等の三次元網目状フッ素系樹脂基材にエポキシ樹脂などの熱硬化性樹脂を含浸させた樹脂−樹脂複合材料等を使用してもよい。   The interlayer insulating layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the polymer material for forming the interlayer insulating layer include thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, polycarbonate resin, acrylic resin, polyacetal resin, polypropylene resin, etc. And other thermoplastic resins. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

前記はんだボールをなす金属としては、搭載される半導体素子の接続端子等の材質等に応じて適宜選択すればよいが、90Pb−10Sn、95Pb−5Sn、40Pb−60SnなどのPb−Sn系ハンダ、Sn−Sb系ハンダ、Sn−Ag系ハンダ、Sn−Ag−Cu系ハンダ、Au−Ge系ハンダ、Au−Sn系ハンダなどのハンダが挙げられる。なお、前記はんだボールは、半導体素子の接続端子に接続するためのものであり、その直径が100μm以下であることが好ましい。   The metal that forms the solder ball may be appropriately selected according to the material of the connection terminal of the semiconductor element to be mounted, etc. Examples of the solder include Sn—Sb solder, Sn—Ag solder, Sn—Ag—Cu solder, Au—Ge solder, Au—Sn solder. The solder ball is for connecting to a connection terminal of a semiconductor element, and preferably has a diameter of 100 μm or less.

以下、本発明を具体化した一実施の形態を図面に基づき詳細に説明する。   Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

図1は、本実施の形態の多数個取り配線基板100を示す平面図である。   FIG. 1 is a plan view showing a multi-piece wiring board 100 of the present embodiment.

この多数個取り配線基板100は、略正方形状の板材であって、上面及び下面を有している。多数個取り配線基板100には、略正方形状をした複数の配線基板領域101(配線基板10の製品となるべき部分)が平面方向に沿って縦横に複数配列されている。図1にて描かれた一点鎖線は切断予定線103である。この切断予定線103上において多数個取り配線基板100を分割することにより、複数の配線基板10が同時に得られるようになっている。個々の配線基板領域101においてその上面の中央部は半導体素子搭載部23であって、その部分には複数のはんだバンプ45がアレイ状に設けられている。   The multi-cavity wiring board 100 is a substantially square plate material, and has an upper surface and a lower surface. In the multi-cavity wiring board 100, a plurality of wiring board regions 101 (parts to be products of the wiring board 10) having a substantially square shape are arranged in the vertical and horizontal directions along the plane direction. The alternate long and short dash line drawn in FIG. By dividing the multi-piece wiring board 100 on the planned cutting line 103, a plurality of wiring boards 10 can be obtained simultaneously. In each wiring board region 101, the central portion of the upper surface thereof is a semiconductor element mounting portion 23, and a plurality of solder bumps 45 are provided in an array in that portion.

また、多数個取り配線基板100において、切断予定線103上であって各配線基板領域101の各辺となる位置には、複数の貫通孔105が均等な間隔で形成されている。各貫通孔105は、後述するボール搭載工程において、はんだボール整列用マスクを吸着するために用いられる。なお、各貫通孔105は、直径が3mm程度のサイズを有する。   In the multi-cavity wiring substrate 100, a plurality of through holes 105 are formed at equal intervals on the planned cutting line 103 and at positions corresponding to each side of each wiring substrate region 101. Each through hole 105 is used for adsorbing a solder ball alignment mask in a ball mounting process described later. Each through hole 105 has a size of about 3 mm in diameter.

さらに、多数個取り配線基板100には、その外形線(図1では左辺及び右辺)において貫通孔105と対応する位置に半円状の凹部107が形成されている。この半円状の凹部107を設けることにより、多数個取り配線基板100の分割時に個々の配線基板10が同一形状となる。具体的には、配線基板10は、4つの辺を有する矩形状であり、対向する2つの辺に半円状の凹部107がそれぞれ形成されている。そして、これら凹部107は、配線基板10を位置決めするための部品位置決め用凹部として利用される。   Further, the multi-cavity wiring board 100 is formed with a semicircular recess 107 at a position corresponding to the through hole 105 in the outline (left side and right side in FIG. 1). By providing the semicircular recess 107, the individual wiring boards 10 have the same shape when the multi-piece wiring board 100 is divided. Specifically, the wiring substrate 10 has a rectangular shape having four sides, and a semicircular recess 107 is formed on each of two opposing sides. These recesses 107 are used as component positioning recesses for positioning the wiring board 10.

図2は、配線基板10の断面図である。図2に示されるように、配線基板10は、ガラスエポキシからなる略矩形板状のコア基板11と、コア基板11の上面12上に形成されるビルドアップ層31(配線積層部)と、コア基板11の下面13上に形成されるビルドアップ層32とからなる。コア基板11における複数箇所にはビア導体16が形成されている。かかるビア導体16は、コア基板11の上面12側と下面13側とを接続導通している。また、コア基板11の上面12及び下面13には、銅からなる導体層41がパターン形成されており、各導体層41は、ビア導体16に電気的に接続されている。   FIG. 2 is a cross-sectional view of the wiring board 10. As shown in FIG. 2, the wiring substrate 10 includes a substantially rectangular plate-shaped core substrate 11 made of glass epoxy, a buildup layer 31 (wiring laminated portion) formed on the upper surface 12 of the core substrate 11, a core The buildup layer 32 is formed on the lower surface 13 of the substrate 11. Via conductors 16 are formed at a plurality of locations on the core substrate 11. The via conductor 16 connects and connects the upper surface 12 side and the lower surface 13 side of the core substrate 11. A conductor layer 41 made of copper is patterned on the upper surface 12 and the lower surface 13 of the core substrate 11, and each conductor layer 41 is electrically connected to the via conductor 16.

コア基板11の上面12上に形成されたビルドアップ層31は、エポキシ樹脂からなる2層の樹脂絶縁層33,35(いわゆる層間絶縁層)と、銅からなる導体層42とを交互に積層した構造を有している。第2層の樹脂絶縁層35の表面上における複数箇所には、端子パッド44(外部端子)がアレイ状に形成されている。また、樹脂絶縁層35の表面は、ソルダーレジスト37によってほぼ全体的に覆われている。ソルダーレジスト37の所定箇所には、端子パッド44を露出させる開口部46が形成されている。端子パッド44の表面上には、複数のはんだバンプ45が配設されている。各はんだバンプ45は、半導体素子であるICチップ21の面接続端子22に電気的に接続される。なお、ビルドアップ層31において、各端子パッド44及び各はんだバンプ45が形成される領域が、半導体素子搭載部23となる。また、樹脂絶縁層33,35内には、それぞれビア導体43が設けられている。これらのビア導体43は、導体層41,42と端子パッド44とを相互に電気的に接続している。   The build-up layer 31 formed on the upper surface 12 of the core substrate 11 is formed by alternately laminating two resin insulating layers 33 and 35 (so-called interlayer insulating layers) made of epoxy resin and a conductor layer 42 made of copper. It has a structure. Terminal pads 44 (external terminals) are formed in an array at a plurality of locations on the surface of the second resin insulating layer 35. The surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 which is a semiconductor element. In the build-up layer 31, the region where each terminal pad 44 and each solder bump 45 is formed becomes the semiconductor element mounting portion 23. In addition, via conductors 43 are provided in the resin insulating layers 33 and 35, respectively. These via conductors 43 electrically connect the conductor layers 41 and 42 and the terminal pads 44 to each other.

コア基板11の下面13上に形成されたビルドアップ層32は、上述したビルドアップ層31とほぼ同じ構造を有している。即ち、ビルドアップ層32は、エポキシ樹脂からなる2層の樹脂絶縁層34,36と、導体層42とを交互に積層した構造を有している。第2層の樹脂絶縁層36の下面上における複数箇所には、ビア導体43を介して導体層42に電気的に接続されるBGA用パッド48がアレイ状に形成されている。また、樹脂絶縁層36の下面は、ソルダーレジスト38によってほぼ全体的に覆われている。ソルダーレジスト38の所定箇所には、BGA用パッド48を露出させる開口部50が形成されている。そして、各BGA用パッド48は、その表面上に配置されるはんだバンプ49によってマザーボード(図示略)との電気的に接続される。これによって、配線基板10がマザーボード上に実装される。   The buildup layer 32 formed on the lower surface 13 of the core substrate 11 has substantially the same structure as the buildup layer 31 described above. That is, the buildup layer 32 has a structure in which two resin insulating layers 34 and 36 made of epoxy resin and the conductor layer 42 are alternately laminated. BGA pads 48 electrically connected to the conductor layer 42 through via conductors 43 are formed in an array at a plurality of locations on the lower surface of the second resin insulating layer 36. The lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 50 for exposing the BGA pad 48 is formed at a predetermined position of the solder resist 38. Each BGA pad 48 is electrically connected to a mother board (not shown) by solder bumps 49 arranged on the surface thereof. Thereby, the wiring board 10 is mounted on the mother board.

本実施の形態の多数個取り配線基板100は例えば以下の手順で作製される。   The multi-cavity wiring board 100 of the present embodiment is manufactured, for example, by the following procedure.

まず、両面に銅箔が貼付された銅張積層板を準備する。次に、銅張積層板に対してドリル機を用いて孔あけ加工を行い、ビア導体16を形成するための貫通孔を所定位置にあらかじめ形成しておく。そして、銅張積層板の全面に対して無電解銅めっきを施し、各貫通孔の内部を銅めっきで埋めることでビア導体16を形成する。さらに、銅張積層板の両面の銅箔のエッチングを行って導体層41を例えばサブトラクティブ法によってパターニングして、コア基板11を得る。   First, a copper clad laminate having copper foil attached on both sides is prepared. Next, drilling is performed on the copper-clad laminate using a drill, and a through hole for forming the via conductor 16 is formed in advance at a predetermined position. And the electroconductive copper plating is given with respect to the whole surface of a copper clad laminated board, and the via conductor 16 is formed by filling the inside of each through-hole with copper plating. Further, the copper foil on both sides of the copper clad laminate is etched, and the conductor layer 41 is patterned by, for example, a subtractive method to obtain the core substrate 11.

図3に示されるように、コア基板11には、製品領域110及び捨て耳領域111が設けられている。製品領域110は、コア基板11の略中央部において平面視矩形状に設けられている。捨て耳領域111は、製品領域110の周囲(つまり基板外周部)において平面視矩形枠状に設けられている。また、コア基板11における捨て耳領域111には、位置決め用孔115等が複数設けられており、各位置決め用孔115等を利用して配線積層部形成工程が実施される。なお、各位置決め用孔115は、例えば6mm程度の直径を有する。   As shown in FIG. 3, the core substrate 11 is provided with a product region 110 and a throw-away region 111. The product region 110 is provided in a rectangular shape in plan view at a substantially central portion of the core substrate 11. The discarded ear region 111 is provided in a rectangular frame shape in plan view around the product region 110 (that is, the outer periphery of the substrate). In addition, a plurality of positioning holes 115 and the like are provided in the abandon ear region 111 in the core substrate 11, and the wiring laminated portion forming step is performed using each positioning hole 115 and the like. Each positioning hole 115 has a diameter of about 6 mm, for example.

配線積層部形成工程では、従来周知のビルドアップ法に基づいて、コア基板11の上面12の上にビルドアップ層31を形成するとともに、コア基板11の下面13の上にビルドアップ層32を形成する。詳述すると、まずコア基板11の上面12及び下面13にシート状の熱硬化性エポキシ樹脂をラミネートし、レーザー加工機により、ビア導体43が形成されるべき位置に盲孔を有する第1層の樹脂絶縁層33,34を形成する。なお、シート状の熱硬化性エポキシ樹脂をラミネートする代わりに、液状の熱硬化性エポキシ樹脂を塗布することにより、樹脂絶縁層33,34を形成してもよい。次に、従来公知の手法(例えばセミアディティブ法)に従って電解銅めっきを行い、前記盲孔の内部にビア導体43を形成するとともに、樹脂絶縁層33,34上に導体層42を形成する。   In the wiring laminated portion forming step, the buildup layer 31 is formed on the upper surface 12 of the core substrate 11 and the buildup layer 32 is formed on the lower surface 13 of the core substrate 11 based on a conventionally known buildup method. To do. More specifically, first, a sheet-like thermosetting epoxy resin is laminated on the upper surface 12 and the lower surface 13 of the core substrate 11, and the first layer having blind holes at positions where the via conductors 43 are to be formed by a laser processing machine. Resin insulating layers 33 and 34 are formed. The resin insulating layers 33 and 34 may be formed by applying a liquid thermosetting epoxy resin instead of laminating the sheet-like thermosetting epoxy resin. Next, electrolytic copper plating is performed according to a conventionally known method (for example, a semi-additive method) to form a via conductor 43 in the blind hole and a conductor layer 42 on the resin insulating layers 33 and 34.

そして、第1層の樹脂絶縁層33,34上にシート状の熱硬化性エポキシ樹脂をラミネートし、レーザー加工機により、ビア導体43が形成されるべき位置に盲孔を有する第2層の樹脂絶縁層35,36を形成する。なお、シート状の熱硬化性エポキシ樹脂をラミネートする代わりに、液状の熱硬化性エポキシ樹脂を塗布することにより、樹脂絶縁層35,36を形成してもよい。次に、従来公知の手法に従って電解銅めっきを行い、前記盲孔の内部にビア導体43を形成するとともに、樹脂絶縁層35上に端子パッド44を形成し、樹脂絶縁層36上にBGA用パッド48を形成する。   Then, a sheet-like thermosetting epoxy resin is laminated on the first resin insulating layers 33 and 34, and a second layer resin having a blind hole at a position where the via conductor 43 is to be formed by a laser processing machine. Insulating layers 35 and 36 are formed. Note that the resin insulation layers 35 and 36 may be formed by applying a liquid thermosetting epoxy resin instead of laminating the sheet-like thermosetting epoxy resin. Next, electrolytic copper plating is performed in accordance with a conventionally known method to form via conductors 43 in the blind holes, terminal pads 44 are formed on the resin insulating layer 35, and BGA pads are formed on the resin insulating layer 36. 48 is formed.

次に、第2層の樹脂絶縁層35,36上に感光性エポキシ樹脂を塗布して硬化させることにより、ソルダーレジスト37,38を形成する。その後、所定のマスクを配置した状態で露光及び現像を行い、ソルダーレジスト37,38に開口部46,50をパターニングする。その結果、コア基板11の上面12及び下面13にビルドアップ層31,32が形成される。   Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the second resin insulation layers 35 and 36. Thereafter, exposure and development are performed with a predetermined mask placed, and the openings 46 and 50 are patterned in the solder resists 37 and 38. As a result, buildup layers 31 and 32 are formed on the upper surface 12 and the lower surface 13 of the core substrate 11.

続く貫通孔配設工程では、ビルドアップ層31,32を形成したコア基板11に、ドリル機を用いて孔あけ加工を行い、図4に示されるように、コア基板11の製品領域110内に複数の貫通孔105を形成する。各貫通孔105は、製品領域110の外形線上を含めた切断予定線103上に設けられている。より詳しくは、各貫通孔105は、配線基板領域101の幅に合わせた均等な間隔で形成され、製品領域110内において均等な密度となるよう分散させた状態で設けられている。   In the subsequent through-hole arrangement process, the core substrate 11 on which the build-up layers 31 and 32 are formed is drilled using a drill machine, and as shown in FIG. A plurality of through holes 105 are formed. Each through-hole 105 is provided on the planned cutting line 103 including the outline of the product region 110. More specifically, the through-holes 105 are formed at equal intervals according to the width of the wiring board region 101 and are provided in a distributed state in the product region 110 so as to have an equal density.

そして、貫通孔配設工程の実施後、切断除去工程を行い、製品領域110の外側にある捨て耳領域111を切断除去して製品領域110のみの基板とする。この基板は、はんだボールを搭載する前の多数個取り配線基板100の中間製品120である(図5参照)。   Then, after performing the through-hole arranging step, a cutting and removing step is performed to cut and remove the abandoned ear region 111 outside the product region 110 to obtain a substrate having only the product region 110. This board is an intermediate product 120 of the multi-piece wiring board 100 before mounting solder balls (see FIG. 5).

次いで、多数個取り配線基板100の中間製品120を図6及び図7に示すはんだボール搭載装置130にセットし、ボール搭載工程を実施する。はんだボール搭載装置130は、中間製品120を固定するための固定ステージ132を備える。固定ステージ132の上面には、基板サイズに合わせた基板セット部134(凹部)が形成されている。基板セット部134には基板外縁部に当接して支える段差が形成され、この基板セット部134に中間製品120がセットされる。そして、その中間製品120の基板上にはんだボール整列用マスク136が配置される。その整列用マスク136には、各配線基板領域101の所定位置(半導体素子搭載部23における複数の端子パッド44に対応した位置)において、例えば100μm以下の直径を有するはんだボール138をアレイ状に整列させるための複数の透孔140が形成されている。   Next, the intermediate product 120 of the multi-piece wiring board 100 is set on the solder ball mounting device 130 shown in FIGS. 6 and 7, and a ball mounting process is performed. The solder ball mounting device 130 includes a fixing stage 132 for fixing the intermediate product 120. On the upper surface of the fixed stage 132, a substrate setting portion 134 (concave portion) that matches the substrate size is formed. A step is formed on the substrate setting portion 134 so as to abut against and support the outer edge of the substrate, and the intermediate product 120 is set on the substrate setting portion 134. Then, a solder ball alignment mask 136 is disposed on the substrate of the intermediate product 120. In the alignment mask 136, solder balls 138 having a diameter of, for example, 100 μm or less are aligned in an array at a predetermined position of each wiring board region 101 (a position corresponding to the plurality of terminal pads 44 in the semiconductor element mounting portion 23). A plurality of through-holes 140 are formed for this purpose.

また、固定ステージ132において、基板セット部134の下方には吸引室142が設けられ、吸引室142は排気ダクト144を介して真空ポンプ146に接続されている。この真空ポンプ146が駆動されることにより吸引室142が負圧状態となる。この結果、中間製品120に形成された貫通孔105を通してはんだボール整列用マスク136が吸引され、その整列用マスク136が移動しないように固定される。はんだボール整列用マスク136の固定後、図示しないはんだボール供給部から整列用マスク136上にはんだボール138が供給され、はんだボール138が各透孔140に収納される。これにより、中間製品120の各配線基板領域101において、半導体素子搭載部23の各端子パッド44上にはんだボール138が搭載される。この後、はんだボール138を所定の温度に加熱してリフローすることにより、各端子パッド44上にはんだバンプ45が形成される。   In the fixed stage 132, a suction chamber 142 is provided below the substrate setting unit 134, and the suction chamber 142 is connected to a vacuum pump 146 through an exhaust duct 144. When the vacuum pump 146 is driven, the suction chamber 142 is in a negative pressure state. As a result, the solder ball alignment mask 136 is sucked through the through-hole 105 formed in the intermediate product 120, and the alignment mask 136 is fixed so as not to move. After the solder ball alignment mask 136 is fixed, the solder balls 138 are supplied onto the alignment mask 136 from a solder ball supply unit (not shown), and the solder balls 138 are accommodated in the respective through holes 140. As a result, the solder balls 138 are mounted on the terminal pads 44 of the semiconductor element mounting portion 23 in each wiring board region 101 of the intermediate product 120. Thereafter, the solder balls 138 are heated to a predetermined temperature and reflowed to form solder bumps 45 on the terminal pads 44.

以上の工程を経て、図1に示すような多数個取り配線基板100が完成する。さらに、基板分割工程を実施して多数個取り配線基板100を分割することにより、複数個の配線基板10が同時に得られる。   Through the above steps, a multi-piece wiring substrate 100 as shown in FIG. 1 is completed. Furthermore, a plurality of wiring boards 10 can be obtained simultaneously by dividing the multi-piece wiring board 100 by carrying out a board dividing step.

従って、本実施の形態によれば以下の効果を得ることができる。   Therefore, according to the present embodiment, the following effects can be obtained.

(1)本実施の形態では、はんだボール搭載装置130にセットされる多数個取り配線基板100の中間製品120は、製品領域110のみの基板であるため、従来の配線基板200のように製品領域210と捨て耳領域211との厚さに起因する段差がなく、ほぼ均一な厚さである。また、中間製品120には、製品領域110内に均等な密度となるように複数の貫通孔105が分散された状態で設けられている。従って、中間製品120の複数の貫通孔105を介してその上面に配置されたはんだボール整列用マスク136を均等に真空吸着して確実に固定することができる。このため、はんだボール整列用マスク136が部分的に浮いてしまうといった問題を回避することができる。その結果、複数の端子パッド44上にはんだボール138を確実に整列させて搭載することができ、ボール搭載の歩留まりを向上させることができる。   (1) In the present embodiment, the intermediate product 120 of the multi-piece wiring board 100 set in the solder ball mounting device 130 is a board having only the product area 110, so that the product area as in the conventional wiring board 200 is used. There is no level difference due to the thickness between 210 and the discarded ear region 211, and the thickness is almost uniform. In addition, the intermediate product 120 is provided with a plurality of through holes 105 dispersed in the product region 110 so as to have a uniform density. Therefore, the solder ball alignment mask 136 disposed on the upper surface of the intermediate product 120 through the plurality of through holes 105 can be uniformly vacuum-sucked and securely fixed. For this reason, the problem that the solder ball alignment mask 136 partially floats can be avoided. As a result, the solder balls 138 can be reliably aligned and mounted on the plurality of terminal pads 44, and the yield of ball mounting can be improved.

(2)本実施の形態の場合、製品領域110のみの中間製品120がはんだボール搭載装置130にセットされているため、捨て耳領域211がある従来の配線基板200と比較して基板サイズが小さくなり、はんだボール搭載装置130の小型化が可能となる。   (2) In the case of the present embodiment, since the intermediate product 120 having only the product area 110 is set in the solder ball mounting device 130, the board size is smaller than that of the conventional wiring board 200 having the discarded ear area 211. Thus, the solder ball mounting device 130 can be downsized.

(3)本実施の形態の多数個取り配線基板100では、製品領域110を切断して複数の配線基板10にするときの切断予定線103上に複数の貫通孔105が設けられている。このように、切断予定線103上に各貫通孔105を形成することにより、配線基板10の機能を損ねることなく、かつ、均等な密度となるように複数の貫通孔105を分散させることができる。また、各貫通孔105は、捨て耳領域111の位置決め用孔115よりも径が小さいので、製品領域110においてより多くの貫通孔105を分散して設けることが可能となる。   (3) In the multi-cavity wiring board 100 of the present embodiment, a plurality of through holes 105 are provided on the planned cutting lines 103 when the product region 110 is cut into a plurality of wiring boards 10. Thus, by forming each through-hole 105 on the planned cutting line 103, the plurality of through-holes 105 can be dispersed so as to obtain a uniform density without impairing the function of the wiring board 10. . Further, since each through hole 105 has a diameter smaller than that of the positioning hole 115 in the disposal ear region 111, it is possible to disperse and provide more through holes 105 in the product region 110.

(4)本実施の形態において、複数の貫通孔105は、製品領域110の外形線上にも設けられるので、製品領域110を分割して個々の配線基板10にしたとき、各配線基板10を全て同一形状とすることができる。   (4) In the present embodiment, since the plurality of through holes 105 are also provided on the outline of the product region 110, when the product region 110 is divided into individual wiring substrates 10, all the wiring substrates 10 are all formed. The same shape can be used.

(5)本実施の形態の場合、多数個取り配線基板100を分割して得られる配線基板10は、4つの辺を有する矩形状であり、対向する2つの辺に部品位置決め用凹部107を有している。この場合、2つの部品位置決め用凹部107を利用して配線基板10の位置決めを確実に行うことができる。また、真空吸着用の貫通孔105が切断工程を経て半円状の凹部107とされ、その凹部107が部品位置決め用凹部として利用されるので、部品位置決め用凹部を別途設ける必要がなくなり、配線基板10の製造コストを抑えることができる。   (5) In the case of the present embodiment, the wiring board 10 obtained by dividing the multi-cavity wiring board 100 has a rectangular shape having four sides, and has the component positioning recesses 107 on the two opposing sides. is doing. In this case, the wiring substrate 10 can be positioned reliably using the two component positioning recesses 107. Further, the through-hole 105 for vacuum suction is formed into a semicircular recess 107 through a cutting process, and the recess 107 is used as a component positioning recess, so that it is not necessary to separately provide a component positioning recess. The manufacturing cost of 10 can be suppressed.

なお、本発明の実施の形態は以下のように変更してもよい。   In addition, you may change embodiment of this invention as follows.

・上記実施の形態の多数個取り配線基板100では、複数の貫通孔105は、切断予定線103上であって、配線基板10の対向する2つの辺となる位置に形成されるものであったが、これに限定されるものではない。例えば、図8に示す多数個取り配線基板100Aのように、切断予定線103同士が交差する点上に貫通孔105をそれぞれ形成してもよい。このようにしても、製品領域110内において均等な密度となるよう分散させた状態で複数の貫通孔105を設けることができ、各貫通孔105を介してボール整列用マスク136を均一に真空吸着することができる。なお、各貫通孔105は切断予定線103上に設ける必要はなく、例えば、ビルドアップ層31,32における導体層41等に重ならない位置であれば、切断予定線103からずれた位置に形成してもよい。   In the multi-cavity wiring board 100 of the above-described embodiment, the plurality of through holes 105 are formed on the planned cutting line 103 at positions that are two opposite sides of the wiring board 10. However, the present invention is not limited to this. For example, like the multi-cavity wiring board 100A shown in FIG. 8, the through holes 105 may be formed on the points where the planned cutting lines 103 intersect each other. Even in this case, a plurality of through holes 105 can be provided in a state of being distributed so as to have a uniform density in the product region 110, and the ball alignment mask 136 is uniformly vacuum-sucked through each through hole 105. can do. Each through hole 105 does not need to be provided on the planned cutting line 103. For example, the through hole 105 is formed at a position shifted from the planned cutting line 103 if it does not overlap the conductor layer 41 or the like in the buildup layers 31 and 32. May be.

・上記実施の形態では、多数個取り配線基板100,100Aに形成される貫通孔105の形状は円形であるが、この形状に限定するものではなく、例えば、四角や三角などの多角形状の貫通孔であってもよい。ただし、上記実施の形態のように、円形の貫通孔105を設ける場合には、ボール整列用マスク136をより均一に吸着することが可能となる。また、各貫通孔105が円形であれば、ドリル加工等によって容易に形成することができる。   In the above embodiment, the shape of the through-hole 105 formed in the multi-piece wiring substrate 100, 100A is circular, but is not limited to this shape. For example, it penetrates in a polygonal shape such as a square or a triangle. It may be a hole. However, when the circular through hole 105 is provided as in the above embodiment, the ball alignment mask 136 can be adsorbed more uniformly. Moreover, if each through-hole 105 is circular, it can be easily formed by drilling or the like.

・上記実施の形態では、配線基板10のパッケージ形態はBGA(ボールグリッドアレイ)であるが、BGAのみに限定されず、例えばPGA(ピングリッドアレイ)やLGA(ランドグリッドアレイ)等であってもよい。   In the above embodiment, the package form of the wiring board 10 is BGA (ball grid array), but is not limited to BGA, and may be, for example, PGA (pin grid array) or LGA (land grid array). Good.

・上記実施の形態における配線基板10は、樹脂材料からなるオーガニックタイプの配線基板であるが、セラミック材料からなる配線基板に本発明を適用してもよい。   The wiring board 10 in the above embodiment is an organic type wiring board made of a resin material, but the present invention may be applied to a wiring board made of a ceramic material.

次に、前述した実施の形態によって把握される技術的思想を以下に列挙する。   Next, the technical ideas grasped by the embodiment described above are listed below.

(1)配線基板の製品となるべき部分が平面方向に沿って縦横に複数配列された製品領域を有する一方、その製品領域の周囲に捨て耳領域を有しない多数個取り配線基板の中間製品であって、樹脂材料を主体として形成されるコア基板と、前記コア基板上に設けられ、層間絶縁層及び導体層を積層した構造を有しかつ半導体素子が接続可能な複数の外部端子を有する配線積層部とを備え、はんだボール整列用マスクを真空吸着するための複数の貫通孔が、前記製品領域内において均等な密度となるように分散させた状態で設けられていることを特徴とする多数個取り配線基板の中間製品。   (1) An intermediate product of a multi-cavity wiring board having a product area in which a plurality of parts to be products of a wiring board have a plurality of vertical and horizontal arrangements along the plane direction and no surrounding area around the product area. A wiring board having a core substrate formed mainly of a resin material and a plurality of external terminals provided on the core substrate and having a structure in which an interlayer insulating layer and a conductor layer are stacked and to which a semiconductor element can be connected A plurality of through holes for vacuum-sucking the solder ball alignment mask, the plurality of through-holes being provided so as to have a uniform density in the product region. Intermediate product of single-sided wiring board.

(2)上記1において、前記はんだボール整列用マスクを用いて前記外部端子上に配列されるはんだボールの直径は100μm以下であることを特徴とする多数個取り配線基板の中間製品。   (2) The intermediate product of the multi-piece wiring board according to 1 above, wherein the solder balls arranged on the external terminals using the solder ball alignment mask have a diameter of 100 μm or less.

(3)製品領域とその製品領域の周囲に設けられる捨て耳領域とを備え、前記製品領域内に、半導体素子を搭載するための配線基板が平面方向に沿って縦横に複数配列された多数個取り配線基板の製造方法において、前記捨て耳領域に設けられた位置決め用孔を利用して、層間絶縁層及び導体層を積層した構造を有しかつ前記半導体素子が接続可能な複数の外部端子を有する配線積層部を前記製品領域に形成する配線積層部形成工程と、前記位置決め用孔よりも径が小さな貫通孔を前記製品領域内において均等な密度となるように分散させた状態で複数設ける貫通孔配設工程と、前記捨て耳領域を切断除去して前記製品領域のみとする切断除去工程と、前記配線積層部形成工程、前記貫通孔配設工程及び前記切断除去工程の後、前記多数個取り配線基板をはんだボール搭載装置にセットし、この状態で前記複数の外部端子に対応した位置に複数の透孔を有するはんだボール整列用マスクを前記複数の貫通孔を介して真空吸着することにより、前記多数個取り配線基板上に前記マスクを固定し、前記複数の外部端子上にはんだボールを整列させて搭載するボール搭載工程とを含むことを特徴とする多数個取り配線基板の製造方法。   (3) A product area and a lump area provided around the product area, and a plurality of wiring boards for mounting semiconductor elements arranged vertically and horizontally along the plane direction in the product area In the manufacturing method of a wiring board, a plurality of external terminals having a structure in which an interlayer insulating layer and a conductor layer are laminated using a positioning hole provided in the abandoned ear region and to which the semiconductor element can be connected A wiring laminated portion forming step for forming a wiring laminated portion having in the product region, and a plurality of through holes provided with a plurality of through holes having a diameter smaller than that of the positioning holes dispersed in a uniform density in the product region After the hole disposing step, the cutting / removing step of cutting and removing the abandoned ear region to make only the product region, the wiring laminated portion forming step, the through-hole disposing step, and the cutting / removing step, Take By setting the wiring board on the solder ball mounting device, and in this state, vacuum-adsorbing a solder ball alignment mask having a plurality of through holes at positions corresponding to the plurality of external terminals through the plurality of through holes, A method of manufacturing a multi-cavity wiring board, comprising: a ball mounting step in which the mask is fixed on the multi-cavity wiring board and solder balls are aligned and mounted on the plurality of external terminals.

本実施の形態の多数個取り配線基板を示す平面図。The top view which shows the multi-piece wiring board of this Embodiment. 本実施の形態の配線基板を示す断面図。Sectional drawing which shows the wiring board of this Embodiment. コア基板における製品領域と捨て耳領域とを説明するための平面図。The top view for demonstrating the product area | region and discard ear | edge area | region in a core board | substrate. ビルドアップ層を積層したコア基板における貫通孔の形成位置を説明するための平面図。The top view for demonstrating the formation position of the through-hole in the core board | substrate which laminated | stacked the buildup layer. 多数個取り配線基板の中間製品を示す平面図。The top view which shows the intermediate product of a multi-piece wiring board. はんだボール搭載装置を示す断面図。Sectional drawing which shows a solder ball mounting apparatus. はんだボール搭載装置を示す平面図。The top view which shows a solder ball mounting apparatus. 別の実施の形態の多数個取り配線基板を示す平面図。The top view which shows the multi-piece wiring board of another embodiment. 従来の多数個取り配線基板を示す平面図。The top view which shows the conventional multi-piece wiring board.

符号の説明Explanation of symbols

10…配線基板
21…半導体素子としてのICチップ
31…配線積層部としてのビルドアップ層
33,35…層間絶縁層としての樹脂絶縁層
42…導体層
44…外部端子としての端子パッド
100,100A…多数個取り配線基板
103…切断予定線
105…貫通孔
107…凹部
110…製品領域
111…捨て耳領域
115…位置決め用孔
120…中間製品
130…はんだボール搭載装置
136…はんだボール整列用マスク
138…はんだボール
140…透孔
DESCRIPTION OF SYMBOLS 10 ... Wiring board 21 ... IC chip as a semiconductor element 31 ... Build-up layer as a wiring lamination part 33, 35 ... Resin insulating layer as an interlayer insulating layer 42 ... Conductive layer 44 ... Terminal pad 100, 100A as an external terminal Multiple circuit board 103 ... Scheduled cutting line 105 ... Through hole 107 ... Recess 110 ... Product region 111 ... Disposal ear region 115 ... Positioning hole 120 ... Intermediate product 130 ... Solder ball mounting device 136 ... Solder ball alignment mask 138 ... Solder ball 140 ... through hole

Claims (7)

製品領域とその製品領域の周囲に設けられる捨て耳領域とを備え、前記製品領域内に、配線基板が平面方向に沿って縦横に複数配列された多数個取り配線基板の製造方法において、
前記捨て耳領域に設けられた位置決め用孔を利用して、層間絶縁層及び導体層を積層した構造を有しかつ半導体素子が接続可能な複数の外部端子を有する配線積層部を前記製品領域に形成する配線積層部形成工程と、
前記製品領域内において均等な密度となるように複数の貫通孔を分散させた状態で設ける貫通孔配設工程と、
前記捨て耳領域を切断除去して前記製品領域のみとする切断除去工程と、
前記配線積層部形成工程、前記貫通孔配設工程及び前記切断除去工程の後、前記多数個取り配線基板をはんだボール搭載装置にセットし、この状態で前記複数の外部端子に対応した位置に複数の透孔を有するはんだボール整列用マスクを前記複数の貫通孔を介して真空吸着することにより、前記多数個取り配線基板上に前記マスクを固定し、前記複数の外部端子上にはんだボールを搭載するボール搭載工程と
を含むことを特徴とする多数個取り配線基板の製造方法。
In the manufacturing method of a multi-piece wiring board comprising a product area and a disposal ear area provided around the product area, wherein a plurality of wiring boards are arranged vertically and horizontally along the plane direction in the product area,
A wiring layered portion having a structure in which an interlayer insulating layer and a conductor layer are stacked using a positioning hole provided in the discard ear region and having a plurality of external terminals to which a semiconductor element can be connected is formed in the product region. A wiring laminate forming step to be formed;
A through-hole disposing step of providing a plurality of through-holes in a dispersed state so as to have a uniform density in the product region;
A cutting and removing step of cutting and removing the abandoned ear region to make only the product region;
After the wiring laminated portion forming step, the through hole arranging step, and the cutting and removing step, the multi-piece wiring substrate is set on a solder ball mounting device, and in this state, a plurality of positions are provided at positions corresponding to the plurality of external terminals. A solder ball alignment mask having a plurality of through-holes is vacuum-adsorbed through the plurality of through-holes, thereby fixing the mask on the multi-piece wiring board and mounting solder balls on the plurality of external terminals. And a ball mounting step for manufacturing a multi-piece wiring board.
前記複数の貫通孔は、前記製品領域を切断して複数の配線基板にするときの切断予定線上に設けられることを特徴とする請求項1に記載の多数個取り配線基板の製造方法。   The method of manufacturing a multi-piece wiring board according to claim 1, wherein the plurality of through holes are provided on a planned cutting line when the product region is cut into a plurality of wiring boards. 前記複数の貫通孔は、前記製品領域の外形線上にも設けられることを特徴とする請求項2に記載の多数個取り配線基板の製造方法。   The method for manufacturing a multi-cavity wiring board according to claim 2, wherein the plurality of through holes are also provided on an outline of the product region. 前記複数の貫通孔は、前記製品領域を切断して複数の配線基板にするときの切断予定線同士が交差する点上に設けられることを特徴とする請求項1に記載の多数個取り配線基板の製造方法。   2. The multi-cavity wiring board according to claim 1, wherein the plurality of through holes are provided on points where the planned cutting lines intersect when the product region is cut into a plurality of wiring boards. Manufacturing method. 前記複数の貫通孔は、前記切断工程を経て半円状の凹部とすることにより、前記配線基板を位置決めするための部品位置決め用凹部として利用されることを特徴とする請求項1乃至3のいずれか1項に記載の多数個取り配線基板の製造方法。   The plurality of through holes are used as component positioning recesses for positioning the wiring board by forming a semicircular recess through the cutting step. A method for manufacturing a multi-piece wiring board according to claim 1. 前記配線基板は、4つの辺を有する矩形状であり、対向する2つの辺に前記部品位置決め用凹部を有していることを特徴とする請求項5に記載の多数個取り配線基板の製造方法。   6. The method of manufacturing a multi-piece wiring board according to claim 5, wherein the wiring board has a rectangular shape having four sides, and the component positioning recesses are provided on two opposing sides. . 配線基板の製品となるべき部分が平面方向に沿って縦横に複数配列された製品領域を有する一方、その製品領域の周囲に捨て耳領域を有しない多数個取り配線基板の中間製品であって、
層間絶縁層及び導体層を積層した構造を有しかつ半導体素子が接続可能な複数の外部端子を有する配線積層部を備え、はんだボール整列用マスクを真空吸着するための複数の貫通孔が、前記製品領域内において均等な密度となるように分散させた状態で設けられていることを特徴とする多数個取り配線基板の中間製品。
While the product area of the wiring board has a product area in which a plurality of parts are arranged vertically and horizontally along the plane direction, it is an intermediate product of a multi-cavity wiring board that does not have a discarded ear area around the product area,
A wiring laminated portion having a plurality of external terminals to which a semiconductor element can be connected, having a structure in which an interlayer insulating layer and a conductor layer are laminated, and a plurality of through holes for vacuum adsorbing a solder ball alignment mask, An intermediate product of a multi-piece wiring board, characterized in that it is provided in a distributed state so as to have a uniform density in the product area.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021048164A (en) * 2019-09-17 2021-03-25 日立金属株式会社 Silicon nitride ceramics sintered substrate, method for manufacturing the same, silicon nitride ceramics assembly substrate, and method for manufacturing circuit board
JP2021048328A (en) * 2019-09-19 2021-03-25 日立金属株式会社 Silicon nitride ceramics sintered substrate, method for manufacturing the same, silicon nitride ceramics assembly substrate, and method for manufacturing circuit board

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59997A (en) * 1982-06-28 1984-01-06 株式会社日立製作所 Method of producing ceramic substrate
JPH06302925A (en) * 1993-04-13 1994-10-28 Sony Corp Substrate and alignment mark used therefor
JPH10173299A (en) * 1996-12-09 1998-06-26 Calsonic Corp Printed wiring board
JP2001237515A (en) * 2000-02-25 2001-08-31 Ibiden Co Ltd Method for manufacturing multilayer printed wiring board and laser-machining device
JP2004055991A (en) * 2002-07-23 2004-02-19 Ngk Spark Plug Co Ltd Wiring board
JP2006173483A (en) * 2004-12-17 2006-06-29 Fuji Photo Film Co Ltd Ceramic assembled substrate set, ceramic substrate, and method for manufacturing ceramic assembled substrate set
JP2006303103A (en) * 2005-04-19 2006-11-02 Hitachi Metals Ltd Conductive ball mounting method and mounting apparatus

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59997A (en) * 1982-06-28 1984-01-06 株式会社日立製作所 Method of producing ceramic substrate
JPH06302925A (en) * 1993-04-13 1994-10-28 Sony Corp Substrate and alignment mark used therefor
JPH10173299A (en) * 1996-12-09 1998-06-26 Calsonic Corp Printed wiring board
JP2001237515A (en) * 2000-02-25 2001-08-31 Ibiden Co Ltd Method for manufacturing multilayer printed wiring board and laser-machining device
JP2004055991A (en) * 2002-07-23 2004-02-19 Ngk Spark Plug Co Ltd Wiring board
JP2006173483A (en) * 2004-12-17 2006-06-29 Fuji Photo Film Co Ltd Ceramic assembled substrate set, ceramic substrate, and method for manufacturing ceramic assembled substrate set
JP2006303103A (en) * 2005-04-19 2006-11-02 Hitachi Metals Ltd Conductive ball mounting method and mounting apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021048164A (en) * 2019-09-17 2021-03-25 日立金属株式会社 Silicon nitride ceramics sintered substrate, method for manufacturing the same, silicon nitride ceramics assembly substrate, and method for manufacturing circuit board
JP7484109B2 (en) 2019-09-17 2024-05-16 株式会社プロテリアル Manufacturing method of silicon nitride ceramic sintered substrate and manufacturing method of circuit board
JP2021048328A (en) * 2019-09-19 2021-03-25 日立金属株式会社 Silicon nitride ceramics sintered substrate, method for manufacturing the same, silicon nitride ceramics assembly substrate, and method for manufacturing circuit board

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