JP2016096281A - Wiring board with cavity and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board with a cavity capable of improving mounting accuracy of an electronic component in a cavity, and also to provide a method of manufacturing the same.SOLUTION: Disclosed is a wiring board 10 with a cavity for built-in electronic component which includes: an outer insulation layer 34 which is arranged in the outside in the thickness direction; and a cavity 30 for the built-in electronic component which is opened on the F-surface 10F facing the outside of the outer insulation layer 34. In the outer insulation layer 34, a positioning opening 34A is formed, separately from the opening 30, which exposes a part of an outer conductor circuit layer 35 formed under the outer insulation layer 34 as an alignment mark 35M.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a wiring board with a cavity having a cavity for incorporating an electronic component and a method for manufacturing the same.

  2. Description of the Related Art Conventionally, an electronic component built-in wiring board that incorporates electronic components is known (see, for example, Patent Document 1). In manufacturing such a wiring board with built-in electronic components, it has been proposed to prepare a wiring board with a cavity having a cavity opened on one side of the front and back, and to mount the electronic component in the cavity.

JP 2011-2111194 A ([0012], FIG. 9)

  However, in the conventional wiring board with a cavity described above, there is a problem that the electronic component is displaced from the cavity when the electronic component is mounted in the cavity.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a wiring board with a cavity capable of improving the mounting accuracy of electronic components in the cavity and a method for manufacturing the wiring board.

  In order to achieve the above object, a wiring board with a cavity according to the present invention includes an outer insulating layer disposed outside in a thickness direction, and a cavity for incorporating an electronic component that opens on a surface facing the outer side of the outer insulating layer. In addition to the cavity opening, the outer insulating layer is provided with a positioning opening that exposes a part of the conductor layer formed under the outer insulating layer as an alignment mark. ing.

Sectional drawing of the wiring board with a cavity which concerns on one Embodiment of this invention Enlarged sectional view around the cavity of a wiring board with a cavity Plan view of alignment mark The figure which shows the manufacturing process of the wiring board with the cavity for electronic component built-in The figure which shows the manufacturing process of the wiring board with the cavity for electronic component built-in The figure which shows the manufacturing process of the wiring board with the cavity for electronic component built-in The figure which shows the manufacturing process of the wiring board with the cavity for electronic component built-in Cross-sectional view of wiring board with built-in electronic components Enlarged sectional view around the electronic component of the electronic component built-in wiring board Diagram showing the manufacturing process of electronic component built-in wiring board Diagram showing the manufacturing process of electronic component built-in wiring board Diagram showing the manufacturing process of electronic component built-in wiring board Plan view of alignment mark according to modification Sectional drawing of the wiring board with a cavity concerning a modification The figure which shows the manufacturing process of the wiring board with a cavity which concerns on a modification. The figure which shows the manufacturing process of the wiring board with a cavity which concerns on a modification.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the wiring board 10 with a cavity according to this embodiment includes a buildup insulating layer 15 and a buildup conductor layer on an F surface 11 </ b> F that is a front side surface and a B surface 11 </ b> B that is a back side surface of a core substrate 11. 16 has a multilayer structure in which 16 and 16 are alternately stacked. And on the 1st buildup conductor layer 16A arrange | positioned on the outermost side among the buildup conductor layers 16, the outer surface which comprises the F surface 10F which is the front side of the wiring board 10 with a cavity, and the B surface 10B which is a back side surface An insulating layer 34 is formed. The outer insulating layer 34 may not be formed on the B surface 10B side.

  Specifically, the core conductor layer 12 is formed on both the front and back surfaces 11 </ b> F and 11 </ b> B of the core substrate 11, and the above-described buildup insulating layer 15 is formed on the core conductor layer 12. The core conductor layer 12 on the front side and the core conductor layer 12 on the back side are connected by a through-hole conductor 13 that penetrates the core substrate 11. The through-hole conductor 13 is formed, for example, by forming copper plating on the wall surface of the through-hole 13A that penetrates the core substrate 11. The core substrate 11 has a thickness of about 700 μm, and the core conductor layer 12 has a thickness of about 35 μm.

  The buildup insulating layer 15 is made of an insulating material, and the buildup conductor layer 16 is made of a metal (for example, copper). The outer insulating layer 34 is made of the same material as the build-up insulating layer 15. The build-up insulating layer 15 has a thickness of about 10 to 30 μm, and the build-up conductor layer 16 has a thickness of about 7 to 15 μm. The outer insulating layer 34 is thinner than the build-up insulating layer 15 and has a thickness of about 7 to 15 μm. Here, the thickness of the buildup insulating layer 15 is defined by the distance between the upper and lower conductor layers, and the thickness of the outer insulating layer 34 is from the upper surface of the first buildup conductor layer 16 to the upper surface of the outer insulating layer 34. Is defined by the distance.

  The innermost buildup conductor layer 16 closest to the core substrate 11 and the core conductor layer 12 are connected by a via conductor 16 that penetrates the innermost buildup insulating layer 15. Further, the build-up conductor layers 16 and 16 adjacent in the stacking direction are connected to each other by a via conductor 18 that penetrates the build-up insulating layer 15 positioned between the build-up conductor layers 16 and 16.

  Among the plurality of buildup conductor layers 16, the buildup conductor layer 16 arranged second from the outside, that is, the buildup conductor layer 16 on the inner side of the first buildup conductor layer 16A described above is used as the second buildup conductor. When referred to as the layer 16B, a conductor circuit layer 31B and a plane layer 31A are formed on the second buildup conductor layer 16B on the F-plane 10F side. The plane layer 31A is, for example, a ground layer connected to the ground. The plane layer 31A is disposed near the center of the wiring board 10 with a cavity, and the conductor circuit layer 31B is disposed so as to sandwich the plane layer 31A from both sides.

  The first buildup conductor layer 16A on the F-plane 10F side has an outer conductor circuit layer 35 (corresponding to the “conductor layer” of the present invention) connected to the conductor circuit layer 31B via the via conductor 18. Is formed.

  As shown in FIG. 2, the cavity wiring board 10 is formed with a cavity 30 opened at the F surface 10F. The cavity 30 penetrates through the first build-up insulating layer 15A (corresponding to the “inner insulating layer” of the present invention) disposed on the outermost side of the build-up insulating layer 15 and the outer insulating layer 34, and is a plain layer. 31A is exposed as a bottom surface.

  The outer insulating layer 34 on the F-plane 10F side is formed with a positioning opening 34A that exposes a part of the outer conductor circuit layer 35 as an alignment mark 35M. As shown in FIG. 3, the positioning opening 34A is disposed at a predetermined position with respect to the cavity 30, and the distance L1 between the positioning opening 34 and the outer edge of the cavity 30 is 10 μm or more and 1500 μm or less. Yes. In the example of FIG. 3, the opening 34A and the alignment mark 35M are circular.

  This completes the description of the structure of the wiring board 10 with a cavity. Next, the manufacturing method of the wiring board 10 with a cavity is demonstrated based on FIGS.

The wiring board 10 with a cavity is manufactured as follows.
(1) As shown in FIG. 4A, a through hole 13A is formed in the core substrate 11 by, for example, drilling or the like. The core substrate 11 is laminated with copper foil (not shown) on both the front and back surfaces of an insulating base material 11K made of a reinforcing material such as epoxy resin or BT (bismaleimide triazine) resin and glass cloth.

  (2) The electroless plating process, the plating resist process, and the electrolytic plating process are performed, and the core conductor layer 12 is formed on the F surface 11F and the B surface 11B of the core substrate 11, and the through hole 13A is formed on the inner surface of the through hole 13A. A hole conductor 13 is formed (see FIG. 4B). The manufacturing method of the core substrate 11 may be a manufacturing method as shown in FIGS. 1 to 2 of JP 2012-69926 A.

  (3) As shown in FIG. 5A, the buildup insulating layer 15 is laminated on the core conductor layer 12, and the buildup conductor layer 16 is laminated on the buildup insulating layer 15. Specifically, a prepreg (B-stage resin sheet obtained by impregnating a core material with resin) and copper from the F surface 11F side and the B surface 11B side of the core substrate 11 onto the core conductor layer 12 as a build-up insulating layer 15 and copper A foil (not shown) is laminated and then heated and pressed. Then, the copper foil is irradiated with a CO 2 laser to form a via formation hole that penetrates the copper foil and the buildup insulating layer 15. Then, an electroless plating process, a plating resist process, and an electrolytic plating process are performed, and the electroplating is filled in the via formation holes to form the via conductors 16, and a predetermined pattern of build-up is formed on the build-up insulating layer 15. A conductor layer 16 is formed. A resin film that does not contain a core material may be used as the buildup insulating layer 15 instead of the prepreg. In that case, a conductor layer can be directly formed on the surface of the resin film by a semi-additive method without laminating a copper foil.

  (4) In the same manner as in the above step (3), the build-up insulating layers 15 and the build-up conductor layers 16 are alternately laminated on the F surface 11F side and the B surface 11B side of the core substrate 11 (FIG. 5 ( (B) Note that only the F-plane 11F side is shown in the figure, and the same applies to FIGS. At that time, a via conductor 18 penetrating the buildup insulating layer 15 is formed, and the buildup conductor layers 16 and 16 adjacent in the stacking direction are connected by the via 18 conductor.

  (5) In the same manner as in the above step (3), the build-up insulating layer 15 is laminated, and the build-up conductor layer 16 is laminated on the build-up insulating layer 15 to form the second build-up conductor layer 16B. Is formed (see FIG. 6A). At that time, the second buildup conductor layer 16B on the F-plane 11F side includes a conductor circuit layer 31B connected to the buildup conductor layer 16 on the inner side of the second buildup conductor layer 16B via the via conductor 18; A solid plane layer 31A is formed.

  (6) In the same manner as in the above step (3), the build-up insulating layer 15 and the build-up conductor layer 16 are laminated on the second build-up conductor layer 16B, and the first build-up insulating layer 15A and the first Build-up conductor layer 16A is formed (see FIG. 6B). At that time, only the first build-up insulating layer 15A is laminated on the plane layer 31A. The first buildup conductor layer 16A is formed with an outer conductor circuit layer 35 connected to the conductor circuit layer 31B through the via 18 penetrating the first buildup insulating layer 15A.

  (7) As shown in FIG. 7A, the outer insulating layer 34 made of the same material as the build-up insulating layer 15 is laminated on the first build-up conductor layer 16A. At this time, the first buildup layer 15A and the outer insulating layer 34 are laminated on the plane layer 31A. However, the material of the outer insulating layer 34 is not particularly limited, and for example, an adhesive such as an acrylic resin, an epoxy resin, or a polyimide having an elastic modulus of 1 to 10 GPa may be used.

  (8) As shown in FIG. 7B, for example, CO2 laser is irradiated from the F surface 11F side of the core substrate 11, and the plane passes through the outer insulating layer 34 and the first buildup insulating layer 15A. A cavity 30 exposing the layer 31A as a bottom surface is formed, and a part of the outer conductor circuit layer 35 is formed as an alignment mark 35M through the outer insulating layer 34 at a predetermined relative position with respect to the cavity 30. A positioning opening 34A to be exposed is formed. Here, since the distance L1 between the positioning opening 34A and the outer edge portion of the cavity 30 is 90 μm or more, the cavity 30 is prevented from being damaged by hitting the laser at the portion where the cavity 30 is formed. In addition, the area of the range irradiated with laser when forming the cavity 30 is smaller than the area of the plane layer 31A, and the entire bottom surface of the cavity 30 is formed only by the plane layer 31A.

  (9) The plain layer 31A exposed as the bottom surface of the cavity 30 is subjected to desmearing and roughening, and the wiring board 10 with the cavity is completed. During the desmear process, the outer conductor circuit layer 35 is protected by the outer insulating layer 34. Here, since the outer insulating layer 34 is thinner than the build-up insulating layer 15, the outer insulating layer 34 is made the minimum thickness necessary for protecting the outer conductor circuit layer 35, and the wiring board 10 with cavity is made thinner. Can be achieved. In the step (8), it is possible to shorten the time required for forming the positioning opening 34A.

  This completes the description of the method for manufacturing the wiring board 10 with a cavity. The wiring board 10 with a cavity is used for manufacturing the wiring board 100 with a built-in electronic component shown in FIG.

  As shown in FIGS. 8 and 9, the electronic component built-in wiring board 100 includes an outer build-up insulating layer 21 and an outer build-up conductor layer 22 on both the front and back surfaces of the wiring board 10 with a cavity that accommodates the electronic component 80 in the cavity 30. Has a laminated structure. The outer buildup insulating layer 21 is made of the same material as the buildup insulating layer 15 described above. The outer buildup conductor layer 22 is made of the same metal (for example, copper) as the buildup conductor layer 16. The outer buildup conductor layer 22 is connected to the first buildup conductor layer 16 </ b> A of the wiring board 10 with a cavity by a via conductor 25 penetrating the outer buildup insulating layer 21. The outer buildup insulating layer 21 has a thickness of about 15 μm, and the outer buildup conductor layer 22 has a thickness of about 15 μm. Here, the thickness of the outer buildup insulating layer 21 is defined by the distance between the upper and lower conductor layers as in the buildup insulating layer 15. The electronic component 80 is, for example, a semiconductor element, a passive component, an interposer having a wiring layer, a semiconductor element having a rewiring layer, or WLP (Wafer Level Package).

  A solder resist layer 29 is formed on the outer buildup conductor layer 22. The solder resist layer 29 constitutes an F surface 100F that is a front side surface of the electronic component built-in wiring board 100 and a B surface 100B that is a back side surface. A plurality of openings 27 are formed in the solder resist layer 29 to expose a part of the outer buildup conductor layer 22 as conductor pads 23. The thickness of the solder resist layer 29 is about 7 to 25 μm. Here, the thickness of the solder resist layer 29 is defined by the distance from the upper surface of the outer buildup conductor layer 22 to the upper surface of the solder resist layer 29.

  A plating layer 41 is formed on the conductor pad 23. The plating layer 41 on the F surface 100F side of the electronic component built-in wiring board 100 is formed in a bump shape protruding from the solder resist layer 29 (see FIG. 9).

  This completes the description of the structure of the electronic component built-in wiring board 100. Next, a method for manufacturing the electronic component built-in wiring board 100 will be described.

The electronic component built-in wiring board 100 is manufactured as follows.
(1) First, as shown in FIG. 10A, an electronic component 80 having an adhesive layer 33 applied on the bottom surface is mounted on the plain layer 31A exposed as the bottom surface of the cavity 30 of the wiring board 10, and the heat A curing process and a CZ process are performed. At this time, since the electronic component 80 is positioned with reference to the alignment mark 35M, the electronic component 80 can be accurately mounted in the cavity 30. Here, since the distance L1 between the alignment mark 35M and the outer edge of the cavity 30 is 1500 μm or less, the mounting accuracy of the electronic component 80 based on the alignment mark 35 can be improved.

  (2) The outer buildup insulating layer 21 made of the same material as the buildup insulating layer 15 is laminated and pressed on the F surface 10F and B surface 10B of the cavity wiring board 10 (see FIG. 10B). In the figure, only the F-plane 10F side is shown, and the same applies to FIG. At this time, the outside buildup insulating layer 21 is filled in the opening 34A exposing the alignment mark 35M.

  (3) As shown in FIG. 11A, laser is irradiated from the F surface 10F side and the B surface 10B side of the wiring board 10 with a cavity, and a via formation hole 45 is formed in the outer buildup insulating layer 21. The

  (4) An electroless plating process, a plating resist process, and an electrolytic plating process are performed, and a via conductor 25 is formed in the via formation hole 45 (see FIG. 11B). Further, the outer buildup conductor layer 22 is formed on the outer buildup insulating layer 21.

  (5) As shown in FIG. 12, a solder resist layer 29 is laminated on the outer buildup conductor layer 22 from both the F surface 10F side and the B surface 10B side of the wiring board 10 with cavity, and the solder resist layer In FIG. 29, an opening 27 for exposing a part of the outer buildup conductor layer 22 as a conductor pad 23 is formed by laser processing.

  (6) An electroless plating process is performed on the F-side 10F side and the B-side 10B side of the substrate 10 with the cavity to form a plating layer 41 on the conductor pad 23, and the electronic component built-in wiring shown in FIG. The plate 100 is completed.

  The above is the description regarding the manufacturing method of the electrical component built-in wiring board 100 using the wiring board 10 with a cavity. Next, the effect of the wiring board 10 with a cavity of this embodiment is demonstrated.

  According to the wiring board with cavity 10 of the present embodiment, the electronic component 80 can be received in the cavity 30 with reference to the alignment mark 35M exposed by the positioning opening 34A, and the electronic component 80 into the cavity 30 can be received. It becomes possible to improve the mounting accuracy. Further, since the positioning opening 34A is formed by laser processing, it is possible to improve the positional accuracy of the positioning opening 34A with respect to the cavity 30. Here, since the distance L1 (see FIG. 3) between the positioning opening 34A and the cavity 30 is 10 μm or more and 1500 μm or less, the positioning opening 34A is formed while improving the mounting accuracy of the electronic component 80. It becomes possible to suppress the damage of the cavity 30 at the time.

  Further, according to the method for manufacturing the wiring board with cavity 10 of the present embodiment, the positioning opening 34A is formed by using the laser used for forming the cavity 30. Therefore, the positioning opening 34A is formed when the cavity 30 is formed. It becomes possible to form.

[Other Embodiments]
The present invention is not limited to the above-described embodiment. For example, the embodiments described below are also included in the technical scope of the present invention, and various modifications are possible within the scope of the invention other than the following. It can be changed and implemented.

  (1) In the above embodiment, the alignment mark 35M has a circular shape, but may have a shape as shown in FIG. Specifically, the alignment mark 35M may have a ring shape (see FIG. 13A), a polygonal shape (see FIGS. 13B and 13C), or a cross. (Refer to FIG. 13D).

  (2) In the wiring board 10 of the above embodiment, the plane layer 31A constituting the bottom surface of the cavity 30 is formed on the second buildup conductor layer 16B located second from the outside. As shown in FIG. 14A, the outermost first buildup conductor layer 16A may be formed, or as shown in FIG. 14B, it is formed on the third third buildup conductor layer 16C from the outside. May be.

  (3) In the above embodiment, the plane layer 31 </ b> A is exposed as the bottom surface of the cavity 30. However, the build-up insulating layer 15 may be exposed as the bottom surface of the cavity 30. In this case, the cavity 30 may penetrate only the outer insulating layer 34 or may penetrate one or a plurality of build-up insulating layers 15.

  (4) In the above-described embodiment, the wiring board 10 with the cavity has the core substrate 11, but the wiring board 10 with the cavity shown in FIG. 16B does not have the core board 11. There may be. Such a wiring board 10V with a cavity is manufactured by the method shown to [1]-[5] below, for example.

  [1] As shown in FIG. 15A, a copper foil 51 with a carrier in which a copper foil 51C is laminated on the upper surface of a carrier 51K is laminated on a support substrate 50. Note that an adhesive layer (not shown) is formed between the carrier 51K and the copper foil 51C, and between the carrier 51K and the support substrate 50, and the adhesive force between the carrier 51K and the copper foil 51C is the carrier 51K. It is weaker than the adhesive force between the support substrate 50 and the support substrate 50.

  [2] A predetermined pattern of plating resist is formed on the copper foil 51C. Then, by electrolytic plating, an electrolytic plating film is formed on the portion where the plating resist is not formed, and an inner conductor layer 52 having a plane layer 31A and a conductor circuit layer 31B is formed on the copper foil 51C (FIG. 15). (See (B)).

  [3] The buildup insulating layer 15 is laminated on the inner conductor layer 52, and the buildup conductor layer 16 is laminated on the buildup insulating layer 15. At this time, an outer conductor circuit layer 35 connected to the conductor circuit layer 31B via the via 18 is formed in the buildup conductor layer 16 (see FIG. 15C).

  [4] The outer insulating layer 34 is laminated on the build-up conductor layer 16, and the cavity 30 is formed by laser processing so as to penetrate the outer insulating layer 34 and the build-up insulating layer 15 and expose the plane layer 31A as the bottom surface. In addition, a positioning opening 34A that exposes a part of the outer conductor circuit layer 35 as an alignment mark 35M is formed (see FIG. 16A).

  [5] The carrier 51K of the copper foil with carrier 51 and the support substrate 50 are peeled off, and then the copper foil 51C is removed by an etching process to complete the wiring board with cavity 10V (FIG. 16B). reference). Note that, thereafter, the steps as shown in FIGS. 9 to 12 of the above embodiment may be performed on the wiring board 10V with the cavity.

10,10V Cavity wiring board 15A 1st buildup insulation layer (inner insulation layer)
30 cavity 31A plane layer 34 outer insulating layer 35 outer conductor circuit layer (conductor layer)
35M alignment mark

Claims (8)

An outer insulating layer disposed outside in the thickness direction;
A cavity-containing wiring board comprising a cavity for incorporating an electronic component that opens on a surface facing the outside of the outer insulating layer,
In addition to the opening of the cavity, the outer insulating layer is formed with a positioning opening that exposes a part of the conductor layer formed under the outer insulating layer as an alignment mark. In the wiring board with a cavity of Claim 1,
The positioning opening is formed by laser processing,
The distance between the positioning opening and the outer edge of the cavity is 10 μm or more. The wiring board with a cavity according to claim 1 or 2, wherein a distance between the positioning opening and an outer edge portion of the cavity is 1500 µm or less. In the wiring board with a cavity according to any one of claims 1 to 3,
An inner insulating layer formed under the conductor layer;
A plain layer formed under the inner insulating layer,
The cavity penetrates the outer insulating layer and the inner insulating layer and exposes the plain layer as a bottom surface. In the wiring board with a cavity of Claim 4,
The outer insulating layer is made of the same material as the inner insulating layer. In the wiring board with a cavity according to claim 4 or 5,
The outer insulating layer is thinner than the inner insulating layer. Forming an inner insulating layer disposed inside in the thickness direction;
Forming a conductor layer on the inner insulating layer;
Forming an outer insulating layer disposed outside on the inner insulating layer and the conductor layer;
Forming a cavity for incorporating an electronic component that penetrates the outer insulating layer and the inner insulating layer and opens on a surface facing the outer side of the outer insulating layer, and a method of manufacturing a wiring board with a cavity, comprising:
In addition to the opening of the cavity, a positioning opening that exposes a part of the conductor layer as an alignment mark is formed in the outer insulating layer. In the wiring board with a cavity of Claim 8,
Both the formation of the cavity and the formation of the positioning opening are performed by laser processing,
The positioning opening is formed by a laser used to form the cavity.

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