JP2013102087A - Semiconductor device having super junction structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a super junction structure which prevents an increase in a leakage current and reduction in a breakdown voltage even when a reverse bias is applied to the semiconductor device under a high-temperature environment for a long period of time.SOLUTION: A semiconductor device 100 having a super junction structure includes: an ntype semiconductor layer (first conductivity type semiconductor layer) 114; a plurality of columnar embedded layers 118 formed in an active region R1; a Schottky barrier metal layer (first electrode layer) 132 formed in the active region R1; a plurality of guard ring layers (annular columnar embedded layers) 124 formed in a breakdown voltage region R2; and an insulating layer 130 formed in the breakdown voltage region R2 and a peripheral region R3. The semiconductor device 100 having the super junction structure further includes: a second guard ring layer (second annular columnar embedded layer) 136 formed in the peripheral region R3; and an annular conductive layer 142 formed in the peripheral region R3.

Description

  The present invention relates to a semiconductor device having a super junction structure.

  A semiconductor device having a super junction structure is known (for example, see Patent Document 1). FIG. 15 is a view for explaining a semiconductor device 900 having a conventional super junction structure. FIG. 15A is a plan view of a semiconductor device 900 having a conventional super junction structure, and FIG. 15B is a cross-sectional view of the semiconductor device 900 having a conventional super junction structure. FIG.15 (b) is AA sectional drawing of Fig.15 (a). In FIG. 15A, only the columnar buried layer 918, the annular columnar buried layer 924, and the Schottky barrier metal layer 932 are shown for easy understanding.

A conventional semiconductor device 900 having a super junction structure is formed on the surface of an n ⁻ type semiconductor layer (first conductivity type semiconductor layer) 914 and the semiconductor layer 914 in the active region R1, as shown in FIG. A plurality of columnar buried layers 918 made of type silicon (second conductivity type semiconductor material), and a Schottky barrier metal layer as an anode electrode layer (on the surface of the n ⁻ type semiconductor layer 914 in the active region R1) A first electrode layer) 932, a plurality of guard rings (annular columnar buried layers) 924 made of p-type silicon formed on the surface of the n ⁻ type semiconductor layer 914 in the breakdown voltage region R2 surrounding the active region R1, a breakdown voltage region; Insulating layer 930 formed on the surface of n ⁻ type semiconductor layer 914 in peripheral region R3 surrounding R2 and breakdown voltage region R2, and cathode electrode layer 950 are provided. This is a Schottky barrier diode. In FIG. 15B, reference numeral 912 indicates an n ⁺ type semiconductor substrate, reference numeral 910 indicates a semiconductor substrate, reference numeral 920 indicates a p-type high-concentration ohmic diffusion region, and reference numeral 926 indicates a Schottky barrier metal electric field relaxation. Reference numeral 928 indicates a relay diffusion region, and reference numeral 933 indicates an anode electrode layer.

According to the conventional semiconductor device 900 having a super junction structure, a plurality of (for example, several tens) guard rings 924 are provided on the surface of the n ⁻ type silicon layer 914 in the breakdown voltage region R2 surrounding the active region. When the reverse bias is applied, the depletion layer extends from the active region R1 to the outermost peripheral portion of the breakdown voltage region R2, so that the breakdown voltage of the semiconductor device having a super junction structure can be increased.

JP 2004-6595 A

  However, according to the research of the inventors of the present invention, it has been found that the conventional semiconductor device 900 having a super junction structure has the following problems. That is, the conventional semiconductor device 900 having a super junction structure has a problem that when a reverse bias is applied to the semiconductor device for a long time in a high temperature environment, a leakage current increases or a breakdown voltage decreases. I understood.

  Therefore, the present invention has been made to solve such problems, and even when a reverse bias is applied to a semiconductor device for a long time in a high temperature environment, the leakage current increases or the breakdown voltage decreases. An object of the present invention is to provide a semiconductor device having a super-junction structure that does not occur.

[1] A semiconductor device having a super junction structure according to the present invention includes a first conductive type semiconductor layer and a plurality of columnar embedded layers formed on the surface of the semiconductor layer in an active region and made of a second conductive type semiconductor material. A first electrode layer formed on the surface of the semiconductor layer in the active region, and a plurality of second conductive type semiconductor materials formed on the surface of the semiconductor layer in the breakdown voltage region surrounding the active region. A semiconductor device having a super junction structure, comprising: an annular columnar buried layer; and an insulating layer formed on a surface of the semiconductor layer in a peripheral region surrounding the breakdown voltage region and the breakdown voltage region, in the peripheral region A second annular columnar buried layer made of a semiconductor material of the second conductivity type, formed on the surface of the semiconductor layer, and an annular formed on the insulating layer in the peripheral region; And further comprising a conductive layer.

[2] In the semiconductor device having a super junction structure according to the present invention, the insulating layer has an opening in a region where the second annular columnar buried layer is formed in the peripheral region, and the annular conductive layer Is preferably connected to the second annular columnar buried layer through the opening.

[3] In the semiconductor device having a super junction structure according to the present invention, a second conductivity type high concentration diffusion region is formed in the vicinity of the surface of the second annular columnar buried layer connected to the annular conductive layer. It is preferable.

[4] In the semiconductor device having a super junction structure according to the present invention, the insulating layer has an opening in a region where the second annular columnar buried layer is not formed in the peripheral region, and the annular conductive layer Is preferably connected to the semiconductor layer through the opening.

[5] In the semiconductor device having a super junction structure according to the present invention, a high-concentration diffusion region of the first conductivity type is formed on the surface of the semiconductor layer in the region connected to the annular conductive layer. Is preferred.

[6] In the semiconductor device having a super junction structure according to the present invention, the width of the second annular conductive layer extending to the outer peripheral side from the outermost second annular columnar embedded layer is the second annular columnar embedded layer. It is preferable that it is larger than the depth dimension.

[7] In the semiconductor device having a super junction structure according to the present invention, it is preferable that a plurality of annular conductive layers are provided as the annular conductive layer.

[8] In the semiconductor device having a super junction structure according to the present invention, it is preferable that a plurality of second annular columnar embedded layers are provided as the second annular columnar embedded layer.

[9] In the semiconductor device having a super junction structure of the present invention, the annular conductive layer is preferably connected to the innermost second annular columnar buried layer.

  According to the semiconductor device having a super junction structure of the present invention, as is apparent from Examples 1 and 2 described later, even when a reverse bias is applied to the semiconductor device for a long time in a high temperature environment, a leakage current is generated. It does not increase or the pressure resistance decreases.

  Although details of the mechanism are not clear at this stage, as shown in FIG. 5 to be described later, in the case of a semiconductor device having a super junction structure of the present invention, the second annular columnar buried layer and the second And an annular conductive layer formed above the annular columnar buried layer, the first electrode layer and the annular conductive layer function as two electrodes of the capacitor at the time of reverse bias, respectively. Under such conditions, when a reverse bias is applied to the semiconductor device for a long time, mobile ions that may be generated on the surface of the insulating layer are trapped by either electrode due to the potential difference between the first electrode layer and the annular conductive layer. As a result, the inventors of the present invention speculate that the leakage current does not increase or the breakdown voltage does not decrease due to the presence of mobile ions.

1 is a view for explaining a semiconductor device 100 having a super junction structure according to Embodiment 1. FIG. 6 is a view for explaining a method of manufacturing the semiconductor device 100 having a super junction structure according to Embodiment 1. FIG. 6 is a view for explaining a method of manufacturing the semiconductor device 100 having a super junction structure according to Embodiment 1. FIG. 6 is a view for explaining a method of manufacturing the semiconductor device 100 having a super junction structure according to Embodiment 1. FIG. 6 is a view for explaining the operation and effect of the semiconductor device 100 having a super junction structure according to Embodiment 1. FIG. 4 is a cross-sectional view of a semiconductor device 100a having a super junction structure according to Embodiment 2. FIG. It is sectional drawing of the semiconductor device 100b which has a super junction structure concerning Embodiment 3. FIG. It is sectional drawing of the semiconductor device 100c which has a super junction structure concerning Embodiment 4. It is sectional drawing of the semiconductor device 100d which has a super junction structure concerning Embodiment 5. FIG. It is sectional drawing of the semiconductor device 100e which has a super junction structure concerning Embodiment 6. 10 is a cross-sectional view of a semiconductor device 200 having a super junction structure according to Embodiment 7. FIG. FIG. 10 is a cross-sectional view of a semiconductor device 300 having a super junction structure according to an eighth embodiment. It is a figure which shows the evaluation result of Example 1. FIG. It is a figure which shows the evaluation result of Example 2. It is a figure shown in order to demonstrate the semiconductor device 900 which has the conventional super junction structure.

  Hereinafter, a semiconductor device having a super junction structure according to the present invention will be described based on embodiments shown in the drawings.

[Embodiment 1]
1. Configuration of Semiconductor Device 100 Having Super Junction Structure According to Embodiment 1 First, the configuration of the semiconductor device 100 having a super junction structure according to Embodiment 1 will be described.
FIG. 1 is a diagram for explaining a semiconductor device 100 having a super junction structure according to the first embodiment. FIG. 1A is a plan view of a semiconductor device 100 having a super junction structure according to the first embodiment, and FIG. 1B is a cross-sectional view of the semiconductor device 100 having a super junction structure according to the first embodiment. FIG.1 (b) is AA sectional drawing of Fig.1 (a). In FIG. 1A, for easy understanding, the columnar buried layer 118, the annular columnar buried layer 124, the second annular columnar buried layer 136, the Schottky barrier metal layer 132, and the annular conductive layer. Only 142 is shown.

  A semiconductor device 100 having a super junction structure according to Embodiment 1 is a Schottky barrier diode having a super junction structure, and as shown in FIG. 1A, an active region R1 and a breakdown voltage region R2 surrounding the active region R1. And a peripheral region R3 surrounding the withstand voltage region R2.

Then, as shown in FIG. 1B, the semiconductor device 100 having a super junction structure according to the first embodiment includes an n ⁻ type semiconductor layer (first conductivity type semiconductor layer) 114 and an n ⁻ in the active region R1. Formed on the surface of the n type semiconductor layer 114 and formed on the surface of the n ⁻ type semiconductor layer 114 in the active region R1 and the plurality of columnar buried layers 118 made of p type silicon (second conductivity type semiconductor material). A plurality of guard rings (p-type silicon) formed on the surface of a Schottky barrier metal layer (first electrode layer) 132 as an anode electrode layer and the n ⁻ type semiconductor layer 114 in the breakdown voltage region R2 surrounding the active region R1. an annular columnar buried layer) 124, n in the peripheral region R3 that surrounds the withstand voltage region R2 and the withstand voltage region R2 ^- -type semiconductor layer 114 insulating layer formed on a surface of 13 When, and a cathode electrode layer 150, a Schottky barrier diode. In FIG. 1B, reference numeral 112 denotes an n ⁺ type semiconductor substrate, reference numeral 110 denotes a semiconductor substrate, reference numeral 120 denotes a p-type high-concentration ohmic diffusion region, and reference numeral 126 denotes a Schottky barrier metal electric field relaxation. Reference numeral 128 denotes a relay diffusion region, and reference numeral 133 denotes an anode electrode layer.

The semiconductor device 100 having the super junction structure according to the first embodiment is formed on the surface of the n ⁻ type semiconductor layer 114 in the peripheral region R3, and includes a second annular columnar embedded layer 136 made of a p-type semiconductor material, And an annular conductive layer 142 formed on the insulating layer 130 in the region R3.

  In the semiconductor device 100 having the super junction structure according to the first embodiment, the insulating layer 130 has the opening 140 in the region where the second annular columnar buried layer 136 is formed in the peripheral region R3, and the annular conductive layer. 142 is connected to the second annular columnar buried layer 136 through the opening 140.

  In the semiconductor device 100 having the super junction structure according to the first embodiment, a p-type high concentration diffusion region (second conductivity type) is formed near the surface of the second annular columnar buried layer 136 connected to the annular conductive layer 142. High concentration diffusion region) 138 is formed.

  In the semiconductor device 100 having the super junction structure according to the first embodiment, the width dimension L of the annular conductive layer 142 extending to the outer peripheral side from the outermost second annular columnar embedded layer 136 is equal to the second annular columnar embedded layer. It is larger than the depth dimension D of 136 (refer FIG.1 (b)).

n ^- -type semiconductor layer 114, which has been formed by epitaxial growth on top of the ^{n +} -type semiconductor substrate 112, ^{n +} -type semiconductor substrate 112 and the n ^- constituting the semiconductor substrate 110 at type semiconductor layer 114 . The thickness of the n ⁻ type semiconductor layer 114 is, for example, 6 μm to 70 μm, and the impurity concentration of the n ⁻ type semiconductor layer is, for example, 2 × 10 ¹⁴ cm ^{−3 to} 5 × 10 ¹⁶ cm ⁻³ .

The columnar buried layer 118 is made of a p-type semiconductor material (second conductivity type semiconductor material) formed by epitaxial growth inside the first trench 116 formed in the active region R1 in the n ⁻ type semiconductor layer 114. The number of the columnar buried layers 118 can be appropriately set according to the purpose of use and the structure. The impurity concentration of the p-type semiconductor material is, for example, 2 × 10 ¹⁴ cm ^{−3 to} 5 × 10 ¹⁶ cm ⁻³ .

  The depth of the columnar embedded layer 118 is, for example, 5 μm to 50 μm, and the width is, for example, 0.5 μm to 5 μm. The columnar buried layers 118 are formed in parallel at the first interval d1. The first interval d1 is, for example, 1 μm to 15 μm.

The annular columnar buried layer 124 is made of a p-type semiconductor material (second conductivity type semiconductor material) formed by epitaxial growth inside the second trench 122 formed in the breakdown voltage region R2 in the n ⁻ type semiconductor layer 114. The number of the annular columnar embedded layers 124 is, for example, 5 to 50, and can be appropriately set according to the purpose of use and the structure. The impurity concentration of the p-type semiconductor material is, for example, 2 × 10 ¹⁴ cm ^{−3 to} 5 × 10 ¹⁶ cm ⁻³ .

  The depth of the annular columnar embedded layer 124 is, for example, 5 μm to 50 μm, and the width is, for example, 0.5 μm to 5 μm. The annular columnar embedded layers 124 are formed in parallel at the first interval d1. The first interval d1 is, for example, 1 μm to 15 μm.

The second annular columnar buried layer 136 is made of a p-type semiconductor material (second conductivity type semiconductor material) formed by epitaxial growth inside the third trench 134 formed in the peripheral region R3 in the n ⁻ type semiconductor layer 114. The number of the second annular columnar embedded layers 136 is, for example, 1 to 10, but can be appropriately set according to the purpose of use and the structure. The impurity concentration of the p-type semiconductor material is, for example, 2 × 10 ¹⁴ cm ^{−3 to} 5 × 10 ¹⁶ cm ⁻³ .

  The depth of the second annular columnar embedded layer 136 is, for example, 5 μm to 50 μm, and the width is, for example, 0.5 μm to 5 μm. The annular columnar embedded layers 124 are formed in parallel at the first interval d1. The first interval d1 is, for example, 1 μm to 15 μm.

The insulating layer 130 is made of a silicon oxide film. The Schottky barrier metal layer 132 forms a Schottky junction with the n ⁻ type semiconductor layer 114, and forms an ohmic junction with the columnar buried layer 118. The material of the Schottky barrier metal layer 132 is, for example, platinum, and the thickness of the Schottky barrier metal layer 132 is, for example, 10 nm. An anode electrode layer 133 is formed above the Schottky barrier metal layer 132. The material of the anode electrode layer 133 is a metal (for example, aluminum), and the thickness of the anode electrode layer 133 is, for example, 3000 nm. The material of the annular conductive layer 142 is a metal (for example, aluminum), and the thickness of the annular conductive layer 142 is, for example, 3000 nm. The cathode electrode layer 150 is formed by evaporating a metal (for example, nickel) as an electrode material on the back surface of the semiconductor substrate 110. The thickness of the cathode electrode layer 150 is 2000 nm, for example.

2. Method of Manufacturing Semiconductor Device 100 Having Super Junction Structure According to Embodiment 1 Next, a method of manufacturing semiconductor device 100 having a super junction structure according to Embodiment 1 will be described along the following steps.
2 to 4 are views for explaining a method of manufacturing a semiconductor device having a super junction structure according to the first embodiment. 2A to FIG. 2D, FIG. 3A to FIG. 3D, and FIG. 4A to FIG. 4D are process diagrams.

1. Semiconductor body preparation step First, the ^{n +} -type semiconductor substrate 112, n on the surface side was formed by epitaxial growth of the ^{n +} -type semiconductor substrate 112 ^- preparing a semiconductor substrate 110 having a type semiconductor layer 114 (FIGS. 2 (a) reference.). As the n ⁺ type semiconductor substrate 112, for example, a silicon substrate can be used, but a substrate made of silicon carbide SiC or gallium nitride GaN may be used.

2. Next, the columnar buried layer 118 is formed in the active region R1, the annular columnar buried layer 124 is formed in the breakdown voltage region R2, and the second annular columnar buried layer 136 is formed in the peripheral region R3. Form. Each columnar buried layer forming step includes a trench forming step, each columnar buried layer forming step, and a p-type high concentration diffusion region forming step (see FIGS. 2B to 3D).

2-1. Trench Formation Step In the trench formation step, first, an oxide film M1 serving as a trench mask is formed on the n ⁻ type semiconductor layer 114 by thermally oxidizing the n ⁻ type semiconductor layer 114 (see FIG. 2B). ). Subsequently, a resist film (thickness: 0.8 μm, for example) (not shown) is formed, and a photographic process is performed, whereby the columnar embedded layer 118, the annular columnar embedded layer 124, and the second annular columnar embedded layer 136 are formed. An opening is provided at the formation position of and the insulating film M in the opening is removed by dry etching (see FIG. 2C). Next, the resist film is removed, and then the n ⁻ type semiconductor layer 114 is dry-etched using the insulating film M as a mask, so that the first trench 116, the second trench 122, and the third trench are formed on the surface of the n ⁻ type semiconductor layer 114. A trench 134 is formed (see FIG. 2D).

2-2. Each columnar buried layer forming step In each columnar buried layer forming step, the inner surface of the first trench 116, the second trench 122, and the third trench 134 is subjected to a trench forming step by chemical dry etching, sacrificial oxidation, hydrogen annealing, or the like. After removing the damaged layer by dry etching, a p-type single crystal semiconductor material is epitaxially grown to a height position exceeding the height position of the surface of the insulating film M while introducing a dopant gas containing a p-type impurity (FIG. 3). (See (a).) Thereafter, the formed cap portion is polished to the surface of the insulating film M by CMP, and then the p-type single crystal semiconductor material embedded in the opening of the insulating film M is applied to the bottom surface of the insulating film M. Dry etching is performed using M as a mask. Thereafter, the insulating film M is removed by wet etching (see FIG. 3B).

2-3. Step of forming p-type high-concentration diffusion region Next, openings are formed in regions corresponding to the p-type high-concentration ohmic diffusion region 120, the Schottky barrier metal electric field relaxation region 126, the relay diffusion region 128, and the p-type high-concentration diffusion region 138. A mask M2 is formed, and a p-type impurity (for example, boron ions) is introduced into the surface of the semiconductor substrate 110 through the mask M2 by ion implantation (see FIG. 3C).
Thereafter, a heat treatment is performed on the semiconductor substrate 110 to form a p-type high-concentration ohmic diffusion region 120, a Schottky barrier metal electric field relaxation region 126, a relay diffusion region 128, and a p-type high-concentration diffusion region 138 (FIG. 3D )reference.).

3. Next, after forming a silicon oxide film having a thickness of 500 nm by the CVD method, the silicon oxide film is etched by using the mask M3 having an opening corresponding to the active region R1 and the opening 140. The insulating film 130 is formed by removing the oxide film (see FIG. 4A).

4). Step of forming Schottky barrier metal layer Next, by sputtering, for example, a platinum film having a thickness of 10 nm is formed from the surface side of the semiconductor substrate 110 and patterned into a predetermined shape. A key barrier metal layer 132 is formed (see FIG. 4B).

5. Next, an anode electrode layer 133 and an annular conductive layer 142 are formed by forming an aluminum film having a thickness of, for example, 3000 nm by sputtering from the surface side of the semiconductor substrate 110 and patterning it into a predetermined shape. (See FIG. 4 (c)).

6). Next, the cathode electrode layer 150 is formed by forming, for example, a nickel film having a thickness of 500 nm on the back surface side of the n ⁺ type semiconductor substrate 112 located on the back surface side of the semiconductor substrate 110 by sputtering. It is formed (see FIG. 4D).

  By sequentially performing the above steps, the semiconductor device 100 having the super junction structure according to the first embodiment can be manufactured.

3. Effect of Semiconductor Device 100 Having Super Junction Structure According to Embodiment 1 According to semiconductor device 100 having a super junction structure according to Embodiment 1, as is apparent from Examples 1 and 2 described later, under a high temperature environment. Even when a reverse bias is applied to the semiconductor device for a long time, the leakage current does not increase or the breakdown voltage does not decrease.

  FIG. 5 is a diagram for explaining the operation and effect of the semiconductor device 100 having the super junction structure according to the first embodiment. FIG. 5A is a diagram showing the movement of mobile ions at the time of reverse bias in the semiconductor device 100 having the super junction structure according to the first embodiment, and FIG. 5B is a semiconductor device 900 having a conventional super junction structure. It is a figure which shows the motion of the movable ion at the time of reverse bias in.

  Although details of the mechanism are not clear at this stage, in the case of the semiconductor device 100 having the super junction structure according to the first embodiment, the second annular columnar embedded layer 136 and the second annular columnar embedded layer 136 Since it further includes an annular conductive layer 142 formed above, the Schottky barrier metal layer 132 and the annular conductive layer 142 function as two electrodes of the capacitor, respectively, during reverse bias. Therefore, mobile ions that may be generated on the surface of the insulating layer 130 when a reverse bias is applied to the semiconductor device for a long time in a high temperature environment, form an annular shape with the Schottky barrier metal layer 132 as shown in FIG. Due to the potential difference with the conductive layer 142, it is trapped by either electrode (negative mobile ions are trapped by the annular conductive layer 142 and positive mobile ions are trapped by the Schottky barrier metal layer 132), and as a result. The inventors of the present invention speculate that the leakage current does not increase or the breakdown voltage does not decrease due to the presence of mobile ions.

  Further, according to the semiconductor device 100 having the super junction structure according to the first embodiment, the annular conductive layer 142 is connected to the second annular columnar embedded layer 136 having a potential close to the potential of the cathode electrode layer 150 at the time of reverse bias. Therefore, a large potential difference is generated between the Schottky barrier metal layer 132 and the annular conductive layer 142. As a result, the mobile ions are surely captured by either electrode due to a large potential difference generated between the Schottky barrier metal layer 132 and the annular conductive layer 142.

  In addition, according to the semiconductor device 100 having the super junction structure according to the first embodiment, a p-type high concentration diffusion region (first region) is formed in the vicinity of the surface of the second annular columnar buried layer 136 connected to the annular conductive layer 142. 2), the resistance between the annular conductive layer 142 and the second annular columnar buried layer 136 can be made extremely small, and a Schottky barrier metal is formed. The potential difference generated between the layer 132 and the annular conductive layer 142 is not impaired.

  Furthermore, according to the semiconductor device 100 having the super junction structure according to the first embodiment, the width dimension of the annular conductive layer 142 extending to the outer peripheral side from the outermost second columnar embedded layer 136 is the second annular columnar embedded. Since it is larger than the depth dimension of the layer 136, the annular conductive layer 142 is disposed above the depletion layer extending from the outermost second annular columnar buried layer 136 to the outer peripheral side, and the outermost second Since the potential of the upper portion of the depletion layer extending from the annular columnar buried layer 136 to the outer peripheral side is fixed to a potential close to the potential of the cathode electrode layer 150, it becomes a stable potential that is not affected by mobile ions.

[Embodiment 2]
FIG. 6 is a cross-sectional view of a semiconductor device 100a having a super junction structure according to the second embodiment.

  The semiconductor device 100a having the super junction structure according to the second embodiment has basically the same configuration as the semiconductor device 100 having the super junction structure according to the first embodiment. However, as shown in FIG. The semiconductor device 100 is different from the semiconductor device 100 having the super junction structure according to the first embodiment in that the annular conductive layers 142 and 142a are provided.

  As described above, the semiconductor device 100a having the super junction structure according to the second embodiment is different from the semiconductor device 100 having the super junction structure according to the first embodiment in that the semiconductor device 100a has a plurality of annular conductive layers 142 and 142a. Includes the second annular columnar embedded layer 136, and the annular conductive layer 142 and the annular conductive layer 142a formed above the second annular columnar embedded layer 136. Therefore, the super junction structure according to the first embodiment is provided. As in the case of the semiconductor device 100 having the above, even when a reverse bias is applied to the semiconductor device for a long time in a high temperature environment, the leakage current does not increase or the breakdown voltage does not decrease.

  In addition, according to the semiconductor device 100a having the super junction structure according to the second embodiment, since the two annular conductive layers 142 and 142a are provided, it is possible to efficiently capture mobile ions.

  In addition, in the semiconductor device 100a having the super junction structure according to the second embodiment, two annular conductive layers are provided as the annular conductivity type layers, but the present invention is not limited to this. For example, three or more annular conductive layers may be provided as the annular conductivity type layer.

  The semiconductor device 100a having the super junction structure according to the second embodiment is the same as the semiconductor device 100 having the super junction structure according to the first embodiment, except that the semiconductor device 100a has two annular conductive layers 142 and 142a. Since the semiconductor device 100 has the configuration, the semiconductor device 100 having the super junction structure according to the first embodiment has a corresponding effect.

[Embodiment 3]
FIG. 7 is a cross-sectional view of a semiconductor device 100b having a super junction structure according to the third embodiment.

  The semiconductor device 100b having the super junction structure according to the third embodiment has basically the same configuration as that of the semiconductor device 100 having the super junction structure according to the first embodiment. However, as shown in FIG. This is different from the semiconductor device 100 having the super junction structure according to the first embodiment in that no opening is formed.

  As described above, the semiconductor device 100b having the super junction structure according to the third embodiment is different from the semiconductor device 100 having the super junction structure according to the first embodiment in that an opening is not formed in the insulating layer. However, as in the semiconductor device 100 having the super junction structure according to the first embodiment, the second annular columnar embedded layer 136 and the annular conductive layer 142b formed above the second annular columnar embedded layer 136 are included. Thus, even when a reverse bias is applied to the semiconductor device for a long time in a high temperature environment, the leakage current does not increase or the breakdown voltage does not decrease.

  In the semiconductor device 100b having the super junction structure according to the third embodiment, since the opening is not formed in the insulating layer, the annular conductive layer 142b does not have the same potential as the second annular columnar embedded layer 136. Since the annular conductive layer 142b is capacitively coupled to the second annular columnar buried layer 136 via the insulating layer 130a, as in the case of the semiconductor device 100 having the super junction structure according to the first embodiment, A large potential difference is generated between the Schottky barrier metal layer 132 and the annular conductive layer 142, and this is generated on the surface of the insulating layer when a reverse bias is applied to the semiconductor device for a long time in a high temperature environment. One mobile ion is applied to either electrode due to the potential difference between the Schottky barrier metal layer 132 and the annular conductive layer 142. Is caught, the result, it is unnecessary to withstand or increase leakage current due to the presence of mobile ions is lowered.

  The semiconductor device 100b having the super junction structure according to the third embodiment has the same configuration as that of the semiconductor device 100 having the super junction structure according to the first embodiment, except that an opening is not formed in the insulating layer. Therefore, the semiconductor device 100 having the super junction structure according to the first embodiment has a corresponding effect.

[Embodiment 4]
FIG. 8 is a cross-sectional view of a semiconductor device 100c having a super junction structure according to the fourth embodiment.

The semiconductor device 100c having the super junction structure according to the fourth embodiment basically has the same configuration as the semiconductor device 100 having the super junction structure according to the first embodiment, but the annular conductive layer 142c is interposed through the opening 140a. This is different from the semiconductor device 100 having the super junction structure according to the first embodiment in that the n ⁻ type semiconductor layer 114 is connected. That is, in the semiconductor device 100c having the super junction structure according to the fourth embodiment, as shown in FIG. 8, the annular conductive layer 142c is an opening formed in a region where the second annular columnar buried layer 136 is not formed. The n ⁻ type semiconductor layer 114 is connected via the portion 140a. An n ⁺ type high concentration diffusion region 146 is formed on the surface of the n ⁻ type semiconductor layer 114 in the region connected to the annular conductive layer 142c.

As described above, the semiconductor device 100c having the super junction structure according to the fourth embodiment is similar to the super device according to the first embodiment in that the annular conductive layer 142c is connected to the n ⁻ type semiconductor layer 114 through the opening 140a. Unlike the case of the semiconductor device 100 having the junction structure, as in the case of the semiconductor device 100 having the super junction structure according to the first embodiment, the second annular columnar embedded layer 136 and the second annular columnar embedded layer are provided. And an annular conductive layer 142c formed above the layer 136, the annular conductive layer 142c is fixed at a potential close to the cathode electrode 150 and is generated between the Schottky barrier metal layer 132 and the annular conductive layer 142c. The mobile potential is trapped by the applied potential difference, so the semiconductor device can be reverse-charged for a long time in a high-temperature environment. Even when the bias is applied, the leakage current does not increase or the breakdown voltage does not decrease.

The semiconductor device 100c having the super junction structure according to the fourth embodiment is related to the first embodiment except that the annular conductive layer 142c is connected to the n ⁻ type semiconductor layer 114 through the opening 140a. Since the semiconductor device 100 has the same configuration as that of the semiconductor device 100 having the super junction structure, the semiconductor device 100 having the super junction structure according to the first embodiment has a corresponding effect.

[Embodiment 5]
FIG. 9 is a cross-sectional view of a semiconductor device 100d having a super junction structure according to the fifth embodiment.

  The semiconductor device 100d having the super junction structure according to the fifth embodiment has basically the same configuration as the semiconductor device 100 having the super junction structure according to the first embodiment, but is formed with the second annular columnar embedded. The number of layers 136 is different from that of the semiconductor device 100 having the super junction structure according to the first embodiment. That is, in the semiconductor device 100d having the super junction structure according to the fifth embodiment, as shown in FIG. 9, one second annular columnar buried layer 136 is formed.

  As described above, the semiconductor device 100d having the super junction structure according to the fifth embodiment is different from the semiconductor device 100 having the super junction structure according to the first embodiment in that the number of second annular columnar embedded layers 136 formed is the same as that of the semiconductor device 100 having the super junction structure. As in the case of the semiconductor device 100 having the super junction structure according to the first embodiment, the second annular columnar embedded layer 136 and the annular conductive layer formed above the second annular columnar embedded layer 136 are different. Since the layer 142d is further provided, the leakage current does not increase or the breakdown voltage does not decrease even when a reverse bias is applied to the semiconductor device for a long time in a high temperature environment.

  The semiconductor device 100d having the super junction structure according to the fifth embodiment is different from the semiconductor device 100 having the super junction structure according to the first embodiment except in the number of the second annular columnar embedded layers 136 formed. Since the semiconductor device 100 has the same configuration, the semiconductor device 100 having the super junction structure according to the first embodiment has a corresponding effect.

[Embodiment 6]
FIG. 10 is a cross-sectional view of a semiconductor device 100e having a super junction structure according to the sixth embodiment.

  The semiconductor device 100e having the super junction structure according to the sixth embodiment has basically the same configuration as the semiconductor device 100d having the super junction structure according to the fifth embodiment, but the region where the annular conductive layer 142d is formed. Is different from the semiconductor device 100d having the super junction structure according to the fifth embodiment in that a third annular columnar embedded layer 136a different from the second annular columnar embedded layer 136 is formed on the outer side of the semiconductor device 100d. . That is, in the semiconductor device 100e having a super junction structure according to the sixth embodiment, as shown in FIG. 10, an annular conductive layer 142d (located above one second annular columnar embedded layer 136) is formed. Two third annular columnar buried layers 136a different from the second annular columnar buried layer 136 are formed on the outer side of the region.

  As described above, in the semiconductor device 100e having the super junction structure according to the sixth embodiment, the third annular columnar buried layer different from the second annular columnar buried layer 136 is further outside the region where the annular conductive layer 142d is formed. Unlike the case of the semiconductor device 100d having the super junction structure according to the fifth embodiment in that the buried layer 136a is formed, as in the case of the semiconductor device 100d having the super junction structure according to the fifth embodiment, Since the semiconductor device further includes a second annular columnar buried layer 136 and an annular conductive layer 142d formed above the second annular columnar buried layer 136, a reverse bias is applied to the semiconductor device for a long time in a high temperature environment. Even in this case, the leakage current does not increase or the breakdown voltage does not decrease.

  Further, according to the semiconductor device 100e having a super junction structure according to the sixth embodiment, the third annular columnar buried layer different from the second annular columnar buried layer 136 is further outside the region where the annular conductive layer 142d is formed. Since the buried layer 136a is formed, the electric field in the vicinity of the second annular columnar buried layer 136 can be relaxed and the breakdown voltage is stabilized.

  Note that the semiconductor device 100d having the super junction structure according to the sixth embodiment has a third annular columnar buried layer separate from the second annular columnar buried layer 136 on the outer side of the region where the annular conductive layer 142d is formed. The semiconductor device 100d having the super junction structure according to the fifth embodiment has the same configuration as that of the semiconductor device 100d having the super junction structure according to the fifth embodiment except for the point where the 136a is formed. Of which, it has a corresponding effect.

[Embodiment 7]
FIG. 11 is a cross-sectional view of a semiconductor device 200 having a super junction structure according to the seventh embodiment. As shown in FIG. 11, a semiconductor device 200 having a super junction structure according to the seventh embodiment includes an n ⁻ type semiconductor layer (first conductivity type semiconductor layer) 214 and an n ⁻ type semiconductor layer 214 in the active region R1. A plurality of columnar buried layers 218 formed on the surface and made of a p-type semiconductor material (second conductivity type semiconductor material), and a p + -type diffusion layer 220 formed on the surface of the n ⁻ -type semiconductor layer 214 in the active region R1. And an anode electrode layer (first electrode layer) 232 formed on the surface of the n ⁻ type semiconductor layer 214 in the active region R1, and a surface of the n ⁻ type semiconductor layer 214 in the breakdown voltage region R2 surrounding the active region R1. is, a plurality of guard rings (annular columnar buried layer) 224 made of p-type semiconductor material, in the peripheral region R3 that surrounds the withstand voltage region R2 and the withstand voltage region R2 n ^- -type semiconductor An insulating layer 230 formed on the surface of 214, the cathode electrode layer 250, n in the peripheral region R3 ^- are formed on the surface of the type semiconductor layer 214, a second annular columnar buried layer 236 made of p-type semiconductor material And a ring-shaped conductive layer 242 formed on the insulating layer 230 in the peripheral region R3. In FIG. 11, reference numeral 212 indicates an n ⁺ type semiconductor substrate, reference numeral 210 indicates a semiconductor substrate, reference numerals 216, 222 and 234 indicate grooves, and reference numeral 220 indicates a p-type high-concentration ohmic diffusion region. , 226 indicates an anode electrode electric field relaxation region, and 228 indicates a relay diffusion region.

  As described above, the semiconductor device 200 having the super junction structure according to the seventh embodiment is different from the semiconductor device 100 having the super junction structure according to the first embodiment in that it is a pn diode. Since the buried layer 236 and the annular conductive layer 242 formed above the second annular columnar buried layer 236 are provided, as in the case of the semiconductor device 100 having the super junction structure according to the first embodiment, the temperature is high. Even when a reverse bias is applied to the semiconductor device for a long time under the environment, the leakage current does not increase or the breakdown voltage does not decrease.

  The semiconductor device 200 having the super junction structure according to the seventh embodiment has the same configuration as that of the semiconductor device 100 having the super junction structure according to the first embodiment except that the semiconductor device 200 is a pn diode. 1 has a corresponding effect among the effects of the semiconductor device 100 having the super junction structure according to 1.

[Embodiment 8]
FIG. 12 is a cross-sectional view of a semiconductor device 300 having a super junction structure according to the eighth embodiment. As shown in FIG. 12, the semiconductor device 300 having the super junction structure according to the eighth embodiment includes an n ⁻ type semiconductor layer (first conductivity type semiconductor layer) 314 and an n ⁻ type semiconductor layer 314 in the active region R1. A plurality of columnar buried layers 318 formed on the surface and made of p-type semiconductor material (second conductivity type semiconductor material), and a p-type body region 360 formed on the surface of the n ⁻ type semiconductor layer 314 in the active region R1. , N ⁺ -type source region 362 and p ⁺ -type contact region 364 formed on the surface of p-type body region 360, gate insulating layer 372 formed on the surface of n ⁻ -type semiconductor layer 314 in active region R1, and gate The electrode layer 370, the interlayer insulating layer 374, the source electrode layer (first electrode layer) 332, and the n ⁻ type semiconductor layer 314 in the breakdown voltage region R2 surrounding the active region R1 A plurality of guard rings (annular columnar buried layers) 324 made of p-type semiconductor material, and on the surface of the n ⁻ type semiconductor layer 314 in the breakdown voltage region R2 and the peripheral region R3 surrounding the breakdown voltage region R2. An insulating layer 330 formed, a drain electrode layer 350, a second annular columnar buried layer 336 made of a semiconductor material of the second conductivity type and formed on the surface of the n ⁻ type semiconductor layer 314 in the peripheral region R3; The power MOSFET includes an annular conductive layer 342 formed on the insulating layer 330 in the region R3. In FIG. 12, reference numeral 312 indicates an n ⁺ type semiconductor substrate, reference numeral 310 indicates a semiconductor substrate, reference numerals 316, 322 and 334 indicate grooves, reference numeral 326 indicates a source electrode electric field relaxation region, reference numeral Reference numeral 328 denotes a relay diffusion area.

  As described above, the semiconductor device 300 having the super junction structure according to the eighth embodiment differs from the semiconductor device 100 having the super junction structure according to the first embodiment in that it is a power MOSFET. Since the buried layer 336 and the annular conductive layer 342 formed above the second annular columnar buried layer 336 are provided, as in the semiconductor device 100 having the super junction structure according to the first embodiment, Even when a reverse bias is applied to the semiconductor device for a long time in a high temperature environment, the leakage current does not increase or the breakdown voltage does not decrease.

  The semiconductor device 300 having the super junction structure according to the eighth embodiment has the same configuration as the semiconductor device 100 having the super junction structure according to the first embodiment except that the semiconductor device 300 is a power MOSFET. 1 has a corresponding effect among the effects of the semiconductor device 100 having the super junction structure according to 1.

[Example 1]
Example 1 is an example for explaining that according to the semiconductor device having a super junction structure of the present invention, the leakage current does not increase even when a reverse bias is applied to the semiconductor device for a long time in a high temperature environment. It is an example.

1. Sample A semiconductor device 100 having a super junction structure according to Embodiment 1 was taken as Example 1. On the other hand, a semiconductor device having a super junction structure (that is, a conventional super junction structure having a structure in which the second annular columnar embedded layer 136 and the annular conductive layer 142 are removed from the semiconductor device 100 having the super junction structure according to the first embodiment). A semiconductor device 900) having the same structure as Comparative Example 1.

2. Evaluation Method The semiconductor device 100 having the super junction structure according to the first embodiment and the semiconductor device 900 having the super junction structure according to the first comparative example are evaluated by the semiconductor device 100 having the super junction structure according to the first embodiment and the first comparative example. After preparing 10 semiconductor devices 900 each having a super junction structure according to the above and setting them in a BT tester, 300 hours with a reverse bias (250 V) applied in a high temperature environment (150 ° C.), leakage current It was performed by measuring.

3. Evaluation Results FIG. 13 is a diagram showing the evaluation results of Example 1.
As is clear from FIG. 13, in the semiconductor device 900 having the super junction structure according to Comparative Example 1, the leakage current increased from 100 times to 1000 times under the above conditions, whereas the super device according to Example 1 In the semiconductor device 100 having the junction structure, the leakage current did not increase at all even under the above conditions.

[Example 2]
Example 2 is an example showing that according to the semiconductor device having a super junction structure of the present invention, the breakdown voltage does not decrease even when a reverse bias is applied to the semiconductor device for a long time in a high temperature environment.

1. Sample A semiconductor device 100 having a super junction structure according to Embodiment 1 was taken as Example 2. On the other hand, a semiconductor device having a super junction structure (that is, having a conventional super junction structure) in which the second annular columnar buried layer 136 and the annular conductive layer 142 are removed from the semiconductor 100 having the super junction structure according to the first embodiment. The semiconductor device 900) was referred to as Comparative Example 2.

2. Evaluation Method The semiconductor device 100 having the super junction structure according to the second embodiment and the semiconductor device 900 having the super junction structure according to the second comparative example are evaluated by the semiconductor device 100 having the super junction structure according to the second embodiment and the second comparative example. Each of the semiconductor devices 900 having the super junction structure according to the above is prepared, and before being held for a long time (63 hours or 2042 hours) in a high temperature environment (150 ° C.) with a reverse bias (250 V) applied. Later, BT test evaluation was performed by measuring the withstand voltage waveform.

3. Evaluation Results FIG. 14 is a diagram showing the evaluation results of Example 2.
As is clear from FIG. 14, in the semiconductor device 900 having the super junction structure according to Comparative Example 2, the breakdown voltage decreased from 360 V to 250 V by holding for 63 hours under a high temperature reverse bias. In the semiconductor device 100 having the super junction structure according to Example 2, the withstand voltage did not decrease at all at 360 V even when held for 63 hours or 2042 hours under high temperature reverse bias.

  As mentioned above, although this invention was demonstrated based on said embodiment, this invention is not limited to said embodiment. The present invention can be implemented in various modes without departing from the spirit thereof, and for example, the following modifications are possible.

(1) Although the aluminum layer formed in the same process as the anode electrode layer 133 is used as the annular conductive layer 142 in the first embodiment, the present invention is not limited to this. For example, a platinum layer and an aluminum layer formed in the same process as the Schottky barrier metal layer 132 and the anode electrode layer 133 can also be used. Alternatively, a metal layer other than aluminum, a conductive layer other than the metal layer (for example, a polysilicon layer or a doped polysilicon layer), or the like can be used.

(2) In each of the above embodiments, the present invention has been described by taking the case where the first conductivity type is n-type and the second conductivity type is p-type as an example, but the present invention is not limited to this. . For example, the present invention can be applied to the case where the first conductivity type is p-type and the second conductivity type is n-type.

(3) In each of the first to sixth embodiments, a Schottky barrier diode is used as a semiconductor device having a super junction structure, a pn diode is used in the seventh embodiment, and a power MOSFET is used in the eighth embodiment. However, the present invention is not limited to this. Other semiconductor devices having a super junction structure (semiconductor devices other than Schottky barrier diodes, pn diodes, and power MOSFETs (eg, thyristors, IGBTs, etc.) and various composite semiconductor devices including these semiconductor devices) are used. You can also.

100, 100a, a semiconductor device having 100b, 100c, 100d, 100 e, a 200, 300 ... superjunction structure, 110,210,310,910 ... semiconductor substrate, 112,212,312,912 ... ^{n +} -type semiconductor substrate, 114 , 214, 314, 914 ... n ^- type semiconductor layer, 116, 216, 316, 916 ... first trench, 118, 218, 318, 918 ... columnar buried layer, 120, 920 ... p-type high-concentration ohmic diffusion region, 122, 222, 322, 922 ... second trench, 124, 224, 324, 924 ... annular columnar buried layer, 126, 926 ... Schottky barrier metal field relaxation region, 128, 228, 328, 928 ... relay diffusion region, 130, 130a, 230, 330, 930 ... insulating layer, 132,932 ... shock Key barrier metal layer (first electrode layer), 133, 933 ... anode electrode layer, 134, 234, 334 ... third trench, 136, 236, 336 ... second annular columnar buried layer, 138, 238, 338 ... p Type high concentration diffusion region, 140, 140a, 240, 340 ... opening, 142, 242, 342 ... annular conductive layer, 144, 944 ... depletion layer termination, 150, 250, 950 ... cathode electrode layer, 220 ... p ⁺ Type diffusion region, 226... Anode electrode layer electric field relaxation region, 232... Anode electrode layer (first electrode layer), 326... Source electrode layer electric field relaxation region, 332... Source electrode layer (first electrode layer), 350. Electrode layer, 360 ... p-type body region, 362 ... n ⁺ type source region, 364 ... p ⁺ type contact region, 370 ... gate electrode, 372 ... gate insulating layer, 374 ... Interlayer insulating layer, R1... Active region, R2 .. breakdown voltage region, R3... Peripheral region

Claims (9)

A first conductivity type semiconductor layer;
A plurality of columnar buried layers made of a semiconductor material of the second conductivity type formed on the surface of the semiconductor layer in the active region;
A first electrode layer formed on a surface of the semiconductor layer in the active region;
A plurality of annular columnar buried layers made of a semiconductor material of the second conductivity type, formed on the surface of the semiconductor layer in the breakdown voltage region surrounding the active region;
A semiconductor device having a super junction structure, comprising: the breakdown voltage region; and an insulating layer formed on a surface of the semiconductor layer in a peripheral region surrounding the breakdown voltage region;
A second annular columnar buried layer made of a semiconductor material of a second conductivity type formed on the surface of the semiconductor layer in the peripheral region;
A semiconductor device having a super junction structure, further comprising: an annular conductive layer formed on the insulating layer in the peripheral region. In the semiconductor device having a super junction structure according to claim 1,
The insulating layer has an opening in a region where the second annular columnar buried layer is formed in the peripheral region,
The semiconductor device having a super junction structure, wherein the annular conductive layer is connected to the second annular columnar buried layer through the opening. The semiconductor device having a super junction structure according to claim 2,
A semiconductor device having a super junction structure, characterized in that a second conductivity type high-concentration diffusion region is formed in the vicinity of the surface of the second annular columnar buried layer connected to the annular conductive layer. In the semiconductor device having a super junction structure according to claim 1,
The insulating layer has an opening in a region where the second annular columnar buried layer is not formed in the peripheral region;
The semiconductor device having a super junction structure, wherein the annular conductive layer is connected to the semiconductor layer through the opening. The semiconductor device having a super junction structure according to claim 4.
A semiconductor device having a super junction structure, wherein a first conductivity type high-concentration diffusion region is formed on a surface of the semiconductor layer in a region connected to the annular conductive layer. In the semiconductor device having a super junction structure according to any one of claims 1 to 5,
A super junction structure characterized in that a width dimension of the second annular conductive layer extending to the outer peripheral side from the outermost second annular columnar embedded layer is larger than a depth dimension of the second annular columnar embedded layer. A semiconductor device. In the semiconductor device having a super junction structure according to any one of claims 1 to 6,
A semiconductor device having a super junction structure, comprising a plurality of annular conductive layers as the annular conductive layer. In the semiconductor device having a super junction structure according to any one of claims 1 to 7,
A semiconductor device having a super junction structure, comprising a plurality of second annular columnar buried layers as the second annular columnar buried layer. The semiconductor device having a super junction structure according to claim 8,
The semiconductor device having a super junction structure, wherein the annular conductive layer is connected to an innermost second annular columnar buried layer.