JP2009004681A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of securing a stable breakdown voltage without generating a difference between potential distributions in both directions even in a drift layer having a stripe type SJ structure. <P>SOLUTION: The semiconductor device has an element region 100 where a semiconductor element is formed and a terminal region 200 enclosing the element region 100. The semiconductor device includes: p-type pillars 1 formed in an n-type drift layer 4 in stripes having lengths along a Y axis parallel to a plane of the n-type drift layer 4 and periodically along an X axis orthogonal to the Y axis; and a plurality of field plate electrodes 2 formed concentrically and annularly enclosing the element region 100 in the terminal region 200. The p-type pillar layer 1 has a Y-axial end beyond the boundary between the element region 100 and terminal region 200. The field plate electrodes 200 are formed to pass near both Y-axial ends of the p-type pillar layer 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having an element region in which a semiconductor element is formed and a termination region surrounding the element region.

  2. Description of the Related Art Conventionally, in a MOSFET or the like, a super junction structure that solves a problem related to a trade-off between element breakdown voltage and on-resistance is known (see, for example, Patent Document 1).

  In a MOSFET having a super junction (hereinafter, SJ) structure in a drift layer, the cell structure and the underlying SJ structure may be designed in a stripe shape. Other than the stripe type, there are square, rectangular and hexagonal mesh types, which are more advantageous than the stripe type in specific aspects such as low gate resistance and low on-resistance.

  However, the mesh type has disadvantages such as an increase in gate capacity and a reduction in breakdown resistance due to variations in the local finish of the FET cell. In recent years, the use of the stripe type has increased.

  Generally, the termination region has the same structure in the vertical direction and the horizontal direction in the chip. However, in the stripe type SJ structure, the termination region does not have the same structure in the vertical direction and the horizontal direction in the chip. Further, in the case of a stripe-type SJ structure, the electric field distribution and the potential distribution are also different depending on the direction.

  A stripe SJ structure that causes the above problem will be described in detail. In the stripe-type SJ structure, a direction in which p-type pillar layers are repeatedly formed in stripes between n-type drift layers is a first direction, and a longitudinal direction of the stripe shape of each p-type pillar layer is a second direction. . Here, when the drift layer is depleted in the first direction from the element region toward the termination region, each p-type pillar layer and the n-type drift layer therebetween are depleted sequentially from the inside to the outside. On the other hand, when the drift layer is depleted in the second direction from the element region toward the termination region, depletion occurs simultaneously between the adjacent p-type pillar layer and the n-type drift layer. Therefore, when the stripe structure is designed to match the depletion in the first direction, there is a problem that the second direction is depleted at a voltage sufficiently lower than the design withstand voltage.

In other words, since the conventional stripe-type SJ structure has the above-described problems, a design that satisfies the characteristics such as withstand voltage and withstand capability in both directions is required. In addition, the behavior when the manufacturing finish varies is different in both directions, and there arises a problem that the breakdown voltage is lowered in either direction.
JP 2003-273355 A

  An object of the present invention is to provide a semiconductor device capable of ensuring a stable breakdown voltage without causing a difference in potential distribution in both directions even if the drift layer has a stripe type SJ structure.

  A semiconductor device according to one embodiment of the present invention is a semiconductor device including an element region where a semiconductor element is formed and a termination region surrounding the element region. Formed on the upper surface side, alternately in a second direction parallel to the upper surface of the first semiconductor layer perpendicular to the first direction, in a stripe shape with the first direction parallel to the upper surface of the first semiconductor layer as a longitudinal direction The first conductivity type first pillar region and the second conductivity type second pillar region that are periodically formed, and the second conductivity type that is selectively formed on the surface of the second pillar region in the element region. A semiconductor base layer, a first conductivity type semiconductor region selectively formed on a surface of the semiconductor base layer, a first main electrode formed so as to be joined to the first semiconductor layer, and the semiconductor base Layer and the semiconductor region A second main electrode formed in such a manner; a control electrode formed through an insulating film so as to be in contact with the semiconductor base layer, the semiconductor region, and the first pillar region; and the element region in the termination region A plurality of field plate electrodes concentrically formed so as to surround the second pillar region, the end in the first direction in the second pillar region is formed beyond the boundary between the element region and the termination region, The plurality of field plate electrodes are formed so as to pass through the vicinity of both ends in the first direction of the second pillar region.

  According to the present invention, it is possible to provide a semiconductor device that can ensure a stable breakdown voltage without causing a difference in potential distribution in both directions even if the drift layer has a stripe type SJ structure.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following embodiments, description will be given by taking as an example a MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type. In the following, the description “p ++” has a higher impurity concentration than the description “p +”, and the description “p +” indicates that the impurity concentration is higher than the description “p”. Similarly, the description “n ++” has a higher impurity concentration than the description “n +”, and the description “n +” indicates that the impurity concentration is higher than the description “n”.

[First Embodiment]
First, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. As an example, the semiconductor device according to the first embodiment of the present invention is a vertical power MOSFET. FIG. 1 shows the configuration of a p-type pillar layer (first pillar layer) 1, a field plate electrode 2, a first p-type guard ring layer 11, and a first p + -type contact layer 12 of a power MOSFET according to the first embodiment of the present invention. It is a top view showing typically. 2 is a cross-sectional view taken along the line AA ′ in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line BB ′ in FIG.

  First, with reference to FIG. 1, the p-type pillar layer 1 and the field plate electrode 2 which are the characteristics of this embodiment are demonstrated.

  As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention mainly includes an element region 100 in which a semiconductor element (here, a MOS transistor) is formed, and a termination region 200 surrounding the element region 100. It is configured. Note that the boundary between the element region 100 and the termination region 200 in the present embodiment is, for example, the center (see FIG. 2) of the outermost p-type base layer 5 described later (see FIGS. 2 to 4). ).

  As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention has a plurality of p-type pillar layers 1 in an element region 100. The plurality of p-type pillar layers 1 are formed in a stripe shape whose longitudinal direction is the Y-axis direction, which is one direction in the plane direction, and are periodically arranged (SJ structure). Note that an n-type pillar layer is formed between the p-type pillar layers by the plurality of p-type pillar layers 1. The semiconductor device also has a plurality of field plate electrodes 2 formed concentrically so as to surround the element region 100.

  Each p-type pillar layer 1 is formed beyond the boundary between the element region 100 in the Y-axis direction parallel to the surface of the element region 100 orthogonal to the X-axis direction and the termination region 200.

  The plurality of field plate electrodes 2 are formed so as to pass over the vicinity of both ends of the p-type pillar layer 1 in the Y-axis direction. The field plate electrodes 2 are connected to different fixed potentials. The field plate electrode 2 is made of metal.

  Next, cross-sectional structures of A-A ′, B-B ′, and C-C ′ of FIG. 1 will be described with reference to FIGS. As shown in FIGS. 2 to 4, the semiconductor device according to this embodiment is formed on an n ++ type substrate 3 that functions as a drain layer. An n type drift layer 4 is formed on the n ++ type substrate 3.

  A p-type base layer 5 is selectively formed on the surface of the n-type drift layer 4 in the element region 100 in a stripe shape with the vertical direction (Y direction) in FIG. 2 as the longitudinal direction. Further, on the surface of the p-type base layer 5, a p + -type contact layer 6 and an n-type source diffusion layer 7 are selectively formed in a stripe shape whose longitudinal direction is the direction perpendicular to the paper surface (Y-axis direction) in FIG. Yes. The p-type pillar layer 1 is periodically formed below the p-type base layer 5 in the Z-axis direction.

  On the n-type source diffusion layer 7, the p-type base layer 5, and the n-type drift layer 4 (n-type pillar layer between the p-type pillar layers 1), a stripe shape is formed in the Y-axis direction via the gate insulating film 8. Gate electrodes 9 extending linearly are periodically formed in the X-axis direction. As shown in FIG. 2, the gate insulating film 8 and the gate electrode 9 are formed in common to two adjacent p-type base layers 5.

  A source electrode S is formed on the p + -type contact layer 6 and the n-type source diffusion layer 7. The source electrode S is insulated from the gate electrode 9 by the gate insulating film 8 or the like. On the other hand, a drain main electrode D is provided on the surface of the n ++ type substrate 3 opposite to the n-type drift layer 4.

  A gate insulating film 8 ′ and a gate electrode 9 ′ having the same shape as the gate insulating film 8 and the gate electrode 9 in the element region 100 are formed in the vicinity of the boundary between the termination region 200 and the element region 100. Note that the gate insulating film 8 ′ and the gate electrode 9 ′ do not function as gates because the n-type source diffusion layer 7 is not substantially formed immediately below the gate insulating film 8 ′ and the gate electrode 9 ′. Further, an annular first p-type guard ring layer 11 surrounding the element region 100 is formed on the surface of the n-type drift layer 4 on the outer peripheral side of the gate insulating film 8 ′ and the gate electrode 9 ′. A first p + type contact layer 12 is formed on the surface of the type guard ring layer 11 (see FIG. 1).

  On the further outer peripheral side of the source electrode S, a gate electrode 9 ″ is provided on the surface of the n-type drift layer 4 via an insulating film 8 ″. A gate signal for turning on / off the MOS transistor in the element region 100 is input to the gate electrode 9 ″. A gate main electrode G is provided on the gate electrode 9 ″. The insulating film 8 ″, the gate electrode 9 ″, and the gate main electrode G are formed in an annular shape so as to surround the outer periphery of the source electrode S. The gate electrodes 9, 9 ′, 9 ″ described above are connected to the gate main electrode G.

  On the outer peripheral side of the gate main electrode G, the field plate electrode 2 described above is provided on the surface of the n-type drift layer 4. An insulating film 8a is formed between the field plate electrode 2 and the n-type drift layer 4, and the field plate electrode 2 and the n-type drift layer 4 are connected via a contact formed on the insulating film 8a. Has been.

  A p-type field stop layer 13 is provided on the surface of the n-type drift layer 4 at the outer end portion (chip end portion) of the termination region 200. An n-type field stop layer 14 is provided on the surface of the p-type field stop layer 13. An insulating film 8b is formed on part of the surface of the p-type field stop layer 13 and the n-type field stop layer 14, and an electrode 15 is provided in the insulating film 8b. Further, a field stop electrode 16 is provided in contact with the p-type field stop layer 13 and the electrode 15. The field stop electrode 16 is connected to the gate electrode G or the source electrode S.

  As described above, according to the semiconductor device of the first embodiment of the present invention, the plurality of concentric field plate electrodes 2 are formed so as to surround the element region 100, and each of the plurality of field plate electrodes 2 is unique to each other. It is set to a fixed potential. Therefore, the field plate electrode 2 can provide a concentric annular potential so as to surround the element region 100 on the upper surface of the termination region 200 of the semiconductor device. As a result, the depletion layer is formed at equal speeds with respect to changes in the applied voltage in the X and Y directions, so that the breakdown voltage characteristics in the X and Y directions of the semiconductor device are equal. That is, according to the present embodiment, a stable breakdown voltage can be ensured without causing a difference in potential distribution in both directions even with a stripe type drift layer having an SJ structure.

[Second Embodiment]
Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. In addition, the same structure as 1st Embodiment attaches | subjects the same code | symbol, and abbreviate | omits the description.

  The semiconductor device according to the second embodiment includes a p-type pillar layer 1 and a field plate electrode 2 similar to those in the first embodiment. In the second embodiment, the top view of the p-type pillar layer 1 and the field plate electrode 2 is the same as FIG. 1 referred to in the first embodiment. That is, the second embodiment is different from the first embodiment in the configuration other than the p-type pillar layer 1 and the field plate electrode 2. 5 is a cross-sectional view taken along line A-A ′ of FIG. 1, FIG. 6 is a cross-sectional view taken along line B-B ′ of FIG. 1, and FIG. 7 is a cross-sectional view taken along line C-C ′ of FIG.

  Unlike the first embodiment, the semiconductor device according to the second embodiment is provided with a second p-type guard ring layer 17 and a second p + -type contact layer 18 below each field plate electrode 2. The second p-type guard ring layer 17 and the second p + -type contact layer 18 are formed concentrically so as to surround the element region 100.

  Since it has the above configuration, the semiconductor device according to the second embodiment can obtain the same effects as those of the first embodiment. Further, in the semiconductor device according to the second embodiment, the equipotential lines extending in the termination region 200 are smoothed by the second p-type guard ring layer 17 and the second p + -type contact layer 18, so that a stable high breakdown voltage can be obtained. It is done.

[Third Embodiment]
Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. In addition, the same structure as 1st Embodiment attaches | subjects the same code | symbol, and abbreviate | omits the description. FIG. 8 schematically shows the configuration of the p-type pillar layers 1 and 1 ′, the field plate electrode 2, the first p-type guard ring layer 11, and the first p + -type contact layer 12 of the semiconductor device according to the third embodiment of the present invention. FIG. 9 is a sectional view taken along the line DD ′ of FIG. 8, FIG. 10 is a sectional view taken along the line EE ′ of FIG. 8, and FIG. 11 is a sectional view taken along the line FF ′ of FIG.

  The semiconductor device according to the third embodiment includes a p-type pillar layer 1 and a field plate electrode 2 similar to those in the first embodiment. The semiconductor device according to the third embodiment differs from the first and second embodiments in that the p-type pillar layer 1 ′ (second pillar layer) extends beyond the element region 100 in the X-axis direction and in the termination region 200. have. The p-type pillar layer 1 ′ is formed below each field plate electrode 2 at the end in the X-axis direction.

  Since it has the above configuration, the semiconductor device according to the third embodiment can transmit the potential from the field plate electrode 2 to the p-type pillar layer 1 ′. Therefore, the effects of the first and second embodiments can be further enhanced.

[Fourth Embodiment]
Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. In addition, the same structure as 3rd Embodiment attaches | subjects the same code | symbol, and abbreviate | omits the description. The plane of the semiconductor device according to the fourth embodiment is formed in the same shape as in FIG. 12 is a sectional view taken along the line DD ′ of FIG. 8, FIG. 13 is a sectional view taken along the line EE ′ of FIG. 8, and FIG. 14 is a sectional view taken along the line FF ′ of FIG.

  The semiconductor device according to the fourth embodiment includes p-type pillar layers 1, 1 ′ and a field plate electrode 2 similar to those of the third embodiment. In the fourth embodiment, the top view of the p-type pillar layers 1, 1 ′ and the field plate electrode 2 is the same as FIG. 8 referred to in the third embodiment. The fourth embodiment differs from the third embodiment in the configuration other than the p-type pillar layers 1, 1 ′ and the field plate electrode 2. 12 is a cross-sectional view taken along line D-D ′ of FIG. 8, FIG. 13 is a cross-sectional view taken along line E-E ′ of FIG. 8, and FIG. 14 is a cross-sectional view taken along line F-F ′ of FIG.

  In the semiconductor device according to the fourth embodiment, in addition to the configuration of the third embodiment, the second p-type guard ring layer 17 and the second p + -type contact layer 18 are provided below each field plate electrode 2 as in the second embodiment. Is formed. In this respect, the fourth embodiment is different from the third embodiment.

  Therefore, the semiconductor device according to the fourth embodiment has the same effects as those of the second embodiment and the third embodiment.

[Fifth Embodiment]
Next, a semiconductor device according to a fifth embodiment of the invention will be described with reference to FIGS. In addition, the structure similar to 1st-4th embodiment attaches | subjects the same code | symbol, and abbreviate | omits the description. The plane of the semiconductor device according to the fifth embodiment is formed in the same shape as in FIG. 15 is a sectional view taken along the line DD ′ of FIG. 8, FIG. 16 is a sectional view taken along the line EE ′ of FIG. 8, and FIG. 17 is a sectional view taken along the line FF ′ of FIG.

  The semiconductor device according to the fifth embodiment is different from the third embodiment in the configuration having the insulating film 8c and the field plate electrode 2 '.

  The semiconductor device according to the fifth embodiment includes an insulating film 8 c in which the insulating films 8 ″, 8 a, and 8 b of the first to fourth embodiments are integrally formed. In the insulating film 8c, a field plate electrode 2 'made of polysilicon (Poly Si) is formed in place of the field plate electrode 2 made of metal in the first to fourth embodiments.

  The semiconductor device according to the fifth embodiment has the same effects as those of the third embodiment.

  Although the first to fifth embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, although the first conductivity type has been described as n-type and the second conductivity type as p-type, the first conductivity type may be p-type and the second conductivity type may be n-type. The configuration of the insulating film 8c and the field plate electrode 2 ′ according to the fifth embodiment can also be applied to the configurations of the first, second, and fourth embodiments, and the metal field plate electrode 2 on one chip. And PolySi field plate electrode 2 'may be formed together. The semiconductor device according to the present invention is not limited to a MOSFET, but may be an IGBT or the like.

The upper surface which shows typically the structure of the p-type pillar layer 1, the field plate electrode 2, the 1st p-type guard ring layer 11, and the 1st p + type contact layer 12 of the semiconductor device which concerns on 1st Embodiment and 2nd Embodiment of this invention. FIG. It is A-A 'sectional drawing of FIG. 1 which concerns on 1st Embodiment of this invention. FIG. 2 is a cross-sectional view taken along the line B-B ′ of FIG. 1 according to the first embodiment of the present invention. It is C-C 'sectional drawing of FIG. 1 which concerns on 1st Embodiment of this invention. It is A-A 'sectional drawing of FIG. 1 which concerns on 2nd Embodiment of this invention. FIG. 6 is a cross-sectional view taken along the line B-B ′ of FIG. 1 according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view taken along the line C-C ′ of FIG. 1 according to the second embodiment of the present invention. The structure of the p-type pillar layer 1, 1 ′ field plate electrode 2, first p-type guard ring layer 11 and first p + -type contact layer 12 of the semiconductor device according to the third, fourth and fifth embodiments of the present invention is schematically shown. FIG. It is D-D 'sectional drawing of FIG. 8 which concerns on 3rd Embodiment of this invention. It is E-E 'sectional drawing of FIG. 8 which concerns on 3rd Embodiment of this invention. It is F-F 'sectional drawing of FIG. 8 which concerns on 3rd Embodiment of this invention. It is D-D 'sectional drawing of FIG. 8 which concerns on 4th Embodiment of this invention. It is E-E 'sectional drawing of FIG. 8 which concerns on 4th Embodiment of this invention. It is F-F 'sectional drawing of FIG. 8 which concerns on 4th Embodiment of this invention. It is D-D 'sectional drawing of FIG. 8 which concerns on 5th Embodiment of this invention. It is E-E 'sectional drawing of FIG. 8 which concerns on 5th Embodiment of this invention. It is F-F 'sectional drawing of FIG. 8 which concerns on 5th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1 '... p-type pillar layer, 2,2' ... Field plate layer, 3 ... n ++ type substrate, 4 ... n type drift layer, 5 ... p type base layer, 6 ... p + type contact layer, 7 ... n type Source diffusion layer, 8, 8 ', 8 "... gate insulating film, 9, 9', 9" ... gate electrode, 11 ... first p-type guard ring layer, 12 ... first p + type contact layer, 13 ... p-type Field stop layer, 14 ... n-type field stop layer, 15 ... electrode, 16 ... field stop electrode, 17 ... second p-type guard ring layer, 18 ... second p + -type contact layer, 100 ... element region, 200 ... termination region, D ... Drain main electrode, G ... Gate main electrode, S ... Source electrode.

Claims (5)

In a semiconductor device having an element region in which a semiconductor element is formed and a termination region surrounding the element region,
A first semiconductor layer of a first conductivity type;
The first semiconductor layer is formed on the upper surface side of the first semiconductor layer, and has a first direction parallel to the upper surface of the first semiconductor layer as a longitudinal direction in a stripe shape and parallel to the upper surface of the first semiconductor layer orthogonal to the first direction. A first conductivity type first pillar region and a second conductivity type second pillar region alternately and periodically formed in a second direction;
A second conductivity type semiconductor base layer selectively formed on the surface of the second pillar region in the element region;
A first conductivity type semiconductor region selectively formed on a surface of the semiconductor base layer;
A first main electrode formed to be bonded to the first semiconductor layer;
A second main electrode formed to be bonded to the semiconductor base layer and the semiconductor region;
A control electrode formed through an insulating film so as to be in contact with the semiconductor base layer, the semiconductor region, and the first pillar region;
A plurality of field plate electrodes formed concentrically so as to surround the element region in the termination region;
The end in the first direction in the second pillar region is formed beyond the boundary between the element region and the termination region,
The plurality of field plate electrodes are formed so as to pass near both ends in the first direction of the second pillar region. The semiconductor device according to claim 1, further comprising: a guard ring layer formed below the plurality of field plate electrodes in the termination region. The second pillar region is periodically arranged in a stripe shape in the termination region beyond the boundary between the element region and the termination region in the second direction, and a part of the second pillar region is formed below the field plate electrode. The semiconductor device according to claim 1, wherein the semiconductor device is provided.   The semiconductor device according to claim 1, wherein the field plate electrode is made of metal.   The semiconductor device according to claim 1, wherein the field plate electrode is made of polysilicon.

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