JP2013090290A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2013090290A5 JP2013090290A5 JP2011232120A JP2011232120A JP2013090290A5 JP 2013090290 A5 JP2013090290 A5 JP 2013090290A5 JP 2011232120 A JP2011232120 A JP 2011232120A JP 2011232120 A JP2011232120 A JP 2011232120A JP 2013090290 A5 JP2013090290 A5 JP 2013090290A5
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- feedback
- feedback clock
- circuit
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011232120A JP5798442B2 (ja) | 2011-10-21 | 2011-10-21 | クロック分配回路及びクロック分配回路の形成方法 |
| US13/603,755 US8736339B2 (en) | 2011-10-21 | 2012-09-05 | Clock distribution circuit and method of forming clock distribution circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011232120A JP5798442B2 (ja) | 2011-10-21 | 2011-10-21 | クロック分配回路及びクロック分配回路の形成方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013090290A JP2013090290A (ja) | 2013-05-13 |
| JP2013090290A5 true JP2013090290A5 (enExample) | 2014-11-27 |
| JP5798442B2 JP5798442B2 (ja) | 2015-10-21 |
Family
ID=48135459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011232120A Active JP5798442B2 (ja) | 2011-10-21 | 2011-10-21 | クロック分配回路及びクロック分配回路の形成方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8736339B2 (enExample) |
| JP (1) | JP5798442B2 (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9523736B2 (en) | 2014-06-19 | 2016-12-20 | Nuvoton Technology Corporation | Detection of fault injection attacks using high-fanout networks |
| US9397663B2 (en) | 2014-07-22 | 2016-07-19 | Winbond Electronics Corporation | Fault protection for high-fanout signal distribution circuitry |
| US9397666B2 (en) * | 2014-07-22 | 2016-07-19 | Winbond Electronics Corporation | Fault protection for clock tree circuitry |
| US10013581B2 (en) | 2014-10-07 | 2018-07-03 | Nuvoton Technology Corporation | Detection of fault injection attacks |
| US9471094B1 (en) * | 2014-12-30 | 2016-10-18 | Cadence Design Systems, Inc. | Method of aligning timing of a chip select signal with a cycle of a memory device |
| CN107300948A (zh) * | 2016-04-14 | 2017-10-27 | 飞思卡尔半导体公司 | 具有多位时钟门控单元的集成电路 |
| US10254782B2 (en) * | 2016-08-30 | 2019-04-09 | Micron Technology, Inc. | Apparatuses for reducing clock path power consumption in low power dynamic random access memory |
| US12182260B2 (en) | 2017-12-18 | 2024-12-31 | Nuvoton Technology Corporation | System and method for detecting fault injection attacks |
| US11366899B2 (en) | 2020-02-18 | 2022-06-21 | Nuvoton Technology Corporation | Digital fault injection detector |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5406590A (en) * | 1992-10-23 | 1995-04-11 | Compaq Computer Corporation | Method of and apparatus for correcting edge placement errors in multiplying phase locked loop circuits |
| JPH06273478A (ja) * | 1993-03-20 | 1994-09-30 | Hitachi Ltd | クロックスキュー補正回路、及び半導体集積回路 |
| JP3180780B2 (ja) | 1998-10-13 | 2001-06-25 | 日本電気株式会社 | デジタルdll回路 |
| US6608530B1 (en) * | 2001-12-14 | 2003-08-19 | Cypress Semiconductor Corp. | Enhanced ZDB feedback methodology utilizing binary weighted techniques |
| US6737902B2 (en) * | 2002-05-16 | 2004-05-18 | Sun Microsystems, Inc. | Method and a system to distribute clock signals in digital circuits |
| US7098714B2 (en) * | 2003-12-08 | 2006-08-29 | Micron Technology, Inc. | Centralizing the lock point of a synchronous circuit |
| KR100705502B1 (ko) * | 2005-12-10 | 2007-04-09 | 한국전자통신연구원 | 클록 편차를 제거하는 클록 발생 장치 및 클록 수신 장치 |
| JP2007336003A (ja) * | 2006-06-12 | 2007-12-27 | Nec Electronics Corp | クロック分配回路、半導体集積回路、クロック分配回路の形成方法及びそのプログラム |
| JP2008010607A (ja) | 2006-06-29 | 2008-01-17 | Nec Computertechno Ltd | 半導体集積回路およびクロックスキュー低減方法 |
| JP2010273286A (ja) * | 2009-05-25 | 2010-12-02 | Renesas Electronics Corp | クロック分配回路およびクロック分配方法 |
-
2011
- 2011-10-21 JP JP2011232120A patent/JP5798442B2/ja active Active
-
2012
- 2012-09-05 US US13/603,755 patent/US8736339B2/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2013090290A5 (enExample) | ||
| Shi et al. | Robust mixed H2/H∞ control of networked control systems with random time delays in both forward and backward communication links | |
| WO2013032753A3 (en) | Systems and methods for switched-inductor integrated voltage regulators | |
| WO2010033436A3 (en) | Techniques for generating fractional clock signals | |
| JP2010088108A5 (enExample) | ||
| JP5798442B2 (ja) | クロック分配回路及びクロック分配回路の形成方法 | |
| WO2010135097A3 (en) | Clock distribution techniques for channels | |
| JP2008157971A5 (enExample) | ||
| JP2008199573A5 (enExample) | ||
| WO2013086247A3 (en) | Multi-phase converter system and method | |
| JP2010243427A5 (enExample) | ||
| EP2903162A3 (en) | A MDLL/PLL hybrid design with uniformly distributed output phases | |
| WO2012136279A3 (en) | Method of controlling pitch systems of a wind turbine | |
| TW201130229A (en) | Delay locked loop and method of driving delay locked loop | |
| JP6242228B2 (ja) | クロック生成方法およびクロック生成回路 | |
| WO2013030528A3 (en) | Digital error correction | |
| WO2012021511A3 (en) | High-speed frequency divider and phase locked loop using same | |
| JP2011055048A5 (enExample) | ||
| JP2012504263A5 (enExample) | ||
| JP2010273187A5 (ja) | Pll回路 | |
| WO2012163979A3 (en) | Assessment of power systems | |
| JP2017508319A5 (enExample) | ||
| WO2014133768A3 (en) | Configurable time delays for equalizing pulse width modulation timing | |
| Rezapour et al. | Stochastic comparison of lifetimes of two (n− k+ 1)-out-of-n systems with heterogeneous dependent components | |
| WO2015132064A3 (de) | Verfahren zur strangstrombestimmung in einem elektrischen mehrphasensystem |