JP2013074185A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress thermal destruction during application of an electrostatic discharge.SOLUTION: An n-type region 23, a p-type region 26, and an n-type buried region 30 are formed in a semiconductor active layer 16 of a semiconductor device 1. The n-type region 23 is electrically connected to a cathode electrode K. The p-type region 26 is electrically connected to an anode electrode A. The buried region 30 is formed including at least a part of the semiconductor active layer 16 on the reverse side of the p-type region 26, comes into contact with the reverse side of the p-type region 26, and has a larger impurity concentration than the semiconductor active layer 16.

Description

  The present invention relates to a semiconductor device for electrostatic protection.

  Development of composite ICs integrating multiple types of circuits is underway. For example, in a composite IC, an analog circuit, a digital circuit, a drive circuit, and the like are integrated. Since these circuits usually require different operating voltages, they are often formed using an SOI (Silicon on Insulator) substrate in order to ensure electrical insulation between circuit elements.

  In addition, in this type of composite IC, a semiconductor device for electrostatic protection is integrally configured in order to cope with a surge voltage caused by electrostatic discharge (ESD). Examples of semiconductor devices for electrostatic protection incorporated in an SOI substrate are disclosed in Patent Documents 1 to 4. Patent Document 1 exemplifies a diode-type semiconductor device for electrostatic protection, Patent Document 2 exemplifies a MOS-type semiconductor device for electrostatic protection, and Patent Documents 3 and 4 disclose thyristor-type semiconductor devices. A semiconductor device for electrostatic protection is illustrated.

FIG. 6 shows a typical example of a diode-type semiconductor device for electrostatic protection. The semiconductor device 10 is formed using an SOI substrate 118. The SOI substrate 118 includes a semiconductor support layer 112, a buried insulating layer 114, and an n ⁻ type semiconductor active layer 116. In the semiconductor active layer 116, an n-type region 123 and a p-type region 126 are formed. The n-type region 123 has an n ⁺ -type contact region 121 and an n-type well region 122 and is electrically connected to the cathode electrode K. The p-type region 126 has a p ⁺ -type contact region 124 and a p-type well region 125, and is electrically connected to the anode electrode A. The n ⁺ -type contact region 121 and the p ⁺ -type contact region 124 are formed with a predetermined distance therebetween, and the LOCOS oxide film 40 is formed therebetween.

  In the semiconductor device 10, when electrostatic discharge is applied to the wiring of the cathode electrode K, the high electric field region inside the element is broken down by the avalanche. As a result, carriers are generated in a high electric field region, and a surge current flows. The surge current is discharged to the ground through the anode electrode A.

JP 2001-257366 A JP 2001-127287 A JP 2002-94010 A JP 2002-94012 A

  A high electric field region inside the device when electrostatic discharge is applied is formed on the pn junction surface. Usually, the high electric field region is formed on the pn junction surface existing in the surface portion of the semiconductor active layer 116. In this example, the pn junction surface of the n-type well 122 of the n-type region 123 and the p-type well 125 of the p-type region 126 becomes a high electric field region (corresponding to “10a” in FIG. 6A). This high electric field region is also a region where the temperature becomes the highest, and it is important to suppress the maximum heat generation temperature in this region in order to suppress thermal breakdown.

  As a result of the study by the present inventors, when the pn junction surface of the high electric field region extends in the thickness direction of the semiconductor active layer 116, the maximum heat generation temperature of the high electric field region strongly depends on the thickness 10H of the semiconductor active layer 116. I understand that. As shown in FIG. 7, when the thickness of the semiconductor active layer 116 is 2.5 μm or less, the maximum heat generation temperature rapidly increases. This phenomenon does not depend on the width in the depth direction of the n-type region 123 and the p-type region 126 (corresponding to “10 W” in FIG. 6B). As described above, it has been found that when the high electric field region extends in the thickness direction, the maximum heat generation temperature exceeds the allowable value for thermal breakdown depending on the thickness 10H of the semiconductor active layer 116.

  In the composite IC, it is desired to reduce the thickness of the semiconductor active layer in order to meet the demand for higher breakdown voltage. Therefore, there is a demand for a semiconductor device for electrostatic protection that is not thermally destroyed even when the semiconductor active layer is thin. An object of the technology disclosed in this specification is to provide a technology for keeping the maximum heat generation temperature of a semiconductor device for electrostatic protection low.

  The technology disclosed in this specification is characterized in that the maximum heat generation temperature is kept low by expanding at least a part of the high electric field region in the plane direction of the semiconductor active layer.

  That is, a semiconductor device disclosed in this specification includes a semiconductor support layer, a buried insulating layer provided on the semiconductor support layer, a first conductivity type semiconductor active layer provided on the buried insulating layer, A first electrode provided on a part of the surface of the semiconductor active layer and connected to one of the electrodes; and provided on another part of the surface of the semiconductor active layer and connected to the other electrode. And a second electrode used. In the semiconductor active layer, at least a first conductivity type first region, a second conductivity type second region, and a first conductivity type buried region are formed. The first region is formed so as to include at least a part of the surface portion of the semiconductor active layer, and is electrically connected to the first electrode. The second region is formed so as to include at least another part of the surface portion of the semiconductor active layer, and is electrically connected to the second electrode. The buried region is formed so as to include at least a part of the back surface side of the second region of the semiconductor active layer, is in contact with the back surface of the second region, and has an impurity concentration of impurities of the semiconductor active layer. It is darker than the concentration. In the semiconductor device of this aspect, at least a part of the high electric field region is formed on the junction surface between the second region and the buried region. Since the joint surface between the second region and the buried region extends in the surface direction of the semiconductor active layer, a high electric field region is formed widely in the surface direction. As a result, the maximum heat generation temperature in the high electric field region is kept low, and thermal destruction is suppressed.

  The thickness of the semiconductor active layer may be 2.5 μm or less. It has been confirmed that when the thickness of the semiconductor active layer is 2.5 μm or less, the maximum heat generation temperature rapidly increases. The technique disclosed in this specification is particularly useful when the thickness of the semiconductor active layer is 2.5 μm or less.

  At the junction surface between the second region and the buried region, the impurity concentration of the first conductivity type in the buried region may be 10 times or more the impurity concentration of the first conductivity type in the semiconductor active layer. In the semiconductor device of this aspect, when the second region is in contact with the high-concentration buried region, a high electric field region is easily formed on the joint surface between the two regions.

  According to the technique disclosed in the present specification, at least a part of the high electric field region is expanded in the plane direction of the semiconductor active layer, and the maximum heat generation temperature can be suppressed low.

FIG. 1A schematically shows a longitudinal sectional view of a main part of a diode-type electrostatic protection semiconductor device according to the first embodiment. FIG. 1B schematically shows a cross-sectional view of a main part of the diode-type semiconductor device for electrostatic protection of the first embodiment (corresponding to the cross-section of the surface portion of the semiconductor active layer). FIG. 2 shows an impurity concentration distribution corresponding to the line II-II in FIG. FIG. 3 shows an impurity concentration distribution corresponding to line III-III in FIG. FIG. 4 schematically shows a longitudinal sectional view of an essential part of a semiconductor device for electrostatic protection of the thyristor type according to the second embodiment. FIG. 5 schematically shows a longitudinal sectional view of an essential part of a MOS type electrostatic protection semiconductor device of the third embodiment. FIG. 6A schematically shows a longitudinal sectional view of a main part of a conventional diode-type electrostatic protection semiconductor device. FIG. 6B schematically shows a cross-sectional view of a main part of a conventional diode-type semiconductor device for electrostatic protection (corresponding to the cross-section of the surface portion of the semiconductor active layer). FIG. 7 shows the dependence of the maximum heat generation temperature on the thickness of the semiconductor active layer.

The techniques disclosed in this specification will be summarized.
(First Feature) It is desirable that the impurity concentration of the n-type buried region is higher than the impurity concentration of the n-type semiconductor active layer. As a result, the electric field strength of the pn junction surface between the p-type second region and the n-type buried region is such that the n-type buried region is not formed (that is, the p-type second region and the n-type semiconductor activity). Higher than in the case of the pn junction surface of the layer. Thereby, at least a part of the high electric field region is formed on the pn junction surface between the p-type second region and the n-type buried region.
(Second Feature) At the junction surface between the p-type second region and the n-type buried region, the impurity concentration of the n-type buried region is 10 times or more, more preferably 100 times the impurity concentration of the n-type semiconductor active layer. It is desirable that it is more than twice. Thereby, most of the high electric field region is formed on the pn junction surface of the p-type second region and the n-type buried region.
(Third Feature) When the n-type well region of the n-type first region and the p-type well region of the p-type second region are in contact with each other at the side surface, the impurity concentration of the n-type buried region is It is desirable that the concentration is higher than the impurity concentration of the region. Thereby, most of the high electric field region is formed on the pn junction surface of the p-type second region and the n-type buried region.
(Fourth feature) The thickness of the semiconductor active layer is preferably in the range of 1 to 2.5 μm.

  Embodiments will be described below with reference to the drawings. In addition, about the common component, a common code | symbol is attached | subjected and the description may be abbreviate | omitted. In the following example, silicon is used as the material for the semiconductor substrate. However, the present invention is not limited to this example, and other semiconductor materials may be used.

FIG. 1 shows a diode-type electrostatic protection semiconductor device 1 mounted on a composite IC. The semiconductor device 1 is formed using an SOI substrate 18. The SOI substrate 18 includes an n ⁺ -type or p ⁺ -type semiconductor support layer 12, a buried insulating layer 14, and an n ⁻ -type semiconductor active layer 16. Single crystal silicon is used as the material of the semiconductor support layer 12. The semiconductor support layer 12 contains phosphorus or boron at a high concentration and is fixed to the ground voltage. Silicon oxide is used as the material of the buried insulating layer 14. The thickness of the buried insulating layer 14 is about 1.0 μm. Single crystal silicon is used as the material of the semiconductor active layer 16. The semiconductor active layer 16 contains phosphorus at a low concentration, and its impurity concentration is about 1 × 10 ¹⁵ cm ⁻³ . The thickness 1H of the semiconductor active layer 16 is extremely thin, about 1.6 μm.

  An n-type region 23 (an example of a first region), a p-type region 26 (an example of a second region), and an n-type buried region 30 are formed in the semiconductor active layer 16. The n-type region 23, the p-type region 26, and the buried region 30 are formed using an ion implantation technique.

The n-type region 23 has an n ⁺ -type contact region 21 and an n-type well region 22 and is a region into which phosphorus is introduced by ion implantation. The n ⁺ type contact region 21 is formed in a part of the surface portion of the semiconductor active layer 16. The n ⁺ -type contact region 21 has a thickness of about 0.2 μm, a peak concentration of about 1 × 10 ²⁰ cm ⁻³ , and a peak depth of about 0.01 μm. The n-type well region 22 is formed so as to surround the n ⁺ -type contact region 21. The n-type well region 22 has a thickness of about 1.2 μm, a peak concentration of about 4 × 10 ¹⁷ cm ⁻³ , and a peak depth of about 0.3 μm.

The p-type region 26 has a p ⁺ -type contact region 24 and a p-type well region 25, and is a region into which boron has been introduced by ion implantation. The p ⁺ type contact region 24 is formed in a part of the surface portion of the semiconductor active layer 16. The p ⁺ -type contact region 24 has a thickness of about 0.3 μm, a peak concentration of about 1 × 10 ²⁰ cm ⁻³ , and a peak depth of about 0.01 μm. The p-type well region 25 is formed so as to surround the p ⁺ -type contact region 24. The p-type well region 25 has a thickness of about 1.0 μm, a peak concentration of about 1.5 × 10 ¹⁸ cm ⁻³ , and a peak depth of about 0.3 μm.

The n ⁺ -type contact region 21 and the p ⁺ -type contact region 24 are arranged at a predetermined distance, and a silicon oxide LOCOS oxide film 40 is formed on the surface of the semiconductor active layer 16 therebetween. The side surface of the n-type well region 22 and the side surface of the p-type well region 25 are in contact under the LOCOS oxide film 40. Further, as shown in FIG. 1B, the width 1W in the depth direction of the n-type region 23 and the p-type region 26 is about 300 μm.

The buried region 30 is formed on the back surface of the semiconductor active layer 16 and extends along the surface direction of the semiconductor active layer 16 while being in contact with the buried insulating layer 14. The buried region 30 is a region where phosphorus is introduced by ion implantation, and is higher than the impurity concentration of the semiconductor active layer 16. In this example, the buried region 30 is selectively formed on the back side of the p-type region 26 and is in contact with the back side of the p-type well region 25 of the p-type region 26. Instead of this example, the buried region 30 may also be formed on the back side of the n-type region 23. The buried region 30 has a thickness of about 0.6 μm, a peak concentration of about 8 × 10 ¹⁷ cm ⁻³ , and a peak depth of about 1.2 μm.

The semiconductor device 1 further includes a cathode electrode K (an example of a first electrode) and an anode electrode A (an example of a second electrode). The cathode electrode K is formed on a part of the surface of the semiconductor active layer 16 and is in ohmic contact with the n ⁺ -type contact region 21. The cathode electrode K is used by being connected to the positive electrode side of a power source (not shown). The anode A is formed on part of the surface of the semiconductor active layer 16 and is in ohmic contact with the p ⁺ -type contact region 24. The anode electrode A is used by being connected to the negative side of a power source (not shown). In this example, the anode electrode A is used while being fixed to the ground voltage.

  FIG. 2 shows an impurity concentration distribution corresponding to the line II-II in FIG. The vertical axis represents the impurity concentration of the n-type well 22 and the p-type well 25 in logarithm form with the impurity concentration of the semiconductor active layer 16 as a reference. The II-II line corresponds to the peak depth of the impurity concentration in the n-type well region 22 and the p-type well region 25. The point where the impurity concentration distribution of the n-type well region 22 and the impurity concentration distribution of the p-type well region 25 intersect corresponds to the pn junction surface of the n-type well region 22 and the p-type well region 25.

  FIG. 3 shows an impurity concentration distribution corresponding to the line III-III in FIG. The vertical axis represents the impurity concentration of the p-type well region 25 and the buried region 30 in logarithm form with the impurity concentration of the semiconductor active layer 16 as a reference. The depth at which the impurity concentration distribution in the p-type well region 25 and the impurity concentration distribution in the buried region 30 intersect corresponds to the pn junction surface between the p-type well region 25 and the buried region 30. As shown in FIG. 3, both the impurity concentration of the p-type well region 25 and the impurity concentration of the buried region 30 are the same as the impurity concentration of the semiconductor active layer 16 at the pn junction surface of the p-type well region 25 and the buried region 30. It is formed 100 times or more, specifically about 500 times. 2 and 3, the impurity concentration of the buried region 30 in the pn junction surface between the p-type well region 25 and the buried region 30 is equal to the pn junction surface between the n-type well region 22 and the p-type well region 25. This is higher than the impurity concentration of the n-type well region 22 in FIG. When such a concentration relationship is established, the high electric field region moves from the pn junction surface between the n-type well region 22 and the p-type well region 25 to the pn junction surface between the p-type well region 25 and the buried region 30.

  When electrostatic discharge is applied to the wiring of the cathode electrode K, the high electric field region (corresponding to “1a” in FIG. 1) of the pn junction surface between the p-type well region 25 and the buried region 30 breaks down by the avalanche. As a result, carriers are generated in a high electric field region, and a surge current flows. The surge current is discharged to the ground through the anode electrode A.

  The high electric field region of the semiconductor device 1 is formed on the pn junction surface of the p-type well region 25 and the buried region 30, and this pn junction surface extends widely in the surface direction of the semiconductor active layer 16. For this reason, since the high electric field region is also formed widely, the heat generation region is also dispersed, and the maximum heat generation temperature is suppressed. Further, since the high electric field region extends in the plane direction, the influence of the thickness 1H of the semiconductor active layer 16 is reduced, and for example, the dependency on the semiconductor active layer 16 as shown in FIG. 7 is also reduced. As a result, in the case where the thickness 1H of the semiconductor active layer 16 is 2.5 μm or less, the maximum heat generation temperature can be suppressed low, and thermal breakdown is suppressed.

FIG. 4 shows a thyristor type semiconductor device 2 for electrostatic protection mounted on a composite IC. The semiconductor active layer 16 of the semiconductor device 2 includes an n-type region 53 (an example of a first region), a p ⁺ -type anode region 54, an n ⁺ -type cathode region 55, and a p-type region 58 (an example of a second region). A buried region 30 is formed. The n-type region 53, the anode region 54, the cathode region 55, the p-type region 58, and the buried region 30 are formed using an ion implantation technique. In this example, the buried region 30 is formed on the entire back surface of the semiconductor active layer 16.

The n-type region 53 has an n ⁺ -type contact region 51 and an n-type well region 52, and is a region into which phosphorus is introduced by ion implantation. The n ⁺ -type contact region 51 is formed on a part of the surface portion of the semiconductor active layer 16. The n ⁺ -type contact region 51 has a thickness of about 0.2 μm, a peak concentration of about 1 × 10 ²⁰ cm ⁻³ , and a peak depth of about 0.01 μm. The n-type well region 52 is formed so as to surround the n ⁺ -type contact region 51. The n-type well region 52 has a thickness of about 1.2 μm, a peak concentration of about 4 × 10 ¹⁷ cm ⁻³ , and a peak depth of about 0.3 μm.

The anode region 54 is formed in part of the surface portion of the semiconductor active layer 16 and is a region into which boron has been introduced by ion implantation. The anode region 54 has a thickness of about 0.3 μm, a peak concentration of about 1 × 10 ²⁰ cm ⁻³ , and a peak depth of about 0.01 μm.

The cathode region 55 is formed in part of the surface portion of the semiconductor active layer 16 and is a region into which phosphorus has been introduced by ion implantation. The cathode region 55 has a thickness of about 0.2 μm, a peak concentration of about 1 × 10 ²⁰ cm ⁻³ , and a peak depth of about 0.01 μm.

The p-type region 58 has a p ⁺ -type contact region 56 and a p-type well region 57, and is a region into which boron has been introduced by ion implantation. The p ⁺ type contact region 56 is formed in a part of the surface portion of the semiconductor active layer 16. The p ⁺ -type contact region 56 has a thickness of about 0.3 μm, a peak concentration of about 1 × 10 ²⁰ cm ⁻³ , and a peak depth of about 0.01 μm. The p-type well region 57 is formed so as to surround the p ⁺ -type contact region 56. The p-type well region 57 has a thickness of about 1.0 μm, a peak concentration of about 1.5 × 10 ¹⁸ cm ⁻³ , and a peak depth of about 0.3 μm.

The semiconductor device 2 further includes an anode electrode A (an example of a first electrode) and a cathode electrode K (an example of a second electrode). The anode electrode A is formed on a part of the surface of the semiconductor active layer 16 and is in ohmic contact with the n ⁺ -type contact region 51 and the anode region 54. The anode electrode A is used by being connected to a positive electrode side of a power source (not shown). The cathode electrode K is formed on a part of the surface of the semiconductor active layer 16 and is in ohmic contact with the p ⁺ -type contact region 56 and the cathode region 55. The cathode electrode K is used by being connected to the negative electrode side of a power supply (not shown), and in this example, is fixed to the ground voltage.

  Also in the semiconductor device 2, the p-type well region 57 and the buried region 30 are in contact with each other, and the electric field tends to concentrate on the pn junction surface. Therefore, when electrostatic discharge is applied to the wiring of the anode electrode A, the high electric field region (corresponding to “2a” in FIG. 4) of the pn junction surface between the p-type well region 57 and the buried region 30 is broken down by the avalanche. To do. As a result, carriers are generated in a high electric field region, and a surge current flows. The surge current is discharged to the ground through the cathode electrode K. The high electric field region of the semiconductor device 2 is also formed on the pn junction surface that extends widely in the plane direction of the semiconductor active layer 16, and since the high electric field region is formed widely, the heat generating region is also dispersed and the maximum heat generating temperature is increased. It is suppressed and thermal destruction is suppressed.

FIG. 5 shows a MOS type electrostatic protection semiconductor device 3 mounted on a composite IC. In the semiconductor active layer 16 of the semiconductor device 3, an n-type region 63 (an example of a first region), an n ⁺ -type source region 64, a p-type region 67 (an example of a second region), and a buried region 30 are formed. Yes. The n-type region 63, the source region 64, the p-type region 67, and the buried region 30 are formed using an ion implantation technique. In this example, the buried region 30 is formed on the entire back surface of the semiconductor active layer 16.

The n-type region 63 has an n ⁺ -type contact region 61 and an n-type well region 62, and is a region into which phosphorus is introduced by ion implantation. The n ⁺ -type contact region 61 is formed on a part of the surface portion of the semiconductor active layer 16. The n ⁺ -type contact region 61 has a thickness of about 0.2 μm, a peak concentration of about 1 × 10 ²⁰ cm ⁻³ , and a peak depth of about 0.01 μm. The n-type well region 62 is formed so as to surround the n ⁺ -type contact region 61. The n-type well region 62 has a thickness of about 1.2 μm, a peak concentration of about 4 × 10 ¹⁷ cm ⁻³ , and a peak depth of about 0.3 μm.

The source region 64 is formed in part of the surface portion of the semiconductor active layer 16 and is a region into which phosphorus has been introduced by ion implantation. Source region 64 is separated from n-type region 63 and buried region 30 by p-type region 67. The source region 64 has a thickness of about 0.2 μm, a peak concentration of about 1 × 10 ²⁰ cm ⁻³ , and a peak depth of about 0.01 μm.

The p-type region 67 has a p ⁺ -type contact region 65 and a p-type well region 66, and is a region into which boron has been introduced by ion implantation. The p ⁺ type contact region 65 is formed in a part of the surface portion of the semiconductor active layer 16. The p ⁺ -type contact region 65 has a thickness of about 0.3 μm, a peak concentration of about 1 × 10 ²⁰ cm ⁻³ , and a peak depth of about 0.01 μm. The p-type well region 66 is formed so as to surround the p ⁺ -type contact region 65. The p-type well region 66 has a thickness of about 1.0 μm, a peak concentration of about 4 × 10 ¹⁷ cm ⁻³ , and a peak depth of about 0.3 μm.

The semiconductor device 3 further includes a drain electrode D (an example of a first electrode), a gate portion 73, a source electrode S, and a base electrode B (an example of a second electrode). The drain electrode D is formed on a part of the surface of the semiconductor active layer 16 and is in ohmic contact with the n ⁺ -type contact region 61. The drain electrode D is used by being connected to a positive electrode side of a power source (not shown). The gate portion 73 is formed on a part of the surface of the semiconductor active layer 16 and has a gate insulating film 71 and a gate electrode 72. The gate electrode 72 is opposed to the p-type region 67 between the n-type region 63 and the source region 64 through the gate insulating film 71. The source electrode S is formed on a part of the surface of the semiconductor active layer 16 and is in ohmic contact with the source region 64. The base electrode B is formed on a part of the surface of the semiconductor active layer 16 and is in ohmic contact with the p ⁺ type contact region 65. The gate electrode 72, the source electrode S, and the base electrode B are used by being connected to a negative electrode side of a power source (not shown), and in this example, are fixed to the ground voltage.

  Also in the semiconductor device 3, the p-type well region 66 and the buried region 30 are in contact with each other, and the electric field tends to concentrate on the pn junction surface. Therefore, when electrostatic discharge is applied to the wiring of the drain electrode D, the high electric field region (corresponding to “3a” in FIG. 5) of the pn junction surface between the p-type well region 66 and the buried region 30 is broken down by the avalanche. To do. As a result, carriers are generated in a high electric field region, and a surge current flows. The surge current is discharged to the ground through the source electrode S and the base electrode B. The high electric field region of the semiconductor device 3 is also formed on the pn junction surface that extends widely in the plane direction of the semiconductor active layer 16, and since the high electric field region is formed widely, the heat generating region is also dispersed and the maximum heat generating temperature is increased. It is suppressed and thermal destruction is suppressed.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

12: Semiconductor support layer 14: Buried insulating layer 16: Semiconductor active layer 18: SOI substrate 23, 53, 63: n-type region 26, 58, 67: p-type region 30: buried region

Claims (3)

A semiconductor support layer;
A buried insulating layer provided on the semiconductor support layer;
A semiconductor active layer of a first conductivity type provided on the buried insulating layer;
A first electrode provided on a part of the surface of the semiconductor active layer and connected to one of the electrodes;
The second electrode is provided on the other part of the surface of the semiconductor active layer and connected to the other electrode.
In the semiconductor active layer, at least a first conductivity type first region, a second conductivity type second region, and a first conductivity type buried region are formed,
The first region is formed so as to include at least a part of a surface portion of the semiconductor active layer, and is electrically connected to the first electrode,
The second region is formed so as to include at least another part of the surface portion of the semiconductor active layer, and is electrically connected to the second electrode,
The buried region is formed so as to include at least a part of the back surface side of the second region of the semiconductor active layer, is in contact with the back surface of the second region, and has an impurity concentration of A semiconductor device having an impurity concentration higher than that of the semiconductor active layer.   The semiconductor device according to claim 1, wherein the semiconductor active layer has a thickness of 2.5 μm or less.   3. The impurity concentration of the first conductivity type of the buried region is 10 times or more of the impurity concentration of the first conductivity type of the semiconductor active layer at a joint surface between the second region and the buried region. The semiconductor device described.

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