JP6455169B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6455169B2
JP6455169B2 JP2015007695A JP2015007695A JP6455169B2 JP 6455169 B2 JP6455169 B2 JP 6455169B2 JP 2015007695 A JP2015007695 A JP 2015007695A JP 2015007695 A JP2015007695 A JP 2015007695A JP 6455169 B2 JP6455169 B2 JP 6455169B2
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鈴木　隆司
隆司 鈴木
振一郎 柳
振一郎 柳
奨悟 池浦
奨悟 池浦
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Toyota Central R&D Labs Inc
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    • H—ELECTRICITY
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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Description

本明細書で開示する技術は、サイリスタを内蔵する半導体装置に関する。   The technology disclosed in this specification relates to a semiconductor device incorporating a thyristor.

特許文献１は、ＬＤＭＯＳ(Lateral Double Diffused Metal Oxide Semiconductor)にサイリスタを内蔵させる技術を開示する。このＬＤＭＯＳは、ドレイン電極に静電気放電(ESD)が印加されたときに内蔵サイリスタが動作するように構成されている。これにより、ＬＤＭＯＳは、高いＥＳＤ耐量を有することができる。   Patent Document 1 discloses a technique for incorporating a thyristor in an LDMOS (Lateral Double Diffused Metal Oxide Semiconductor). The LDMOS is configured such that the built-in thyristor operates when electrostatic discharge (ESD) is applied to the drain electrode. Thereby, the LDMOS can have a high ESD tolerance.

特開２００１−３２００４７号公報JP 2001-320047 A

しかしながら、特許文献１のＬＤＭＯＳでは、内蔵サイリスタを構成する複数の半導体領域が半導体活性層の表層部に設けられている。このため、内蔵サイリスタが動作したときの電流が半導体活性層の表層部を主に流れるので、局所的な電流集中による素子破壊が問題となる。本明細書は、内蔵サイリスタが動作したとき、電流が半導体活性層の厚み方向にも広がって流れるようにする技術を提供する。   However, in the LDMOS of Patent Document 1, a plurality of semiconductor regions constituting the built-in thyristor are provided in the surface layer portion of the semiconductor active layer. For this reason, since the current when the built-in thyristor operates mainly flows in the surface layer portion of the semiconductor active layer, element breakdown due to local current concentration becomes a problem. The present specification provides a technique for allowing a current to flow in the thickness direction of a semiconductor active layer when an internal thyristor is operated.

本明細書で開示する半導体装置の一実施形態は、半導体活性層、ソース電極及びドレイン電極を備える。半導体活性層は、第１導電型のソース領域、第２導電型のボディ領域、第１導電型のドレイン領域、第１導電型のドリフト領域、第２導電型のベース領域及び第２導電型の第１深部半導体領域を有する。ソース領域は、半導体活性層の上面に露出しており、ソース電極に接する。ボディ領域は、半導体活性層の上面に露出しており、ソース領域を囲んでおり、ソース電極に接する。ドレイン領域は、半導体活性層の上面に露出しており、半導体活性層の上面に平行な少なくとも一方向においてボディ領域から離れて配置されており、ドレイン電極に接する。ドリフト領域は、ボディ領域とドレイン領域の間に配置されており、ドレイン領域の不純物濃度よりも薄い不純物濃度を含む。ベース領域は、前記一方向においてボディ領域から離れて配置されており、ドリフト領域によってボディ領域から隔てられており、半導体活性層の上面に露出しており、ドレイン電極に接する。第１深部半導体領域は、ドリフト領域によって半導体活性層の上面から隔てられており、ボディ領域に接しており、前記一方向に沿ってボディ領域からベース領域側に向けて延びている。   One embodiment of a semiconductor device disclosed in this specification includes a semiconductor active layer, a source electrode, and a drain electrode. The semiconductor active layer includes a first conductivity type source region, a second conductivity type body region, a first conductivity type drain region, a first conductivity type drift region, a second conductivity type base region, and a second conductivity type. The first deep semiconductor region is included. The source region is exposed on the upper surface of the semiconductor active layer and is in contact with the source electrode. The body region is exposed on the upper surface of the semiconductor active layer, surrounds the source region, and is in contact with the source electrode. The drain region is exposed on the upper surface of the semiconductor active layer, is disposed away from the body region in at least one direction parallel to the upper surface of the semiconductor active layer, and is in contact with the drain electrode. The drift region is disposed between the body region and the drain region, and includes an impurity concentration lower than the impurity concentration of the drain region. The base region is disposed away from the body region in the one direction, is separated from the body region by the drift region, is exposed on the upper surface of the semiconductor active layer, and is in contact with the drain electrode. The first deep semiconductor region is separated from the upper surface of the semiconductor active layer by the drift region, is in contact with the body region, and extends from the body region toward the base region along the one direction.

上記半導体装置に内蔵されるサイリスタは、ベース領域とドリフト領域と第１深部半導体領域で構成されるトランジスタを含む。このため、内蔵サイリスタが動作したときの電流の一部は、第１深部半導体領域を介して流れる。第１深部半導体領域は、半導体活性層の深い位置に設けられているので、内蔵サイリスタが動作したときの電流は、半導体活性層の厚み方向にも広がって流れることができる。このように、上記半導体装置では、内蔵サイリスタが動作したときの電流集中が緩和され、局所的な電流集中による素子破壊が抑制される。   The thyristor incorporated in the semiconductor device includes a transistor including a base region, a drift region, and a first deep semiconductor region. For this reason, a part of current when the built-in thyristor is operated flows through the first deep semiconductor region. Since the first deep semiconductor region is provided at a deep position in the semiconductor active layer, the current when the built-in thyristor operates can spread and flow in the thickness direction of the semiconductor active layer. Thus, in the semiconductor device, current concentration when the built-in thyristor is operated is alleviated, and element destruction due to local current concentration is suppressed.

実施例の半導体装置の要部断面図を模式的に示す。The principal part sectional drawing of the semiconductor device of an Example is shown typically. 図１のII-II線に対応した断面図を模式的に示す。FIG. 2 schematically shows a cross-sectional view corresponding to line II-II in FIG. 1. 図１のIII-III線に対応した断面図を模式的に示す。FIG. 3 schematically shows a cross-sectional view corresponding to line III-III in FIG. 1. 変形例の半導体装置の要部断面図を模式的に示す。The principal part sectional drawing of the semiconductor device of a modification is typically shown.

以下、本明細書で開示される技術の特徴を整理する。なお、以下に記す事項は、各々単独で技術的な有用性を有している。   The technical features disclosed in this specification will be summarized below. The items described below have technical usefulness independently.

本明細書で開示する半導体装置の一実施形態は、半導体活性層、ソース電極及びドレイン電極を備えていてもよい。半導体活性層は、ＳＯＩ基板の構成要素であってもよい。半導体活性層は、第１導電型のソース領域、第２導電型のボディ領域、第１導電型のドレイン領域、第１導電型のドリフト領域、第２導電型のベース領域及び第２導電型の第１深部半導体領域を有していてもよい。ソース領域は、半導体活性層の上面に露出しており、ソース電極に接する。ボディ領域は、半導体活性層の上面に露出しており、ソース領域を囲んでおり、ソース電極に接する。ドレイン領域は、半導体活性層の上面に露出しており、半導体活性層の上面に平行な少なくとも一方向においてボディ領域から離れて配置されており、ドレイン電極に接する。ドリフト領域は、ボディ領域とドレイン領域の間に配置されており、ドレイン領域の不純物濃度よりも薄い不純物濃度を含む。ベース領域は、半導体活性層の上面に露出しており、前記一方向においてボディ領域から離れて配置されており、ドリフト領域によってボディ領域から隔てられており、ドレイン電極に接する。ベース領域は、ドレイン領域よりもボディ領域側に配置されているのが望ましい。第１深部半導体領域は、ドリフト領域によって半導体活性層の上面から隔てられており、ボディ領域に接しており、前記一方向に沿ってボディ領域からベース領域側に向けて延びている。半導体装置はさらに、ゲート電極を備えていてもよい。ゲート電極は、ソース領域とドリフト領域を隔てるボディ領域に絶縁膜を介して対向する。   One embodiment of the semiconductor device disclosed in this specification may include a semiconductor active layer, a source electrode, and a drain electrode. The semiconductor active layer may be a component of the SOI substrate. The semiconductor active layer includes a first conductivity type source region, a second conductivity type body region, a first conductivity type drain region, a first conductivity type drift region, a second conductivity type base region, and a second conductivity type. The first deep semiconductor region may be included. The source region is exposed on the upper surface of the semiconductor active layer and is in contact with the source electrode. The body region is exposed on the upper surface of the semiconductor active layer, surrounds the source region, and is in contact with the source electrode. The drain region is exposed on the upper surface of the semiconductor active layer, is disposed away from the body region in at least one direction parallel to the upper surface of the semiconductor active layer, and is in contact with the drain electrode. The drift region is disposed between the body region and the drain region, and includes an impurity concentration lower than the impurity concentration of the drain region. The base region is exposed on the upper surface of the semiconductor active layer, is disposed away from the body region in the one direction, is separated from the body region by the drift region, and is in contact with the drain electrode. The base region is desirably disposed on the body region side with respect to the drain region. The first deep semiconductor region is separated from the upper surface of the semiconductor active layer by the drift region, is in contact with the body region, and extends from the body region toward the base region along the one direction. The semiconductor device may further include a gate electrode. The gate electrode faces the body region that separates the source region and the drift region via an insulating film.

半導体活性層はさらに、第１導電型の第２深部半導体領域を有していてもよい。第２深部半導体領域は、ドリフト領域によって半導体活性層の上面から隔てられており、第１深部半導体領域よりもドレイン領域側に設けられており、ドリフト領域の不純物濃度よりも濃い不純物濃度を含む。第２深部半導体領域を有する半導体装置では、内蔵サイリスタが動作したときの電流集中がさらに緩和され、局所的な電流集中による素子破壊がさらに抑制される。   The semiconductor active layer may further include a first conductivity type second deep semiconductor region. The second deep semiconductor region is separated from the upper surface of the semiconductor active layer by the drift region, is provided closer to the drain region than the first deep semiconductor region, and includes an impurity concentration higher than the impurity concentration of the drift region. In the semiconductor device having the second deep semiconductor region, the current concentration when the built-in thyristor is operated is further relaxed, and the element breakdown due to the local current concentration is further suppressed.

図１〜図３に示されるように、半導体装置１は、ＬＤＭＯＳであり、半導体基板１０、複数の電極３２，３４，３６及びＬＯＣＯＳ酸化膜４２を備える。   As shown in FIGS. 1 to 3, the semiconductor device 1 is an LDMOS, and includes a semiconductor substrate 10, a plurality of electrodes 32, 34, 36 and a LOCOS oxide film 42.

半導体基板１０は、半導体支持層１２、埋込み絶縁層１４及び半導体活性層１６を有する。半導体支持層１２の材料は、リン又はボロンの不純物を高濃度に含むシリコン単結晶である。埋込み絶縁層１４は、半導体支持層１２の上面に接しており、半導体支持層１２と半導体活性層１６を隔てる。埋込み絶縁層１４の材料は、酸化シリコンである。半導体活性層１６は、埋込み絶縁層１４の上面に接する。半導体活性層１６の材料は、リンを低濃度に含むシリコン単結晶である。このように、半導体基板１０は、半導体支持層１２、埋込み絶縁層１４及び半導体活性層１６が積層して構成されており、ＳＯＩ基板と称されるものである。   The semiconductor substrate 10 has a semiconductor support layer 12, a buried insulating layer 14, and a semiconductor active layer 16. The material of the semiconductor support layer 12 is a silicon single crystal containing a high concentration of phosphorus or boron impurities. The buried insulating layer 14 is in contact with the upper surface of the semiconductor support layer 12 and separates the semiconductor support layer 12 and the semiconductor active layer 16. The material of the buried insulating layer 14 is silicon oxide. The semiconductor active layer 16 is in contact with the upper surface of the buried insulating layer 14. The material of the semiconductor active layer 16 is a silicon single crystal containing phosphorus at a low concentration. As described above, the semiconductor substrate 10 is configured by laminating the semiconductor support layer 12, the buried insulating layer 14, and the semiconductor active layer 16, and is referred to as an SOI substrate.

半導体活性層１６は、ｐ型のボディ領域２１、ｎ型のソース領域２２、ｐ型の第１深部半導体領域２３、ｎ型のドリフト領域２４、ｐ型のベース領域２５及びｎ型のドレイン領域２６を含む。   The semiconductor active layer 16 includes a p-type body region 21, an n-type source region 22, a p-type first deep semiconductor region 23, an n-type drift region 24, a p-type base region 25, and an n-type drain region 26. including.

ボディ領域２１は、半導体活性層１６の表層部の一部に設けられており、半導体活性層１６の上面に露出しており、不純物濃度が相対的に濃いコンタクト部２１ａと不純物濃度が相対的に薄いメイン部２１ｂを有する。ボディ領域２１のコンタクト部２１ａは、半導体活性層１６の上面の一部を被覆するソース電極３２にオーミック接触する。ボディ領域２１は、イオン注入技術を利用して、半導体活性層１６の上面からボロンを注入することで形成される。   The body region 21 is provided in a part of the surface layer portion of the semiconductor active layer 16 and is exposed on the upper surface of the semiconductor active layer 16, and the impurity concentration is relatively higher than that of the contact portion 21 a having a relatively high impurity concentration. It has a thin main part 21b. The contact portion 21 a of the body region 21 is in ohmic contact with the source electrode 32 that covers a part of the upper surface of the semiconductor active layer 16. The body region 21 is formed by implanting boron from the upper surface of the semiconductor active layer 16 using an ion implantation technique.

ソース領域２２は、半導体活性層１６の表層部の一部に設けられており、半導体活性層１６の上面に露出しており、ボディ領域２１のメイン部２１ｂに囲まれている。ソース領域２２は、半導体活性層１６の上面の一部を被覆するソース電極３２にオーミック接触する。ソース領域２２は、イオン注入技術を利用して、半導体活性層１６の上面からリンを高濃度に注入することで形成される。なお、ボディ領域２１のコンタクト部２１ａとソース領域２２は、離れているのが望ましい。ボディ領域２１のコンタクト部２１ａとソース領域２２が離れていると、製造バラツキによってこれらの面方向の位置が変動しても、半導体装置１の電気的特性に与える影響が抑えられる。また、必要に応じて、ボディ領域２１のコンタクト部２１ａとソース領域２２の間に絶縁層を設けてもよい。   The source region 22 is provided in a part of the surface layer portion of the semiconductor active layer 16, is exposed on the upper surface of the semiconductor active layer 16, and is surrounded by the main portion 21 b of the body region 21. The source region 22 is in ohmic contact with the source electrode 32 that covers a part of the upper surface of the semiconductor active layer 16. The source region 22 is formed by implanting phosphorus at a high concentration from the upper surface of the semiconductor active layer 16 using an ion implantation technique. It is desirable that the contact portion 21a of the body region 21 and the source region 22 are separated from each other. When the contact portion 21a and the source region 22 are separated from each other in the body region 21, the influence on the electrical characteristics of the semiconductor device 1 can be suppressed even if the position in the surface direction varies due to manufacturing variations. In addition, an insulating layer may be provided between the contact portion 21a of the body region 21 and the source region 22 as necessary.

第１深部半導体領域２３は、ドリフト領域２４によって半導体活性層１６の上面から隔てられており、半導体活性層１６の所定深さを面的に広がって形成されている。第１深部半導体領域２３は、ボディ領域２１のメイン部２１ｂの下面に接している。第１深部半導体領域２３は、ソース領域２２とドレイン領域２６を結ぶ方向（紙面左右方向であり、以下、ソース・ドレイン間方向という）に沿って、ボディ領域２１からベース領域２５側に向けて延びている。半導体活性層１６の上面に直交する方向から観測したときに、第１深部半導体領域２３のベース領域２５側の先端は、ＬＯＣＯＳ酸化膜４２の下方に配置されている。第１深部半導体領域２３は、イオン注入技術を利用して、半導体活性層１６の上面からボロンを注入することで形成される。なお、第１深部半導体領域２３は、埋込み絶縁層１４に接するように設けられていてもよい。   The first deep semiconductor region 23 is separated from the upper surface of the semiconductor active layer 16 by the drift region 24, and is formed by extending a predetermined depth of the semiconductor active layer 16 in a plane. The first deep semiconductor region 23 is in contact with the lower surface of the main portion 21 b of the body region 21. The first deep semiconductor region 23 extends from the body region 21 toward the base region 25 along the direction connecting the source region 22 and the drain region 26 (the horizontal direction in the drawing, hereinafter referred to as the source-drain direction). ing. When observed from a direction orthogonal to the upper surface of the semiconductor active layer 16, the tip of the first deep semiconductor region 23 on the base region 25 side is disposed below the LOCOS oxide film 42. The first deep semiconductor region 23 is formed by implanting boron from the upper surface of the semiconductor active layer 16 using an ion implantation technique. The first deep semiconductor region 23 may be provided so as to be in contact with the buried insulating layer 14.

ドリフト領域２４は、半導体活性層１６の上面に露出しており、ボディ領域２１、第１深部半導体領域２３、ベース領域２５、ドレイン領域２６及び埋込み絶縁層１４に接する。ドリフト領域２４は、ボディ領域２１によってソース領域２２から隔てられている。ドリフト領域２４を間において、ソース・ドレイン間方向の一方側にボディ領域２１とソース領域２２と第１深部半導体領域２３が配置されており、ソース・ドレイン間方向の他方側にベース領域２５とドレイン領域２６が配置されている。ドリフト領域２４の不純物濃度は、ドレイン領域２６の不純物濃度よりも薄い。ドリフト領域２４は、半導体活性層１６に他の半導体領域を形成した残部である。   The drift region 24 is exposed on the upper surface of the semiconductor active layer 16 and is in contact with the body region 21, the first deep semiconductor region 23, the base region 25, the drain region 26, and the buried insulating layer 14. The drift region 24 is separated from the source region 22 by the body region 21. Between the drift region 24, the body region 21, the source region 22, and the first deep semiconductor region 23 are disposed on one side in the source-drain direction, and the base region 25 and the drain are disposed on the other side in the source-drain direction. A region 26 is arranged. The impurity concentration of the drift region 24 is lower than the impurity concentration of the drain region 26. The drift region 24 is a remaining part in which another semiconductor region is formed in the semiconductor active layer 16.

ベース領域２５は、半導体活性層１６の表層部の一部に設けられており、半導体活性層１６の上面に露出する。ベース領域２５は、ソース・ドレイン間方向においてボディ領域２１から離れて配置されており、ドレイン領域２６よりもボディ領域２１側に配置されており、ドリフト領域２４によってボディ領域２１から隔てられている。ベース領域２５は、半導体活性層１６の上面の一部を被覆するドレイン電極３６にオーミック接触する。ベース領域２５は、イオン注入技術を利用して、半導体活性層１６の上面からボロンを高濃度に注入することで形成される。   The base region 25 is provided in a part of the surface layer portion of the semiconductor active layer 16 and is exposed on the upper surface of the semiconductor active layer 16. The base region 25 is disposed away from the body region 21 in the source-drain direction, is disposed closer to the body region 21 than the drain region 26, and is separated from the body region 21 by the drift region 24. The base region 25 is in ohmic contact with the drain electrode 36 that covers a part of the upper surface of the semiconductor active layer 16. The base region 25 is formed by implanting boron at a high concentration from the upper surface of the semiconductor active layer 16 using an ion implantation technique.

ドレイン領域２６は、半導体活性層１６の表層部の一部に設けられており、半導体活性層１６の上面に露出する。ドレイン領域２６は、ソース・ドレイン間方向においてボディ領域２１から離れて配置されており、ドリフト領域２４によってボディ領域２１から隔てられている。ドレイン領域２６は、半導体活性層１６の上面の一部を被覆するドレイン電極３６にオーミック接触する。ドレイン領域２６は、イオン注入技術を利用して、半導体活性層１６の上面からリンを高濃度に注入することで形成される。なお、ベース領域２５とドレイン領域２６は、離れているのが望ましい。ベース領域２５とドレイン領域２６が離れていると、製造バラツキによってこれらの面内方向の位置が変動しても、半導体装置１の電気的特性に与える影響が抑えられる。また、必要に応じて、ベース領域２５とドレイン領域２６の間に絶縁層を設けてもよい。   The drain region 26 is provided in a part of the surface layer portion of the semiconductor active layer 16 and is exposed on the upper surface of the semiconductor active layer 16. The drain region 26 is disposed away from the body region 21 in the source-drain direction, and is separated from the body region 21 by the drift region 24. The drain region 26 is in ohmic contact with a drain electrode 36 that covers a part of the upper surface of the semiconductor active layer 16. The drain region 26 is formed by implanting phosphorus at a high concentration from the upper surface of the semiconductor active layer 16 using an ion implantation technique. Note that the base region 25 and the drain region 26 are preferably separated from each other. When the base region 25 and the drain region 26 are separated from each other, even if the position in the in-plane direction varies due to manufacturing variations, the influence on the electrical characteristics of the semiconductor device 1 can be suppressed. Further, an insulating layer may be provided between the base region 25 and the drain region 26 as necessary.

ゲート電極３４は、ソース領域２２とドリフト領域２４を隔てるボディ領域２１のメイン部２１ｂに絶縁膜を介して対向する。   The gate electrode 34 faces the main portion 21b of the body region 21 that separates the source region 22 and the drift region 24 via an insulating film.

ＬＯＣＯＳ酸化膜４２は、半導体活性層１６の上面を被覆しており、半導体活性層１６の上面に直交する方向から観測したときに、ボディ領域２１とベース領域２５の間に配置されている。   The LOCOS oxide film 42 covers the upper surface of the semiconductor active layer 16 and is disposed between the body region 21 and the base region 25 when observed from a direction orthogonal to the upper surface of the semiconductor active layer 16.

半導体装置１は、ＮＰＮトランジスタとＰＮＰトランジスタで構成されるサイリスタを内蔵する。ＮＰＮトランジスタは、ソース領域２２、ボディ領域２１及びドリフト領域２４によって構成されている。ＰＮＰトランジスタは、ボディ領域２１、ドリフト領域２４及びベース領域２５によって構成されている。さらに、ＰＮＰトランジスタは、第１深部半導体領域２３、ドリフト領域２４及びベース領域２５によっても構成されている。   The semiconductor device 1 includes a thyristor composed of an NPN transistor and a PNP transistor. The NPN transistor is composed of a source region 22, a body region 21 and a drift region 24. The PNP transistor includes a body region 21, a drift region 24, and a base region 25. Further, the PNP transistor is also constituted by the first deep semiconductor region 23, the drift region 24 and the base region 25.

半導体装置１では、ソース電極３２が接地されており、ドレイン電極３６が図示しない電源に接続されている。半導体装置１では、ドレイン電極３６の配線に静電気放電（ESD）が印加されると、第１深部半導体領域２３とドリフト領域２４のｐｎ接合面の高電界領域がアバランシェによってブレークダウンし、高電界領域でキャリアが発生し、第１深部半導体領域２３とドリフト領域２４に電流が流れる。このため、ＮＰＮトランジスタのベース電位（第１深部半導体領域２３及びボディ領域２１の電位）が上昇してＮＰＮトランジスタが動作するとともに、ＰＮＰトランジスタのベース電位（ドリフト領域２４の電位）が上昇してＰＮＰトランジスタが動作する。これにより、内蔵サイリスタが動作し、ドレイン電極３６の電位がサイリスタ動作の保持電圧まで低下する。   In the semiconductor device 1, the source electrode 32 is grounded, and the drain electrode 36 is connected to a power source (not shown). In the semiconductor device 1, when electrostatic discharge (ESD) is applied to the wiring of the drain electrode 36, the high electric field region of the pn junction surface between the first deep semiconductor region 23 and the drift region 24 breaks down by the avalanche, and the high electric field region Carriers are generated at this time, and current flows through the first deep semiconductor region 23 and the drift region 24. For this reason, the base potential of the NPN transistor (the potential of the first deep semiconductor region 23 and the body region 21) is increased to operate the NPN transistor, and the base potential of the PNP transistor (the potential of the drift region 24) is increased to increase the PNP. The transistor operates. As a result, the built-in thyristor operates, and the potential of the drain electrode 36 decreases to the holding voltage of the thyristor operation.

半導体装置１では、第１深部半導体領域２３が半導体活性層１６の深い位置に形成されているとともにボディ領域２１よりもベース領域２５に近い位置に配置されているので、内蔵サイリスタのトリガとなる高電界領域が半導体活性層１６の深い位置に存在するようになる。これにより、第１深部半導体領域２３、ドリフト領域２４及びベース領域２５で構成されるＰＮＰトランジスタを流れる電流は、半導体活性層１６の深い位置を流れるようになる。即ち、内蔵サイリスタが動作したときの電流の一部が、半導体活性層１６の深い位置を流れる。このように、半導体装置１では、内蔵サイリスタが動作したときの電流が半導体活性層１６の厚み方向にも流れることができるので、電流集中が緩和され、局所的な電流集中による素子破壊が抑制される。また、半導体装置１では、第１深部半導体領域２３が半導体活性層１６の深い位置に形成されているので、ＬＤＭＯＳとしての動作に影響を与えない。   In the semiconductor device 1, the first deep semiconductor region 23 is formed deep in the semiconductor active layer 16 and is located closer to the base region 25 than the body region 21. The electric field region exists at a deep position in the semiconductor active layer 16. As a result, the current flowing through the PNP transistor constituted by the first deep semiconductor region 23, the drift region 24, and the base region 25 flows in a deep position of the semiconductor active layer 16. That is, a part of the current when the built-in thyristor is operated flows deep in the semiconductor active layer 16. As described above, in the semiconductor device 1, the current when the built-in thyristor operates can also flow in the thickness direction of the semiconductor active layer 16, so that the current concentration is relaxed and the element breakdown due to the local current concentration is suppressed. The In the semiconductor device 1, the first deep semiconductor region 23 is formed at a deep position in the semiconductor active layer 16, so that the operation as an LDMOS is not affected.

図４に示される変形例の半導体装置２は、半導体活性層１６内にｎ型の第２深部半導体領域２７が形成されていることを特徴とする。第２深部半導体領域２７は、ドリフト領域２４によって半導体活性層１６の上面から隔てられており、半導体活性層１６の所定深さを面的に広がって形成されている。第２深部半導体領域２７は、第１深部半導体領域２３とドレイン領域２６の間に設けられており、ドリフト領域２４の不純物濃度よりも濃い不純物濃度を含む。半導体活性層１６の上面に直交する方向から観測したときに、第２深部半導体領域２７は、ドレイン領域２６の下方に配置されるとともに、そのボディ領域２１側の先端がＬＯＣＯＳ酸化膜４２の下方に配置されている。第２深部半導体領域２７は、イオン注入技術を利用して、半導体活性層１６の上面からリンを注入することで形成される。   The semiconductor device 2 of the modification shown in FIG. 4 is characterized in that an n-type second deep semiconductor region 27 is formed in the semiconductor active layer 16. The second deep semiconductor region 27 is separated from the upper surface of the semiconductor active layer 16 by the drift region 24, and is formed so as to extend a predetermined depth of the semiconductor active layer 16 in a plane. The second deep semiconductor region 27 is provided between the first deep semiconductor region 23 and the drain region 26 and includes an impurity concentration higher than that of the drift region 24. When observed from a direction orthogonal to the upper surface of the semiconductor active layer 16, the second deep semiconductor region 27 is disposed below the drain region 26, and the tip on the body region 21 side is below the LOCOS oxide film 42. Has been placed. The second deep semiconductor region 27 is formed by implanting phosphorus from the upper surface of the semiconductor active layer 16 using an ion implantation technique.

第２深部半導体領域２７が設けられていると、内蔵サイリスタが動作したときの電流のうちのソース領域２２、ボディ領域２１及びドリフト領域２４で構成されるＮＰＮトランジスタを流れる電流の一部は、低抵抗な第２深部半導体領域２７を通過する。このため、ＮＰＮトランジスタを流れる電流一部は、半導体活性層１６の深い位置を流れるようになる。このように、半導体装置２では、内蔵サイリスタが動作したときの電流の多くが厚み方向にも広がって流れるので、電流集中がさらに緩和され、局所的な電流集中による素子破壊がさらに抑制される。   When the second deep semiconductor region 27 is provided, a part of the current flowing through the NPN transistor composed of the source region 22, the body region 21, and the drift region 24 among the current when the built-in thyristor operates is low. It passes through the resistive second deep semiconductor region 27. For this reason, a part of the current flowing through the NPN transistor flows in a deep position of the semiconductor active layer 16. As described above, in the semiconductor device 2, since most of the current when the built-in thyristor is operated flows in the thickness direction, current concentration is further relaxed, and element breakdown due to local current concentration is further suppressed.

なお、この変形例では、第２深部半導体領域２７が１つの層として形成されている場合を例示したが、この例に代えて、第２深部半導体領域２７は、半導体活性層１６の面内方向及び／又は厚み方向に分散して配置された複数のｎ型半導体領域の集合として構成されてもよい。また、この変形例では、第１深部半導体領域２３と第２深部半導体領域２７の半導体活性層１６内における深さが同一の場合を例示したが、この例に代えて、第１深部半導体領域２３と第２深部半導体領域２７の半導体活性層１６内における深さが異なっていてもよい。具体的には、第１深部半導体領域２３と第２深部半導体領域２７の半導体活性層１６の厚み方向における不純物濃度の各々のピーク位置が同一であってもよく、異なっていてもよい。また、この変形例では、第１深部半導体領域２３の先端と第２深部半導体領域２７の先端が離れている場合を例示したが、この例に代えて、第１深部半導体領域２３の先端と第２深部半導体領域２７の先端が接していてもよい。   In this modification, the case where the second deep semiconductor region 27 is formed as one layer is illustrated, but instead of this example, the second deep semiconductor region 27 is formed in the in-plane direction of the semiconductor active layer 16. And / or it may be configured as a set of a plurality of n-type semiconductor regions arranged dispersed in the thickness direction. Further, in this modification, the case where the first deep semiconductor region 23 and the second deep semiconductor region 27 have the same depth in the semiconductor active layer 16 is illustrated, but instead of this example, the first deep semiconductor region 23 is used. And the depth of the second deep semiconductor region 27 in the semiconductor active layer 16 may be different. Specifically, the peak positions of the impurity concentrations in the thickness direction of the semiconductor active layer 16 in the first deep semiconductor region 23 and the second deep semiconductor region 27 may be the same or different. Further, in this modification, the case where the tip of the first deep semiconductor region 23 and the tip of the second deep semiconductor region 27 are separated is illustrated, but instead of this example, the tip of the first deep semiconductor region 23 and the second deep semiconductor region 23 2 The tip of the deep semiconductor region 27 may be in contact.

以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。   Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

１０：半導体基板
１２：半導体支持層
１４：埋込み絶縁層
１６：半導体活性層
２１：ボディ領域
２１ａ：コンタクト部
２１ｂ：メイン部
２２：ソース領域
２３：第１深部半導体領域
２４：ドリフト領域
２５：ベース領域
２６：ドレイン領域
３２：ソース電極
３４：ゲート電極
３６：ドレイン電極
４２：ＬＯＣＯＳ酸化膜 10: Semiconductor substrate 12: Semiconductor support layer 14: Buried insulating layer 16: Semiconductor active layer 21: Body region 21a: Contact portion 21b: Main portion 22: Source region 23: First deep semiconductor region 24: Drift region 25: Base region 26: drain region 32: source electrode 34: gate electrode 36: drain electrode 42: LOCOS oxide film

Claims (1)

半導体活性層、ソース電極及びドレイン電極を備え、
前記半導体活性層は、
前記半導体活性層の上面に露出しており、前記ソース電極に接する第１導電型のソース領域と、
前記半導体活性層の上面に露出しており、前記ソース領域を囲んでおり、前記ソース電極に接する第２導電型のボディ領域と、
前記半導体活性層の上面に露出しており、前記半導体活性層の上面に平行な少なくとも一方向において前記ボディ領域から離れて配置されており、前記ドレイン電極に接する第１導電型のドレイン領域と、
前記ボディ領域と前記ドレイン領域の間に配置されており、前記ドレイン領域の不純物濃度よりも薄い不純物濃度を含む第１導電型のドリフト領域と、
前記半導体活性層の上面に露出しており、前記一方向において前記ボディ領域から離れて配置されており、前記ドリフト領域によって前記ボディ領域から隔てられており、前記ドレイン電極に接する第２導電型のベース領域と、
前記ドリフト領域によって前記半導体活性層の上面から隔てられており、前記ボディ領域に接しており、前記一方向に沿って前記ボディ領域から前記ベース領域側に向けて延びている第２導電型の第１深部半導体領域と、
前記ドリフト領域によって前記半導体活性層の上面から隔てられており、前記第１深部半導体領域よりも前記ドレイン領域側に設けられており、前記ドリフト領域の不純物濃度よりも濃い不純物濃度を含む第１導電型の第２深部半導体領域と、を有しており、
前記第１深部半導体領域と前記第２深部半導体領域が前記半導体活性層内の同一深さに設けられており、前記第１深部半導体領域の先端と前記第２深部半導体領域の先端が接しており、
前記第１深部半導体領域と前記第２深部半導体領域は、前記半導体活性層の下面から隔てられており、
前記半導体活性層の一部である第１導電型の部分が、前記第１深部半導体領域と前記第２深部半導体領域の下方に存在している、半導体装置。
A semiconductor active layer, a source electrode and a drain electrode;
The semiconductor active layer is
A source region of a first conductivity type exposed on an upper surface of the semiconductor active layer and in contact with the source electrode;
A body region of a second conductivity type exposed on an upper surface of the semiconductor active layer, surrounding the source region, and in contact with the source electrode;
A drain region of a first conductivity type that is exposed on the upper surface of the semiconductor active layer, is spaced apart from the body region in at least one direction parallel to the upper surface of the semiconductor active layer, and is in contact with the drain electrode;
A first conductivity type drift region that is disposed between the body region and the drain region and includes an impurity concentration lower than an impurity concentration of the drain region;
Exposed on the upper surface of the semiconductor active layer, arranged away from the body region in the one direction, separated from the body region by the drift region, and of a second conductivity type in contact with the drain electrode The base region,
The second conductivity type is separated from the upper surface of the semiconductor active layer by the drift region, is in contact with the body region, and extends from the body region toward the base region along the one direction. 1 deep semiconductor region;
First conductivity separated from the upper surface of the semiconductor active layer by the drift region, provided closer to the drain region than the first deep semiconductor region, and having a higher impurity concentration than the impurity concentration of the drift region. A second deep semiconductor region of the mold,
The first deep semiconductor region and the second deep semiconductor region are provided at the same depth in the semiconductor active layer, and a tip of the first deep semiconductor region and a tip of the second deep semiconductor region are in contact with each other. ,
The first deep semiconductor region and the second deep semiconductor region are separated from a lower surface of the semiconductor active layer;
A semiconductor device, wherein a portion of the first conductivity type, which is a part of the semiconductor active layer, exists below the first deep semiconductor region and the second deep semiconductor region .
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