JP6796034B2 - Semiconductor device - Google Patents

Description

Embodiments of the present invention relate to semiconductor devices.

MOSFET (Metal Oxide Semiconductor Field) is one of the semiconductors used for electric power.
Effect Transistor). When this MOSFET is off, the gate voltage oscillates, and the gate noise level may exceed the EMI specified level of the power supply circuit.

Japanese Unexamined Patent Publication No. 2011-134998

An object to be solved by the present invention is to provide a semiconductor device having an improved ESD (Electro-Static Discharge) withstand capacity.

The semiconductor device according to the embodiment is a semiconductor device having a cell portion, an outer peripheral portion, and a lead-out portion, and the cell portion includes a drain metal layer and a laminated semiconductor layer provided on the drain metal layer. A part of the above, a gate oxide film provided on the laminated semiconductor layer, a gate conductive layer provided on the gate oxide film, and a source provided on the gate conductive layer via an insulating interlayer film. The laminated semiconductor layer including an electrode includes a first conductive type first semiconductor region provided on the drain metal layer and a second conductive type second semiconductor region provided on the first semiconductor region. a semiconductor region, the third semiconductor region of the first conductivity type selectively formed on a surface of the second semiconductor region, selectively formed second conductivity type contact regions on a surface of said second semiconductor region The outer peripheral portion includes the drain metal layer, a part of the laminated semiconductor layer, and a first oxide film provided on the laminated semiconductor layer and in contact with the gate oxide film, and the said. The wiring layer provided on the first oxide film and the wiring layer are insulated from each other via an insulating interlayer film, and the gate metal layer provided on the insulating interlayer film and the wiring layer A first contact portion with which the gate metal layer contacts, a resistance portion formed on the wiring layer, and a field oxide film provided on the laminated semiconductor layer are included, and the drawer portion is the drain metal. The layer, a part of the laminated semiconductor layer, the insulating interlayer film, the second oxide film provided on the laminated semiconductor layer, the extraction layer provided on the second oxide film, and the above. A semiconductor device having the gate metal layer provided on the lead-out layer and a second contact portion in which the lead-out layer comes into contact with the gate metal layer.

It is an image diagram seen from the upper surface of the semiconductor device 100 which concerns on 1st Embodiment. FIG. 1A is an image view of the upper surface of the semiconductor device 100 through which the upper gate metal layer 5 and the source electrode 4 are transmitted. In FIG. 1 (b), the oxide film volume part is illustrated. It is sectional drawing which enlarged the part of FIG. 1 (a) in AA'. It is sectional drawing which enlarged the part of FIG. 1 (a) in BB'. It is sectional drawing which enlarged the part of FIG. 1 (a) in CC'. It is sectional drawing which enlarged the part of FIG. 1 (a) in DD'. It is a top view when the gate pad 70 is attached in the semiconductor device 100 which concerns on 1st Embodiment. It is a circuit schematic diagram of the semiconductor device 100 which concerns on 1st Embodiment. It is a transmission image view seen from the upper surface of the semiconductor device 200 which concerns on 1st modification of 1st Embodiment. It is sectional drawing corresponding to FIG. 2 of the semiconductor device 200. It is a transmission image diagram corresponding to FIG. 1 (b) of the semiconductor device 300 which concerns on a comparative example. In FIG. 10A, the oxide film capacity is illustrated. It is sectional drawing which corresponds to FIG. 2 of the semiconductor device 300.

Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same members are designated by the same reference numerals, and the description of the members once described will be omitted as appropriate.

The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between the parts, and the like are not necessarily the same as the actual ones. Further, even when the same parts are represented, the dimensions and ratios may be different from each other depending on the drawings.

An XYZ Cartesian coordinate system is used for the description of each embodiment. The direction from the n ^{+ type} semiconductor region 9 to the n ^{− type} semiconductor region 10 is defined as the Z direction (first direction). Perpendicular to the Z direction
The two directions orthogonal to each other are the X direction and the Y direction (second direction).

In the following description, the notation of n ⁺ , n ⁻ and p ⁺ , p represents the relative high and low of the impurity concentration in each conductive form. That is, the notation with "+" has a relatively higher impurity concentration than the notation without either "+" or "-", and any notation with "-" will be used. Indicates that the impurity concentration is relatively lower than the notation not marked with.

For each embodiment described below, the p-type and n-type of each semiconductor region may be inverted to carry out each embodiment.

(First Embodiment)
A first embodiment of the present invention will be described with reference to FIGS. 1 to 7. FIG. 1A is an image view of the semiconductor device 100 according to the first embodiment as viewed from above. FIG. 1 (b) is shown in FIG. 1 (a).
It is an image view seen from the upper surface of the semiconductor device 100 through which the upper gate metal layer 5 and the source electrode 4 are transmitted. FIG. 1 (c) shows the oxide film volume portion in FIG. 1 (b). FIG. 2 is an enlarged cross-sectional view of a part of FIG. 1 (a) in AA'. Figure 3
Is an enlarged cross-sectional view of a part of FIG. 1 (a) in BB'. FIG. 4 is an enlarged cross-sectional view of a part of FIG. 1A in CC'. FIG. 5 is an enlarged cross-sectional view of a part of FIG. 1 (a) in DD'. FIG. 6 is a top view of the semiconductor device 100 according to the first embodiment when a gate pad is attached. FIG. 7 is a schematic circuit diagram of the semiconductor device 100 according to the first embodiment.

The semiconductor device 100 is, for example, a MOSFET.

As shown in FIGS. 1B and 2, the semiconductor device 100 includes a cell portion 1, an outer peripheral portion 2, and the like.
Includes a drawer 3. Further, each of the cell portion 1, the outer peripheral portion 2, and the lead-out portion 3 shares a part of the drain electrode 20 and the laminated semiconductor region 17.

A laminated semiconductor region 17 is provided on the upper surface of the drain electrode 20.

The laminated semiconductor region 17 includes an n ^{+ type} (first conductive type) drain region 9 and an n ^{− type} semiconductor region 1.
0 (first semiconductor region), p-type (second conductive type) base region 11 (second semiconductor region), and n
⁺ Including -type source region 12 (third semiconductor region), and ^{p +} -type contact region 13.

The n ^{+ type} (first conductive type) drain region 9 is provided on the drain electrode 20 and is electrically connected to the drain electrode 20.

the n ^- type semiconductor region 10 is provided on the ^{n +} -type drain region 9.

p-type base region 11, n ^- is provided on the type semiconductor region 10. A plurality of p-shaped base regions 11 are provided in the Y direction, and each of them extends in the X direction.

n ⁺ -type source region 12 and ^{p +} -type contact region 13 is selectively provided on the p-type base region 11.

First, the configuration of the cell unit 1 will be described. The cell portion 1 includes the drain electrode 20 and the cell portion 1 as described above.
A part of the laminated semiconductor region 17, a gate oxide film 14, a gate conductive layer 7, and an insulating interlayer film 15.
And the source electrode 4.

In the cell portion 1, the gate oxide film 14 and the insulating interlayer film 15 are placed on the laminated semiconductor region 17.
Is provided. Further, the gate conductive layer 7 is provided on the gate oxide film 14. An insulating interlayer film 15 is provided between the gate conductive layer 7 and the source electrode 4. A plurality of the gate conductive layer 7 and the gate oxide film 14 are provided in the Y direction in FIG. 2, and each of them extends in the X direction.

The source electrode 4 is provided on the n ^{+ type} source region 12 and the p ^{+ type} contact region 13, and n
⁺ -Type source region 12 and p ⁺ -type contact region 13 are electrically connected to the.

Next, as described above, the outer peripheral portion 2 includes the drain electrode 20, a part of the laminated semiconductor region 17, the first oxide film 18, the field oxide film 16, the wiring layer 6, and the insulating interlayer film 15. , The gate metal layer 5 and the first contact portion 40.

In the outer peripheral portion 2, the first oxide film 18 and the wiring layer 6 are provided in this order on the laminated semiconductor region 17. A plurality of the first oxide films 18 are provided in the Y direction in FIG. 2, and each of them extends in the X direction. Further, an insulating interlayer film 15 and a gate metal layer 5 are provided in this order on the wiring layer 6. The field oxide film 16 is provided between the laminated semiconductor region 17 and the wiring layer 6. The portion where the gate metal layer 5 and the wiring layer 6 are in contact with each other without sandwiching the insulating interlayer film 15 is the first contact portion 40.

The lead-out portion 3 includes a drain electrode 20, a part of the laminated semiconductor region 17, and a second oxide film 1.
9, the lead-out layer 8, the insulating interlayer film 15, the second contact portion 41, and the gate metal layer 5.
And consists of.

In the drawing portion 3, the second oxide film 19 and the drawing layer 8 are placed on the laminated semiconductor region 17 in this order.
Is provided. The lead-out layer 8 and the gate metal layer 5 are in contact with each other without sandwiching the insulating interlayer film 15. This portion is shown as the second contact portion 41.

The insulating interlayer film 15 is provided on the laminated semiconductor region 17. The outer peripheral portion 2 and the drawer portion 3 share the gate metal layer 5.

An insulating interlayer film 15 is provided between the gate metal layer 5 of the semiconductor device 100 and the source electrode 4, and these electrodes are electrically separated.

As shown in FIG. 6, the gate potential is input from the gate pad 70, and the potential is transmitted to the wiring layer 6 via the gate metal layer 5 and the first contact portion 40. Wiring layer 6 and gate conductive layer 7
Is connected in the XY plane of FIG. 2 and is also electrically connected. Therefore, the wiring layer 6
The potential of is transmitted to the gate conductive layer 7 of the cell portion 1.

Further, the drawer layer 8 of the drawer portion 3 is not connected to the wiring layer 6 of the outer peripheral portion 2 or the gate conductive layer 7 of the cell portion 1 in the X-axis direction of FIG.

Further, as shown in FIGS. 1A and 5, the resistance portion 50 is provided on the laminated semiconductor layer 17 adjacent to the wiring layer 6. The resistance portion 50 is formed of a conductive material such as high-resistance polysilicon. The resistance portion 50 may be created by changing the content of impurity atoms in the wiring layer 6. As will be described later, the resistance portion 50 is provided to intentionally increase the resistance component of the semiconductor device 100 in order to make the switching waveform gentle.

Since the outer peripheral portion 2 and the drawer portion 3 were separated in the description, the first oxide film 18 and the second oxide film 19 were described by different names, but in FIG. 5, the first oxide film 18 was described. , The second oxide film 19 may be combined to form the first oxide film 18.

<Material>
An example of the material of each component will be described.

The n ^{+ type} drain region 9, the n ^{− type} semiconductor region 10, the p type base region 11, the n ^{+ type} source region 12, and the p ^{+ type} contact region 13 are semiconductor materials such as silicon, silicon carbide, gallium nitride, or gallium. Contains arsenic. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity.

The wiring layer 6, the gate conductive layer 7, and the lead-out layer 8 include a conductive material such as polysilicon.

The gate oxide film 14 contains an insulating material such as silicon oxide or silicon nitride.

The source electrode 4, the gate metal layer 5, and the drain electrode 20 include a metal such as aluminum.

<Comparison example>
First, a comparative example will be described.

The MOSFET has a large voltage change rate when it is off, and the gate voltage may oscillate. In order to prevent this noise level from exceeding the EMI regulation level of the power supply circuit, the switching waveform is made gentle by intentionally designing a large resistance in the semiconductor device.

FIG. 10A is a transmission image diagram seen from the upper surface of the semiconductor device 300 according to the comparative example, and is one of the structures to which the above measures have been taken. FIG. 10 (b) shows in FIG. 10 (b).
The oxide film capacity is illustrated, and FIG. 11 is a cross-sectional view corresponding to FIG. 2 of the semiconductor device 300. The field oxide film boundary portion 80, which is the boundary line between the field oxide film 16 and the first oxide film 18, is also shown in preparation for the description of the semiconductor device 200 described later.

The semiconductor device 300 includes a cell portion 1 and an outer peripheral portion 2. A gate metal layer 5 is provided on the upper surface of the wiring layer 6 on the outer peripheral portion 2. The difference from the semiconductor device 100 according to the first embodiment is that it does not have the drawer portion 3 and the second contact portion 41.

As in the comparative examples shown in FIGS. 10 and 11, in the semiconductor device 300, there is a problem that the machine model (MM) withstand capacity of electrostatic breakdown (ESD) is low.

ESD is a phenomenon in which a discharge current flows in a device due to a surge or the like. The semiconductor device may be destroyed by local heat generation or electric field concentration due to ESD. The machine model tolerance is a kind of test for evaluating the tolerance for this ESD.

Generally, as the area of a semiconductor device increases, the area of the gate oxide film also increases accordingly, and ESD (M)
M) The withstand capacity also increases. However, in the semiconductor device 300, even if the gate length and the gate width are widened to increase the gate oxide film area and the gate capacitance is increased in proportion to the gate length and the gate width, the ESD resistance is substantially constant. Therefore, it does not show any dependence on gate capacitance.

Further, although there is usually no correlation between the ESD withstand capacity and the resistance value, the ES in the semiconductor device 300
It is known that the D tolerance shows resistance dependence.

As described above, the ESD withstand capacity of the semiconductor device 300 does not show any dependence on the gate capacitance, but shows resistance dependence.

Normally, when ESD occurs, the potential of the gate oxide film of the entire semiconductor device rises, and the gate oxide film at the portion having the highest electric field strength in the semiconductor device should be destroyed. However, in the case of the semiconductor device 300, the potential of the region forming the first contact portion 40 rises first, and the potential in the semiconductor device rises later.

Therefore, in the case of the ESD withstand capacity of the semiconductor device 300, it is considered that there is substantially only the input capacitance of the portion forming the first contact portion 40. More specifically in Figure 1
As shown in 0 (b), the input capacitance (Ciss) is only the oxide film capacitance section 60. actually,
It has been confirmed that the fractured portion in ESD is destroyed in the above portion, and it can be estimated that the oxide film capacity in this portion is the actual input capacitance when ESD occurs. In addition, in FIG. 10B, the first
The contact portion 40 of the above is not shown.

As for the resistance dependence of the ESD withstand, the area of the oxide film capacitance portion 60 changes according to the resistance because the resistance is adjusted by the length of the contact portion. That is, it is considered that the ESD tolerance is not dependent on the gate capacitance but on the resistance due to the area dependence of the oxide film capacitance section 60.

<Action, effect>
In contrast to the above, the semiconductor device 100 according to the first embodiment is provided with a lead-out portion 3 as shown in FIG. 1 (b). In the drawer portion 3, the gate metal layer 5 is formed in the Z direction of FIG.
A drawer layer 8 is installed underneath to form a second contact portion 41. That is, at the second contact portion 41, the gate metal layer 5 and the lead-out layer 8 are connected to each other with low resistance. Unlike the wiring layer 6 on the outer peripheral portion 2, the drawer layer 8 is not connected to the gate conductive layer 7 on the cell portion 1. The semiconductor device 100 increases the oxide film capacity of the second oxide film 19 located under the lead-out layer 8 by increasing the area connected by the first contact portion 40 with low resistance. As a result, in the semiconductor device 100, the ESD withstand capacity is increased. FIG. 1 (c)
The oxide film capacity unit 60 shown in FIG. 6 illustrates a substantial input capacity at the time of ESD. However, Fig. 1
In (c), the second contact portion 41 is not shown.

Further, an explanation will be added using the circuit diagram of FIG. FIG. 7 is a schematic circuit diagram of the semiconductor device 100 according to the first embodiment. Input the gate potential from the gate pad GPAD, and source S
, Drain D are also shown in the figure. Each transistor corresponds to an effective cell of the cell unit 1. Further, the resistance portion 50 and the oxide film capacitance portion 60 are also shown in the figure. Similar to the semiconductor device 300 according to the comparative example, when the gate potential is input from the gate pad to the cell portion, the resistance portion 5
0s are intentionally placed to take measures against noise. The gate potential input from the gate pad is applied to the wiring layer 6, the gate conductive layer 7, and the like via the gate metal layer 5 to the first contact portion 40.
The potential is transmitted to the inner cell 1.

When a surge enters the gate pad, the resistance part 50 exists in the gate line, so
The gate potential on the left side of the resistance portion 50 in FIG. 7 rises. However, by having the input capacitance section 60, it is possible to increase the withstand capacity and prevent the gate oxide film (diode section in the circuit diagram) hanging therein from being destroyed.

Similarly, as shown in FIGS. 10A and 11, in the semiconductor device 300, the gate potential input from the gate pad 70 passes through the gate metal layer 5 and the wiring layer 6. At this time,
An electric potential is applied from the gate metal layer 5 to the wiring layer 6 immediately below the gate metal layer 5 via the first contact portion 40. Further, in the X-axis direction of FIG. 12, the wiring layer 6 and the gate conductive layer 7 are integrated and electrically connected. Therefore, the electric potential is supplied to the cell portion 1 via the gate conductive layer 7. However, the potential of the first oxide film 18 under the first contact portion 40 is easily raised by the resistance portion 50 and is easily destroyed.

On the other hand, as shown in FIG. 2, in the semiconductor device 100, the drawer layer 8 of the drawer portion 3 is
Not directly connected to the gate conductive layer 7. The gate potential input from the gate pad passes through the gate metal layer 5, the first contact portion 40, the wiring layer 6, and the gate conductive layer 7, and the cell portion 1
The electric potential is also applied to the extraction layer 8 and the second oxide film 19 from the gate metal layer 5 via the first contact portion 40. In the semiconductor device 100, not only the first oxide film 18 but also the second oxide film 19 can have a gate capacitance, so that the semiconductor device 30 can have a gate capacitance.
It is different from 0. As a result, it is possible to prevent the first oxide film 18 from being destroyed by the surge from the gate electrode.

As described above, in the semiconductor device 100, it is possible to increase the ESD withstand capability even when the switching waveform is made gentle by intentionally designing the resistance in the semiconductor device to be large.

Further, in FIG. 1A, the first contact portion 40 is shown using a T-shape, but the contact portion may be extended in any direction up, down, left, or right, and the contact portion may be thickened.
It may be extended in multiple directions, or the length and size may be changed as appropriate.

(First modified example according to the first embodiment)
FIG. 8 is a transmission image view of the semiconductor device 200 according to the first modification of the first embodiment as viewed from above. Further, FIG. 11 is a cross-sectional view corresponding to FIG. 2 of the semiconductor device 300.

In the semiconductor device 200, the field oxide film boundary portion 80, which is the boundary line between the field oxide film 16 and the first oxide film 18, is narrower than the structures of the semiconductor device 100 and the semiconductor device 300. In other words, the length of the field oxide film 16 of the semiconductor device 300 in the Y-axis direction in FIG. 10 is longer than that of the semiconductor device 100 and the field oxide film 16 of the semiconductor device 300. Further, the first contact portion 40 of the semiconductor device 200 is provided on the field oxide film 16. In the case of the semiconductor device 100 according to the first embodiment, when the first contact portion 40 is formed, the contact portion is excessively etched due to the length of the etching time, and there is a risk of breaking through the wiring layer 6. is there. However, the semiconductor device 20 according to the first modification
When 0, the field oxide film 16 can suppress a decrease in yield due to etching when the contact portion is formed.

Although the embodiments and modifications of the present invention have been described, these embodiments and modifications are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. As for the specific configuration of each element included in the embodiment, those skilled in the art can appropriately select from known techniques. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1 Cell part 2 Outer part 3 Drawer part 4 Source electrode 5 Gate metal layer 6 Wiring layer 7 Gate conductive layer 8 Drawer layer 9 n ^{+ type} (first conductive type) Drain region 10 n ^{− type} semiconductor region (first semiconductor region)
11 p type (second conductive type) base region (second semiconductor region)
12 n ^{+ type} source region (third semiconductor region)
13 p ^{+ type} contact region 14 Gate oxide film 15 Insulation interlayer film 16 Field oxide film 17 Laminated semiconductor region 18 First oxide film 19 Second oxide film 20 Drain electrode 40 First contact portion 41 Second contact portion 50 Resistance unit 60 Oxidation film capacitance (input capacitance) section 70 Gate pad 80 Field oxide film boundary section 100 Semiconductor device according to the first embodiment of the present invention 200 Semiconductor device according to the first modification 300 Semiconductor device according to a comparative example

Claims (3)

Cell part and
Outer circumference and
A semiconductor device having a drawer and
The cell part is
With the drain metal layer,
A part of the laminated semiconductor layer provided on the drain metal layer and
A gate oxide film provided on the laminated semiconductor layer and
The gate conductive layer provided on the gate oxide film and
A source electrode provided on the gate conductive layer via an insulating interlayer film, and the like.
The laminated semiconductor layer is
The first conductive type first semiconductor region provided on the drain metal layer and
A second conductive type second semiconductor region provided above the first semiconductor region,
A first conductive type third semiconductor region selectively formed on the surface of the second semiconductor region,
A second conductive type contact region selectively formed on the surface of the second semiconductor region,
Including
The outer peripheral portion is
With the drain metal layer
With a part of the laminated semiconductor layer
A first oxide film provided on the laminated semiconductor layer and in contact with the gate oxide film , and
The wiring layer provided on the first oxide film and
The wiring layer includes a gate metal layer provided on the insulating interlayer film in a state of being insulated via the insulating interlayer film.
A first contact portion in which the wiring layer and the gate metal layer come into contact with each other.
The resistance portion formed in the wiring layer and
The field oxide film provided on the laminated semiconductor layer and
Including
The drawer is
With the drain metal layer
With a part of the laminated semiconductor layer
With the insulating interlayer film
A second oxide film provided on the laminated semiconductor layer and
A drawer layer provided on the second oxide film and
With the gate metal layer provided on the drawer layer,
With a second contact portion where the drawer layer comes into contact with the gate metal layer,
Semiconductor devices that have a. The semiconductor device according to claim 1, wherein the second contact portion is formed on the drawer layer provided on the field oxide film. The semiconductor device according to claim 1 or 2, wherein the first contact portion is formed in a region directly above the field oxide film.

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