JP2015018950A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that allows improving resistance characteristics.SOLUTION: A semiconductor device includes: a first semiconductor region provided on a first semiconductor layer in a first region of the first semiconductor layer; a second semiconductor region provided on the first semiconductor region; an insulating film reaching to the first semiconductor layer from a surface of the second semiconductor region; a Zener diode region provided on the first semiconductor layer in the second region of the first semiconductor layer and including a second semiconductor layer in which third semiconductor regions and fourth semiconductor regions are alternately arranged; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the first semiconductor region and the second semiconductor region, and electrically connected to any of the third semiconductor regions in the Zener diode region; and a third electrode in contact with the first semiconductor layer, the first semiconductor region, and the second semiconductor region via the insulating film, and electrically connected to any other of the third semiconductor regions in the Zener diode region.

Description

  Embodiments described herein relate generally to a semiconductor device.

  A semiconductor device having a power semiconductor element has high-speed switching characteristics and high breakdown voltage characteristics, and is used for power conversion, control, and the like in household electrical equipment, communication equipment, and in-vehicle motors. Such a semiconductor device generally has an upper and lower electrode structure that allows current to flow vertically from the viewpoint of effective area ratio (ratio of current-carrying region and non-conducting region of the chip) and heat dissipation during package mounting. .

  However, the gate voltage in a practical circuit may instantaneously exceed the gate guarantee voltage due to a surge due to circuit inductance. If the dielectric strength of the gate oxide film is exceeded, the device is destroyed and the function of the device is lost. Even if the dielectric strength is not exceeded, long-term reliability may be deteriorated due to electrical damage to the gate oxide film. Therefore, there is a demand for a semiconductor device with higher breakdown voltage.

JP 2012-049258 A

  The problem to be solved by the present invention is to provide a semiconductor device capable of improving resistance.

  The semiconductor device according to the embodiment includes a first semiconductor layer, a first semiconductor region of a first conductivity type provided on the first semiconductor layer in the first region of the first semiconductor layer, and the first semiconductor region. A second semiconductor region of a second conductivity type provided on the insulating layer, an insulating film reaching from the surface of the second semiconductor region to the first semiconductor layer, and the first region in the second region of the first semiconductor layer. A Zener diode region including a second semiconductor layer provided on the semiconductor layer, the second semiconductor layer having a second conductive type third semiconductor region and a first conductive type fourth semiconductor region alternately arranged; and the first semiconductor layer A first electrode electrically connected to the first semiconductor region, the first semiconductor region and the second semiconductor region, and electrically connected to any one of the third semiconductor regions in the Zener diode region. Through the second electrode and the insulating film A third electrode in contact with the first semiconductor layer, the first semiconductor region, and the second semiconductor region, and electrically connected to the third semiconductor region other than the one in the Zener diode region; Prepare.

FIG. 1A is a schematic plan view showing the semiconductor device according to the first embodiment, and FIG. 1B is a schematic view at a position along the line AA ′ in FIG. FIG. 1C is a cross-sectional view, and FIG. 1C is a schematic cross-sectional view at a position along the line BB ′ in FIG. FIG. 2 is a schematic plan view showing the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing the semiconductor device according to the first embodiment. FIG. 4A to FIG. 4C are schematic views showing the operation of the semiconductor device according to the first embodiment. FIG. 5 is a schematic plan view showing the semiconductor device according to the second embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same members are denoted by the same reference numerals, and the description of the members once described is omitted as appropriate.

(First embodiment)
FIG. 1A is a schematic plan view showing the semiconductor device according to the first embodiment, and FIG. 1B is a schematic view at a position along the line AA ′ in FIG. FIG. 1C is a cross-sectional view, and FIG. 1C is a schematic cross-sectional view at a position along the line BB ′ in FIG.

  The surface side of the semiconductor device (semiconductor chip) shown in FIG. 1A is, for example, the surface side. On the other hand, the opposite side of the front side is the back side.

  As shown in FIG. 1A, the semiconductor device 1 includes an active region 1a (first region) and a peripheral region 1p (second region) surrounding the active region 1a. A plurality of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are disposed in the active region 1a (described later). No MOSFET is disposed in the peripheral region 1p.

  On the front side of the semiconductor device 1, a source electrode 51 (second electrode) and a gate pad 30p are arranged. The gate pad 30p is electrically connected to a gate electrode of a MOSFET described later. A connection region 30c further extends from the gate pad 30p. Accordingly, the connection region 30c is electrically connected to the gate electrode of the MOSFET. The connection region 30c is provided in the peripheral region 1p.

  As shown in FIGS. 1B and 1C, the active region 1a and the peripheral region 1p are, for example, a drain electrode 50 (first electrode), a drain layer 10 and a drift layer 11 of the semiconductor device 1. (First semiconductor layer) is shared. That is, the active region 1a has a part (first portion) of each of the drain electrode 50, the drain layer 10, and the drift layer 11. The peripheral region 1p has portions (second portions) of the drain electrode 50, the drain layer 10, and the drift layer 11 other than the above part.

  In the peripheral region 1p, the drift layer 11 is provided on the drain layer 10. An insulating layer 80 is provided on the drift layer 11. A connection region 30 c is provided on the drift layer 11 via an insulating layer 80. A drain electrode 50 is electrically connected to the drain layer 10. Further, in the cross section A-A ′ of FIG. 1A (FIG. 1B), the connection region 30 c and the source electrode 51 are not in contact with each other. On the other hand, in the B-B ′ cross section of FIG. 1A (FIG. 1C), a part of the source electrode 51 extends from the active region 1 a to the peripheral region 1 p.

  A Zener diode region 100A is provided in the peripheral region 1p. The Zener diode region 100 </ b> A is provided on the drift layer 11. At least a part of the Zener diode region 100A is located below the connection region 30c. The Zener diode region 100A is surrounded by the insulating layer 80.

The Zener diode region 100A has a semiconductor layer (second semiconductor layer) in which n ⁺ type semiconductor regions (third semiconductor regions) and p ⁺ type semiconductor regions (fourth semiconductor regions) are alternately arranged.

FIG. 2 is a schematic plan view showing the semiconductor device according to the first embodiment.
FIG. 2 shows a plan view when the semiconductor device is cut at a position along the line CC ′ in FIGS. 1B and 1C.

The Zener diode region 100A surrounds the active region 1a. The n ⁺ type semiconductor regions and the p ⁺ type semiconductor regions of the Zener diode region 100A are alternately arranged from the inner periphery toward the outer periphery of the Zener diode region 100A. The number of n ⁺ type semiconductor regions and the number of p ⁺ type semiconductor regions are not limited to the illustrated numbers.

For example, in the semiconductor device 1, in the order of ^{n +} -type semiconductor region 101 / ^{p +} -type semiconductor regions 102 / ^{n +} -type semiconductor region 103 / ^{p +} -type semiconductor region 104 / ^{n +} -type semiconductor region 105, and ^{the n +} -type semiconductor region The p ⁺ type semiconductor regions are alternately arranged from the inner periphery to the outer periphery of the Zener diode region 100A. In the Zener diode region 100A, adjacent n ⁺ type semiconductor regions and p ⁺ type semiconductor regions constitute a Zener diode.

In the semiconductor device 1, the gate electrode of the MOSFET is electrically connected to any n ⁺ type semiconductor region in the Zener diode region 100A via the connection region 30c. Further, the source electrode 51 is electrically connected to any n ⁺ type semiconductor region in the Zener diode region 100A. And electrically connected to the n ⁺ -type semiconductor region to the source electrode 51, it is disposed at a position different from the electrically connected n ⁺ -type semiconductor region to a gate electrode.

This connection state will be described again with reference to FIGS. 1B and 1C.
For example, as shown in FIG. 1B, a part of the insulating layer 80 is opened, and the n ⁺ type semiconductor region 101 and the connection region 30c are electrically connected. The n ⁺ type semiconductor region 101 connected to the connection region 30c is located on the innermost periphery of the Zener diode region 100A.

On the other hand, as shown in FIG. 1C, a part of the insulating layer 80 is opened, and the n ⁺ type semiconductor region 105 and the source electrode 51 are electrically connected. The n ⁺ type semiconductor region 105 connected to the source electrode 51 is located on the outermost periphery of the Zener diode region 100A.

A plurality of gate wirings 30 ⁱ connected to the n ⁺ type semiconductor region 101 are routed through the active region 1 a (see FIG. 2). Each of the plurality of gate wirings 30i is connected to the gate electrode of the MOSFET.

  In the active region 1 a, a channel is formed when the semiconductor device 1 is turned on, and a current flows between the source electrode 51 and the drain electrode 50. A channel is not formed in the peripheral region 1p when the semiconductor device 1 is turned on, and no current flows in the vertical direction (Z direction in the drawing) of the semiconductor device 1. An equipotential ring 90 is provided on the surface of the peripheral region 1p. The equipotential ring 90 has a floating potential or substantially the same potential as the drain electrode 50. If the depletion layer reaches the end of the semiconductor device 1 when the semiconductor device 1 is turned off, a leakage current may occur. By providing the equipotential ring 90 in the peripheral region 1p, the extension of the depletion layer at the end is suppressed.

A cross-sectional structure in the active region 1a of the semiconductor device 1 will be described.
FIG. 3 is a schematic cross-sectional view showing the semiconductor device according to the first embodiment.
FIG. 3 shows a schematic cross section at a position along the line DD ′ in FIG.

  In the active region 1a of the semiconductor device 1, for example, a plurality of MOSFETs having upper and lower electrode structures are arranged. The MOSFET is provided on the surface layer of the semiconductor substrate, and switching (on and off) is controlled by a gate voltage. Here, one MOSFET (MOSFET unit) is, for example, a transistor element having one gate electrode 30.

In the active region 1 a, an n type drift layer 11 is provided on the n ⁺ type drain layer 10. A p-type base region 20 (first semiconductor region) is provided on the drift layer 11. An n ⁺ -type source region 21 (second semiconductor region) is provided on the base region 20. In addition, a p ⁺ region 22 (a hole extraction region) in contact with the source region 21 is provided on the base region 20.

  A drain electrode 50 is electrically connected to the drift layer 11 through the drain layer 10. A source electrode 51 is electrically connected to the base region 20 and the source region 21. Further, the gate insulating film 31 reaches the drift layer 11 from the surface of the source region 21. The gate electrode 30 (third electrode) is in contact with the source region 21, the base region 20, and the drift layer 11 through the gate insulating film 31. The gate electrode 30 is connected to the gate wiring 30i described above.

The material of the drain layer 10, the drift layer 11, the base region 20, the source region 21, the p ⁺ region 22, the n ⁺ type semiconductor region, and the p ⁺ type semiconductor region is, for example, silicon (Si), silicon carbide (SiC), For example, gallium arsenide (GaAs). The material of the gate pad 30p, the connection region 30c, the source electrode 51, and the drain electrode 50 is, for example, at least any one of metals such as aluminum (Al), nickel (Ni), copper (Cu), and titanium (Ti). . The material of the gate electrode 30 and the gate wiring 30i includes a semiconductor into which an impurity element is introduced or a metal (for example, tungsten).

The “insulating film” and “insulating layer” according to the embodiment include silicon dioxide (SiO _x ), silicon nitride (SiN _x ), and the like.

In the embodiment, the n ⁺ type and the n type are referred to as “second conductivity type”, and the p ⁺ type and the p type having a conductivity type different from the second conductivity type are referred to as “first conductivity type”. Also good. In addition, the impurity concentration decreases in the order of n ⁺ type, n type, and n ⁻ type, and the impurity concentration decreases in the order of p ⁺ type, p type, and p ⁻ type. Means.

Examples of n ⁺ -type and n-type impurity elements include phosphorus (P) and arsenic (As). Examples of the p ⁺ -type and p-type impurity elements include boron (B).

  FIG. 4A to FIG. 4C are schematic views showing the operation of the semiconductor device according to the first embodiment.

  4A to 4C show the gate electrode 30 (G), the source electrode 51 (S), and the drain electrode 50 (D). In the semiconductor device 1, the gate electrode 30 and the source electrode 51 are connected via the Zener diode region 100A.

4A to 4C exemplify a Zener diode region 100A composed of n ⁺ type semiconductor region / p ⁺ type semiconductor region / n ⁺ type semiconductor region as an example. That is, the Zener diode region 100A includes the diode A and the diode B.

  When the semiconductor device 1 is operated, a ground potential is applied to the source electrode 51 and a potential of several hundreds (V) is applied to the drain electrode 50. In the ON operation of the MOSFET, a potential equal to or higher than the threshold potential (Vth) is applied to the gate electrode 30. The potential equal to or higher than the threshold potential is, for example, a positive potential as shown in FIG. Here, the MOSFET is an n-type MOSFET.

  In the on state, the potential of the gate electrode 30 is several (V) to several tens (V) with respect to the potential of the source electrode 51. In this case, a reverse bias is applied to the diode A. For this reason, no current flows between the gate electrode 30 and the source electrode 51. That is, the gate electrode 30 and the source electrode 51 are insulated.

  In the off state, the potential of the gate electrode 30 is substantially equal to the potential of the source electrode 51, for example. For this reason, no current flows between the gate electrode 30 and the source electrode 51. That is, the semiconductor device 1 can perform a normal on / off operation.

  On the other hand, as shown in FIG. 4B, for example, when an excessive negative potential is applied to the gate electrode 30 due to static electricity or the like, a forward bias is applied to the diode A, and the breakdown voltage of the Zener diode is less than or equal to the breakdown voltage. A reverse bias is applied. As a result, the negative charge supplied to the gate electrode 30 is quickly discharged to the source electrode 51.

  As shown in FIG. 4C, for example, when an excessive positive potential is applied to the gate electrode 30, a forward bias is applied to the diode B, and a reverse bias equal to or lower than the breakdown voltage of the Zener diode is applied to the diode A. Applied. As a result, the positive charge supplied to the gate electrode 30 is quickly discharged to the source electrode 51.

  Thus, in the semiconductor device 1, the gate electrode 30 is reliably protected from overvoltage. That is, the semiconductor device 1 stably operates on and off even when placed in an environment where an overvoltage is applied to the gate electrode 30.

  As means for protecting the gate electrode 30 from overvoltage, a method of providing a control circuit in which no overvoltage is applied to the gate electrode, and a method of increasing the dielectric strength capability of the semiconductor device itself can be considered.

  However, the method of adding a control circuit causes an increase in cost. Alternatively, when the control circuit is added, the device size may increase. Further, a technique for increasing the dielectric strength capability of the semiconductor device itself may require a large dimensional change or material change.

On the other hand, in the first embodiment, the Zener diode region 100A described above is arranged in the peripheral region 1p in the semiconductor device 1. The n ⁺ type semiconductor regions and the p ⁺ type semiconductor regions are alternately arranged from the inner periphery to the outer periphery of the Zener diode region 100A. The pn junction of each Zener diode surrounds the active region 1a. According to such an arrangement of the Zener diodes, the pn junction area of each Zener diode is increased. This means that the semiconductor device 1 has a large-capacity Zener diode between the gate and the source. Therefore, the gate electrode 30 is reliably protected from overvoltage.

  There is also a method of incorporating a Zener diode in the transistor element. However, if a Zener diode is built in between the gate electrode 30 and the source electrode 51 for each transistor element, the capacitance of the Zener diode becomes smaller than that of the first embodiment. This is because the Zener diode region formed in the surface layer of the semiconductor is limited in the wafer process. In such a case, the Zener diode itself may be destroyed by an overcurrent flowing between the gate and the source. In the first embodiment, the pn junction area is increased to eliminate such a problem.

  When the Zener diode region 100A is replaced with a conductor, and this conductor is connected to the source electrode 51, the conductor functions as a so-called field plate electrode. In other words, in the semiconductor device 1, the region where the conventional field plate electrode is disposed is replaced with a Zener diode region. Therefore, even if the Zener diode region 100A is provided in the peripheral region 1p, the planar area of the semiconductor device does not increase.

(Second Embodiment)
FIG. 5 is a schematic plan view showing the semiconductor device according to the second embodiment.

  FIG. 5 shows a cut surface corresponding to the position along the line C-C ′ in FIG. 1B and FIG.

In the semiconductor device 2 according to the second embodiment, the Zener diode region 100B surrounds the active region 1a. However, in the semiconductor device 2, the n ⁺ type semiconductor regions 101 and the p ⁺ type semiconductor regions 102 are alternately arranged along the direction in which the Zener diode region 100B goes around. The number of n ⁺ type semiconductor regions and the number of p ⁺ type semiconductor regions are not limited to the illustrated numbers. A contact region 150 and a contact region 151 are connected to an arbitrary n ⁺ type semiconductor region 101.

In the semiconductor device 2, the gate electrode 30 is electrically connected to one of the n ⁺ type semiconductor regions 101 in the Zener diode region 100B. Further, the source electrode 51 to one of the n ⁺ -type semiconductor region 101 other than the n ⁺ -type semiconductor region 101 which is electrically connected to the gate electrode 30 are electrically connected. For example, the gate electrode 30 (or the connection region 30 c) is electrically connected to the n ⁺ type semiconductor region 101 connected to the contact region 150 through the contact region 150. The source electrode 51 is electrically connected to the n ⁺ type semiconductor region 101 connected to the contact region 151 through the contact region 151.

The active region 1 a is located between the n ⁺ type semiconductor region 101 electrically connected to the gate electrode 30 and the n ⁺ type semiconductor region 101 electrically connected to the source electrode 51. That is, the Zener diode region 100B is a region in which the Zener diode region indicated by reference numeral 100B-1 and the Zener diode region indicated by reference numeral 100B-2 are connected in parallel. That is, the semiconductor device 2 has a large-capacity Zener diode between the gate and the source due to the parallel connection. Therefore, also in the second embodiment, the gate electrode 30 is reliably protected from overvoltage.

  Each of the plurality of gate wirings 30i arranged in the active region 1a is connected to the connection region 30c by a lead line (not shown).

  In the above embodiment, the semiconductor device provided with MOSFET was illustrated. The transistor element is not limited to a MOSFET but may be an IGBT (Insulated Gate Bipolar Transistor). In the IGBT, in addition to the structure shown in FIGS. 1B and 1C, a p-type semiconductor layer (collector layer) is provided between the drain layer 10 and the drain electrode 50. The source region is read as the emitter region, and the drift layer is read as the base layer. In the above embodiment, an n-type channel MOSFET is exemplified as the MOSFET. However, a semiconductor device using a p-type channel MOSFET in which the conductivity type of each part of the n-type channel MOSFET is inverted is also included in this embodiment. .

  The embodiment has been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the embodiments as long as they include the features of the embodiments. Each element included in each of the specific examples described above and their arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be appropriately changed.

  In the embodiment, “on top” when “part A is provided on part B” means that part A contacts part B and part A is provided on part B. It may be used in the sense that the part A is not in contact with the part B and the part A is provided above the part B. In addition, “part A is provided on part B” means that part A and part B are reversed and part A is located below part B, or part A and part B are placed sideways. It may also apply when lined up. This is because even if the semiconductor device according to the embodiment is rotated, the structure of the semiconductor device is not changed before and after the rotation.

  In addition, each element included in each of the above-described embodiments can be combined as long as technically possible, and combinations thereof are also included in the scope of the embodiment as long as they include the features of the embodiment. In addition, in the category of the idea of the embodiment, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the embodiment. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1, 2 semiconductor device, 1a active region, 1p peripheral region, 10 drain layer, 11 drift layer (first semiconductor layer), 20 base region (first semiconductor region), 21 source region (second semiconductor region), 22 p ⁺ Region, 30 gate electrode (third electrode), 30c connection region, 30i gate wiring, 30p gate pad, 31 gate insulating film, 50 drain electrode (first electrode), 51 source electrode (second electrode), 80 insulating layer , 90 equipotential ring, 100A, 100B Zener diode region, 101, 103, 105 n ^{+ type} semiconductor region (third semiconductor region), 102, 104 p ^{+ type} semiconductor region (fourth semiconductor region), 150, 151 contact region

Claims (5)

A first semiconductor layer;
A first conductivity type first semiconductor region provided on the first semiconductor layer in the first region of the first semiconductor layer;
A second semiconductor region of a second conductivity type provided on the first semiconductor region;
An insulating film reaching from the surface of the second semiconductor region to the first semiconductor layer;
A second semiconductor provided on the first semiconductor layer in the second region of the first semiconductor layer, wherein the second conductive type third semiconductor region and the first conductive type fourth semiconductor region are alternately arranged. A zener diode region including a layer; and
A first electrode electrically connected to the first semiconductor layer;
A second electrode electrically connected to the first semiconductor region and the second semiconductor region and electrically connected to any of the third semiconductor regions in the Zener diode region;
The first semiconductor layer, the first semiconductor region, and the second semiconductor region are in contact with each other through the insulating film, and are electrically connected to the third semiconductor region other than the one in the Zener diode region. A third electrode;
A connection region for electrically connecting the third electrode and the third semiconductor region other than any of the above, and
A semiconductor device comprising: A first semiconductor layer;
A first conductivity type first semiconductor region provided on the first semiconductor layer in the first region of the first semiconductor layer;
A second semiconductor region of a second conductivity type provided on the first semiconductor region;
An insulating film reaching from the surface of the second semiconductor region to the first semiconductor layer;
A second semiconductor provided on the first semiconductor layer in the second region of the first semiconductor layer, wherein the second conductive type third semiconductor region and the first conductive type fourth semiconductor region are alternately arranged. A zener diode region including a layer; and
A first electrode electrically connected to the first semiconductor layer;
A second electrode electrically connected to the first semiconductor region and the second semiconductor region and electrically connected to any of the third semiconductor regions in the Zener diode region;
The first semiconductor layer, the first semiconductor region, and the second semiconductor region are in contact with each other through the insulating film, and are electrically connected to the third semiconductor region other than the one in the Zener diode region. A third electrode;
A semiconductor device comprising: The second region further includes a connection region electrically connected to the third electrode,
The connection region is provided on the first semiconductor layer;
The semiconductor device according to claim 2, wherein the third electrode is electrically connected to the third semiconductor region other than any one of the third electrodes via the connection region. The zener diode region surrounds the first region;
The third semiconductor region and the fourth semiconductor region are alternately arranged from the inner periphery to the outer periphery of the Zener diode region,
The third semiconductor region other than the one is located on the innermost periphery of the Zener diode region,
The semiconductor device according to claim 1, wherein any one of the third semiconductor regions is located on an outermost periphery of the Zener diode region. The zener diode region surrounds the first region;
The third semiconductor region and the fourth semiconductor region are alternately arranged along a direction in which the Zener diode region goes around,
The semiconductor device according to claim 1, wherein the first region is located between any one of the third semiconductor regions and any third semiconductor region other than the one.

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