JP2013062473A - Wiring board and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a novel wiring board having a high density wiring pattern, suitable for solving such a problem that it is difficult to form through electrodes (VIA) at fine intervals of several tens μm, and to apply the method especially to a wiring board using glass as the base material.SOLUTION: The manufacturing method of a wiring board includes a step for forming, on at least one surface of a glass plate, a wiring pattern of parallel stripes composed of a conductive material by photolithography or a printing method, and then laminating and pressing other similar glass plate, and a step for laminating a plurality of glass plates so that the stripe arrangement direction of wiring pattern is arranged between the glass plates and no gap is generated between the glass plates, and then mechanically slicing the glass plates thus laminated along two cross-sectional lines extending in a direction perpendicular to the lamination direction and adjoining in parallel with the parallel direction of the stripes thus producing planar members.

Description

  The present invention relates to a wiring board and a method for manufacturing the wiring board, and in particular, provides a manufacturing method suitable for manufacturing a glass wiring board and a glass interposer board having a narrow via interval, and a wiring board obtained thereby.

With the advent of advanced information technology, information communication technology has been rapidly developed, and various semiconductor elements have been increased in density accordingly.
Accordingly, in a semiconductor package, an interposer substrate for mounting a semiconductor element and a printed wiring board generically including a printed circuit board on which an electronic component including the semiconductor element is mounted are required to have high density and high-speed response.
On the other hand, since electronic devices are often required to be small, thin, and light, it is necessary to balance high density, high speed, miniaturization, and thinning in a balanced manner.

In order to realize these, for printed wiring boards, miniaturization of wiring rules, multilayering of wiring layers, use of insulating materials with physical properties for high-speed response, and connection between layers of insulating layers There are demands for miniaturization of connecting via holes and thinning of insulating layers.

  In the field of chip size packages and interposers, research and development on through silicon vias, which are said to be able to shorten the wiring length using silicon as a base material, are being actively conducted. This is due in part to the fact that the process is relatively easy because the substrate is silicon.

However, as research progresses, it has become clear that the electrical properties are worse than conventional organic substrates due to the fact that the base material is silicon.
This is because the silicon base material that is generally used has conductivity, so that a very thin insulating layer (for example, polyimide resin or SiO ₂ ) is applied to the surface of the silicon substrate in order to obtain insulation from the wiring. Keep.
For this reason, a capacitor having a structure in which a very thin insulating layer is sandwiched between a wiring which is a conductor and a silicon substrate is formed, which is caused by having an adverse effect on a high-frequency signal.
One method of solving this problem is to use high-resistance silicon as a base material, but there is a problem that the cost increases when high-resistance silicon is used.

In addition, various methods for obtaining a multilayer ceramic substrate by firing a green sheet after laminating and pressing multiple ceramic green sheets to form a multilayer structure are also known. Since the ceramic substrate is a porous material, there is a problem that reliability is not sufficient in terms of airtightness when mounting electronic components that require airtightness.
Therefore, development of a glass substrate based on glass, which is a dense and sufficiently insulating material and very advantageous in terms of electrical characteristics, has begun.

As a method of providing a through electrode on a glass substrate, a method of physically drilling a glass substrate by a drill or a dry blast method and embedding a metal column, or a method of providing a through hole in a glass substrate using photosensitive glass is proposed. Has been.
However, in these methods, for example, when dry blasting is used, there is a limit due to mechanical accuracy, and there is a problem that the opening diameter differs between the front and back of the through electrode, and when photosensitive glass is used, the distance between the through electrodes depends on the shape. Cannot be narrowed, and at most a few hundred μm intervals was the limit.
Prior art documents disclosing methods for forming through holes on a glass substrate made of borosilicate glass by a dry blasting method using fine granular media such as alumina or silicon carbide or an etching method are disclosed in Patent Documents 1 and 2. Etc.

Japanese Patent No. 4214068 Japanese Patent No. 4702794

On the other hand, glass drilling methods using laser and gas etching have also been proposed, but there are many problems such as the etching rate being too slow and anisotropic etching not being possible, and it is thought that it will still take time to put it into practical use. .
From the current situation, through electrodes with an interval of several tens of μm that have already been realized in silicon wiring substrates cannot be realized in glass substrates, and it is difficult to make fine wiring and miniaturization, so adoption of glass substrates for interposer applications etc. There are almost no reported cases.
An object of the present invention is to propose a novel manufacturing method suitable for solving the problem that it is difficult to form through electrodes (VIA) at fine intervals, and in particular, wiring based on glass. Its main purpose is application to substrates.

In the manufacturing method according to the present invention, a method of forming a conductive pattern that finally becomes a through electrode (VIA) on the surface of the glass plate is employed instead of a method of forming a through hole in the thickness direction with respect to the glass plate.

That is, the method for manufacturing a wiring board according to the present invention includes:
Wiring between glass plates is the process of forming a wiring pattern in which stripes made of conductive material are arranged in parallel on at least one side of a glass plate by photolithography or printing, and laminating and bonding other similar glass plates. After laminating multiple sheets so that the stripe parallel direction of the pattern is aligned and so that no gap is generated between the glass plates,
A step of mechanically slicing the laminated glass plates along two cross-sectional lines adjacent to each other in a direction perpendicular to the lamination direction and parallel to the parallel direction of the stripes to form a plate-like member It is characterized by comprising.

The obtained sliced body (plate-like member) has a configuration in which cross sections of the stripes are scattered on the slice surface so as to penetrate to the front and back surfaces.
A semiconductor element or the like is mounted on the slice surface, and a new wiring pattern is formed, so that the slice body becomes a wiring board.

The wiring board obtained by the above method has slit-like glass connected in one direction without a gap, resulting in a structure similar to that of a plate-like glass substrate and corresponding to the stripes scattered on the surface of the plate-like member Will function as a VIA (through electrode) that penetrates the plate-like member.
Furthermore, a wiring board having a multilayer structure can be obtained by laminating a plurality of wiring boards obtained as described above as necessary.

According to the method of the present invention, a conventional method for forming a through hole in a glass plate by drilling, dry blasting, laser, gas etching, or the like.
0. It is possible to stably manufacture a glass substrate for a wiring board having through electrodes with a fine interval of about several tens of μm that could not be realized by the method.
In the wiring board of the present invention, a wiring board having excellent airtightness and electrical characteristics and having a high density wiring pattern formed by multilayering is realized.

Explanatory drawing which shows the laminated body 100 formed by forming the conductor layer 2 (stripe pattern) on the surface of the insulator (glass) 1. FIG. Explanatory drawing which shows the laminated structure formed by carrying out the lamination | stacking crimping | compression-bonding of the other laminated body 100 by which the conductor layer 2 is similarly formed in the laminated body 100 of FIG. 1 through the adhesive agent. FIG. 3 is an explanatory view showing a wiring board member 200 obtained by slicing the laminated structure of FIG. 2 along A-A ′ and B-B ′ lines. Sectional drawing in C-C 'of the member 200 for wiring boards of FIG. Explanatory drawing which shows the wiring board | substrate 300 formed by forming a wiring pattern in the front and back of the member 200 for wiring boards of FIG. FIG. 6 is an explanatory diagram showing a state in which the wiring board 300 of FIG. 5 is connected and mounted to an external circuit board or a device as an interposer board.

  Hereinafter, a glass wiring board according to an embodiment of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
1st process: The laminated structure laminated body 100 of several laminated body is obtained by laminating | stacking the insulator 1 and the conductor layer 2. FIG.
The insulator 1 can be mainly made of silicon oxide, glass, or an organic material, processed into a plate shape, or a vapor deposition method or coating method on the surface of a sheet made of another insulating material. However, it is not limited to these.
For the material of the conductor layer 2 (wiring layer in which stripes are arranged in parallel), copper, nickel, tungsten, aluminum and the like can be used, and a vapor deposition method, a plating method, and a method of bonding foils using an adhesive can be selected. It is not limited to.
The conductor layer 2 (wiring pattern) is formed by forming a wiring pattern using a general photolithography technique regardless of whether it is wet or dry, and finally the VIA (through electrode) arranged at fine intervals. Become.
In forming the conductor layer 2, a wiring pattern may be formed on the surface of the insulator 1 by a printing method using conductive ink. (Figure 1)

A laminated structure shown in FIG. 2 is obtained by laminating and bonding a laminated body 100 in which the conductor layer 2 is formed on the insulator 1 to the laminated body 100 shown in FIG. 1 with an adhesive.
In FIG. 2, a plurality of third layers consisting of only the first layered body, the second layered body, and the insulator 1 where the conductor layer 2 is not formed are laminated and pressure-bonded.
Further, in the same figure, the concave portions corresponding to the gaps between the stripes confirmed in FIG. 1 are not filled, but are illustrated as being filled. The recesses are filled with an adhesive so that no gaps are generated between them.
Alternatively, a step of filling the recesses between the stripes with SiO ₂ by a CVD method may be performed prior to the lamination pressure bonding of the laminate 100 via an adhesive.

The supply of SiO ₂ by the CVD method may be performed so as to sufficiently fill the recesses between the stripes, or may be performed so as to cover the entire surface of the stripes (conductor layer 2).
In the latter case, since SiO ₂ is in direct contact with the surface of the stripe (conductor layer 2), superiority in electrical characteristics is ensured over the state in which the adhesive is in contact.

The laminated pressure bonding of the laminated body 100 is not limited to the configuration shown in FIG. 2 and may be repeated many times.
However, it should be noted that the stripes (conductor layer 2) formed in the laminate must not be in direct contact between the laminates and that the parallel direction of the stripes must be substantially aligned. Become.
As described above, a laminated structure formed by combining a plurality of laminated bodies as unit structures is obtained.

Second Step: Mechanical Slicing By slicing the laminated structure shown in FIG. 2 along the cross-sectional lines AA ′ and BB ′ shown in FIG. 2, a wiring board member 200 shown in FIG. 3 is obtained. . (FIG. 2 shows a cross section of the right side surface and FIG. 3 shows the front side.)
The widths between A and B and between A 'and B' can be set arbitrarily, but correspond to the plate thickness that will later become a wiring board, and therefore it is necessary to set the parallelism and interval appropriately.

As a cutting (slicing) method, when the insulator is glass or silicon oxide, a general wafer cutting method or dicing can be used if the laminate is thin.
In the case of organic insulators, it is possible to use a router cutting method.
After cutting, chemical cross-sectional polishing is performed on the cross section as necessary to smooth the cut surface that becomes the mounting portion of the semiconductor element or the wiring pattern forming portion.
By repeating cutting (slicing), a plurality of wiring board members 200 can be obtained from one laminated structure.

Third Step: Formation of Wiring Pattern → Production of Wiring Substrate FIG. 4 is a cross-sectional view taken along the line CC ′ of FIG.
By forming the wiring pattern 3 using at least one surface (at least one of the upper surface and the lower surface in the figure) of the wiring board member 200 using a plating method or a photolithography method generally used, FIG. A wiring substrate 300 shown in FIG.
As shown in FIG. 5, when the wiring patterns are formed on both upper and lower surfaces, the conductor layer 2 functions as a VIA that connects the upper and lower wiring patterns.
When the wiring pattern is formed only on the upper surface, the lower side of the conductor layer 2 functions as a VIA for connection to an external circuit board or equipment.

Fourth Step: Fabrication of Interposer Substrate The semiconductor element 5 is mounted on the wiring substrate 300 obtained in the third step, and the connection terminals of the wiring pattern formed on the connection terminals of the semiconductor element 5 and the upper surface of the wiring substrate 300 are electrically connected. It is possible to connect and mount to an external circuit board or equipment as an interposer board by performing various other processes such as resin sealing. (Fig. 6)
This figure is an illustration when the semiconductor element 5 is flip-chip mounted, but the present invention can also be applied to mounting by a wire bonding mounting method.

Second Embodiment
In the first step of the first embodiment, the conductor layer can be formed by a subtractive method.

<Third Embodiment>
In the first step of the first embodiment, the conductor layer can be formed by a printing method using a conductive paste.
As the conductive paste, silver paste, copper paste, and carbon paste can be used, but are not limited thereto.

By the above method, it is possible to manufacture a through electrode having a distance equivalent to a wiring distance that can be formed on a glass substrate by an existing photolithography method.
For example, a gap of about 20 μm can be formed by the subtractive method, and a gap of 1 μm can be formed by using the gas etching method.

A copper film having a thickness of 100 nm was formed on a glass substrate having a thickness of 1 mm by chemical vapor deposition, and a conductor layer of copper having a thickness of 30 μm was formed by electrolytic copper plating using this as a seed layer.
A resist pattern was formed on the conductor layer using a photolithography method, and copper was etched using an iron chloride solution to form a striped wiring pattern having a wiring width of 30 μm and a wiring interval of 60 μm.

A silicon dioxide film was formed on the wiring pattern by chemical vapor deposition, and an insulating layer was formed by laminating a glass plate having a thickness of 100 μm after planarization.

Again, a copper conductor layer was formed, patterned, and repeated the lamination of the silicon oxide film and the glass substrate. When this was repeated 23 times, a glass substrate having a thickness of 1 mm was finally laminated. A laminate having a thickness of 5 mm was completed.

The completed laminate was diced, cut into a width of 1 mm in a direction perpendicular to the stripe pattern of the wiring layer, and both surfaces were polished by chemical mechanical polishing to a thickness of 750 μm.

Copper was deposited on the cut out substrate by plating, and wiring was formed on the cross-sectional portion by photolithography.

The substrate on which the wiring was formed was further cut into a 5 mm chip shape to form a wiring substrate. As a result, a glass wiring board having a through electrode having a wiring gap of 30 μm could be produced.

When a continuity test of the front and back surfaces of the glass wiring board having the completed through electrode was performed, continuity was exhibited between the electrodes connected to the front and back by the through electrode, and insulation was exhibited in the portion not connected between the wires.

According to the embodiment, it is possible to provide a glass wiring substrate in which the interval between the through electrodes is narrow and fine wiring is possible.

By mounting this substrate on one side and mounting the semiconductor device on the other side, it can be used as an interposer substrate.

DESCRIPTION OF SYMBOLS 1 ... Insulating layer 2 ... Conductor layer, penetration electrode 3 ... Wiring 4 ... Wiring board 5 ... Semiconductor device 6 ... Solder 100 ... Laminate 200 ... Wiring board member 300 ... Wiring board AA '... Board | substrate cut surface BB '... Substrate cutting plane CC' ... Substrate cross section

Claims (6)

Forming a wiring pattern in which stripes made of a conductive material are arranged in parallel on at least one surface of an insulating substrate by photolithography or printing;
Similarly, a process of laminating a plurality of other insulating substrates on which wiring patterns are formed so as not to generate a gap between the insulating substrates by pressure bonding with an adhesive,
Mechanically slicing the obtained laminate in a direction perpendicular to the lamination direction and in a direction along the parallel direction of the stripes;
Repeating the slicing step at intervals adjacent to each other in parallel with the cross-sectional line;
A method for manufacturing a wiring board, comprising: Forming a wiring pattern constituting a circuit for inputting / outputting an electric signal to / from a semiconductor element to be mounted on a cross section of a plate member mechanically sliced;
The method for manufacturing a wiring board according to claim 1, further comprising: A step of laminating and pressing a plurality of plate-like members on which wiring patterns are formed;
The method for manufacturing a wiring board according to claim 2, further comprising: A step of filling the recesses between the stripes in the insulating substrate formed with the wiring pattern in which the stripes made of the conductive material are arranged in parallel with SiO ₂ by a CVD method;
The method for manufacturing a wiring board according to claim 1, further comprising:   The method for manufacturing a wiring substrate according to claim 1, wherein the insulating substrate is glass. A wiring board obtained by the method of manufacturing a wiring board according to claim 5,
A wiring pattern constituting a circuit for inputting / outputting electric signals to / from a semiconductor element to be mounted is formed on at least one surface of a plate-like glass substrate formed by connecting slit-like glass members in one direction without gaps. A wiring board,
A wiring board having a configuration in which conductive portions to be VIA (penetrating electrodes) penetrating a plate-like member are scattered on the front and back surfaces of the wiring board.